[mirror_ubuntu-hirsute-kernel.git] / drivers / soc / mediatek / mtk-scpsys.c

/*
 * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/regulator/consumer.h>
#include <linux/soc/mediatek/infracfg.h>

#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/power/mt8173-power.h>

#define SPM_VDE_PWR_CON			0x0210
#define SPM_MFG_PWR_CON			0x0214
#define SPM_VEN_PWR_CON			0x0230
#define SPM_ISP_PWR_CON			0x0238
#define SPM_DIS_PWR_CON			0x023c
#define SPM_CONN_PWR_CON		0x0280
#define SPM_VEN2_PWR_CON		0x0298
#define SPM_AUDIO_PWR_CON		0x029c	/* MT8173 */
#define SPM_BDP_PWR_CON			0x029c	/* MT2701 */
#define SPM_ETH_PWR_CON			0x02a0
#define SPM_HIF_PWR_CON			0x02a4
#define SPM_IFR_MSC_PWR_CON		0x02a8
#define SPM_MFG_2D_PWR_CON		0x02c0
#define SPM_MFG_ASYNC_PWR_CON		0x02c4
#define SPM_USB_PWR_CON			0x02cc

#define SPM_PWR_STATUS			0x060c
#define SPM_PWR_STATUS_2ND		0x0610

#define PWR_RST_B_BIT			BIT(0)
#define PWR_ISO_BIT			BIT(1)
#define PWR_ON_BIT			BIT(2)
#define PWR_ON_2ND_BIT			BIT(3)
#define PWR_CLK_DIS_BIT			BIT(4)

#define PWR_STATUS_CONN			BIT(1)
#define PWR_STATUS_DISP			BIT(3)
#define PWR_STATUS_MFG			BIT(4)
#define PWR_STATUS_ISP			BIT(5)
#define PWR_STATUS_VDEC			BIT(7)
#define PWR_STATUS_BDP			BIT(14)
#define PWR_STATUS_ETH			BIT(15)
#define PWR_STATUS_HIF			BIT(16)
#define PWR_STATUS_IFR_MSC		BIT(17)
#define PWR_STATUS_VENC_LT		BIT(20)
#define PWR_STATUS_VENC			BIT(21)
#define PWR_STATUS_MFG_2D		BIT(22)
#define PWR_STATUS_MFG_ASYNC		BIT(23)
#define PWR_STATUS_AUDIO		BIT(24)
#define PWR_STATUS_USB			BIT(25)

enum clk_id {
	CLK_NONE,
	CLK_MM,
	CLK_MFG,
	CLK_VENC,
	CLK_VENC_LT,
	CLK_ETHIF,
	CLK_MAX,
};

static const char * const clk_names[] = {
	NULL,
	"mm",
	"mfg",
	"venc",
	"venc_lt",
	"ethif",
	NULL,
};

#define MAX_CLKS	2

struct scp_domain_data {
	const char *name;
	u32 sta_mask;
	int ctl_offs;
	u32 sram_pdn_bits;
	u32 sram_pdn_ack_bits;
	u32 bus_prot_mask;
	enum clk_id clk_id[MAX_CLKS];
	bool active_wakeup;
};

struct scp;

struct scp_domain {
	struct generic_pm_domain genpd;
	struct scp *scp;
	struct clk *clk[MAX_CLKS];
	const struct scp_domain_data *data;
	struct regulator *supply;
};

struct scp {
	struct scp_domain *domains;
	struct genpd_onecell_data pd_data;
	struct device *dev;
	void __iomem *base;
	struct regmap *infracfg;
};

static int scpsys_domain_is_on(struct scp_domain *scpd)
{
	struct scp *scp = scpd->scp;

	u32 status = readl(scp->base + SPM_PWR_STATUS) & scpd->data->sta_mask;
	u32 status2 = readl(scp->base + SPM_PWR_STATUS_2ND) &
				scpd->data->sta_mask;

	/*
	 * A domain is on when both status bits are set. If only one is set
	 * return an error. This happens while powering up a domain
	 */

	if (status && status2)
		return true;
	if (!status && !status2)
		return false;

	return -EINVAL;
}

static int scpsys_power_on(struct generic_pm_domain *genpd)
{
	struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
	struct scp *scp = scpd->scp;
	unsigned long timeout;
	bool expired;
	void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs;
	u32 sram_pdn_ack = scpd->data->sram_pdn_ack_bits;
	u32 val;
	int ret;
	int i;

	if (scpd->supply) {
		ret = regulator_enable(scpd->supply);
		if (ret)
			return ret;
	}

	for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++) {
		ret = clk_prepare_enable(scpd->clk[i]);
		if (ret) {
			for (--i; i >= 0; i--)
				clk_disable_unprepare(scpd->clk[i]);

			goto err_clk;
		}
	}

	val = readl(ctl_addr);
	val |= PWR_ON_BIT;
	writel(val, ctl_addr);
	val |= PWR_ON_2ND_BIT;
	writel(val, ctl_addr);

	/* wait until PWR_ACK = 1 */
	timeout = jiffies + HZ;
	expired = false;
	while (1) {
		ret = scpsys_domain_is_on(scpd);
		if (ret > 0)
			break;

		if (expired) {
			ret = -ETIMEDOUT;
			goto err_pwr_ack;
		}

		cpu_relax();

		if (time_after(jiffies, timeout))
			expired = true;
	}

	val &= ~PWR_CLK_DIS_BIT;
	writel(val, ctl_addr);

	val &= ~PWR_ISO_BIT;
	writel(val, ctl_addr);

	val |= PWR_RST_B_BIT;
	writel(val, ctl_addr);

	val &= ~scpd->data->sram_pdn_bits;
	writel(val, ctl_addr);

	/* wait until SRAM_PDN_ACK all 0 */
	timeout = jiffies + HZ;
	expired = false;
	while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {

		if (expired) {
			ret = -ETIMEDOUT;
			goto err_pwr_ack;
		}

		cpu_relax();

		if (time_after(jiffies, timeout))
			expired = true;
	}

	if (scpd->data->bus_prot_mask) {
		ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
				scpd->data->bus_prot_mask);
		if (ret)
			goto err_pwr_ack;
	}

	return 0;

err_pwr_ack:
	for (i = MAX_CLKS - 1; i >= 0; i--) {
		if (scpd->clk[i])
			clk_disable_unprepare(scpd->clk[i]);
	}
err_clk:
	if (scpd->supply)
		regulator_disable(scpd->supply);

	dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);

	return ret;
}

static int scpsys_power_off(struct generic_pm_domain *genpd)
{
	struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
	struct scp *scp = scpd->scp;
	unsigned long timeout;
	bool expired;
	void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs;
	u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
	u32 val;
	int ret;
	int i;

	if (scpd->data->bus_prot_mask) {
		ret = mtk_infracfg_set_bus_protection(scp->infracfg,
				scpd->data->bus_prot_mask);
		if (ret)
			goto out;
	}

	val = readl(ctl_addr);
	val |= scpd->data->sram_pdn_bits;
	writel(val, ctl_addr);

	/* wait until SRAM_PDN_ACK all 1 */
	timeout = jiffies + HZ;
	expired = false;
	while (pdn_ack && (readl(ctl_addr) & pdn_ack) != pdn_ack) {
		if (expired) {
			ret = -ETIMEDOUT;
			goto out;
		}

		cpu_relax();

		if (time_after(jiffies, timeout))
			expired = true;
	}

	val |= PWR_ISO_BIT;
	writel(val, ctl_addr);

	val &= ~PWR_RST_B_BIT;
	writel(val, ctl_addr);

	val |= PWR_CLK_DIS_BIT;
	writel(val, ctl_addr);

	val &= ~PWR_ON_BIT;
	writel(val, ctl_addr);

	val &= ~PWR_ON_2ND_BIT;
	writel(val, ctl_addr);

	/* wait until PWR_ACK = 0 */
	timeout = jiffies + HZ;
	expired = false;
	while (1) {
		ret = scpsys_domain_is_on(scpd);
		if (ret == 0)
			break;

		if (expired) {
			ret = -ETIMEDOUT;
			goto out;
		}

		cpu_relax();

		if (time_after(jiffies, timeout))
			expired = true;
	}

	for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++)
		clk_disable_unprepare(scpd->clk[i]);

	if (scpd->supply)
		regulator_disable(scpd->supply);

	return 0;

out:
	dev_err(scp->dev, "Failed to power off domain %s\n", genpd->name);

	return ret;
}

static bool scpsys_active_wakeup(struct device *dev)
{
	struct generic_pm_domain *genpd;
	struct scp_domain *scpd;

	genpd = pd_to_genpd(dev->pm_domain);
	scpd = container_of(genpd, struct scp_domain, genpd);

	return scpd->data->active_wakeup;
}

static void init_clks(struct platform_device *pdev, struct clk **clk)
{
	int i;

	for (i = CLK_NONE + 1; i < CLK_MAX; i++)
		clk[i] = devm_clk_get(&pdev->dev, clk_names[i]);
}

static struct scp *init_scp(struct platform_device *pdev,
			const struct scp_domain_data *scp_domain_data, int num)
{
	struct genpd_onecell_data *pd_data;
	struct resource *res;
	int i, j;
	struct scp *scp;
	struct clk *clk[CLK_MAX];

	scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
	if (!scp)
		return ERR_PTR(-ENOMEM);

	scp->dev = &pdev->dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	scp->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(scp->base))
		return ERR_CAST(scp->base);

	scp->domains = devm_kzalloc(&pdev->dev,
				sizeof(*scp->domains) * num, GFP_KERNEL);
	if (!scp->domains)
		return ERR_PTR(-ENOMEM);

	pd_data = &scp->pd_data;

	pd_data->domains = devm_kzalloc(&pdev->dev,
			sizeof(*pd_data->domains) * num, GFP_KERNEL);
	if (!pd_data->domains)
		return ERR_PTR(-ENOMEM);

	scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
			"infracfg");
	if (IS_ERR(scp->infracfg)) {
		dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
				PTR_ERR(scp->infracfg));
		return ERR_CAST(scp->infracfg);
	}

	for (i = 0; i < num; i++) {
		struct scp_domain *scpd = &scp->domains[i];
		const struct scp_domain_data *data = &scp_domain_data[i];

		scpd->supply = devm_regulator_get_optional(&pdev->dev, data->name);
		if (IS_ERR(scpd->supply)) {
			if (PTR_ERR(scpd->supply) == -ENODEV)
				scpd->supply = NULL;
			else
				return ERR_CAST(scpd->supply);
		}
	}

	pd_data->num_domains = num;

	init_clks(pdev, clk);

	for (i = 0; i < num; i++) {
		struct scp_domain *scpd = &scp->domains[i];
		struct generic_pm_domain *genpd = &scpd->genpd;
		const struct scp_domain_data *data = &scp_domain_data[i];

		pd_data->domains[i] = genpd;
		scpd->scp = scp;

		scpd->data = data;

		for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
			struct clk *c = clk[data->clk_id[j]];

			if (IS_ERR(c)) {
				dev_err(&pdev->dev, "%s: clk unavailable\n",
					data->name);
				return ERR_CAST(c);
			}

			scpd->clk[j] = c;
		}

		genpd->name = data->name;
		genpd->power_off = scpsys_power_off;
		genpd->power_on = scpsys_power_on;
		genpd->dev_ops.active_wakeup = scpsys_active_wakeup;
	}

	return scp;
}

static void mtk_register_power_domains(struct platform_device *pdev,
				struct scp *scp, int num)
{
	struct genpd_onecell_data *pd_data;
	int i, ret;

	for (i = 0; i < num; i++) {
		struct scp_domain *scpd = &scp->domains[i];
		struct generic_pm_domain *genpd = &scpd->genpd;

		/*
		 * Initially turn on all domains to make the domains usable
		 * with !CONFIG_PM and to get the hardware in sync with the
		 * software.  The unused domains will be switched off during
		 * late_init time.
		 */
		genpd->power_on(genpd);

		pm_genpd_init(genpd, NULL, false);
	}

	/*
	 * We are not allowed to fail here since there is no way to unregister
	 * a power domain. Once registered above we have to keep the domains
	 * valid.
	 */

	pd_data = &scp->pd_data;

	ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
	if (ret)
		dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
}

/*
 * MT2701 power domain support
 */

static const struct scp_domain_data scp_domain_data_mt2701[] = {
	[MT2701_POWER_DOMAIN_CONN] = {
		.name = "conn",
		.sta_mask = PWR_STATUS_CONN,
		.ctl_offs = SPM_CONN_PWR_CON,
		.bus_prot_mask = 0x0104,
		.clk_id = {CLK_NONE},
		.active_wakeup = true,
	},
	[MT2701_POWER_DOMAIN_DISP] = {
		.name = "disp",
		.sta_mask = PWR_STATUS_DISP,
		.ctl_offs = SPM_DIS_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.clk_id = {CLK_MM},
		.bus_prot_mask = 0x0002,
		.active_wakeup = true,
	},
	[MT2701_POWER_DOMAIN_MFG] = {
		.name = "mfg",
		.sta_mask = PWR_STATUS_MFG,
		.ctl_offs = SPM_MFG_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(12, 12),
		.clk_id = {CLK_MFG},
		.active_wakeup = true,
	},
	[MT2701_POWER_DOMAIN_VDEC] = {
		.name = "vdec",
		.sta_mask = PWR_STATUS_VDEC,
		.ctl_offs = SPM_VDE_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(12, 12),
		.clk_id = {CLK_MM},
		.active_wakeup = true,
	},
	[MT2701_POWER_DOMAIN_ISP] = {
		.name = "isp",
		.sta_mask = PWR_STATUS_ISP,
		.ctl_offs = SPM_ISP_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(13, 12),
		.clk_id = {CLK_MM},
		.active_wakeup = true,
	},
	[MT2701_POWER_DOMAIN_BDP] = {
		.name = "bdp",
		.sta_mask = PWR_STATUS_BDP,
		.ctl_offs = SPM_BDP_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.clk_id = {CLK_NONE},
		.active_wakeup = true,
	},
	[MT2701_POWER_DOMAIN_ETH] = {
		.name = "eth",
		.sta_mask = PWR_STATUS_ETH,
		.ctl_offs = SPM_ETH_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(15, 12),
		.clk_id = {CLK_ETHIF},
		.active_wakeup = true,
	},
	[MT2701_POWER_DOMAIN_HIF] = {
		.name = "hif",
		.sta_mask = PWR_STATUS_HIF,
		.ctl_offs = SPM_HIF_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(15, 12),
		.clk_id = {CLK_ETHIF},
		.active_wakeup = true,
	},
	[MT2701_POWER_DOMAIN_IFR_MSC] = {
		.name = "ifr_msc",
		.sta_mask = PWR_STATUS_IFR_MSC,
		.ctl_offs = SPM_IFR_MSC_PWR_CON,
		.clk_id = {CLK_NONE},
		.active_wakeup = true,
	},
};

#define NUM_DOMAINS_MT2701	ARRAY_SIZE(scp_domain_data_mt2701)

static int __init scpsys_probe_mt2701(struct platform_device *pdev)
{
	struct scp *scp;

	scp = init_scp(pdev, scp_domain_data_mt2701, NUM_DOMAINS_MT2701);
	if (IS_ERR(scp))
		return PTR_ERR(scp);

	mtk_register_power_domains(pdev, scp, NUM_DOMAINS_MT2701);

	return 0;
}

/*
 * MT8173 power domain support
 */

static const struct scp_domain_data scp_domain_data_mt8173[] = {
	[MT8173_POWER_DOMAIN_VDEC] = {
		.name = "vdec",
		.sta_mask = PWR_STATUS_VDEC,
		.ctl_offs = SPM_VDE_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(12, 12),
		.clk_id = {CLK_MM},
	},
	[MT8173_POWER_DOMAIN_VENC] = {
		.name = "venc",
		.sta_mask = PWR_STATUS_VENC,
		.ctl_offs = SPM_VEN_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(15, 12),
		.clk_id = {CLK_MM, CLK_VENC},
	},
	[MT8173_POWER_DOMAIN_ISP] = {
		.name = "isp",
		.sta_mask = PWR_STATUS_ISP,
		.ctl_offs = SPM_ISP_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(13, 12),
		.clk_id = {CLK_MM},
	},
	[MT8173_POWER_DOMAIN_MM] = {
		.name = "mm",
		.sta_mask = PWR_STATUS_DISP,
		.ctl_offs = SPM_DIS_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(12, 12),
		.clk_id = {CLK_MM},
		.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
			MT8173_TOP_AXI_PROT_EN_MM_M1,
	},
	[MT8173_POWER_DOMAIN_VENC_LT] = {
		.name = "venc_lt",
		.sta_mask = PWR_STATUS_VENC_LT,
		.ctl_offs = SPM_VEN2_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(15, 12),
		.clk_id = {CLK_MM, CLK_VENC_LT},
	},
	[MT8173_POWER_DOMAIN_AUDIO] = {
		.name = "audio",
		.sta_mask = PWR_STATUS_AUDIO,
		.ctl_offs = SPM_AUDIO_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(15, 12),
		.clk_id = {CLK_NONE},
	},
	[MT8173_POWER_DOMAIN_USB] = {
		.name = "usb",
		.sta_mask = PWR_STATUS_USB,
		.ctl_offs = SPM_USB_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(15, 12),
		.clk_id = {CLK_NONE},
		.active_wakeup = true,
	},
	[MT8173_POWER_DOMAIN_MFG_ASYNC] = {
		.name = "mfg_async",
		.sta_mask = PWR_STATUS_MFG_ASYNC,
		.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = 0,
		.clk_id = {CLK_MFG},
	},
	[MT8173_POWER_DOMAIN_MFG_2D] = {
		.name = "mfg_2d",
		.sta_mask = PWR_STATUS_MFG_2D,
		.ctl_offs = SPM_MFG_2D_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(13, 12),
		.clk_id = {CLK_NONE},
	},
	[MT8173_POWER_DOMAIN_MFG] = {
		.name = "mfg",
		.sta_mask = PWR_STATUS_MFG,
		.ctl_offs = SPM_MFG_PWR_CON,
		.sram_pdn_bits = GENMASK(13, 8),
		.sram_pdn_ack_bits = GENMASK(21, 16),
		.clk_id = {CLK_NONE},
		.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
			MT8173_TOP_AXI_PROT_EN_MFG_M0 |
			MT8173_TOP_AXI_PROT_EN_MFG_M1 |
			MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
	},
};

#define NUM_DOMAINS_MT8173	ARRAY_SIZE(scp_domain_data_mt8173)

static int __init scpsys_probe_mt8173(struct platform_device *pdev)
{
	struct scp *scp;
	struct genpd_onecell_data *pd_data;
	int ret;

	scp = init_scp(pdev, scp_domain_data_mt8173, NUM_DOMAINS_MT8173);
	if (IS_ERR(scp))
		return PTR_ERR(scp);

	mtk_register_power_domains(pdev, scp, NUM_DOMAINS_MT8173);

	pd_data = &scp->pd_data;

	ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
		pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
	if (ret && IS_ENABLED(CONFIG_PM))
		dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);

	ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D],
		pd_data->domains[MT8173_POWER_DOMAIN_MFG]);
	if (ret && IS_ENABLED(CONFIG_PM))
		dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);

	return 0;
}

/*
 * scpsys driver init
 */

static const struct of_device_id of_scpsys_match_tbl[] = {
	{
		.compatible = "mediatek,mt2701-scpsys",
		.data = scpsys_probe_mt2701,
	}, {
		.compatible = "mediatek,mt8173-scpsys",
		.data = scpsys_probe_mt8173,
	}, {
		/* sentinel */
	}
};

static int scpsys_probe(struct platform_device *pdev)
{
	int (*probe)(struct platform_device *);
	const struct of_device_id *of_id;

	of_id = of_match_node(of_scpsys_match_tbl, pdev->dev.of_node);
	if (!of_id || !of_id->data)
		return -EINVAL;

	probe = of_id->data;

	return probe(pdev);
}

static struct platform_driver scpsys_drv = {
	.probe = scpsys_probe,
	.driver = {
		.name = "mtk-scpsys",
		.suppress_bind_attrs = true,
		.owner = THIS_MODULE,
		.of_match_table = of_match_ptr(of_scpsys_match_tbl),
	},
};
builtin_platform_driver(scpsys_drv);
Commit	Line	Data
c84e3587 SH	1	/*
	2	* Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13	#include <linux/clk.h>
6078c651	14	#include <linux/init.h>
c84e3587	15	#include <linux/io.h>
c84e3587 SH	16	#include <linux/mfd/syscon.h>
	17	#include <linux/of_device.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/pm_domain.h>
4688f385	20	#include <linux/regulator/consumer.h>
6078c651 JL	21	#include <linux/soc/mediatek/infracfg.h>
6078c651 JL	22
112ef188	23	#include <dt-bindings/power/mt2701-power.h>
c84e3587 SH	24	#include <dt-bindings/power/mt8173-power.h>
	25
	26	#define SPM_VDE_PWR_CON 0x0210
	27	#define SPM_MFG_PWR_CON 0x0214
	28	#define SPM_VEN_PWR_CON 0x0230
	29	#define SPM_ISP_PWR_CON 0x0238
	30	#define SPM_DIS_PWR_CON 0x023c
112ef188	31	#define SPM_CONN_PWR_CON 0x0280
c84e3587	32	#define SPM_VEN2_PWR_CON 0x0298
112ef188 SW	33	#define SPM_AUDIO_PWR_CON 0x029c /* MT8173 */
	34	#define SPM_BDP_PWR_CON 0x029c /* MT2701 */
	35	#define SPM_ETH_PWR_CON 0x02a0
	36	#define SPM_HIF_PWR_CON 0x02a4
	37	#define SPM_IFR_MSC_PWR_CON 0x02a8
c84e3587 SH	38	#define SPM_MFG_2D_PWR_CON 0x02c0
	39	#define SPM_MFG_ASYNC_PWR_CON 0x02c4
	40	#define SPM_USB_PWR_CON 0x02cc
6078c651	41
c84e3587 SH	42	#define SPM_PWR_STATUS 0x060c
	43	#define SPM_PWR_STATUS_2ND 0x0610
	44
	45	#define PWR_RST_B_BIT BIT(0)
	46	#define PWR_ISO_BIT BIT(1)
	47	#define PWR_ON_BIT BIT(2)
	48	#define PWR_ON_2ND_BIT BIT(3)
	49	#define PWR_CLK_DIS_BIT BIT(4)
	50
112ef188	51	#define PWR_STATUS_CONN BIT(1)
c84e3587 SH	52	#define PWR_STATUS_DISP BIT(3)
	53	#define PWR_STATUS_MFG BIT(4)
	54	#define PWR_STATUS_ISP BIT(5)
	55	#define PWR_STATUS_VDEC BIT(7)
112ef188 SW	56	#define PWR_STATUS_BDP BIT(14)
	57	#define PWR_STATUS_ETH BIT(15)
	58	#define PWR_STATUS_HIF BIT(16)
	59	#define PWR_STATUS_IFR_MSC BIT(17)
c84e3587 SH	60	#define PWR_STATUS_VENC_LT BIT(20)
	61	#define PWR_STATUS_VENC BIT(21)
	62	#define PWR_STATUS_MFG_2D BIT(22)
	63	#define PWR_STATUS_MFG_ASYNC BIT(23)
	64	#define PWR_STATUS_AUDIO BIT(24)
	65	#define PWR_STATUS_USB BIT(25)
	66
	67	enum clk_id {
6078c651 JL	68	CLK_NONE,
	69	CLK_MM,
	70	CLK_MFG,
	71	CLK_VENC,
	72	CLK_VENC_LT,
112ef188	73	CLK_ETHIF,
6078c651 JL	74	CLK_MAX,
	75	};
	76
	77	static const char * const clk_names[] = {
	78	NULL,
	79	"mm",
	80	"mfg",
	81	"venc",
	82	"venc_lt",
112ef188	83	"ethif",
6078c651	84	NULL,
c84e3587 SH	85	};
c84e3587 SH	86
41b3e0f0 JL	87	#define MAX_CLKS 2
41b3e0f0 JL	88
c84e3587 SH	89	struct scp_domain_data {
	90	const char *name;
	91	u32 sta_mask;
	92	int ctl_offs;
	93	u32 sram_pdn_bits;
	94	u32 sram_pdn_ack_bits;
	95	u32 bus_prot_mask;
41b3e0f0	96	enum clk_id clk_id[MAX_CLKS];
47e90154	97	bool active_wakeup;
c84e3587 SH	98	};
c84e3587 SH	99
c84e3587 SH	100	struct scp;
	101
	102	struct scp_domain {
	103	struct generic_pm_domain genpd;
	104	struct scp *scp;
41b3e0f0	105	struct clk *clk[MAX_CLKS];
be29523d	106	const struct scp_domain_data *data;
4688f385	107	struct regulator *supply;
c84e3587 SH	108	};
	109
	110	struct scp {
6078c651	111	struct scp_domain *domains;
c84e3587 SH	112	struct genpd_onecell_data pd_data;
	113	struct device *dev;
	114	void __iomem *base;
	115	struct regmap *infracfg;
	116	};
	117
	118	static int scpsys_domain_is_on(struct scp_domain *scpd)
	119	{
	120	struct scp *scp = scpd->scp;
	121
be29523d MB	122	u32 status = readl(scp->base + SPM_PWR_STATUS) & scpd->data->sta_mask;
	123	u32 status2 = readl(scp->base + SPM_PWR_STATUS_2ND) &
	124	scpd->data->sta_mask;
c84e3587 SH	125
	126	/*
	127	* A domain is on when both status bits are set. If only one is set
	128	* return an error. This happens while powering up a domain
	129	*/
	130
	131	if (status && status2)
	132	return true;
	133	if (!status && !status2)
	134	return false;
	135
	136	return -EINVAL;
	137	}
	138
	139	static int scpsys_power_on(struct generic_pm_domain *genpd)
	140	{
	141	struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
	142	struct scp *scp = scpd->scp;
	143	unsigned long timeout;
	144	bool expired;
be29523d MB	145	void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs;
be29523d MB	146	u32 sram_pdn_ack = scpd->data->sram_pdn_ack_bits;
c84e3587 SH	147	u32 val;
c84e3587 SH	148	int ret;
41b3e0f0 JL	149	int i;
41b3e0f0 JL	150
4688f385 SH	151	if (scpd->supply) {
	152	ret = regulator_enable(scpd->supply);
	153	if (ret)
	154	return ret;
	155	}
	156
41b3e0f0 JL	157	for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++) {
	158	ret = clk_prepare_enable(scpd->clk[i]);
	159	if (ret) {
	160	for (--i; i >= 0; i--)
	161	clk_disable_unprepare(scpd->clk[i]);
c84e3587	162
c84e3587	163	goto err_clk;
41b3e0f0	164	}
c84e3587 SH	165	}
	166
	167	val = readl(ctl_addr);
	168	val \|= PWR_ON_BIT;
	169	writel(val, ctl_addr);
	170	val \|= PWR_ON_2ND_BIT;
	171	writel(val, ctl_addr);
	172
	173	/* wait until PWR_ACK = 1 */
	174	timeout = jiffies + HZ;
	175	expired = false;
	176	while (1) {
	177	ret = scpsys_domain_is_on(scpd);
	178	if (ret > 0)
	179	break;
	180
	181	if (expired) {
	182	ret = -ETIMEDOUT;
	183	goto err_pwr_ack;
	184	}
	185
	186	cpu_relax();
	187
	188	if (time_after(jiffies, timeout))
	189	expired = true;
	190	}
	191
	192	val &= ~PWR_CLK_DIS_BIT;
	193	writel(val, ctl_addr);
	194
	195	val &= ~PWR_ISO_BIT;
	196	writel(val, ctl_addr);
	197
	198	val \|= PWR_RST_B_BIT;
	199	writel(val, ctl_addr);
	200
be29523d	201	val &= ~scpd->data->sram_pdn_bits;
c84e3587 SH	202	writel(val, ctl_addr);
	203
	204	/* wait until SRAM_PDN_ACK all 0 */
	205	timeout = jiffies + HZ;
	206	expired = false;
	207	while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {
	208
	209	if (expired) {
	210	ret = -ETIMEDOUT;
	211	goto err_pwr_ack;
	212	}
	213
	214	cpu_relax();
	215
	216	if (time_after(jiffies, timeout))
	217	expired = true;
	218	}
	219
be29523d	220	if (scpd->data->bus_prot_mask) {
c84e3587	221	ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
be29523d	222	scpd->data->bus_prot_mask);
c84e3587 SH	223	if (ret)
	224	goto err_pwr_ack;
	225	}
	226
	227	return 0;
	228
	229	err_pwr_ack:
41b3e0f0 JL	230	for (i = MAX_CLKS - 1; i >= 0; i--) {
	231	if (scpd->clk[i])
	232	clk_disable_unprepare(scpd->clk[i]);
	233	}
c84e3587	234	err_clk:
4688f385 SH	235	if (scpd->supply)
	236	regulator_disable(scpd->supply);
	237
c84e3587 SH	238	dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
	239
	240	return ret;
	241	}
	242
	243	static int scpsys_power_off(struct generic_pm_domain *genpd)
	244	{
	245	struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
	246	struct scp *scp = scpd->scp;
	247	unsigned long timeout;
	248	bool expired;
be29523d MB	249	void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs;
be29523d MB	250	u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
c84e3587 SH	251	u32 val;
c84e3587 SH	252	int ret;
41b3e0f0	253	int i;
c84e3587	254
be29523d	255	if (scpd->data->bus_prot_mask) {
c84e3587	256	ret = mtk_infracfg_set_bus_protection(scp->infracfg,
be29523d	257	scpd->data->bus_prot_mask);
c84e3587 SH	258	if (ret)
	259	goto out;
	260	}
	261
	262	val = readl(ctl_addr);
be29523d	263	val \|= scpd->data->sram_pdn_bits;
c84e3587 SH	264	writel(val, ctl_addr);
	265
	266	/* wait until SRAM_PDN_ACK all 1 */
	267	timeout = jiffies + HZ;
	268	expired = false;
	269	while (pdn_ack && (readl(ctl_addr) & pdn_ack) != pdn_ack) {
	270	if (expired) {
	271	ret = -ETIMEDOUT;
	272	goto out;
	273	}
	274
	275	cpu_relax();
	276
	277	if (time_after(jiffies, timeout))
	278	expired = true;
	279	}
	280
	281	val \|= PWR_ISO_BIT;
	282	writel(val, ctl_addr);
	283
	284	val &= ~PWR_RST_B_BIT;
	285	writel(val, ctl_addr);
	286
	287	val \|= PWR_CLK_DIS_BIT;
	288	writel(val, ctl_addr);
	289
	290	val &= ~PWR_ON_BIT;
	291	writel(val, ctl_addr);
	292
	293	val &= ~PWR_ON_2ND_BIT;
	294	writel(val, ctl_addr);
	295
	296	/* wait until PWR_ACK = 0 */
	297	timeout = jiffies + HZ;
	298	expired = false;
	299	while (1) {
	300	ret = scpsys_domain_is_on(scpd);
	301	if (ret == 0)
	302	break;
	303
	304	if (expired) {
	305	ret = -ETIMEDOUT;
	306	goto out;
	307	}
	308
	309	cpu_relax();
	310
	311	if (time_after(jiffies, timeout))
	312	expired = true;
	313	}
	314
41b3e0f0 JL	315	for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++)
41b3e0f0 JL	316	clk_disable_unprepare(scpd->clk[i]);
c84e3587	317
4688f385 SH	318	if (scpd->supply)
	319	regulator_disable(scpd->supply);
	320
c84e3587 SH	321	return 0;
	322
	323	out:
	324	dev_err(scp->dev, "Failed to power off domain %s\n", genpd->name);
	325
	326	return ret;
	327	}
	328
47e90154 EH	329	static bool scpsys_active_wakeup(struct device *dev)
	330	{
	331	struct generic_pm_domain *genpd;
	332	struct scp_domain *scpd;
	333
	334	genpd = pd_to_genpd(dev->pm_domain);
	335	scpd = container_of(genpd, struct scp_domain, genpd);
	336
be29523d	337	return scpd->data->active_wakeup;
47e90154 EH	338	}
47e90154 EH	339
6078c651 JL	340	static void init_clks(struct platform_device pdev, struct clk *clk)
	341	{
	342	int i;
	343
	344	for (i = CLK_NONE + 1; i < CLK_MAX; i++)
	345	clk[i] = devm_clk_get(&pdev->dev, clk_names[i]);
	346	}
	347
	348	static struct scp init_scp(struct platform_device pdev,
	349	const struct scp_domain_data *scp_domain_data, int num)
c84e3587 SH	350	{
	351	struct genpd_onecell_data *pd_data;
	352	struct resource *res;
6078c651	353	int i, j;
c84e3587	354	struct scp *scp;
6078c651	355	struct clk *clk[CLK_MAX];
c84e3587 SH	356
	357	scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
	358	if (!scp)
6078c651	359	return ERR_PTR(-ENOMEM);
c84e3587 SH	360
	361	scp->dev = &pdev->dev;
	362
	363	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	364	scp->base = devm_ioremap_resource(&pdev->dev, res);
	365	if (IS_ERR(scp->base))
6078c651 JL	366	return ERR_CAST(scp->base);
	367
	368	scp->domains = devm_kzalloc(&pdev->dev,
	369	sizeof(scp->domains) num, GFP_KERNEL);
	370	if (!scp->domains)
	371	return ERR_PTR(-ENOMEM);
c84e3587 SH	372
	373	pd_data = &scp->pd_data;
	374
	375	pd_data->domains = devm_kzalloc(&pdev->dev,
6078c651	376	sizeof(pd_data->domains) num, GFP_KERNEL);
c84e3587	377	if (!pd_data->domains)
6078c651	378	return ERR_PTR(-ENOMEM);
41b3e0f0	379
c84e3587 SH	380	scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
	381	"infracfg");
	382	if (IS_ERR(scp->infracfg)) {
	383	dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
	384	PTR_ERR(scp->infracfg));
6078c651	385	return ERR_CAST(scp->infracfg);
c84e3587 SH	386	}
c84e3587 SH	387
6078c651	388	for (i = 0; i < num; i++) {
4688f385 SH	389	struct scp_domain *scpd = &scp->domains[i];
	390	const struct scp_domain_data *data = &scp_domain_data[i];
	391
	392	scpd->supply = devm_regulator_get_optional(&pdev->dev, data->name);
	393	if (IS_ERR(scpd->supply)) {
	394	if (PTR_ERR(scpd->supply) == -ENODEV)
	395	scpd->supply = NULL;
	396	else
6078c651	397	return ERR_CAST(scpd->supply);
4688f385 SH	398	}
	399	}
	400
6078c651	401	pd_data->num_domains = num;
c84e3587	402
6078c651 JL	403	init_clks(pdev, clk);
	404
	405	for (i = 0; i < num; i++) {
c84e3587 SH	406	struct scp_domain *scpd = &scp->domains[i];
	407	struct generic_pm_domain *genpd = &scpd->genpd;
	408	const struct scp_domain_data *data = &scp_domain_data[i];
	409
	410	pd_data->domains[i] = genpd;
	411	scpd->scp = scp;
	412
be29523d	413	scpd->data = data;
6078c651 JL	414
	415	for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
	416	struct clk *c = clk[data->clk_id[j]];
	417
	418	if (IS_ERR(c)) {
	419	dev_err(&pdev->dev, "%s: clk unavailable\n",
	420	data->name);
	421	return ERR_CAST(c);
	422	}
	423
	424	scpd->clk[j] = c;
	425	}
c84e3587 SH	426
	427	genpd->name = data->name;
	428	genpd->power_off = scpsys_power_off;
	429	genpd->power_on = scpsys_power_on;
47e90154	430	genpd->dev_ops.active_wakeup = scpsys_active_wakeup;
6078c651 JL	431	}
	432
	433	return scp;
	434	}
	435
	436	static void mtk_register_power_domains(struct platform_device *pdev,
	437	struct scp *scp, int num)
	438	{
	439	struct genpd_onecell_data *pd_data;
	440	int i, ret;
	441
	442	for (i = 0; i < num; i++) {
	443	struct scp_domain *scpd = &scp->domains[i];
	444	struct generic_pm_domain *genpd = &scpd->genpd;
c84e3587 SH	445
c84e3587 SH	446	/*
d9c9f3b8 JL	447	* Initially turn on all domains to make the domains usable
	448	* with !CONFIG_PM and to get the hardware in sync with the
	449	* software. The unused domains will be switched off during
	450	* late_init time.
c84e3587	451	*/
d9c9f3b8	452	genpd->power_on(genpd);
c84e3587	453
d9c9f3b8	454	pm_genpd_init(genpd, NULL, false);
c84e3587 SH	455	}
	456
	457	/*
	458	* We are not allowed to fail here since there is no way to unregister
	459	* a power domain. Once registered above we have to keep the domains
	460	* valid.
	461	*/
	462
6078c651 JL	463	pd_data = &scp->pd_data;
	464
	465	ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
	466	if (ret)
	467	dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
	468	}
	469
112ef188 SW	470	/*
	471	* MT2701 power domain support
	472	*/
	473
	474	static const struct scp_domain_data scp_domain_data_mt2701[] = {
	475	[MT2701_POWER_DOMAIN_CONN] = {
	476	.name = "conn",
	477	.sta_mask = PWR_STATUS_CONN,
	478	.ctl_offs = SPM_CONN_PWR_CON,
	479	.bus_prot_mask = 0x0104,
	480	.clk_id = {CLK_NONE},
	481	.active_wakeup = true,
	482	},
	483	[MT2701_POWER_DOMAIN_DISP] = {
	484	.name = "disp",
	485	.sta_mask = PWR_STATUS_DISP,
	486	.ctl_offs = SPM_DIS_PWR_CON,
	487	.sram_pdn_bits = GENMASK(11, 8),
	488	.clk_id = {CLK_MM},
	489	.bus_prot_mask = 0x0002,
	490	.active_wakeup = true,
	491	},
	492	[MT2701_POWER_DOMAIN_MFG] = {
	493	.name = "mfg",
	494	.sta_mask = PWR_STATUS_MFG,
	495	.ctl_offs = SPM_MFG_PWR_CON,
	496	.sram_pdn_bits = GENMASK(11, 8),
	497	.sram_pdn_ack_bits = GENMASK(12, 12),
	498	.clk_id = {CLK_MFG},
	499	.active_wakeup = true,
	500	},
	501	[MT2701_POWER_DOMAIN_VDEC] = {
	502	.name = "vdec",
	503	.sta_mask = PWR_STATUS_VDEC,
	504	.ctl_offs = SPM_VDE_PWR_CON,
	505	.sram_pdn_bits = GENMASK(11, 8),
	506	.sram_pdn_ack_bits = GENMASK(12, 12),
	507	.clk_id = {CLK_MM},
	508	.active_wakeup = true,
	509	},
	510	[MT2701_POWER_DOMAIN_ISP] = {
	511	.name = "isp",
	512	.sta_mask = PWR_STATUS_ISP,
	513	.ctl_offs = SPM_ISP_PWR_CON,
	514	.sram_pdn_bits = GENMASK(11, 8),
	515	.sram_pdn_ack_bits = GENMASK(13, 12),
	516	.clk_id = {CLK_MM},
	517	.active_wakeup = true,
	518	},
	519	[MT2701_POWER_DOMAIN_BDP] = {
	520	.name = "bdp",
	521	.sta_mask = PWR_STATUS_BDP,
	522	.ctl_offs = SPM_BDP_PWR_CON,
	523	.sram_pdn_bits = GENMASK(11, 8),
	524	.clk_id = {CLK_NONE},
	525	.active_wakeup = true,
	526	},
	527	[MT2701_POWER_DOMAIN_ETH] = {
	528	.name = "eth",
	529	.sta_mask = PWR_STATUS_ETH,
	530	.ctl_offs = SPM_ETH_PWR_CON,
	531	.sram_pdn_bits = GENMASK(11, 8),
	532	.sram_pdn_ack_bits = GENMASK(15, 12),
	533	.clk_id = {CLK_ETHIF},
534	.active_wakeup = true,
535	},
536	[MT2701_POWER_DOMAIN_HIF] = {
537	.name = "hif",
538	.sta_mask = PWR_STATUS_HIF,
539	.ctl_offs = SPM_HIF_PWR_CON,
540	.sram_pdn_bits = GENMASK(11, 8),
541	.sram_pdn_ack_bits = GENMASK(15, 12),
542	.clk_id = {CLK_ETHIF},
543	.active_wakeup = true,
544	},
545	[MT2701_POWER_DOMAIN_IFR_MSC] = {
546	.name = "ifr_msc",
547	.sta_mask = PWR_STATUS_IFR_MSC,
548	.ctl_offs = SPM_IFR_MSC_PWR_CON,
549	.clk_id = {CLK_NONE},
550	.active_wakeup = true,
551	},
552	};
553
554	#define NUM_DOMAINS_MT2701 ARRAY_SIZE(scp_domain_data_mt2701)
555
556	static int __init scpsys_probe_mt2701(struct platform_device *pdev)
557	{
558	struct scp *scp;
559
560	scp = init_scp(pdev, scp_domain_data_mt2701, NUM_DOMAINS_MT2701);
561	if (IS_ERR(scp))
562	return PTR_ERR(scp);
563
564	mtk_register_power_domains(pdev, scp, NUM_DOMAINS_MT2701);
565
566	return 0;
567	}
568
6078c651 JL	569	/*
	570	* MT8173 power domain support
	571	*/
	572
	573	static const struct scp_domain_data scp_domain_data_mt8173[] = {
	574	[MT8173_POWER_DOMAIN_VDEC] = {
	575	.name = "vdec",
	576	.sta_mask = PWR_STATUS_VDEC,
	577	.ctl_offs = SPM_VDE_PWR_CON,
	578	.sram_pdn_bits = GENMASK(11, 8),
	579	.sram_pdn_ack_bits = GENMASK(12, 12),
	580	.clk_id = {CLK_MM},
	581	},
	582	[MT8173_POWER_DOMAIN_VENC] = {
	583	.name = "venc",
	584	.sta_mask = PWR_STATUS_VENC,
	585	.ctl_offs = SPM_VEN_PWR_CON,
	586	.sram_pdn_bits = GENMASK(11, 8),
	587	.sram_pdn_ack_bits = GENMASK(15, 12),
	588	.clk_id = {CLK_MM, CLK_VENC},
	589	},
	590	[MT8173_POWER_DOMAIN_ISP] = {
	591	.name = "isp",
	592	.sta_mask = PWR_STATUS_ISP,
	593	.ctl_offs = SPM_ISP_PWR_CON,
	594	.sram_pdn_bits = GENMASK(11, 8),
	595	.sram_pdn_ack_bits = GENMASK(13, 12),
	596	.clk_id = {CLK_MM},
	597	},
	598	[MT8173_POWER_DOMAIN_MM] = {
	599	.name = "mm",
	600	.sta_mask = PWR_STATUS_DISP,
	601	.ctl_offs = SPM_DIS_PWR_CON,
	602	.sram_pdn_bits = GENMASK(11, 8),
	603	.sram_pdn_ack_bits = GENMASK(12, 12),
	604	.clk_id = {CLK_MM},
	605	.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 \|
	606	MT8173_TOP_AXI_PROT_EN_MM_M1,
	607	},
	608	[MT8173_POWER_DOMAIN_VENC_LT] = {
	609	.name = "venc_lt",
	610	.sta_mask = PWR_STATUS_VENC_LT,
	611	.ctl_offs = SPM_VEN2_PWR_CON,
	612	.sram_pdn_bits = GENMASK(11, 8),
	613	.sram_pdn_ack_bits = GENMASK(15, 12),
	614	.clk_id = {CLK_MM, CLK_VENC_LT},
	615	},
	616	[MT8173_POWER_DOMAIN_AUDIO] = {
	617	.name = "audio",
	618	.sta_mask = PWR_STATUS_AUDIO,
	619	.ctl_offs = SPM_AUDIO_PWR_CON,
	620	.sram_pdn_bits = GENMASK(11, 8),
	621	.sram_pdn_ack_bits = GENMASK(15, 12),
	622	.clk_id = {CLK_NONE},
	623	},
	624	[MT8173_POWER_DOMAIN_USB] = {
	625	.name = "usb",
	626	.sta_mask = PWR_STATUS_USB,
	627	.ctl_offs = SPM_USB_PWR_CON,
	628	.sram_pdn_bits = GENMASK(11, 8),
	629	.sram_pdn_ack_bits = GENMASK(15, 12),
	630	.clk_id = {CLK_NONE},
	631	.active_wakeup = true,
	632	},
633	[MT8173_POWER_DOMAIN_MFG_ASYNC] = {
634	.name = "mfg_async",
635	.sta_mask = PWR_STATUS_MFG_ASYNC,
636	.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
637	.sram_pdn_bits = GENMASK(11, 8),
638	.sram_pdn_ack_bits = 0,
639	.clk_id = {CLK_MFG},
640	},
641	[MT8173_POWER_DOMAIN_MFG_2D] = {
642	.name = "mfg_2d",
643	.sta_mask = PWR_STATUS_MFG_2D,
644	.ctl_offs = SPM_MFG_2D_PWR_CON,
645	.sram_pdn_bits = GENMASK(11, 8),
646	.sram_pdn_ack_bits = GENMASK(13, 12),
647	.clk_id = {CLK_NONE},
648	},
649	[MT8173_POWER_DOMAIN_MFG] = {
650	.name = "mfg",
651	.sta_mask = PWR_STATUS_MFG,
652	.ctl_offs = SPM_MFG_PWR_CON,
653	.sram_pdn_bits = GENMASK(13, 8),
654	.sram_pdn_ack_bits = GENMASK(21, 16),
655	.clk_id = {CLK_NONE},
656	.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S \|
657	MT8173_TOP_AXI_PROT_EN_MFG_M0 \|
658	MT8173_TOP_AXI_PROT_EN_MFG_M1 \|
659	MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
660	},
661	};
662
663	#define NUM_DOMAINS_MT8173 ARRAY_SIZE(scp_domain_data_mt8173)
664
665	static int __init scpsys_probe_mt8173(struct platform_device *pdev)
666	{
667	struct scp *scp;
668	struct genpd_onecell_data *pd_data;
669	int ret;
670
671	scp = init_scp(pdev, scp_domain_data_mt8173, NUM_DOMAINS_MT8173);
672	if (IS_ERR(scp))
673	return PTR_ERR(scp);
674
675	mtk_register_power_domains(pdev, scp, NUM_DOMAINS_MT8173);
676
677	pd_data = &scp->pd_data;
678
c84e3587 SH	679	ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
	680	pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
	681	if (ret && IS_ENABLED(CONFIG_PM))
	682	dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
	683
	684	ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D],
	685	pd_data->domains[MT8173_POWER_DOMAIN_MFG]);
	686	if (ret && IS_ENABLED(CONFIG_PM))
	687	dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
	688
c84e3587 SH	689	return 0;
	690	}
	691
6078c651 JL	692	/*
	693	* scpsys driver init
	694	*/
	695
c84e3587 SH	696	static const struct of_device_id of_scpsys_match_tbl[] = {
c84e3587 SH	697	{
112ef188 SW	698	.compatible = "mediatek,mt2701-scpsys",
	699	.data = scpsys_probe_mt2701,
	700	}, {
c84e3587	701	.compatible = "mediatek,mt8173-scpsys",
6078c651	702	.data = scpsys_probe_mt8173,
c84e3587 SH	703	}, {
	704	/* sentinel */
	705	}
	706	};
	707
6078c651 JL	708	static int scpsys_probe(struct platform_device *pdev)
	709	{
	710	int (probe)(struct platform_device );
	711	const struct of_device_id *of_id;
	712
	713	of_id = of_match_node(of_scpsys_match_tbl, pdev->dev.of_node);
	714	if (!of_id \|\| !of_id->data)
	715	return -EINVAL;
	716
	717	probe = of_id->data;
	718
	719	return probe(pdev);
	720	}
	721
c84e3587	722	static struct platform_driver scpsys_drv = {
be29523d	723	.probe = scpsys_probe,
c84e3587 SH	724	.driver = {
c84e3587 SH	725	.name = "mtk-scpsys",
be29523d	726	.suppress_bind_attrs = true,
c84e3587 SH	727	.owner = THIS_MODULE,
	728	.of_match_table = of_match_ptr(of_scpsys_match_tbl),
	729	},
	730	};
be29523d	731	builtin_platform_driver(scpsys_drv);