]>
Commit | Line | Data |
---|---|---|
7d44d2ba | 1 | /* |
14fc8b93 | 2 | * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. |
e28e3014 JL |
3 | * http://www.samsung.com/ |
4 | * | |
7d44d2ba | 5 | * EXYNOS - CPU PMU(Power Management Unit) support |
e28e3014 JL |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
14fc8b93 | 12 | #include <linux/of.h> |
8cfc7fdd | 13 | #include <linux/of_address.h> |
14fc8b93 | 14 | #include <linux/platform_device.h> |
af2e0a07 AK |
15 | #include <linux/delay.h> |
16 | ||
2262d6ef PD |
17 | #include <linux/soc/samsung/exynos-regs-pmu.h> |
18 | #include <linux/soc/samsung/exynos-pmu.h> | |
e28e3014 | 19 | |
c21100c9 | 20 | #include "exynos-pmu.h" |
14fc8b93 PD |
21 | |
22 | struct exynos_pmu_context { | |
23 | struct device *dev; | |
24 | const struct exynos_pmu_data *pmu_data; | |
25 | }; | |
26 | ||
c21100c9 | 27 | void __iomem *pmu_base_addr; |
14fc8b93 | 28 | static struct exynos_pmu_context *pmu_context; |
e28e3014 | 29 | |
c21100c9 | 30 | void pmu_raw_writel(u32 val, u32 offset) |
6b7bfd82 PD |
31 | { |
32 | writel_relaxed(val, pmu_base_addr + offset); | |
33 | } | |
34 | ||
c21100c9 | 35 | u32 pmu_raw_readl(u32 offset) |
6b7bfd82 PD |
36 | { |
37 | return readl_relaxed(pmu_base_addr + offset); | |
38 | } | |
39 | ||
7d44d2ba | 40 | void exynos_sys_powerdown_conf(enum sys_powerdown mode) |
e28e3014 | 41 | { |
0dba4dc4 | 42 | unsigned int i; |
ce36f6ad PD |
43 | const struct exynos_pmu_data *pmu_data; |
44 | ||
45 | if (!pmu_context) | |
46 | return; | |
0dba4dc4 | 47 | |
ce36f6ad | 48 | pmu_data = pmu_context->pmu_data; |
60e49ca6 | 49 | |
14fc8b93 PD |
50 | if (pmu_data->powerdown_conf) |
51 | pmu_data->powerdown_conf(mode); | |
5ddfa842 | 52 | |
14fc8b93 PD |
53 | if (pmu_data->pmu_config) { |
54 | for (i = 0; (pmu_data->pmu_config[i].offset != PMU_TABLE_END); i++) | |
55 | pmu_raw_writel(pmu_data->pmu_config[i].val[mode], | |
56 | pmu_data->pmu_config[i].offset); | |
57 | } | |
58 | ||
8fcc774f BZ |
59 | if (pmu_data->powerdown_conf_extra) |
60 | pmu_data->powerdown_conf_extra(mode); | |
61 | ||
14fc8b93 PD |
62 | if (pmu_data->pmu_config_extra) { |
63 | for (i = 0; pmu_data->pmu_config_extra[i].offset != PMU_TABLE_END; i++) | |
64 | pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode], | |
65 | pmu_data->pmu_config_extra[i].offset); | |
5ddfa842 | 66 | } |
0dba4dc4 JL |
67 | } |
68 | ||
14fc8b93 PD |
69 | /* |
70 | * PMU platform driver and devicetree bindings. | |
71 | */ | |
72 | static const struct of_device_id exynos_pmu_of_device_ids[] = { | |
73 | { | |
8fcc774f BZ |
74 | .compatible = "samsung,exynos3250-pmu", |
75 | .data = &exynos3250_pmu_data, | |
76 | }, { | |
14fc8b93 PD |
77 | .compatible = "samsung,exynos4210-pmu", |
78 | .data = &exynos4210_pmu_data, | |
79 | }, { | |
80 | .compatible = "samsung,exynos4212-pmu", | |
81 | .data = &exynos4212_pmu_data, | |
82 | }, { | |
83 | .compatible = "samsung,exynos4412-pmu", | |
84 | .data = &exynos4412_pmu_data, | |
85 | }, { | |
86 | .compatible = "samsung,exynos5250-pmu", | |
87 | .data = &exynos5250_pmu_data, | |
af2e0a07 AK |
88 | }, { |
89 | .compatible = "samsung,exynos5420-pmu", | |
90 | .data = &exynos5420_pmu_data, | |
14fc8b93 PD |
91 | }, |
92 | { /*sentinel*/ }, | |
93 | }; | |
7d896aac | 94 | |
14fc8b93 PD |
95 | static int exynos_pmu_probe(struct platform_device *pdev) |
96 | { | |
97 | const struct of_device_id *match; | |
98 | struct device *dev = &pdev->dev; | |
99 | struct resource *res; | |
100 | ||
101 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
102 | pmu_base_addr = devm_ioremap_resource(dev, res); | |
103 | if (IS_ERR(pmu_base_addr)) | |
104 | return PTR_ERR(pmu_base_addr); | |
105 | ||
106 | pmu_context = devm_kzalloc(&pdev->dev, | |
107 | sizeof(struct exynos_pmu_context), | |
108 | GFP_KERNEL); | |
109 | if (!pmu_context) { | |
110 | dev_err(dev, "Cannot allocate memory.\n"); | |
111 | return -ENOMEM; | |
00a351f2 | 112 | } |
14fc8b93 PD |
113 | pmu_context->dev = dev; |
114 | ||
115 | match = of_match_node(exynos_pmu_of_device_ids, dev->of_node); | |
116 | ||
117 | pmu_context->pmu_data = match->data; | |
e28e3014 | 118 | |
14fc8b93 PD |
119 | if (pmu_context->pmu_data->pmu_init) |
120 | pmu_context->pmu_data->pmu_init(); | |
121 | ||
122 | platform_set_drvdata(pdev, pmu_context); | |
123 | ||
124 | dev_dbg(dev, "Exynos PMU Driver probe done\n"); | |
0dba4dc4 | 125 | return 0; |
e28e3014 | 126 | } |
14fc8b93 PD |
127 | |
128 | static struct platform_driver exynos_pmu_driver = { | |
129 | .driver = { | |
130 | .name = "exynos-pmu", | |
14fc8b93 PD |
131 | .of_match_table = exynos_pmu_of_device_ids, |
132 | }, | |
133 | .probe = exynos_pmu_probe, | |
134 | }; | |
135 | ||
136 | static int __init exynos_pmu_init(void) | |
137 | { | |
138 | return platform_driver_register(&exynos_pmu_driver); | |
139 | ||
140 | } | |
141 | postcore_initcall(exynos_pmu_init); |