projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 3900d6a8 PD |
1 | /* |
| 2 | * Copyright (c) 2011-2015 Samsung Electronics Co., Ltd. | |
| 3 | * http://www.samsung.com/ | |
| 4 | * | |
| 5 | * EXYNOS5250 - CPU PMU (Power Management Unit) support | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License version 2 as | |
| 9 | * published by the Free Software Foundation. | |
| 10 | */ | |
| 11 | ||
| 12 | #include <linux/soc/samsung/exynos-regs-pmu.h> | |
| 13 | #include <linux/soc/samsung/exynos-pmu.h> | |
| 14 | ||
| 15 | #include "exynos-pmu.h" | |
| 16 | ||
| 17 | static const struct exynos_pmu_conf exynos5250_pmu_config[] = { | |
| 18 | /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */ | |
| 19 | { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, | |
| 20 | { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, | |
| 21 | { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, | |
| 22 | { EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, | |
| 23 | { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, | |
| 24 | { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, | |
| 25 | { EXYNOS5_FSYS_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 26 | { EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, | |
| 27 | { EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 28 | { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, | |
| 29 | { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, | |
| 30 | { EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, | |
| 31 | { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} }, | |
| ee55ae61 | 32 | { EXYNOS_L2_OPTION(0), { 0x10, 0x10, 0x0 } }, |
| 3900d6a8 PD |
33 | { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, |
| 34 | { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, | |
| 35 | { EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, | |
| 36 | { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, | |
| 37 | { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, | |
| 38 | { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, | |
| 39 | { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, | |
| 40 | { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, | |
| 41 | { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, | |
| 42 | { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 43 | { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 44 | { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 45 | { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, | |
| 46 | { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 47 | { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 48 | { EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 49 | { EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 50 | { EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, | |
| 51 | { EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, | |
| 52 | { EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x0, 0x3} }, | |
| 53 | { EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, | |
| 54 | { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, | |
| 55 | { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} }, | |
| 56 | { EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, | |
| 57 | { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, | |
| 58 | { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, | |
| 59 | { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, | |
| 60 | { EXYNOS5_USBOTG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, | |
| 61 | { EXYNOS5_G2D_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, | |
| 62 | { EXYNOS5_USBDRD_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, | |
| 63 | { EXYNOS5_SDMMC_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, | |
| 64 | { EXYNOS5_CSSYS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, | |
| 65 | { EXYNOS5_SECSS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, | |
| 66 | { EXYNOS5_ROTATOR_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, | |
| 67 | { EXYNOS5_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, | |
| 68 | { EXYNOS5_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, | |
| 69 | { EXYNOS5_JPEG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, | |
| 70 | { EXYNOS5_JPEG_MEM_OPTION, { 0x10, 0x10, 0x0} }, | |
| 71 | { EXYNOS5_HSI_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, | |
| 72 | { EXYNOS5_MCUIOP_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, | |
| 73 | { EXYNOS5_SATA_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, | |
| 74 | { EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 75 | { EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, | |
| 76 | { EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 77 | { EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 78 | { EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 79 | { EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 80 | { EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 81 | { EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 82 | { EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 83 | { EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 84 | { EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 85 | { EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 86 | { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 87 | { EXYNOS5_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, | |
| 88 | { EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, | |
| 89 | { EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, | |
| 90 | { EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 91 | { EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 92 | { EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, | |
| 93 | { EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, | |
| 94 | { EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, | |
| 95 | { EXYNOS5_GSCL_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, | |
| 96 | { EXYNOS5_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, | |
| 97 | { EXYNOS5_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, | |
| 98 | { EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, | |
| 99 | { EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, | |
| 100 | { EXYNOS5_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} }, | |
| 101 | { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 102 | { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 103 | { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 104 | { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 105 | { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 106 | { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, | |
| 107 | { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 108 | { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 109 | { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 110 | { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 111 | { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 112 | { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, | |
| 113 | { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 114 | { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 115 | { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 116 | { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 117 | { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, | |
| 118 | { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, | |
| 119 | { PMU_TABLE_END,}, | |
| 120 | }; | |
| 121 | ||
| 122 | static unsigned int const exynos5_list_both_cnt_feed[] = { | |
| 123 | EXYNOS5_ARM_CORE0_OPTION, | |
| 124 | EXYNOS5_ARM_CORE1_OPTION, | |
| 125 | EXYNOS5_ARM_COMMON_OPTION, | |
| 126 | EXYNOS5_GSCL_OPTION, | |
| 127 | EXYNOS5_ISP_OPTION, | |
| 128 | EXYNOS5_MFC_OPTION, | |
| 129 | EXYNOS5_G3D_OPTION, | |
| 130 | EXYNOS5_DISP1_OPTION, | |
| 131 | EXYNOS5_MAU_OPTION, | |
| 132 | EXYNOS5_TOP_PWR_OPTION, | |
| 133 | EXYNOS5_TOP_PWR_SYSMEM_OPTION, | |
| 134 | }; | |
| 135 | ||
| 136 | static unsigned int const exynos5_list_disable_wfi_wfe[] = { | |
| 137 | EXYNOS5_ARM_CORE1_OPTION, | |
| 138 | EXYNOS5_FSYS_ARM_OPTION, | |
| 139 | EXYNOS5_ISP_ARM_OPTION, | |
| 140 | }; | |
| 141 | ||
| 142 | static void exynos5250_pmu_init(void) | |
| 143 | { | |
| 144 | unsigned int value; | |
| 145 | /* | |
| 146 | * When SYS_WDTRESET is set, watchdog timer reset request | |
| 147 | * is ignored by power management unit. | |
| 148 | */ | |
| 149 | value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE); | |
| 150 | value &= ~EXYNOS5_SYS_WDTRESET; | |
| 151 | pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE); | |
| 152 | ||
| 153 | value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST); | |
| 154 | value &= ~EXYNOS5_SYS_WDTRESET; | |
| 155 | pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); | |
| 156 | } | |
| 157 | ||
| 158 | static void exynos5_powerdown_conf(enum sys_powerdown mode) | |
| 159 | { | |
| 160 | unsigned int i; | |
| 161 | unsigned int tmp; | |
| 162 | ||
| 163 | /* | |
| 164 | * Enable both SC_FEEDBACK and SC_COUNTER | |
| 165 | */ | |
| 166 | for (i = 0; i < ARRAY_SIZE(exynos5_list_both_cnt_feed); i++) { | |
| 167 | tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]); | |
| 168 | tmp |= (EXYNOS5_USE_SC_FEEDBACK | | |
| 169 | EXYNOS5_USE_SC_COUNTER); | |
| 170 | pmu_raw_writel(tmp, exynos5_list_both_cnt_feed[i]); | |
| 171 | } | |
| 172 | ||
| 173 | /* | |
| 174 | * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable | |
| 175 | */ | |
| 176 | tmp = pmu_raw_readl(EXYNOS5_ARM_COMMON_OPTION); | |
| 177 | tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN; | |
| 178 | pmu_raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION); | |
| 179 | ||
| 180 | /* | |
| 181 | * Disable WFI/WFE on XXX_OPTION | |
| 182 | */ | |
| 183 | for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_wfi_wfe); i++) { | |
| 184 | tmp = pmu_raw_readl(exynos5_list_disable_wfi_wfe[i]); | |
| 185 | tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE | | |
| 186 | EXYNOS5_OPTION_USE_STANDBYWFI); | |
| 187 | pmu_raw_writel(tmp, exynos5_list_disable_wfi_wfe[i]); | |
| 188 | } | |
| 189 | } | |
| 190 | ||
| 191 | const struct exynos_pmu_data exynos5250_pmu_data = { | |
| 192 | .pmu_config = exynos5250_pmu_config, | |
| 193 | .pmu_init = exynos5250_pmu_init, | |
| 194 | .powerdown_conf = exynos5_powerdown_conf, | |
| 195 | }; |