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Commit | Line | Data |
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7232398a TR |
1 | /* |
2 | * drivers/soc/tegra/pmc.c | |
3 | * | |
4 | * Copyright (c) 2010 Google, Inc | |
5 | * | |
6 | * Author: | |
7 | * Colin Cross <ccross@google.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
7d71e903 TR |
20 | #define pr_fmt(fmt) "tegra-pmc: " fmt |
21 | ||
7232398a TR |
22 | #include <linux/kernel.h> |
23 | #include <linux/clk.h> | |
24 | #include <linux/clk/tegra.h> | |
25 | #include <linux/debugfs.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/err.h> | |
28 | #include <linux/export.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/io.h> | |
0a2d87e0 | 31 | #include <linux/iopoll.h> |
7232398a TR |
32 | #include <linux/of.h> |
33 | #include <linux/of_address.h> | |
a3804512 | 34 | #include <linux/of_platform.h> |
7232398a | 35 | #include <linux/platform_device.h> |
a3804512 | 36 | #include <linux/pm_domain.h> |
7232398a TR |
37 | #include <linux/reboot.h> |
38 | #include <linux/reset.h> | |
39 | #include <linux/seq_file.h> | |
a3804512 | 40 | #include <linux/slab.h> |
7232398a TR |
41 | #include <linux/spinlock.h> |
42 | ||
43 | #include <soc/tegra/common.h> | |
44 | #include <soc/tegra/fuse.h> | |
45 | #include <soc/tegra/pmc.h> | |
46 | ||
47 | #define PMC_CNTRL 0x0 | |
6c0bd217 | 48 | #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ |
95b780b3 TR |
49 | #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ |
50 | #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ | |
51 | #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ | |
52 | #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ | |
53 | #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ | |
54 | #define PMC_CNTRL_MAIN_RST BIT(4) | |
7232398a TR |
55 | |
56 | #define DPD_SAMPLE 0x020 | |
6c0bd217 | 57 | #define DPD_SAMPLE_ENABLE BIT(0) |
7232398a TR |
58 | #define DPD_SAMPLE_DISABLE (0 << 0) |
59 | ||
60 | #define PWRGATE_TOGGLE 0x30 | |
6c0bd217 | 61 | #define PWRGATE_TOGGLE_START BIT(8) |
7232398a TR |
62 | |
63 | #define REMOVE_CLAMPING 0x34 | |
64 | ||
65 | #define PWRGATE_STATUS 0x38 | |
66 | ||
21b49910 LD |
67 | #define PMC_PWR_DET 0x48 |
68 | ||
7232398a | 69 | #define PMC_SCRATCH0 0x50 |
6c0bd217 LD |
70 | #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) |
71 | #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) | |
72 | #define PMC_SCRATCH0_MODE_RCM BIT(1) | |
7232398a TR |
73 | #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ |
74 | PMC_SCRATCH0_MODE_BOOTLOADER | \ | |
75 | PMC_SCRATCH0_MODE_RCM) | |
76 | ||
77 | #define PMC_CPUPWRGOOD_TIMER 0xc8 | |
78 | #define PMC_CPUPWROFF_TIMER 0xcc | |
79 | ||
21b49910 LD |
80 | #define PMC_PWR_DET_VALUE 0xe4 |
81 | ||
7232398a TR |
82 | #define PMC_SCRATCH41 0x140 |
83 | ||
3568df3d | 84 | #define PMC_SENSOR_CTRL 0x1b0 |
6c0bd217 LD |
85 | #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) |
86 | #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) | |
3568df3d | 87 | |
f5353c60 TR |
88 | #define PMC_RST_STATUS 0x1b4 |
89 | #define PMC_RST_STATUS_POR 0 | |
90 | #define PMC_RST_STATUS_WATCHDOG 1 | |
91 | #define PMC_RST_STATUS_SENSOR 2 | |
92 | #define PMC_RST_STATUS_SW_MAIN 3 | |
93 | #define PMC_RST_STATUS_LP0 4 | |
94 | #define PMC_RST_STATUS_AOTAG 5 | |
95 | ||
7232398a | 96 | #define IO_DPD_REQ 0x1b8 |
6c0bd217 LD |
97 | #define IO_DPD_REQ_CODE_IDLE (0U << 30) |
98 | #define IO_DPD_REQ_CODE_OFF (1U << 30) | |
99 | #define IO_DPD_REQ_CODE_ON (2U << 30) | |
100 | #define IO_DPD_REQ_CODE_MASK (3U << 30) | |
7232398a TR |
101 | |
102 | #define IO_DPD_STATUS 0x1bc | |
103 | #define IO_DPD2_REQ 0x1c0 | |
104 | #define IO_DPD2_STATUS 0x1c4 | |
105 | #define SEL_DPD_TIM 0x1c8 | |
106 | ||
3568df3d | 107 | #define PMC_SCRATCH54 0x258 |
6c0bd217 LD |
108 | #define PMC_SCRATCH54_DATA_SHIFT 8 |
109 | #define PMC_SCRATCH54_ADDR_SHIFT 0 | |
3568df3d MP |
110 | |
111 | #define PMC_SCRATCH55 0x25c | |
6c0bd217 LD |
112 | #define PMC_SCRATCH55_RESET_TEGRA BIT(31) |
113 | #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 | |
114 | #define PMC_SCRATCH55_PINMUX_SHIFT 24 | |
115 | #define PMC_SCRATCH55_16BITOP BIT(15) | |
116 | #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 | |
117 | #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 | |
3568df3d | 118 | |
7232398a TR |
119 | #define GPU_RG_CNTRL 0x2d4 |
120 | ||
a3804512 JH |
121 | struct tegra_powergate { |
122 | struct generic_pm_domain genpd; | |
123 | struct tegra_pmc *pmc; | |
124 | unsigned int id; | |
125 | struct clk **clks; | |
126 | unsigned int num_clks; | |
127 | struct reset_control **resets; | |
128 | unsigned int num_resets; | |
129 | }; | |
130 | ||
21b49910 LD |
131 | struct tegra_io_pad_soc { |
132 | enum tegra_io_pad id; | |
133 | unsigned int dpd; | |
134 | unsigned int voltage; | |
135 | }; | |
136 | ||
7232398a TR |
137 | struct tegra_pmc_soc { |
138 | unsigned int num_powergates; | |
139 | const char *const *powergates; | |
140 | unsigned int num_cpu_powergates; | |
141 | const u8 *cpu_powergates; | |
a9a40a4a | 142 | |
3568df3d | 143 | bool has_tsense_reset; |
a9a40a4a | 144 | bool has_gpu_clamps; |
21b49910 LD |
145 | |
146 | const struct tegra_io_pad_soc *io_pads; | |
147 | unsigned int num_io_pads; | |
7232398a TR |
148 | }; |
149 | ||
150 | /** | |
151 | * struct tegra_pmc - NVIDIA Tegra PMC | |
35b67291 | 152 | * @dev: pointer to PMC device structure |
7232398a TR |
153 | * @base: pointer to I/O remapped register region |
154 | * @clk: pointer to pclk clock | |
35b67291 | 155 | * @soc: pointer to SoC data structure |
3195ac6d | 156 | * @debugfs: pointer to debugfs entry |
7232398a TR |
157 | * @rate: currently configured rate of pclk |
158 | * @suspend_mode: lowest suspend mode available | |
159 | * @cpu_good_time: CPU power good time (in microseconds) | |
160 | * @cpu_off_time: CPU power off time (in microsecends) | |
161 | * @core_osc_time: core power good OSC time (in microseconds) | |
162 | * @core_pmu_time: core power good PMU time (in microseconds) | |
163 | * @core_off_time: core power off time (in microseconds) | |
164 | * @corereq_high: core power request is active-high | |
165 | * @sysclkreq_high: system clock request is active-high | |
166 | * @combined_req: combined power request for CPU & core | |
167 | * @cpu_pwr_good_en: CPU power good signal is enabled | |
168 | * @lp0_vec_phys: physical base address of the LP0 warm boot code | |
169 | * @lp0_vec_size: size of the LP0 warm boot code | |
a3804512 | 170 | * @powergates_available: Bitmap of available power gates |
7232398a TR |
171 | * @powergates_lock: mutex for power gate register access |
172 | */ | |
173 | struct tegra_pmc { | |
3568df3d | 174 | struct device *dev; |
7232398a TR |
175 | void __iomem *base; |
176 | struct clk *clk; | |
3195ac6d | 177 | struct dentry *debugfs; |
7232398a TR |
178 | |
179 | const struct tegra_pmc_soc *soc; | |
180 | ||
181 | unsigned long rate; | |
182 | ||
183 | enum tegra_suspend_mode suspend_mode; | |
184 | u32 cpu_good_time; | |
185 | u32 cpu_off_time; | |
186 | u32 core_osc_time; | |
187 | u32 core_pmu_time; | |
188 | u32 core_off_time; | |
189 | bool corereq_high; | |
190 | bool sysclkreq_high; | |
191 | bool combined_req; | |
192 | bool cpu_pwr_good_en; | |
193 | u32 lp0_vec_phys; | |
194 | u32 lp0_vec_size; | |
a3804512 | 195 | DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); |
7232398a TR |
196 | |
197 | struct mutex powergates_lock; | |
198 | }; | |
199 | ||
200 | static struct tegra_pmc *pmc = &(struct tegra_pmc) { | |
201 | .base = NULL, | |
202 | .suspend_mode = TEGRA_SUSPEND_NONE, | |
203 | }; | |
204 | ||
a3804512 JH |
205 | static inline struct tegra_powergate * |
206 | to_powergate(struct generic_pm_domain *domain) | |
207 | { | |
208 | return container_of(domain, struct tegra_powergate, genpd); | |
209 | } | |
210 | ||
7232398a TR |
211 | static u32 tegra_pmc_readl(unsigned long offset) |
212 | { | |
213 | return readl(pmc->base + offset); | |
214 | } | |
215 | ||
216 | static void tegra_pmc_writel(u32 value, unsigned long offset) | |
217 | { | |
218 | writel(value, pmc->base + offset); | |
219 | } | |
220 | ||
0ecf2d33 JH |
221 | static inline bool tegra_powergate_state(int id) |
222 | { | |
bc9af23d JH |
223 | if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) |
224 | return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0; | |
225 | else | |
226 | return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0; | |
0ecf2d33 JH |
227 | } |
228 | ||
0a243bd4 JH |
229 | static inline bool tegra_powergate_is_valid(int id) |
230 | { | |
231 | return (pmc->soc && pmc->soc->powergates[id]); | |
232 | } | |
233 | ||
a3804512 JH |
234 | static inline bool tegra_powergate_is_available(int id) |
235 | { | |
236 | return test_bit(id, pmc->powergates_available); | |
237 | } | |
238 | ||
239 | static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) | |
240 | { | |
241 | unsigned int i; | |
242 | ||
243 | if (!pmc || !pmc->soc || !name) | |
244 | return -EINVAL; | |
245 | ||
246 | for (i = 0; i < pmc->soc->num_powergates; i++) { | |
247 | if (!tegra_powergate_is_valid(i)) | |
248 | continue; | |
249 | ||
250 | if (!strcmp(name, pmc->soc->powergates[i])) | |
251 | return i; | |
252 | } | |
253 | ||
a3804512 JH |
254 | return -ENODEV; |
255 | } | |
256 | ||
7232398a TR |
257 | /** |
258 | * tegra_powergate_set() - set the state of a partition | |
259 | * @id: partition ID | |
260 | * @new_state: new state of the partition | |
261 | */ | |
70293ed0 | 262 | static int tegra_powergate_set(unsigned int id, bool new_state) |
7232398a | 263 | { |
0a2d87e0 JH |
264 | bool status; |
265 | int err; | |
266 | ||
bc9af23d JH |
267 | if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) |
268 | return -EINVAL; | |
269 | ||
7232398a TR |
270 | mutex_lock(&pmc->powergates_lock); |
271 | ||
0ecf2d33 | 272 | if (tegra_powergate_state(id) == new_state) { |
7232398a TR |
273 | mutex_unlock(&pmc->powergates_lock); |
274 | return 0; | |
275 | } | |
276 | ||
277 | tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); | |
278 | ||
0a2d87e0 JH |
279 | err = readx_poll_timeout(tegra_powergate_state, id, status, |
280 | status == new_state, 10, 100000); | |
281 | ||
7232398a TR |
282 | mutex_unlock(&pmc->powergates_lock); |
283 | ||
0a2d87e0 | 284 | return err; |
7232398a TR |
285 | } |
286 | ||
a3804512 JH |
287 | static int __tegra_powergate_remove_clamping(unsigned int id) |
288 | { | |
289 | u32 mask; | |
290 | ||
291 | mutex_lock(&pmc->powergates_lock); | |
292 | ||
293 | /* | |
294 | * On Tegra124 and later, the clamps for the GPU are controlled by a | |
295 | * separate register (with different semantics). | |
296 | */ | |
297 | if (id == TEGRA_POWERGATE_3D) { | |
298 | if (pmc->soc->has_gpu_clamps) { | |
299 | tegra_pmc_writel(0, GPU_RG_CNTRL); | |
300 | goto out; | |
301 | } | |
302 | } | |
303 | ||
304 | /* | |
305 | * Tegra 2 has a bug where PCIE and VDE clamping masks are | |
306 | * swapped relatively to the partition ids | |
307 | */ | |
308 | if (id == TEGRA_POWERGATE_VDEC) | |
309 | mask = (1 << TEGRA_POWERGATE_PCIE); | |
310 | else if (id == TEGRA_POWERGATE_PCIE) | |
311 | mask = (1 << TEGRA_POWERGATE_VDEC); | |
312 | else | |
313 | mask = (1 << id); | |
314 | ||
315 | tegra_pmc_writel(mask, REMOVE_CLAMPING); | |
316 | ||
317 | out: | |
318 | mutex_unlock(&pmc->powergates_lock); | |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
323 | static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) | |
324 | { | |
325 | unsigned int i; | |
326 | ||
327 | for (i = 0; i < pg->num_clks; i++) | |
328 | clk_disable_unprepare(pg->clks[i]); | |
329 | } | |
330 | ||
331 | static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) | |
332 | { | |
333 | unsigned int i; | |
334 | int err; | |
335 | ||
336 | for (i = 0; i < pg->num_clks; i++) { | |
337 | err = clk_prepare_enable(pg->clks[i]); | |
338 | if (err) | |
339 | goto out; | |
340 | } | |
341 | ||
342 | return 0; | |
343 | ||
344 | out: | |
345 | while (i--) | |
346 | clk_disable_unprepare(pg->clks[i]); | |
347 | ||
348 | return err; | |
349 | } | |
350 | ||
351 | static int tegra_powergate_reset_assert(struct tegra_powergate *pg) | |
352 | { | |
353 | unsigned int i; | |
354 | int err; | |
355 | ||
356 | for (i = 0; i < pg->num_resets; i++) { | |
357 | err = reset_control_assert(pg->resets[i]); | |
358 | if (err) | |
359 | return err; | |
360 | } | |
361 | ||
362 | return 0; | |
363 | } | |
364 | ||
365 | static int tegra_powergate_reset_deassert(struct tegra_powergate *pg) | |
366 | { | |
367 | unsigned int i; | |
368 | int err; | |
369 | ||
370 | for (i = 0; i < pg->num_resets; i++) { | |
371 | err = reset_control_deassert(pg->resets[i]); | |
372 | if (err) | |
373 | return err; | |
374 | } | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
379 | static int tegra_powergate_power_up(struct tegra_powergate *pg, | |
380 | bool disable_clocks) | |
381 | { | |
382 | int err; | |
383 | ||
384 | err = tegra_powergate_reset_assert(pg); | |
385 | if (err) | |
386 | return err; | |
387 | ||
388 | usleep_range(10, 20); | |
389 | ||
390 | err = tegra_powergate_set(pg->id, true); | |
391 | if (err < 0) | |
392 | return err; | |
393 | ||
394 | usleep_range(10, 20); | |
395 | ||
396 | err = tegra_powergate_enable_clocks(pg); | |
397 | if (err) | |
398 | goto disable_clks; | |
399 | ||
400 | usleep_range(10, 20); | |
401 | ||
402 | err = __tegra_powergate_remove_clamping(pg->id); | |
403 | if (err) | |
404 | goto disable_clks; | |
405 | ||
406 | usleep_range(10, 20); | |
407 | ||
408 | err = tegra_powergate_reset_deassert(pg); | |
409 | if (err) | |
410 | goto powergate_off; | |
411 | ||
412 | usleep_range(10, 20); | |
413 | ||
414 | if (disable_clocks) | |
415 | tegra_powergate_disable_clocks(pg); | |
416 | ||
417 | return 0; | |
418 | ||
419 | disable_clks: | |
420 | tegra_powergate_disable_clocks(pg); | |
421 | usleep_range(10, 20); | |
da8f4b45 | 422 | |
a3804512 JH |
423 | powergate_off: |
424 | tegra_powergate_set(pg->id, false); | |
425 | ||
426 | return err; | |
427 | } | |
428 | ||
429 | static int tegra_powergate_power_down(struct tegra_powergate *pg) | |
430 | { | |
431 | int err; | |
432 | ||
433 | err = tegra_powergate_enable_clocks(pg); | |
434 | if (err) | |
435 | return err; | |
436 | ||
437 | usleep_range(10, 20); | |
438 | ||
439 | err = tegra_powergate_reset_assert(pg); | |
440 | if (err) | |
441 | goto disable_clks; | |
442 | ||
443 | usleep_range(10, 20); | |
444 | ||
445 | tegra_powergate_disable_clocks(pg); | |
446 | ||
447 | usleep_range(10, 20); | |
448 | ||
449 | err = tegra_powergate_set(pg->id, false); | |
450 | if (err) | |
451 | goto assert_resets; | |
452 | ||
453 | return 0; | |
454 | ||
455 | assert_resets: | |
456 | tegra_powergate_enable_clocks(pg); | |
457 | usleep_range(10, 20); | |
458 | tegra_powergate_reset_deassert(pg); | |
459 | usleep_range(10, 20); | |
da8f4b45 | 460 | |
a3804512 JH |
461 | disable_clks: |
462 | tegra_powergate_disable_clocks(pg); | |
463 | ||
464 | return err; | |
465 | } | |
466 | ||
467 | static int tegra_genpd_power_on(struct generic_pm_domain *domain) | |
468 | { | |
469 | struct tegra_powergate *pg = to_powergate(domain); | |
a3804512 JH |
470 | int err; |
471 | ||
472 | err = tegra_powergate_power_up(pg, true); | |
473 | if (err) | |
54e24721 TR |
474 | pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name, |
475 | err); | |
a3804512 JH |
476 | |
477 | return err; | |
478 | } | |
479 | ||
480 | static int tegra_genpd_power_off(struct generic_pm_domain *domain) | |
481 | { | |
482 | struct tegra_powergate *pg = to_powergate(domain); | |
a3804512 JH |
483 | int err; |
484 | ||
485 | err = tegra_powergate_power_down(pg); | |
486 | if (err) | |
54e24721 TR |
487 | pr_err("failed to turn off PM domain %s: %d\n", |
488 | pg->genpd.name, err); | |
a3804512 JH |
489 | |
490 | return err; | |
491 | } | |
492 | ||
7232398a TR |
493 | /** |
494 | * tegra_powergate_power_on() - power on partition | |
495 | * @id: partition ID | |
496 | */ | |
70293ed0 | 497 | int tegra_powergate_power_on(unsigned int id) |
7232398a | 498 | { |
a3804512 | 499 | if (!tegra_powergate_is_available(id)) |
7232398a TR |
500 | return -EINVAL; |
501 | ||
502 | return tegra_powergate_set(id, true); | |
503 | } | |
504 | ||
505 | /** | |
506 | * tegra_powergate_power_off() - power off partition | |
507 | * @id: partition ID | |
508 | */ | |
70293ed0 | 509 | int tegra_powergate_power_off(unsigned int id) |
7232398a | 510 | { |
a3804512 | 511 | if (!tegra_powergate_is_available(id)) |
7232398a TR |
512 | return -EINVAL; |
513 | ||
514 | return tegra_powergate_set(id, false); | |
515 | } | |
516 | EXPORT_SYMBOL(tegra_powergate_power_off); | |
517 | ||
518 | /** | |
519 | * tegra_powergate_is_powered() - check if partition is powered | |
520 | * @id: partition ID | |
521 | */ | |
70293ed0 | 522 | int tegra_powergate_is_powered(unsigned int id) |
7232398a | 523 | { |
0ecf2d33 | 524 | int status; |
7232398a | 525 | |
0a243bd4 | 526 | if (!tegra_powergate_is_valid(id)) |
7232398a TR |
527 | return -EINVAL; |
528 | ||
e8cf6616 | 529 | mutex_lock(&pmc->powergates_lock); |
0ecf2d33 | 530 | status = tegra_powergate_state(id); |
e8cf6616 JH |
531 | mutex_unlock(&pmc->powergates_lock); |
532 | ||
0ecf2d33 | 533 | return status; |
7232398a TR |
534 | } |
535 | ||
536 | /** | |
537 | * tegra_powergate_remove_clamping() - remove power clamps for partition | |
538 | * @id: partition ID | |
539 | */ | |
70293ed0 | 540 | int tegra_powergate_remove_clamping(unsigned int id) |
7232398a | 541 | { |
a3804512 | 542 | if (!tegra_powergate_is_available(id)) |
7232398a TR |
543 | return -EINVAL; |
544 | ||
a3804512 | 545 | return __tegra_powergate_remove_clamping(id); |
7232398a TR |
546 | } |
547 | EXPORT_SYMBOL(tegra_powergate_remove_clamping); | |
548 | ||
549 | /** | |
550 | * tegra_powergate_sequence_power_up() - power up partition | |
551 | * @id: partition ID | |
552 | * @clk: clock for partition | |
553 | * @rst: reset for partition | |
554 | * | |
555 | * Must be called with clk disabled, and returns with clk enabled. | |
556 | */ | |
70293ed0 | 557 | int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, |
7232398a TR |
558 | struct reset_control *rst) |
559 | { | |
a3804512 JH |
560 | struct tegra_powergate pg; |
561 | int err; | |
7232398a | 562 | |
403db2d2 JH |
563 | if (!tegra_powergate_is_available(id)) |
564 | return -EINVAL; | |
565 | ||
a3804512 JH |
566 | pg.id = id; |
567 | pg.clks = &clk; | |
568 | pg.num_clks = 1; | |
569 | pg.resets = &rst; | |
570 | pg.num_resets = 1; | |
7232398a | 571 | |
a3804512 JH |
572 | err = tegra_powergate_power_up(&pg, false); |
573 | if (err) | |
574 | pr_err("failed to turn on partition %d: %d\n", id, err); | |
7232398a | 575 | |
a3804512 | 576 | return err; |
7232398a TR |
577 | } |
578 | EXPORT_SYMBOL(tegra_powergate_sequence_power_up); | |
579 | ||
580 | #ifdef CONFIG_SMP | |
581 | /** | |
582 | * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID | |
583 | * @cpuid: CPU partition ID | |
584 | * | |
585 | * Returns the partition ID corresponding to the CPU partition ID or a | |
586 | * negative error code on failure. | |
587 | */ | |
70293ed0 | 588 | static int tegra_get_cpu_powergate_id(unsigned int cpuid) |
7232398a | 589 | { |
70293ed0 | 590 | if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) |
7232398a TR |
591 | return pmc->soc->cpu_powergates[cpuid]; |
592 | ||
593 | return -EINVAL; | |
594 | } | |
595 | ||
596 | /** | |
597 | * tegra_pmc_cpu_is_powered() - check if CPU partition is powered | |
598 | * @cpuid: CPU partition ID | |
599 | */ | |
70293ed0 | 600 | bool tegra_pmc_cpu_is_powered(unsigned int cpuid) |
7232398a TR |
601 | { |
602 | int id; | |
603 | ||
604 | id = tegra_get_cpu_powergate_id(cpuid); | |
605 | if (id < 0) | |
606 | return false; | |
607 | ||
608 | return tegra_powergate_is_powered(id); | |
609 | } | |
610 | ||
611 | /** | |
612 | * tegra_pmc_cpu_power_on() - power on CPU partition | |
613 | * @cpuid: CPU partition ID | |
614 | */ | |
70293ed0 | 615 | int tegra_pmc_cpu_power_on(unsigned int cpuid) |
7232398a TR |
616 | { |
617 | int id; | |
618 | ||
619 | id = tegra_get_cpu_powergate_id(cpuid); | |
620 | if (id < 0) | |
621 | return id; | |
622 | ||
623 | return tegra_powergate_set(id, true); | |
624 | } | |
625 | ||
626 | /** | |
627 | * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition | |
628 | * @cpuid: CPU partition ID | |
629 | */ | |
70293ed0 | 630 | int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) |
7232398a TR |
631 | { |
632 | int id; | |
633 | ||
634 | id = tegra_get_cpu_powergate_id(cpuid); | |
635 | if (id < 0) | |
636 | return id; | |
637 | ||
638 | return tegra_powergate_remove_clamping(id); | |
639 | } | |
640 | #endif /* CONFIG_SMP */ | |
641 | ||
7892158a DR |
642 | static int tegra_pmc_restart_notify(struct notifier_block *this, |
643 | unsigned long action, void *data) | |
7232398a | 644 | { |
7892158a | 645 | const char *cmd = data; |
7232398a TR |
646 | u32 value; |
647 | ||
648 | value = tegra_pmc_readl(PMC_SCRATCH0); | |
649 | value &= ~PMC_SCRATCH0_MODE_MASK; | |
650 | ||
651 | if (cmd) { | |
652 | if (strcmp(cmd, "recovery") == 0) | |
653 | value |= PMC_SCRATCH0_MODE_RECOVERY; | |
654 | ||
655 | if (strcmp(cmd, "bootloader") == 0) | |
656 | value |= PMC_SCRATCH0_MODE_BOOTLOADER; | |
657 | ||
658 | if (strcmp(cmd, "forced-recovery") == 0) | |
659 | value |= PMC_SCRATCH0_MODE_RCM; | |
660 | } | |
661 | ||
662 | tegra_pmc_writel(value, PMC_SCRATCH0); | |
663 | ||
f5353c60 TR |
664 | /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ |
665 | value = tegra_pmc_readl(PMC_CNTRL); | |
666 | value |= PMC_CNTRL_MAIN_RST; | |
667 | tegra_pmc_writel(value, PMC_CNTRL); | |
7892158a DR |
668 | |
669 | return NOTIFY_DONE; | |
7232398a TR |
670 | } |
671 | ||
7892158a DR |
672 | static struct notifier_block tegra_pmc_restart_handler = { |
673 | .notifier_call = tegra_pmc_restart_notify, | |
674 | .priority = 128, | |
675 | }; | |
676 | ||
7232398a TR |
677 | static int powergate_show(struct seq_file *s, void *data) |
678 | { | |
679 | unsigned int i; | |
c3ea2972 | 680 | int status; |
7232398a TR |
681 | |
682 | seq_printf(s, " powergate powered\n"); | |
683 | seq_printf(s, "------------------\n"); | |
684 | ||
685 | for (i = 0; i < pmc->soc->num_powergates; i++) { | |
c3ea2972 JH |
686 | status = tegra_powergate_is_powered(i); |
687 | if (status < 0) | |
7232398a TR |
688 | continue; |
689 | ||
690 | seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], | |
c3ea2972 | 691 | status ? "yes" : "no"); |
7232398a TR |
692 | } |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
697 | static int powergate_open(struct inode *inode, struct file *file) | |
698 | { | |
699 | return single_open(file, powergate_show, inode->i_private); | |
700 | } | |
701 | ||
702 | static const struct file_operations powergate_fops = { | |
703 | .open = powergate_open, | |
704 | .read = seq_read, | |
705 | .llseek = seq_lseek, | |
706 | .release = single_release, | |
707 | }; | |
708 | ||
709 | static int tegra_powergate_debugfs_init(void) | |
710 | { | |
3195ac6d JH |
711 | pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, |
712 | &powergate_fops); | |
713 | if (!pmc->debugfs) | |
7232398a TR |
714 | return -ENOMEM; |
715 | ||
716 | return 0; | |
717 | } | |
718 | ||
a3804512 JH |
719 | static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, |
720 | struct device_node *np) | |
721 | { | |
722 | struct clk *clk; | |
723 | unsigned int i, count; | |
724 | int err; | |
725 | ||
726 | count = of_count_phandle_with_args(np, "clocks", "#clock-cells"); | |
727 | if (count == 0) | |
728 | return -ENODEV; | |
729 | ||
730 | pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); | |
731 | if (!pg->clks) | |
732 | return -ENOMEM; | |
733 | ||
734 | for (i = 0; i < count; i++) { | |
735 | pg->clks[i] = of_clk_get(np, i); | |
736 | if (IS_ERR(pg->clks[i])) { | |
737 | err = PTR_ERR(pg->clks[i]); | |
738 | goto err; | |
739 | } | |
740 | } | |
741 | ||
742 | pg->num_clks = count; | |
743 | ||
744 | return 0; | |
745 | ||
746 | err: | |
747 | while (i--) | |
748 | clk_put(pg->clks[i]); | |
da8f4b45 | 749 | |
a3804512 JH |
750 | kfree(pg->clks); |
751 | ||
752 | return err; | |
753 | } | |
754 | ||
755 | static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, | |
05cfb988 | 756 | struct device_node *np, bool off) |
a3804512 JH |
757 | { |
758 | struct reset_control *rst; | |
759 | unsigned int i, count; | |
760 | int err; | |
761 | ||
762 | count = of_count_phandle_with_args(np, "resets", "#reset-cells"); | |
763 | if (count == 0) | |
764 | return -ENODEV; | |
765 | ||
766 | pg->resets = kcalloc(count, sizeof(rst), GFP_KERNEL); | |
767 | if (!pg->resets) | |
768 | return -ENOMEM; | |
769 | ||
770 | for (i = 0; i < count; i++) { | |
771 | pg->resets[i] = of_reset_control_get_by_index(np, i); | |
772 | if (IS_ERR(pg->resets[i])) { | |
773 | err = PTR_ERR(pg->resets[i]); | |
774 | goto error; | |
775 | } | |
05cfb988 JH |
776 | |
777 | if (off) | |
778 | err = reset_control_assert(pg->resets[i]); | |
779 | else | |
780 | err = reset_control_deassert(pg->resets[i]); | |
781 | ||
782 | if (err) { | |
783 | reset_control_put(pg->resets[i]); | |
784 | goto error; | |
785 | } | |
a3804512 JH |
786 | } |
787 | ||
788 | pg->num_resets = count; | |
789 | ||
790 | return 0; | |
791 | ||
792 | error: | |
793 | while (i--) | |
794 | reset_control_put(pg->resets[i]); | |
da8f4b45 | 795 | |
a3804512 JH |
796 | kfree(pg->resets); |
797 | ||
798 | return err; | |
799 | } | |
800 | ||
801 | static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) | |
802 | { | |
803 | struct tegra_powergate *pg; | |
c2710ac9 | 804 | int id, err; |
a3804512 | 805 | bool off; |
a3804512 JH |
806 | |
807 | pg = kzalloc(sizeof(*pg), GFP_KERNEL); | |
808 | if (!pg) | |
c2710ac9 | 809 | return; |
a3804512 JH |
810 | |
811 | id = tegra_powergate_lookup(pmc, np->name); | |
c2710ac9 | 812 | if (id < 0) { |
54e24721 | 813 | pr_err("powergate lookup failed for %s: %d\n", np->name, id); |
a3804512 | 814 | goto free_mem; |
c2710ac9 | 815 | } |
a3804512 JH |
816 | |
817 | /* | |
818 | * Clear the bit for this powergate so it cannot be managed | |
819 | * directly via the legacy APIs for controlling powergates. | |
820 | */ | |
821 | clear_bit(id, pmc->powergates_available); | |
822 | ||
823 | pg->id = id; | |
824 | pg->genpd.name = np->name; | |
825 | pg->genpd.power_off = tegra_genpd_power_off; | |
826 | pg->genpd.power_on = tegra_genpd_power_on; | |
827 | pg->pmc = pmc; | |
828 | ||
05cfb988 JH |
829 | off = !tegra_powergate_is_powered(pg->id); |
830 | ||
c2710ac9 JH |
831 | err = tegra_powergate_of_get_clks(pg, np); |
832 | if (err < 0) { | |
54e24721 | 833 | pr_err("failed to get clocks for %s: %d\n", np->name, err); |
a3804512 | 834 | goto set_available; |
c2710ac9 | 835 | } |
a3804512 | 836 | |
c2710ac9 JH |
837 | err = tegra_powergate_of_get_resets(pg, np, off); |
838 | if (err < 0) { | |
54e24721 | 839 | pr_err("failed to get resets for %s: %d\n", np->name, err); |
a3804512 | 840 | goto remove_clks; |
c2710ac9 | 841 | } |
a3804512 | 842 | |
0b137340 JH |
843 | if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { |
844 | if (off) | |
845 | WARN_ON(tegra_powergate_power_up(pg, true)); | |
846 | ||
847 | goto remove_resets; | |
848 | } | |
e2d17960 | 849 | |
8df12745 JH |
850 | /* |
851 | * FIXME: If XHCI is enabled for Tegra, then power-up the XUSB | |
852 | * host and super-speed partitions. Once the XHCI driver | |
853 | * manages the partitions itself this code can be removed. Note | |
854 | * that we don't register these partitions with the genpd core | |
855 | * to avoid it from powering down the partitions as they appear | |
856 | * to be unused. | |
857 | */ | |
858 | if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) && | |
0b137340 JH |
859 | (id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC)) { |
860 | if (off) | |
861 | WARN_ON(tegra_powergate_power_up(pg, true)); | |
862 | ||
863 | goto remove_resets; | |
864 | } | |
8df12745 | 865 | |
cd5ceda2 JH |
866 | err = pm_genpd_init(&pg->genpd, NULL, off); |
867 | if (err < 0) { | |
45221120 | 868 | pr_err("failed to initialise PM domain %s: %d\n", np->name, |
cd5ceda2 JH |
869 | err); |
870 | goto remove_resets; | |
871 | } | |
a3804512 | 872 | |
c2710ac9 JH |
873 | err = of_genpd_add_provider_simple(np, &pg->genpd); |
874 | if (err < 0) { | |
45221120 TR |
875 | pr_err("failed to add PM domain provider for %s: %d\n", |
876 | np->name, err); | |
0b137340 | 877 | goto remove_genpd; |
c2710ac9 | 878 | } |
a3804512 | 879 | |
45221120 | 880 | pr_debug("added PM domain %s\n", pg->genpd.name); |
a3804512 JH |
881 | |
882 | return; | |
883 | ||
0b137340 JH |
884 | remove_genpd: |
885 | pm_genpd_remove(&pg->genpd); | |
e2d17960 | 886 | |
a3804512 JH |
887 | remove_resets: |
888 | while (pg->num_resets--) | |
889 | reset_control_put(pg->resets[pg->num_resets]); | |
da8f4b45 | 890 | |
a3804512 JH |
891 | kfree(pg->resets); |
892 | ||
893 | remove_clks: | |
894 | while (pg->num_clks--) | |
895 | clk_put(pg->clks[pg->num_clks]); | |
da8f4b45 | 896 | |
a3804512 JH |
897 | kfree(pg->clks); |
898 | ||
899 | set_available: | |
900 | set_bit(id, pmc->powergates_available); | |
901 | ||
902 | free_mem: | |
903 | kfree(pg); | |
a3804512 JH |
904 | } |
905 | ||
e2d17960 JH |
906 | static void tegra_powergate_init(struct tegra_pmc *pmc, |
907 | struct device_node *parent) | |
a3804512 JH |
908 | { |
909 | struct device_node *np, *child; | |
e2d17960 | 910 | unsigned int i; |
a3804512 | 911 | |
e2d17960 JH |
912 | /* Create a bitmap of the available and valid partitions */ |
913 | for (i = 0; i < pmc->soc->num_powergates; i++) | |
914 | if (pmc->soc->powergates[i]) | |
915 | set_bit(i, pmc->powergates_available); | |
916 | ||
917 | np = of_get_child_by_name(parent, "powergates"); | |
a3804512 JH |
918 | if (!np) |
919 | return; | |
920 | ||
921 | for_each_child_of_node(np, child) { | |
922 | tegra_powergate_add(pmc, child); | |
923 | of_node_put(child); | |
924 | } | |
925 | ||
926 | of_node_put(np); | |
927 | } | |
928 | ||
21b49910 LD |
929 | static const struct tegra_io_pad_soc * |
930 | tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) | |
931 | { | |
932 | unsigned int i; | |
933 | ||
934 | for (i = 0; i < pmc->soc->num_io_pads; i++) | |
935 | if (pmc->soc->io_pads[i].id == id) | |
936 | return &pmc->soc->io_pads[i]; | |
937 | ||
938 | return NULL; | |
939 | } | |
940 | ||
941 | static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request, | |
27b12b4e | 942 | unsigned long *status, u32 *mask) |
7232398a | 943 | { |
21b49910 | 944 | const struct tegra_io_pad_soc *pad; |
7232398a | 945 | unsigned long rate, value; |
7232398a | 946 | |
21b49910 | 947 | pad = tegra_io_pad_find(pmc, id); |
54e24721 TR |
948 | if (!pad) { |
949 | pr_err("invalid I/O pad ID %u\n", id); | |
21b49910 | 950 | return -ENOENT; |
54e24721 | 951 | } |
7232398a | 952 | |
21b49910 LD |
953 | if (pad->dpd == UINT_MAX) |
954 | return -ENOTSUPP; | |
7232398a | 955 | |
27b12b4e | 956 | *mask = BIT(pad->dpd % 32); |
21b49910 LD |
957 | |
958 | if (pad->dpd < 32) { | |
7232398a TR |
959 | *status = IO_DPD_STATUS; |
960 | *request = IO_DPD_REQ; | |
961 | } else { | |
962 | *status = IO_DPD2_STATUS; | |
963 | *request = IO_DPD2_REQ; | |
964 | } | |
965 | ||
592431b0 | 966 | rate = clk_get_rate(pmc->clk); |
54e24721 TR |
967 | if (!rate) { |
968 | pr_err("failed to get clock rate\n"); | |
f4392d6d | 969 | return -ENODEV; |
54e24721 | 970 | } |
7232398a TR |
971 | |
972 | tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE); | |
973 | ||
974 | /* must be at least 200 ns, in APB (PCLK) clock cycles */ | |
975 | value = DIV_ROUND_UP(1000000000, rate); | |
976 | value = DIV_ROUND_UP(200, value); | |
977 | tegra_pmc_writel(value, SEL_DPD_TIM); | |
978 | ||
979 | return 0; | |
980 | } | |
981 | ||
21b49910 LD |
982 | static int tegra_io_pad_poll(unsigned long offset, u32 mask, |
983 | u32 val, unsigned long timeout) | |
7232398a | 984 | { |
84cf85ea | 985 | u32 value; |
7232398a TR |
986 | |
987 | timeout = jiffies + msecs_to_jiffies(timeout); | |
988 | ||
989 | while (time_after(timeout, jiffies)) { | |
990 | value = tegra_pmc_readl(offset); | |
991 | if ((value & mask) == val) | |
992 | return 0; | |
993 | ||
994 | usleep_range(250, 1000); | |
995 | } | |
996 | ||
997 | return -ETIMEDOUT; | |
998 | } | |
999 | ||
21b49910 | 1000 | static void tegra_io_pad_unprepare(void) |
7232398a TR |
1001 | { |
1002 | tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE); | |
1003 | } | |
1004 | ||
21b49910 LD |
1005 | /** |
1006 | * tegra_io_pad_power_enable() - enable power to I/O pad | |
1007 | * @id: Tegra I/O pad ID for which to enable power | |
1008 | * | |
1009 | * Returns: 0 on success or a negative error code on failure. | |
1010 | */ | |
1011 | int tegra_io_pad_power_enable(enum tegra_io_pad id) | |
7232398a | 1012 | { |
a9ccc123 | 1013 | unsigned long request, status; |
27b12b4e | 1014 | u32 mask; |
7232398a TR |
1015 | int err; |
1016 | ||
e8cf6616 JH |
1017 | mutex_lock(&pmc->powergates_lock); |
1018 | ||
27b12b4e | 1019 | err = tegra_io_pad_prepare(id, &request, &status, &mask); |
21b49910 | 1020 | if (err < 0) { |
54e24721 | 1021 | pr_err("failed to prepare I/O pad: %d\n", err); |
21b49910 LD |
1022 | goto unlock; |
1023 | } | |
7232398a | 1024 | |
27b12b4e | 1025 | tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | mask, request); |
7232398a | 1026 | |
27b12b4e | 1027 | err = tegra_io_pad_poll(status, mask, 0, 250); |
21b49910 | 1028 | if (err < 0) { |
54e24721 | 1029 | pr_err("failed to enable I/O pad: %d\n", err); |
21b49910 | 1030 | goto unlock; |
592431b0 | 1031 | } |
7232398a | 1032 | |
21b49910 | 1033 | tegra_io_pad_unprepare(); |
7232398a | 1034 | |
21b49910 | 1035 | unlock: |
e8cf6616 | 1036 | mutex_unlock(&pmc->powergates_lock); |
e8cf6616 | 1037 | return err; |
7232398a | 1038 | } |
21b49910 | 1039 | EXPORT_SYMBOL(tegra_io_pad_power_enable); |
7232398a | 1040 | |
21b49910 LD |
1041 | /** |
1042 | * tegra_io_pad_power_disable() - disable power to I/O pad | |
1043 | * @id: Tegra I/O pad ID for which to disable power | |
1044 | * | |
1045 | * Returns: 0 on success or a negative error code on failure. | |
1046 | */ | |
1047 | int tegra_io_pad_power_disable(enum tegra_io_pad id) | |
7232398a | 1048 | { |
a9ccc123 | 1049 | unsigned long request, status; |
27b12b4e | 1050 | u32 mask; |
7232398a TR |
1051 | int err; |
1052 | ||
e8cf6616 JH |
1053 | mutex_lock(&pmc->powergates_lock); |
1054 | ||
27b12b4e | 1055 | err = tegra_io_pad_prepare(id, &request, &status, &mask); |
21b49910 | 1056 | if (err < 0) { |
54e24721 | 1057 | pr_err("failed to prepare I/O pad: %d\n", err); |
21b49910 | 1058 | goto unlock; |
592431b0 | 1059 | } |
7232398a | 1060 | |
27b12b4e | 1061 | tegra_pmc_writel(IO_DPD_REQ_CODE_ON | mask, request); |
7232398a | 1062 | |
27b12b4e | 1063 | err = tegra_io_pad_poll(status, mask, mask, 250); |
21b49910 | 1064 | if (err < 0) { |
54e24721 | 1065 | pr_err("failed to disable I/O pad: %d\n", err); |
21b49910 LD |
1066 | goto unlock; |
1067 | } | |
7232398a | 1068 | |
21b49910 | 1069 | tegra_io_pad_unprepare(); |
7232398a | 1070 | |
21b49910 | 1071 | unlock: |
e8cf6616 | 1072 | mutex_unlock(&pmc->powergates_lock); |
e8cf6616 | 1073 | return err; |
7232398a | 1074 | } |
21b49910 LD |
1075 | EXPORT_SYMBOL(tegra_io_pad_power_disable); |
1076 | ||
1077 | int tegra_io_pad_set_voltage(enum tegra_io_pad id, | |
1078 | enum tegra_io_pad_voltage voltage) | |
1079 | { | |
1080 | const struct tegra_io_pad_soc *pad; | |
1081 | u32 value; | |
1082 | ||
1083 | pad = tegra_io_pad_find(pmc, id); | |
1084 | if (!pad) | |
1085 | return -ENOENT; | |
1086 | ||
1087 | if (pad->voltage == UINT_MAX) | |
1088 | return -ENOTSUPP; | |
1089 | ||
1090 | mutex_lock(&pmc->powergates_lock); | |
1091 | ||
1092 | /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ | |
1093 | value = tegra_pmc_readl(PMC_PWR_DET); | |
1094 | value |= BIT(pad->voltage); | |
1095 | tegra_pmc_writel(value, PMC_PWR_DET); | |
1096 | ||
1097 | /* update I/O voltage */ | |
1098 | value = tegra_pmc_readl(PMC_PWR_DET_VALUE); | |
1099 | ||
1100 | if (voltage == TEGRA_IO_PAD_1800000UV) | |
1101 | value &= ~BIT(pad->voltage); | |
1102 | else | |
1103 | value |= BIT(pad->voltage); | |
1104 | ||
1105 | tegra_pmc_writel(value, PMC_PWR_DET_VALUE); | |
1106 | ||
1107 | mutex_unlock(&pmc->powergates_lock); | |
1108 | ||
1109 | usleep_range(100, 250); | |
1110 | ||
1111 | return 0; | |
1112 | } | |
1113 | EXPORT_SYMBOL(tegra_io_pad_set_voltage); | |
1114 | ||
1115 | int tegra_io_pad_get_voltage(enum tegra_io_pad id) | |
1116 | { | |
1117 | const struct tegra_io_pad_soc *pad; | |
1118 | u32 value; | |
1119 | ||
1120 | pad = tegra_io_pad_find(pmc, id); | |
1121 | if (!pad) | |
1122 | return -ENOENT; | |
1123 | ||
1124 | if (pad->voltage == UINT_MAX) | |
1125 | return -ENOTSUPP; | |
1126 | ||
1127 | value = tegra_pmc_readl(PMC_PWR_DET_VALUE); | |
1128 | ||
1129 | if ((value & BIT(pad->voltage)) == 0) | |
1130 | return TEGRA_IO_PAD_1800000UV; | |
1131 | ||
1132 | return TEGRA_IO_PAD_3300000UV; | |
1133 | } | |
1134 | EXPORT_SYMBOL(tegra_io_pad_get_voltage); | |
1135 | ||
1136 | /** | |
1137 | * tegra_io_rail_power_on() - enable power to I/O rail | |
1138 | * @id: Tegra I/O pad ID for which to enable power | |
1139 | * | |
1140 | * See also: tegra_io_pad_power_enable() | |
1141 | */ | |
1142 | int tegra_io_rail_power_on(unsigned int id) | |
1143 | { | |
1144 | return tegra_io_pad_power_enable(id); | |
1145 | } | |
1146 | EXPORT_SYMBOL(tegra_io_rail_power_on); | |
1147 | ||
1148 | /** | |
1149 | * tegra_io_rail_power_off() - disable power to I/O rail | |
1150 | * @id: Tegra I/O pad ID for which to disable power | |
1151 | * | |
1152 | * See also: tegra_io_pad_power_disable() | |
1153 | */ | |
1154 | int tegra_io_rail_power_off(unsigned int id) | |
1155 | { | |
1156 | return tegra_io_pad_power_disable(id); | |
1157 | } | |
7232398a TR |
1158 | EXPORT_SYMBOL(tegra_io_rail_power_off); |
1159 | ||
1160 | #ifdef CONFIG_PM_SLEEP | |
1161 | enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) | |
1162 | { | |
1163 | return pmc->suspend_mode; | |
1164 | } | |
1165 | ||
1166 | void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) | |
1167 | { | |
1168 | if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) | |
1169 | return; | |
1170 | ||
1171 | pmc->suspend_mode = mode; | |
1172 | } | |
1173 | ||
1174 | void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) | |
1175 | { | |
1176 | unsigned long long rate = 0; | |
1177 | u32 value; | |
1178 | ||
1179 | switch (mode) { | |
1180 | case TEGRA_SUSPEND_LP1: | |
1181 | rate = 32768; | |
1182 | break; | |
1183 | ||
1184 | case TEGRA_SUSPEND_LP2: | |
1185 | rate = clk_get_rate(pmc->clk); | |
1186 | break; | |
1187 | ||
1188 | default: | |
1189 | break; | |
1190 | } | |
1191 | ||
1192 | if (WARN_ON_ONCE(rate == 0)) | |
1193 | rate = 100000000; | |
1194 | ||
1195 | if (rate != pmc->rate) { | |
1196 | u64 ticks; | |
1197 | ||
1198 | ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; | |
1199 | do_div(ticks, USEC_PER_SEC); | |
1200 | tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER); | |
1201 | ||
1202 | ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; | |
1203 | do_div(ticks, USEC_PER_SEC); | |
1204 | tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER); | |
1205 | ||
1206 | wmb(); | |
1207 | ||
1208 | pmc->rate = rate; | |
1209 | } | |
1210 | ||
1211 | value = tegra_pmc_readl(PMC_CNTRL); | |
1212 | value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; | |
1213 | value |= PMC_CNTRL_CPU_PWRREQ_OE; | |
1214 | tegra_pmc_writel(value, PMC_CNTRL); | |
1215 | } | |
1216 | #endif | |
1217 | ||
1218 | static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) | |
1219 | { | |
1220 | u32 value, values[2]; | |
1221 | ||
1222 | if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { | |
1223 | } else { | |
1224 | switch (value) { | |
1225 | case 0: | |
1226 | pmc->suspend_mode = TEGRA_SUSPEND_LP0; | |
1227 | break; | |
1228 | ||
1229 | case 1: | |
1230 | pmc->suspend_mode = TEGRA_SUSPEND_LP1; | |
1231 | break; | |
1232 | ||
1233 | case 2: | |
1234 | pmc->suspend_mode = TEGRA_SUSPEND_LP2; | |
1235 | break; | |
1236 | ||
1237 | default: | |
1238 | pmc->suspend_mode = TEGRA_SUSPEND_NONE; | |
1239 | break; | |
1240 | } | |
1241 | } | |
1242 | ||
1243 | pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); | |
1244 | ||
1245 | if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) | |
1246 | pmc->suspend_mode = TEGRA_SUSPEND_NONE; | |
1247 | ||
1248 | pmc->cpu_good_time = value; | |
1249 | ||
1250 | if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) | |
1251 | pmc->suspend_mode = TEGRA_SUSPEND_NONE; | |
1252 | ||
1253 | pmc->cpu_off_time = value; | |
1254 | ||
1255 | if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", | |
1256 | values, ARRAY_SIZE(values))) | |
1257 | pmc->suspend_mode = TEGRA_SUSPEND_NONE; | |
1258 | ||
1259 | pmc->core_osc_time = values[0]; | |
1260 | pmc->core_pmu_time = values[1]; | |
1261 | ||
1262 | if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) | |
1263 | pmc->suspend_mode = TEGRA_SUSPEND_NONE; | |
1264 | ||
1265 | pmc->core_off_time = value; | |
1266 | ||
1267 | pmc->corereq_high = of_property_read_bool(np, | |
1268 | "nvidia,core-power-req-active-high"); | |
1269 | ||
1270 | pmc->sysclkreq_high = of_property_read_bool(np, | |
1271 | "nvidia,sys-clock-req-active-high"); | |
1272 | ||
1273 | pmc->combined_req = of_property_read_bool(np, | |
1274 | "nvidia,combined-power-req"); | |
1275 | ||
1276 | pmc->cpu_pwr_good_en = of_property_read_bool(np, | |
1277 | "nvidia,cpu-pwr-good-en"); | |
1278 | ||
1279 | if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, | |
1280 | ARRAY_SIZE(values))) | |
1281 | if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) | |
1282 | pmc->suspend_mode = TEGRA_SUSPEND_LP1; | |
1283 | ||
1284 | pmc->lp0_vec_phys = values[0]; | |
1285 | pmc->lp0_vec_size = values[1]; | |
1286 | ||
1287 | return 0; | |
1288 | } | |
1289 | ||
1290 | static void tegra_pmc_init(struct tegra_pmc *pmc) | |
1291 | { | |
1292 | u32 value; | |
1293 | ||
1294 | /* Always enable CPU power request */ | |
1295 | value = tegra_pmc_readl(PMC_CNTRL); | |
1296 | value |= PMC_CNTRL_CPU_PWRREQ_OE; | |
1297 | tegra_pmc_writel(value, PMC_CNTRL); | |
1298 | ||
1299 | value = tegra_pmc_readl(PMC_CNTRL); | |
1300 | ||
1301 | if (pmc->sysclkreq_high) | |
1302 | value &= ~PMC_CNTRL_SYSCLK_POLARITY; | |
1303 | else | |
1304 | value |= PMC_CNTRL_SYSCLK_POLARITY; | |
1305 | ||
1306 | /* configure the output polarity while the request is tristated */ | |
1307 | tegra_pmc_writel(value, PMC_CNTRL); | |
1308 | ||
1309 | /* now enable the request */ | |
1310 | value = tegra_pmc_readl(PMC_CNTRL); | |
1311 | value |= PMC_CNTRL_SYSCLK_OE; | |
1312 | tegra_pmc_writel(value, PMC_CNTRL); | |
1313 | } | |
1314 | ||
1e52efdf | 1315 | static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) |
3568df3d MP |
1316 | { |
1317 | static const char disabled[] = "emergency thermal reset disabled"; | |
1318 | u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; | |
1319 | struct device *dev = pmc->dev; | |
1320 | struct device_node *np; | |
1321 | u32 value, checksum; | |
1322 | ||
1323 | if (!pmc->soc->has_tsense_reset) | |
95169cd2 | 1324 | return; |
3568df3d MP |
1325 | |
1326 | np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip"); | |
1327 | if (!np) { | |
1328 | dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); | |
95169cd2 | 1329 | return; |
3568df3d MP |
1330 | } |
1331 | ||
1332 | if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { | |
1333 | dev_err(dev, "I2C controller ID missing, %s.\n", disabled); | |
1334 | goto out; | |
1335 | } | |
1336 | ||
1337 | if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { | |
1338 | dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); | |
1339 | goto out; | |
1340 | } | |
1341 | ||
1342 | if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { | |
1343 | dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); | |
1344 | goto out; | |
1345 | } | |
1346 | ||
1347 | if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { | |
1348 | dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); | |
1349 | goto out; | |
1350 | } | |
1351 | ||
1352 | if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) | |
1353 | pinmux = 0; | |
1354 | ||
1355 | value = tegra_pmc_readl(PMC_SENSOR_CTRL); | |
1356 | value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; | |
1357 | tegra_pmc_writel(value, PMC_SENSOR_CTRL); | |
1358 | ||
1359 | value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | | |
1360 | (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); | |
1361 | tegra_pmc_writel(value, PMC_SCRATCH54); | |
1362 | ||
1363 | value = PMC_SCRATCH55_RESET_TEGRA; | |
1364 | value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; | |
1365 | value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; | |
1366 | value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; | |
1367 | ||
1368 | /* | |
1369 | * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will | |
1370 | * contain the checksum and are currently zero, so they are not added. | |
1371 | */ | |
1372 | checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) | |
1373 | + ((value >> 24) & 0xff); | |
1374 | checksum &= 0xff; | |
1375 | checksum = 0x100 - checksum; | |
1376 | ||
1377 | value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; | |
1378 | ||
1379 | tegra_pmc_writel(value, PMC_SCRATCH55); | |
1380 | ||
1381 | value = tegra_pmc_readl(PMC_SENSOR_CTRL); | |
1382 | value |= PMC_SENSOR_CTRL_ENABLE_RST; | |
1383 | tegra_pmc_writel(value, PMC_SENSOR_CTRL); | |
1384 | ||
1385 | dev_info(pmc->dev, "emergency thermal reset enabled\n"); | |
1386 | ||
1387 | out: | |
1388 | of_node_put(np); | |
3568df3d MP |
1389 | } |
1390 | ||
7232398a TR |
1391 | static int tegra_pmc_probe(struct platform_device *pdev) |
1392 | { | |
e8cf6616 | 1393 | void __iomem *base; |
7232398a TR |
1394 | struct resource *res; |
1395 | int err; | |
1396 | ||
a83f1fc3 JH |
1397 | /* |
1398 | * Early initialisation should have configured an initial | |
1399 | * register mapping and setup the soc data pointer. If these | |
1400 | * are not valid then something went badly wrong! | |
1401 | */ | |
1402 | if (WARN_ON(!pmc->base || !pmc->soc)) | |
1403 | return -ENODEV; | |
1404 | ||
7232398a TR |
1405 | err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); |
1406 | if (err < 0) | |
1407 | return err; | |
1408 | ||
1409 | /* take over the memory region from the early initialization */ | |
1410 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
0259f522 JH |
1411 | base = devm_ioremap_resource(&pdev->dev, res); |
1412 | if (IS_ERR(base)) | |
1413 | return PTR_ERR(base); | |
7232398a TR |
1414 | |
1415 | pmc->clk = devm_clk_get(&pdev->dev, "pclk"); | |
1416 | if (IS_ERR(pmc->clk)) { | |
1417 | err = PTR_ERR(pmc->clk); | |
1418 | dev_err(&pdev->dev, "failed to get pclk: %d\n", err); | |
1419 | return err; | |
1420 | } | |
1421 | ||
3568df3d MP |
1422 | pmc->dev = &pdev->dev; |
1423 | ||
7232398a TR |
1424 | tegra_pmc_init(pmc); |
1425 | ||
3568df3d MP |
1426 | tegra_pmc_init_tsense_reset(pmc); |
1427 | ||
7232398a TR |
1428 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
1429 | err = tegra_powergate_debugfs_init(); | |
1430 | if (err < 0) | |
1431 | return err; | |
7892158a DR |
1432 | } |
1433 | ||
1434 | err = register_restart_handler(&tegra_pmc_restart_handler); | |
1435 | if (err) { | |
3195ac6d | 1436 | debugfs_remove(pmc->debugfs); |
7892158a DR |
1437 | dev_err(&pdev->dev, "unable to register restart handler, %d\n", |
1438 | err); | |
1439 | return err; | |
7232398a TR |
1440 | } |
1441 | ||
e8cf6616 JH |
1442 | mutex_lock(&pmc->powergates_lock); |
1443 | iounmap(pmc->base); | |
0259f522 | 1444 | pmc->base = base; |
e8cf6616 | 1445 | mutex_unlock(&pmc->powergates_lock); |
0259f522 | 1446 | |
7232398a TR |
1447 | return 0; |
1448 | } | |
1449 | ||
2b20b616 | 1450 | #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) |
7232398a TR |
1451 | static int tegra_pmc_suspend(struct device *dev) |
1452 | { | |
1453 | tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); | |
1454 | ||
1455 | return 0; | |
1456 | } | |
1457 | ||
1458 | static int tegra_pmc_resume(struct device *dev) | |
1459 | { | |
1460 | tegra_pmc_writel(0x0, PMC_SCRATCH41); | |
1461 | ||
1462 | return 0; | |
1463 | } | |
7232398a TR |
1464 | |
1465 | static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); | |
1466 | ||
2b20b616 PW |
1467 | #endif |
1468 | ||
7232398a TR |
1469 | static const char * const tegra20_powergates[] = { |
1470 | [TEGRA_POWERGATE_CPU] = "cpu", | |
1471 | [TEGRA_POWERGATE_3D] = "3d", | |
1472 | [TEGRA_POWERGATE_VENC] = "venc", | |
1473 | [TEGRA_POWERGATE_VDEC] = "vdec", | |
1474 | [TEGRA_POWERGATE_PCIE] = "pcie", | |
1475 | [TEGRA_POWERGATE_L2] = "l2", | |
1476 | [TEGRA_POWERGATE_MPE] = "mpe", | |
1477 | }; | |
1478 | ||
1479 | static const struct tegra_pmc_soc tegra20_pmc_soc = { | |
1480 | .num_powergates = ARRAY_SIZE(tegra20_powergates), | |
1481 | .powergates = tegra20_powergates, | |
1482 | .num_cpu_powergates = 0, | |
1483 | .cpu_powergates = NULL, | |
3568df3d | 1484 | .has_tsense_reset = false, |
a9a40a4a | 1485 | .has_gpu_clamps = false, |
7232398a TR |
1486 | }; |
1487 | ||
1488 | static const char * const tegra30_powergates[] = { | |
1489 | [TEGRA_POWERGATE_CPU] = "cpu0", | |
1490 | [TEGRA_POWERGATE_3D] = "3d0", | |
1491 | [TEGRA_POWERGATE_VENC] = "venc", | |
1492 | [TEGRA_POWERGATE_VDEC] = "vdec", | |
1493 | [TEGRA_POWERGATE_PCIE] = "pcie", | |
1494 | [TEGRA_POWERGATE_L2] = "l2", | |
1495 | [TEGRA_POWERGATE_MPE] = "mpe", | |
1496 | [TEGRA_POWERGATE_HEG] = "heg", | |
1497 | [TEGRA_POWERGATE_SATA] = "sata", | |
1498 | [TEGRA_POWERGATE_CPU1] = "cpu1", | |
1499 | [TEGRA_POWERGATE_CPU2] = "cpu2", | |
1500 | [TEGRA_POWERGATE_CPU3] = "cpu3", | |
1501 | [TEGRA_POWERGATE_CELP] = "celp", | |
1502 | [TEGRA_POWERGATE_3D1] = "3d1", | |
1503 | }; | |
1504 | ||
1505 | static const u8 tegra30_cpu_powergates[] = { | |
1506 | TEGRA_POWERGATE_CPU, | |
1507 | TEGRA_POWERGATE_CPU1, | |
1508 | TEGRA_POWERGATE_CPU2, | |
1509 | TEGRA_POWERGATE_CPU3, | |
1510 | }; | |
1511 | ||
1512 | static const struct tegra_pmc_soc tegra30_pmc_soc = { | |
1513 | .num_powergates = ARRAY_SIZE(tegra30_powergates), | |
1514 | .powergates = tegra30_powergates, | |
1515 | .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), | |
1516 | .cpu_powergates = tegra30_cpu_powergates, | |
3568df3d | 1517 | .has_tsense_reset = true, |
a9a40a4a | 1518 | .has_gpu_clamps = false, |
7232398a TR |
1519 | }; |
1520 | ||
1521 | static const char * const tegra114_powergates[] = { | |
1522 | [TEGRA_POWERGATE_CPU] = "crail", | |
1523 | [TEGRA_POWERGATE_3D] = "3d", | |
1524 | [TEGRA_POWERGATE_VENC] = "venc", | |
1525 | [TEGRA_POWERGATE_VDEC] = "vdec", | |
1526 | [TEGRA_POWERGATE_MPE] = "mpe", | |
1527 | [TEGRA_POWERGATE_HEG] = "heg", | |
1528 | [TEGRA_POWERGATE_CPU1] = "cpu1", | |
1529 | [TEGRA_POWERGATE_CPU2] = "cpu2", | |
1530 | [TEGRA_POWERGATE_CPU3] = "cpu3", | |
1531 | [TEGRA_POWERGATE_CELP] = "celp", | |
1532 | [TEGRA_POWERGATE_CPU0] = "cpu0", | |
1533 | [TEGRA_POWERGATE_C0NC] = "c0nc", | |
1534 | [TEGRA_POWERGATE_C1NC] = "c1nc", | |
1535 | [TEGRA_POWERGATE_DIS] = "dis", | |
1536 | [TEGRA_POWERGATE_DISB] = "disb", | |
1537 | [TEGRA_POWERGATE_XUSBA] = "xusba", | |
1538 | [TEGRA_POWERGATE_XUSBB] = "xusbb", | |
1539 | [TEGRA_POWERGATE_XUSBC] = "xusbc", | |
1540 | }; | |
1541 | ||
1542 | static const u8 tegra114_cpu_powergates[] = { | |
1543 | TEGRA_POWERGATE_CPU0, | |
1544 | TEGRA_POWERGATE_CPU1, | |
1545 | TEGRA_POWERGATE_CPU2, | |
1546 | TEGRA_POWERGATE_CPU3, | |
1547 | }; | |
1548 | ||
1549 | static const struct tegra_pmc_soc tegra114_pmc_soc = { | |
1550 | .num_powergates = ARRAY_SIZE(tegra114_powergates), | |
1551 | .powergates = tegra114_powergates, | |
1552 | .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), | |
1553 | .cpu_powergates = tegra114_cpu_powergates, | |
3568df3d | 1554 | .has_tsense_reset = true, |
a9a40a4a | 1555 | .has_gpu_clamps = false, |
7232398a TR |
1556 | }; |
1557 | ||
1558 | static const char * const tegra124_powergates[] = { | |
1559 | [TEGRA_POWERGATE_CPU] = "crail", | |
1560 | [TEGRA_POWERGATE_3D] = "3d", | |
1561 | [TEGRA_POWERGATE_VENC] = "venc", | |
1562 | [TEGRA_POWERGATE_PCIE] = "pcie", | |
1563 | [TEGRA_POWERGATE_VDEC] = "vdec", | |
7232398a TR |
1564 | [TEGRA_POWERGATE_MPE] = "mpe", |
1565 | [TEGRA_POWERGATE_HEG] = "heg", | |
1566 | [TEGRA_POWERGATE_SATA] = "sata", | |
1567 | [TEGRA_POWERGATE_CPU1] = "cpu1", | |
1568 | [TEGRA_POWERGATE_CPU2] = "cpu2", | |
1569 | [TEGRA_POWERGATE_CPU3] = "cpu3", | |
1570 | [TEGRA_POWERGATE_CELP] = "celp", | |
1571 | [TEGRA_POWERGATE_CPU0] = "cpu0", | |
1572 | [TEGRA_POWERGATE_C0NC] = "c0nc", | |
1573 | [TEGRA_POWERGATE_C1NC] = "c1nc", | |
1574 | [TEGRA_POWERGATE_SOR] = "sor", | |
1575 | [TEGRA_POWERGATE_DIS] = "dis", | |
1576 | [TEGRA_POWERGATE_DISB] = "disb", | |
1577 | [TEGRA_POWERGATE_XUSBA] = "xusba", | |
1578 | [TEGRA_POWERGATE_XUSBB] = "xusbb", | |
1579 | [TEGRA_POWERGATE_XUSBC] = "xusbc", | |
1580 | [TEGRA_POWERGATE_VIC] = "vic", | |
1581 | [TEGRA_POWERGATE_IRAM] = "iram", | |
1582 | }; | |
1583 | ||
1584 | static const u8 tegra124_cpu_powergates[] = { | |
1585 | TEGRA_POWERGATE_CPU0, | |
1586 | TEGRA_POWERGATE_CPU1, | |
1587 | TEGRA_POWERGATE_CPU2, | |
1588 | TEGRA_POWERGATE_CPU3, | |
1589 | }; | |
1590 | ||
21b49910 LD |
1591 | static const struct tegra_io_pad_soc tegra124_io_pads[] = { |
1592 | { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX }, | |
1593 | { .id = TEGRA_IO_PAD_BB, .dpd = 15, .voltage = UINT_MAX }, | |
1594 | { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = UINT_MAX }, | |
1595 | { .id = TEGRA_IO_PAD_COMP, .dpd = 22, .voltage = UINT_MAX }, | |
1596 | { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, | |
1597 | { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, | |
1598 | { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX }, | |
1599 | { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX }, | |
1600 | { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX }, | |
1601 | { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX }, | |
1602 | { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX }, | |
1603 | { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX }, | |
1604 | { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX }, | |
1605 | { .id = TEGRA_IO_PAD_HV, .dpd = 38, .voltage = UINT_MAX }, | |
1606 | { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX }, | |
1607 | { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, | |
1608 | { .id = TEGRA_IO_PAD_NAND, .dpd = 13, .voltage = UINT_MAX }, | |
1609 | { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX }, | |
1610 | { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX }, | |
1611 | { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, | |
1612 | { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX }, | |
1613 | { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = UINT_MAX }, | |
1614 | { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = UINT_MAX }, | |
1615 | { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 35, .voltage = UINT_MAX }, | |
1616 | { .id = TEGRA_IO_PAD_SYS_DDC, .dpd = 58, .voltage = UINT_MAX }, | |
1617 | { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX }, | |
1618 | { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX }, | |
1619 | { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX }, | |
1620 | { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX }, | |
1621 | { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX }, | |
1622 | }; | |
1623 | ||
7232398a TR |
1624 | static const struct tegra_pmc_soc tegra124_pmc_soc = { |
1625 | .num_powergates = ARRAY_SIZE(tegra124_powergates), | |
1626 | .powergates = tegra124_powergates, | |
1627 | .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), | |
1628 | .cpu_powergates = tegra124_cpu_powergates, | |
3568df3d | 1629 | .has_tsense_reset = true, |
a9a40a4a | 1630 | .has_gpu_clamps = true, |
21b49910 LD |
1631 | .num_io_pads = ARRAY_SIZE(tegra124_io_pads), |
1632 | .io_pads = tegra124_io_pads, | |
7232398a TR |
1633 | }; |
1634 | ||
c2fe4694 TR |
1635 | static const char * const tegra210_powergates[] = { |
1636 | [TEGRA_POWERGATE_CPU] = "crail", | |
1637 | [TEGRA_POWERGATE_3D] = "3d", | |
1638 | [TEGRA_POWERGATE_VENC] = "venc", | |
1639 | [TEGRA_POWERGATE_PCIE] = "pcie", | |
c2fe4694 | 1640 | [TEGRA_POWERGATE_MPE] = "mpe", |
c2fe4694 TR |
1641 | [TEGRA_POWERGATE_SATA] = "sata", |
1642 | [TEGRA_POWERGATE_CPU1] = "cpu1", | |
1643 | [TEGRA_POWERGATE_CPU2] = "cpu2", | |
1644 | [TEGRA_POWERGATE_CPU3] = "cpu3", | |
c2fe4694 TR |
1645 | [TEGRA_POWERGATE_CPU0] = "cpu0", |
1646 | [TEGRA_POWERGATE_C0NC] = "c0nc", | |
c2fe4694 TR |
1647 | [TEGRA_POWERGATE_SOR] = "sor", |
1648 | [TEGRA_POWERGATE_DIS] = "dis", | |
1649 | [TEGRA_POWERGATE_DISB] = "disb", | |
1650 | [TEGRA_POWERGATE_XUSBA] = "xusba", | |
1651 | [TEGRA_POWERGATE_XUSBB] = "xusbb", | |
1652 | [TEGRA_POWERGATE_XUSBC] = "xusbc", | |
1653 | [TEGRA_POWERGATE_VIC] = "vic", | |
1654 | [TEGRA_POWERGATE_IRAM] = "iram", | |
1655 | [TEGRA_POWERGATE_NVDEC] = "nvdec", | |
1656 | [TEGRA_POWERGATE_NVJPG] = "nvjpg", | |
1657 | [TEGRA_POWERGATE_AUD] = "aud", | |
1658 | [TEGRA_POWERGATE_DFD] = "dfd", | |
1659 | [TEGRA_POWERGATE_VE2] = "ve2", | |
1660 | }; | |
1661 | ||
1662 | static const u8 tegra210_cpu_powergates[] = { | |
1663 | TEGRA_POWERGATE_CPU0, | |
1664 | TEGRA_POWERGATE_CPU1, | |
1665 | TEGRA_POWERGATE_CPU2, | |
1666 | TEGRA_POWERGATE_CPU3, | |
1667 | }; | |
1668 | ||
21b49910 LD |
1669 | static const struct tegra_io_pad_soc tegra210_io_pads[] = { |
1670 | { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = 5 }, | |
1671 | { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 18 }, | |
1672 | { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = 10 }, | |
1673 | { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, | |
1674 | { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, | |
1675 | { .id = TEGRA_IO_PAD_CSIC, .dpd = 42, .voltage = UINT_MAX }, | |
1676 | { .id = TEGRA_IO_PAD_CSID, .dpd = 43, .voltage = UINT_MAX }, | |
1677 | { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX }, | |
1678 | { .id = TEGRA_IO_PAD_CSIF, .dpd = 45, .voltage = UINT_MAX }, | |
1679 | { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = 19 }, | |
1680 | { .id = TEGRA_IO_PAD_DEBUG_NONAO, .dpd = 26, .voltage = UINT_MAX }, | |
1681 | { .id = TEGRA_IO_PAD_DMIC, .dpd = 50, .voltage = 20 }, | |
1682 | { .id = TEGRA_IO_PAD_DP, .dpd = 51, .voltage = UINT_MAX }, | |
1683 | { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX }, | |
1684 | { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX }, | |
1685 | { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX }, | |
1686 | { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX }, | |
1687 | { .id = TEGRA_IO_PAD_EMMC, .dpd = 35, .voltage = UINT_MAX }, | |
1688 | { .id = TEGRA_IO_PAD_EMMC2, .dpd = 37, .voltage = UINT_MAX }, | |
1689 | { .id = TEGRA_IO_PAD_GPIO, .dpd = 27, .voltage = 21 }, | |
1690 | { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX }, | |
1691 | { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX }, | |
1692 | { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX }, | |
1693 | { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, | |
1694 | { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX }, | |
1695 | { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX }, | |
1696 | { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, | |
1697 | { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = UINT_MAX, .voltage = 11 }, | |
1698 | { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = 12 }, | |
1699 | { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = 13 }, | |
1700 | { .id = TEGRA_IO_PAD_SPI, .dpd = 46, .voltage = 22 }, | |
1701 | { .id = TEGRA_IO_PAD_SPI_HV, .dpd = 47, .voltage = 23 }, | |
1702 | { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = 2 }, | |
1703 | { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX }, | |
1704 | { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX }, | |
1705 | { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX }, | |
1706 | { .id = TEGRA_IO_PAD_USB3, .dpd = 18, .voltage = UINT_MAX }, | |
1707 | { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX }, | |
1708 | }; | |
1709 | ||
c2fe4694 TR |
1710 | static const struct tegra_pmc_soc tegra210_pmc_soc = { |
1711 | .num_powergates = ARRAY_SIZE(tegra210_powergates), | |
1712 | .powergates = tegra210_powergates, | |
1713 | .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), | |
1714 | .cpu_powergates = tegra210_cpu_powergates, | |
1715 | .has_tsense_reset = true, | |
1716 | .has_gpu_clamps = true, | |
21b49910 LD |
1717 | .num_io_pads = ARRAY_SIZE(tegra210_io_pads), |
1718 | .io_pads = tegra210_io_pads, | |
c2fe4694 TR |
1719 | }; |
1720 | ||
7232398a | 1721 | static const struct of_device_id tegra_pmc_match[] = { |
c2fe4694 | 1722 | { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, |
7d71e903 | 1723 | { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, |
7232398a TR |
1724 | { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, |
1725 | { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, | |
1726 | { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, | |
1727 | { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, | |
1728 | { } | |
1729 | }; | |
1730 | ||
1731 | static struct platform_driver tegra_pmc_driver = { | |
1732 | .driver = { | |
1733 | .name = "tegra-pmc", | |
1734 | .suppress_bind_attrs = true, | |
1735 | .of_match_table = tegra_pmc_match, | |
2b20b616 | 1736 | #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) |
7232398a | 1737 | .pm = &tegra_pmc_pm_ops, |
2b20b616 | 1738 | #endif |
7232398a TR |
1739 | }, |
1740 | .probe = tegra_pmc_probe, | |
1741 | }; | |
7d4d9ed6 | 1742 | builtin_platform_driver(tegra_pmc_driver); |
7232398a TR |
1743 | |
1744 | /* | |
1745 | * Early initialization to allow access to registers in the very early boot | |
1746 | * process. | |
1747 | */ | |
1748 | static int __init tegra_pmc_early_init(void) | |
1749 | { | |
1750 | const struct of_device_id *match; | |
1751 | struct device_node *np; | |
1752 | struct resource regs; | |
1753 | bool invert; | |
1754 | u32 value; | |
1755 | ||
61fd284b JH |
1756 | mutex_init(&pmc->powergates_lock); |
1757 | ||
7232398a TR |
1758 | np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); |
1759 | if (!np) { | |
7d71e903 TR |
1760 | /* |
1761 | * Fall back to legacy initialization for 32-bit ARM only. All | |
1762 | * 64-bit ARM device tree files for Tegra are required to have | |
1763 | * a PMC node. | |
1764 | * | |
1765 | * This is for backwards-compatibility with old device trees | |
1766 | * that didn't contain a PMC node. Note that in this case the | |
1767 | * SoC data can't be matched and therefore powergating is | |
1768 | * disabled. | |
1769 | */ | |
1770 | if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { | |
1771 | pr_warn("DT node not found, powergating disabled\n"); | |
1772 | ||
1773 | regs.start = 0x7000e400; | |
1774 | regs.end = 0x7000e7ff; | |
1775 | regs.flags = IORESOURCE_MEM; | |
1776 | ||
1777 | pr_warn("Using memory region %pR\n", ®s); | |
1778 | } else { | |
1779 | /* | |
1780 | * At this point we're not running on Tegra, so play | |
1781 | * nice with multi-platform kernels. | |
1782 | */ | |
1783 | return 0; | |
1784 | } | |
7232398a | 1785 | } else { |
7d71e903 TR |
1786 | /* |
1787 | * Extract information from the device tree if we've found a | |
1788 | * matching node. | |
1789 | */ | |
1790 | if (of_address_to_resource(np, 0, ®s) < 0) { | |
1791 | pr_err("failed to get PMC registers\n"); | |
b69a6258 | 1792 | of_node_put(np); |
7d71e903 TR |
1793 | return -ENXIO; |
1794 | } | |
7232398a TR |
1795 | } |
1796 | ||
1797 | pmc->base = ioremap_nocache(regs.start, resource_size(®s)); | |
1798 | if (!pmc->base) { | |
1799 | pr_err("failed to map PMC registers\n"); | |
b69a6258 | 1800 | of_node_put(np); |
7232398a TR |
1801 | return -ENXIO; |
1802 | } | |
1803 | ||
11131895 | 1804 | if (np) { |
718a2426 JH |
1805 | pmc->soc = match->data; |
1806 | ||
e2d17960 | 1807 | tegra_powergate_init(pmc, np); |
7232398a | 1808 | |
11131895 JH |
1809 | /* |
1810 | * Invert the interrupt polarity if a PMC device tree node | |
1811 | * exists and contains the nvidia,invert-interrupt property. | |
1812 | */ | |
1813 | invert = of_property_read_bool(np, "nvidia,invert-interrupt"); | |
7232398a | 1814 | |
11131895 | 1815 | value = tegra_pmc_readl(PMC_CNTRL); |
7232398a | 1816 | |
11131895 JH |
1817 | if (invert) |
1818 | value |= PMC_CNTRL_INTR_POLARITY; | |
1819 | else | |
1820 | value &= ~PMC_CNTRL_INTR_POLARITY; | |
1821 | ||
1822 | tegra_pmc_writel(value, PMC_CNTRL); | |
b69a6258 JH |
1823 | |
1824 | of_node_put(np); | |
11131895 | 1825 | } |
7232398a TR |
1826 | |
1827 | return 0; | |
1828 | } | |
1829 | early_initcall(tegra_pmc_early_init); |