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9c92ab61 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
7232398a TR |
2 | /* |
3 | * drivers/soc/tegra/pmc.c | |
4 | * | |
5 | * Copyright (c) 2010 Google, Inc | |
5f84bb1a | 6 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. |
7232398a TR |
7 | * |
8 | * Author: | |
9 | * Colin Cross <ccross@google.com> | |
7232398a TR |
10 | */ |
11 | ||
7d71e903 TR |
12 | #define pr_fmt(fmt) "tegra-pmc: " fmt |
13 | ||
e247deae | 14 | #include <linux/arm-smccc.h> |
7232398a TR |
15 | #include <linux/clk.h> |
16 | #include <linux/clk/tegra.h> | |
17 | #include <linux/debugfs.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/export.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/io.h> | |
0a2d87e0 | 23 | #include <linux/iopoll.h> |
19906e6b | 24 | #include <linux/irqdomain.h> |
4659db5e TR |
25 | #include <linux/irq.h> |
26 | #include <linux/kernel.h> | |
7232398a | 27 | #include <linux/of_address.h> |
3fd0121b | 28 | #include <linux/of_clk.h> |
4659db5e | 29 | #include <linux/of.h> |
19906e6b | 30 | #include <linux/of_irq.h> |
a3804512 | 31 | #include <linux/of_platform.h> |
4a37f11c | 32 | #include <linux/pinctrl/pinconf-generic.h> |
4659db5e TR |
33 | #include <linux/pinctrl/pinconf.h> |
34 | #include <linux/pinctrl/pinctrl.h> | |
7232398a | 35 | #include <linux/platform_device.h> |
a3804512 | 36 | #include <linux/pm_domain.h> |
7232398a TR |
37 | #include <linux/reboot.h> |
38 | #include <linux/reset.h> | |
39 | #include <linux/seq_file.h> | |
a3804512 | 40 | #include <linux/slab.h> |
7232398a TR |
41 | #include <linux/spinlock.h> |
42 | ||
43 | #include <soc/tegra/common.h> | |
44 | #include <soc/tegra/fuse.h> | |
45 | #include <soc/tegra/pmc.h> | |
46 | ||
19906e6b | 47 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
fccf0f76 | 48 | #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> |
e59333c8 | 49 | #include <dt-bindings/gpio/tegra186-gpio.h> |
e3e403c2 | 50 | #include <dt-bindings/gpio/tegra194-gpio.h> |
fccf0f76 | 51 | |
7232398a | 52 | #define PMC_CNTRL 0x0 |
6c0bd217 | 53 | #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ |
95b780b3 TR |
54 | #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ |
55 | #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ | |
56 | #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ | |
57 | #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ | |
58 | #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ | |
59 | #define PMC_CNTRL_MAIN_RST BIT(4) | |
7232398a TR |
60 | |
61 | #define DPD_SAMPLE 0x020 | |
6c0bd217 | 62 | #define DPD_SAMPLE_ENABLE BIT(0) |
7232398a TR |
63 | #define DPD_SAMPLE_DISABLE (0 << 0) |
64 | ||
65 | #define PWRGATE_TOGGLE 0x30 | |
6c0bd217 | 66 | #define PWRGATE_TOGGLE_START BIT(8) |
7232398a TR |
67 | |
68 | #define REMOVE_CLAMPING 0x34 | |
69 | ||
70 | #define PWRGATE_STATUS 0x38 | |
71 | ||
13136a47 AV |
72 | #define PMC_IMPL_E_33V_PWR 0x40 |
73 | ||
21b49910 LD |
74 | #define PMC_PWR_DET 0x48 |
75 | ||
5be22556 TR |
76 | #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) |
77 | #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) | |
78 | #define PMC_SCRATCH0_MODE_RCM BIT(1) | |
79 | #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ | |
7232398a TR |
80 | PMC_SCRATCH0_MODE_BOOTLOADER | \ |
81 | PMC_SCRATCH0_MODE_RCM) | |
82 | ||
83 | #define PMC_CPUPWRGOOD_TIMER 0xc8 | |
84 | #define PMC_CPUPWROFF_TIMER 0xcc | |
85 | ||
21b49910 LD |
86 | #define PMC_PWR_DET_VALUE 0xe4 |
87 | ||
7232398a TR |
88 | #define PMC_SCRATCH41 0x140 |
89 | ||
3568df3d | 90 | #define PMC_SENSOR_CTRL 0x1b0 |
6c0bd217 LD |
91 | #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) |
92 | #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) | |
3568df3d | 93 | |
f5353c60 TR |
94 | #define PMC_RST_STATUS_POR 0 |
95 | #define PMC_RST_STATUS_WATCHDOG 1 | |
96 | #define PMC_RST_STATUS_SENSOR 2 | |
97 | #define PMC_RST_STATUS_SW_MAIN 3 | |
98 | #define PMC_RST_STATUS_LP0 4 | |
99 | #define PMC_RST_STATUS_AOTAG 5 | |
100 | ||
7232398a | 101 | #define IO_DPD_REQ 0x1b8 |
6c0bd217 LD |
102 | #define IO_DPD_REQ_CODE_IDLE (0U << 30) |
103 | #define IO_DPD_REQ_CODE_OFF (1U << 30) | |
104 | #define IO_DPD_REQ_CODE_ON (2U << 30) | |
105 | #define IO_DPD_REQ_CODE_MASK (3U << 30) | |
7232398a TR |
106 | |
107 | #define IO_DPD_STATUS 0x1bc | |
108 | #define IO_DPD2_REQ 0x1c0 | |
109 | #define IO_DPD2_STATUS 0x1c4 | |
110 | #define SEL_DPD_TIM 0x1c8 | |
111 | ||
3568df3d | 112 | #define PMC_SCRATCH54 0x258 |
6c0bd217 LD |
113 | #define PMC_SCRATCH54_DATA_SHIFT 8 |
114 | #define PMC_SCRATCH54_ADDR_SHIFT 0 | |
3568df3d MP |
115 | |
116 | #define PMC_SCRATCH55 0x25c | |
6c0bd217 LD |
117 | #define PMC_SCRATCH55_RESET_TEGRA BIT(31) |
118 | #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 | |
119 | #define PMC_SCRATCH55_PINMUX_SHIFT 24 | |
120 | #define PMC_SCRATCH55_16BITOP BIT(15) | |
121 | #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 | |
122 | #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 | |
3568df3d | 123 | |
7232398a TR |
124 | #define GPU_RG_CNTRL 0x2d4 |
125 | ||
c641ec6e | 126 | /* Tegra186 and later */ |
19906e6b TR |
127 | #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2)) |
128 | #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3) | |
129 | #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2)) | |
130 | #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2)) | |
131 | #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2)) | |
132 | #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2)) | |
133 | #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2)) | |
134 | #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2)) | |
135 | #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2)) | |
136 | ||
c641ec6e TR |
137 | #define WAKE_AOWAKE_CTRL 0x4f4 |
138 | #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) | |
139 | ||
e247deae MP |
140 | /* for secure PMC */ |
141 | #define TEGRA_SMC_PMC 0xc2fffe00 | |
142 | #define TEGRA_SMC_PMC_READ 0xaa | |
143 | #define TEGRA_SMC_PMC_WRITE 0xbb | |
144 | ||
a3804512 JH |
145 | struct tegra_powergate { |
146 | struct generic_pm_domain genpd; | |
147 | struct tegra_pmc *pmc; | |
148 | unsigned int id; | |
149 | struct clk **clks; | |
150 | unsigned int num_clks; | |
4c817ccf | 151 | struct reset_control *reset; |
a3804512 JH |
152 | }; |
153 | ||
21b49910 LD |
154 | struct tegra_io_pad_soc { |
155 | enum tegra_io_pad id; | |
156 | unsigned int dpd; | |
157 | unsigned int voltage; | |
437c4f26 | 158 | const char *name; |
21b49910 LD |
159 | }; |
160 | ||
5be22556 TR |
161 | struct tegra_pmc_regs { |
162 | unsigned int scratch0; | |
163 | unsigned int dpd_req; | |
164 | unsigned int dpd_status; | |
165 | unsigned int dpd2_req; | |
166 | unsigned int dpd2_status; | |
5f84bb1a SP |
167 | unsigned int rst_status; |
168 | unsigned int rst_source_shift; | |
169 | unsigned int rst_source_mask; | |
170 | unsigned int rst_level_shift; | |
171 | unsigned int rst_level_mask; | |
5be22556 TR |
172 | }; |
173 | ||
19906e6b TR |
174 | struct tegra_wake_event { |
175 | const char *name; | |
176 | unsigned int id; | |
177 | unsigned int irq; | |
178 | struct { | |
179 | unsigned int instance; | |
180 | unsigned int pin; | |
181 | } gpio; | |
5be22556 TR |
182 | }; |
183 | ||
19906e6b TR |
184 | #define TEGRA_WAKE_IRQ(_name, _id, _irq) \ |
185 | { \ | |
186 | .name = _name, \ | |
187 | .id = _id, \ | |
188 | .irq = _irq, \ | |
189 | .gpio = { \ | |
190 | .instance = UINT_MAX, \ | |
191 | .pin = UINT_MAX, \ | |
192 | }, \ | |
193 | } | |
194 | ||
195 | #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \ | |
196 | { \ | |
197 | .name = _name, \ | |
198 | .id = _id, \ | |
199 | .irq = 0, \ | |
200 | .gpio = { \ | |
201 | .instance = _instance, \ | |
202 | .pin = _pin, \ | |
203 | }, \ | |
204 | } | |
205 | ||
7232398a TR |
206 | struct tegra_pmc_soc { |
207 | unsigned int num_powergates; | |
208 | const char *const *powergates; | |
209 | unsigned int num_cpu_powergates; | |
210 | const u8 *cpu_powergates; | |
a9a40a4a | 211 | |
3568df3d | 212 | bool has_tsense_reset; |
a9a40a4a | 213 | bool has_gpu_clamps; |
a263394a | 214 | bool needs_mbist_war; |
13136a47 | 215 | bool has_impl_33v_pwr; |
e247deae | 216 | bool maybe_tz_only; |
21b49910 LD |
217 | |
218 | const struct tegra_io_pad_soc *io_pads; | |
219 | unsigned int num_io_pads; | |
5be22556 | 220 | |
4a37f11c AV |
221 | const struct pinctrl_pin_desc *pin_descs; |
222 | unsigned int num_pin_descs; | |
223 | ||
5be22556 TR |
224 | const struct tegra_pmc_regs *regs; |
225 | void (*init)(struct tegra_pmc *pmc); | |
226 | void (*setup_irq_polarity)(struct tegra_pmc *pmc, | |
227 | struct device_node *np, | |
228 | bool invert); | |
5f84bb1a SP |
229 | |
230 | const char * const *reset_sources; | |
231 | unsigned int num_reset_sources; | |
232 | const char * const *reset_levels; | |
233 | unsigned int num_reset_levels; | |
19906e6b TR |
234 | |
235 | const struct tegra_wake_event *wake_events; | |
236 | unsigned int num_wake_events; | |
5f84bb1a SP |
237 | }; |
238 | ||
239 | static const char * const tegra186_reset_sources[] = { | |
240 | "SYS_RESET", | |
241 | "AOWDT", | |
242 | "MCCPLEXWDT", | |
243 | "BPMPWDT", | |
244 | "SCEWDT", | |
245 | "SPEWDT", | |
246 | "APEWDT", | |
247 | "BCCPLEXWDT", | |
248 | "SENSOR", | |
249 | "AOTAG", | |
250 | "VFSENSOR", | |
251 | "SWREST", | |
252 | "SC7", | |
253 | "HSM", | |
254 | "CORESIGHT" | |
255 | }; | |
256 | ||
257 | static const char * const tegra186_reset_levels[] = { | |
258 | "L0", "L1", "L2", "WARM" | |
259 | }; | |
260 | ||
261 | static const char * const tegra30_reset_sources[] = { | |
00cdaa1b JH |
262 | "POWER_ON_RESET", |
263 | "WATCHDOG", | |
264 | "SENSOR", | |
265 | "SW_MAIN", | |
266 | "LP0" | |
267 | }; | |
268 | ||
269 | static const char * const tegra210_reset_sources[] = { | |
5f84bb1a SP |
270 | "POWER_ON_RESET", |
271 | "WATCHDOG", | |
272 | "SENSOR", | |
273 | "SW_MAIN", | |
274 | "LP0", | |
275 | "AOTAG" | |
7232398a TR |
276 | }; |
277 | ||
278 | /** | |
279 | * struct tegra_pmc - NVIDIA Tegra PMC | |
35b67291 | 280 | * @dev: pointer to PMC device structure |
7232398a | 281 | * @base: pointer to I/O remapped register region |
bbe5af60 TR |
282 | * @wake: pointer to I/O remapped region for WAKE registers |
283 | * @aotag: pointer to I/O remapped region for AOTAG registers | |
284 | * @scratch: pointer to I/O remapped region for scratch registers | |
7232398a | 285 | * @clk: pointer to pclk clock |
35b67291 | 286 | * @soc: pointer to SoC data structure |
e247deae | 287 | * @tz_only: flag specifying if the PMC can only be accessed via TrustZone |
3195ac6d | 288 | * @debugfs: pointer to debugfs entry |
7232398a TR |
289 | * @rate: currently configured rate of pclk |
290 | * @suspend_mode: lowest suspend mode available | |
291 | * @cpu_good_time: CPU power good time (in microseconds) | |
292 | * @cpu_off_time: CPU power off time (in microsecends) | |
293 | * @core_osc_time: core power good OSC time (in microseconds) | |
294 | * @core_pmu_time: core power good PMU time (in microseconds) | |
295 | * @core_off_time: core power off time (in microseconds) | |
296 | * @corereq_high: core power request is active-high | |
297 | * @sysclkreq_high: system clock request is active-high | |
298 | * @combined_req: combined power request for CPU & core | |
299 | * @cpu_pwr_good_en: CPU power good signal is enabled | |
300 | * @lp0_vec_phys: physical base address of the LP0 warm boot code | |
301 | * @lp0_vec_size: size of the LP0 warm boot code | |
a3804512 | 302 | * @powergates_available: Bitmap of available power gates |
7232398a | 303 | * @powergates_lock: mutex for power gate register access |
bbe5af60 TR |
304 | * @pctl_dev: pin controller exposed by the PMC |
305 | * @domain: IRQ domain provided by the PMC | |
306 | * @irq: chip implementation for the IRQ domain | |
7232398a TR |
307 | */ |
308 | struct tegra_pmc { | |
3568df3d | 309 | struct device *dev; |
7232398a | 310 | void __iomem *base; |
c641ec6e TR |
311 | void __iomem *wake; |
312 | void __iomem *aotag; | |
5be22556 | 313 | void __iomem *scratch; |
7232398a | 314 | struct clk *clk; |
3195ac6d | 315 | struct dentry *debugfs; |
7232398a TR |
316 | |
317 | const struct tegra_pmc_soc *soc; | |
e247deae | 318 | bool tz_only; |
7232398a TR |
319 | |
320 | unsigned long rate; | |
321 | ||
322 | enum tegra_suspend_mode suspend_mode; | |
323 | u32 cpu_good_time; | |
324 | u32 cpu_off_time; | |
325 | u32 core_osc_time; | |
326 | u32 core_pmu_time; | |
327 | u32 core_off_time; | |
328 | bool corereq_high; | |
329 | bool sysclkreq_high; | |
330 | bool combined_req; | |
331 | bool cpu_pwr_good_en; | |
332 | u32 lp0_vec_phys; | |
333 | u32 lp0_vec_size; | |
a3804512 | 334 | DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); |
7232398a TR |
335 | |
336 | struct mutex powergates_lock; | |
4a37f11c AV |
337 | |
338 | struct pinctrl_dev *pctl_dev; | |
19906e6b TR |
339 | |
340 | struct irq_domain *domain; | |
341 | struct irq_chip irq; | |
7232398a TR |
342 | }; |
343 | ||
344 | static struct tegra_pmc *pmc = &(struct tegra_pmc) { | |
345 | .base = NULL, | |
346 | .suspend_mode = TEGRA_SUSPEND_NONE, | |
347 | }; | |
348 | ||
a3804512 JH |
349 | static inline struct tegra_powergate * |
350 | to_powergate(struct generic_pm_domain *domain) | |
351 | { | |
352 | return container_of(domain, struct tegra_powergate, genpd); | |
353 | } | |
354 | ||
589997a1 | 355 | static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) |
7232398a | 356 | { |
e247deae MP |
357 | struct arm_smccc_res res; |
358 | ||
359 | if (pmc->tz_only) { | |
360 | arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, | |
361 | 0, 0, 0, &res); | |
362 | if (res.a0) { | |
363 | if (pmc->dev) | |
364 | dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", | |
365 | __func__, res.a0); | |
366 | else | |
367 | pr_warn("%s(): SMC failed: %lu\n", __func__, | |
368 | res.a0); | |
369 | } | |
370 | ||
371 | return res.a1; | |
372 | } | |
373 | ||
7232398a TR |
374 | return readl(pmc->base + offset); |
375 | } | |
376 | ||
589997a1 TR |
377 | static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, |
378 | unsigned long offset) | |
7232398a | 379 | { |
e247deae MP |
380 | struct arm_smccc_res res; |
381 | ||
382 | if (pmc->tz_only) { | |
383 | arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset, | |
384 | value, 0, 0, 0, 0, &res); | |
385 | if (res.a0) { | |
386 | if (pmc->dev) | |
387 | dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", | |
388 | __func__, res.a0); | |
389 | else | |
390 | pr_warn("%s(): SMC failed: %lu\n", __func__, | |
391 | res.a0); | |
392 | } | |
393 | } else { | |
394 | writel(value, pmc->base + offset); | |
395 | } | |
396 | } | |
397 | ||
398 | static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) | |
399 | { | |
400 | if (pmc->tz_only) | |
401 | return tegra_pmc_readl(pmc, offset); | |
402 | ||
403 | return readl(pmc->scratch + offset); | |
404 | } | |
405 | ||
406 | static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, | |
407 | unsigned long offset) | |
408 | { | |
409 | if (pmc->tz_only) | |
410 | tegra_pmc_writel(pmc, value, offset); | |
411 | else | |
412 | writel(value, pmc->scratch + offset); | |
7232398a TR |
413 | } |
414 | ||
589997a1 TR |
415 | /* |
416 | * TODO Figure out a way to call this with the struct tegra_pmc * passed in. | |
417 | * This currently doesn't work because readx_poll_timeout() can only operate | |
418 | * on functions that take a single argument. | |
419 | */ | |
0ecf2d33 JH |
420 | static inline bool tegra_powergate_state(int id) |
421 | { | |
bc9af23d | 422 | if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) |
589997a1 | 423 | return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; |
bc9af23d | 424 | else |
589997a1 | 425 | return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; |
0ecf2d33 JH |
426 | } |
427 | ||
589997a1 | 428 | static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) |
0a243bd4 JH |
429 | { |
430 | return (pmc->soc && pmc->soc->powergates[id]); | |
431 | } | |
432 | ||
589997a1 | 433 | static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) |
a3804512 JH |
434 | { |
435 | return test_bit(id, pmc->powergates_available); | |
436 | } | |
437 | ||
438 | static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) | |
439 | { | |
440 | unsigned int i; | |
441 | ||
442 | if (!pmc || !pmc->soc || !name) | |
443 | return -EINVAL; | |
444 | ||
445 | for (i = 0; i < pmc->soc->num_powergates; i++) { | |
589997a1 | 446 | if (!tegra_powergate_is_valid(pmc, i)) |
a3804512 JH |
447 | continue; |
448 | ||
449 | if (!strcmp(name, pmc->soc->powergates[i])) | |
450 | return i; | |
451 | } | |
452 | ||
a3804512 JH |
453 | return -ENODEV; |
454 | } | |
455 | ||
7232398a TR |
456 | /** |
457 | * tegra_powergate_set() - set the state of a partition | |
589997a1 | 458 | * @pmc: power management controller |
7232398a TR |
459 | * @id: partition ID |
460 | * @new_state: new state of the partition | |
461 | */ | |
589997a1 TR |
462 | static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, |
463 | bool new_state) | |
7232398a | 464 | { |
0a2d87e0 JH |
465 | bool status; |
466 | int err; | |
467 | ||
bc9af23d JH |
468 | if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) |
469 | return -EINVAL; | |
470 | ||
7232398a TR |
471 | mutex_lock(&pmc->powergates_lock); |
472 | ||
0ecf2d33 | 473 | if (tegra_powergate_state(id) == new_state) { |
7232398a TR |
474 | mutex_unlock(&pmc->powergates_lock); |
475 | return 0; | |
476 | } | |
477 | ||
589997a1 | 478 | tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); |
7232398a | 479 | |
0a2d87e0 JH |
480 | err = readx_poll_timeout(tegra_powergate_state, id, status, |
481 | status == new_state, 10, 100000); | |
482 | ||
7232398a TR |
483 | mutex_unlock(&pmc->powergates_lock); |
484 | ||
0a2d87e0 | 485 | return err; |
7232398a TR |
486 | } |
487 | ||
589997a1 TR |
488 | static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, |
489 | unsigned int id) | |
a3804512 JH |
490 | { |
491 | u32 mask; | |
492 | ||
493 | mutex_lock(&pmc->powergates_lock); | |
494 | ||
495 | /* | |
496 | * On Tegra124 and later, the clamps for the GPU are controlled by a | |
497 | * separate register (with different semantics). | |
498 | */ | |
499 | if (id == TEGRA_POWERGATE_3D) { | |
500 | if (pmc->soc->has_gpu_clamps) { | |
589997a1 | 501 | tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); |
a3804512 JH |
502 | goto out; |
503 | } | |
504 | } | |
505 | ||
506 | /* | |
507 | * Tegra 2 has a bug where PCIE and VDE clamping masks are | |
508 | * swapped relatively to the partition ids | |
509 | */ | |
510 | if (id == TEGRA_POWERGATE_VDEC) | |
511 | mask = (1 << TEGRA_POWERGATE_PCIE); | |
512 | else if (id == TEGRA_POWERGATE_PCIE) | |
513 | mask = (1 << TEGRA_POWERGATE_VDEC); | |
514 | else | |
515 | mask = (1 << id); | |
516 | ||
589997a1 | 517 | tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); |
a3804512 JH |
518 | |
519 | out: | |
520 | mutex_unlock(&pmc->powergates_lock); | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
525 | static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) | |
526 | { | |
527 | unsigned int i; | |
528 | ||
529 | for (i = 0; i < pg->num_clks; i++) | |
530 | clk_disable_unprepare(pg->clks[i]); | |
531 | } | |
532 | ||
533 | static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) | |
534 | { | |
535 | unsigned int i; | |
536 | int err; | |
537 | ||
538 | for (i = 0; i < pg->num_clks; i++) { | |
539 | err = clk_prepare_enable(pg->clks[i]); | |
540 | if (err) | |
541 | goto out; | |
542 | } | |
543 | ||
544 | return 0; | |
545 | ||
546 | out: | |
547 | while (i--) | |
548 | clk_disable_unprepare(pg->clks[i]); | |
549 | ||
550 | return err; | |
551 | } | |
552 | ||
a263394a PDS |
553 | int __weak tegra210_clk_handle_mbist_war(unsigned int id) |
554 | { | |
555 | return 0; | |
556 | } | |
557 | ||
a3804512 JH |
558 | static int tegra_powergate_power_up(struct tegra_powergate *pg, |
559 | bool disable_clocks) | |
560 | { | |
561 | int err; | |
562 | ||
4c817ccf | 563 | err = reset_control_assert(pg->reset); |
a3804512 JH |
564 | if (err) |
565 | return err; | |
566 | ||
567 | usleep_range(10, 20); | |
568 | ||
589997a1 | 569 | err = tegra_powergate_set(pg->pmc, pg->id, true); |
a3804512 JH |
570 | if (err < 0) |
571 | return err; | |
572 | ||
573 | usleep_range(10, 20); | |
574 | ||
575 | err = tegra_powergate_enable_clocks(pg); | |
576 | if (err) | |
577 | goto disable_clks; | |
578 | ||
579 | usleep_range(10, 20); | |
580 | ||
589997a1 | 581 | err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); |
a3804512 JH |
582 | if (err) |
583 | goto disable_clks; | |
584 | ||
585 | usleep_range(10, 20); | |
586 | ||
4c817ccf | 587 | err = reset_control_deassert(pg->reset); |
a3804512 JH |
588 | if (err) |
589 | goto powergate_off; | |
590 | ||
591 | usleep_range(10, 20); | |
592 | ||
a263394a PDS |
593 | if (pg->pmc->soc->needs_mbist_war) |
594 | err = tegra210_clk_handle_mbist_war(pg->id); | |
595 | if (err) | |
596 | goto disable_clks; | |
597 | ||
a3804512 JH |
598 | if (disable_clocks) |
599 | tegra_powergate_disable_clocks(pg); | |
600 | ||
601 | return 0; | |
602 | ||
603 | disable_clks: | |
604 | tegra_powergate_disable_clocks(pg); | |
605 | usleep_range(10, 20); | |
da8f4b45 | 606 | |
a3804512 | 607 | powergate_off: |
589997a1 | 608 | tegra_powergate_set(pg->pmc, pg->id, false); |
a3804512 JH |
609 | |
610 | return err; | |
611 | } | |
612 | ||
613 | static int tegra_powergate_power_down(struct tegra_powergate *pg) | |
614 | { | |
615 | int err; | |
616 | ||
617 | err = tegra_powergate_enable_clocks(pg); | |
618 | if (err) | |
619 | return err; | |
620 | ||
621 | usleep_range(10, 20); | |
622 | ||
4c817ccf | 623 | err = reset_control_assert(pg->reset); |
a3804512 JH |
624 | if (err) |
625 | goto disable_clks; | |
626 | ||
627 | usleep_range(10, 20); | |
628 | ||
629 | tegra_powergate_disable_clocks(pg); | |
630 | ||
631 | usleep_range(10, 20); | |
632 | ||
589997a1 | 633 | err = tegra_powergate_set(pg->pmc, pg->id, false); |
a3804512 JH |
634 | if (err) |
635 | goto assert_resets; | |
636 | ||
637 | return 0; | |
638 | ||
639 | assert_resets: | |
640 | tegra_powergate_enable_clocks(pg); | |
641 | usleep_range(10, 20); | |
4c817ccf | 642 | reset_control_deassert(pg->reset); |
a3804512 | 643 | usleep_range(10, 20); |
da8f4b45 | 644 | |
a3804512 JH |
645 | disable_clks: |
646 | tegra_powergate_disable_clocks(pg); | |
647 | ||
648 | return err; | |
649 | } | |
650 | ||
651 | static int tegra_genpd_power_on(struct generic_pm_domain *domain) | |
652 | { | |
653 | struct tegra_powergate *pg = to_powergate(domain); | |
589997a1 | 654 | struct device *dev = pg->pmc->dev; |
a3804512 JH |
655 | int err; |
656 | ||
657 | err = tegra_powergate_power_up(pg, true); | |
7fe5719b | 658 | if (err) { |
589997a1 TR |
659 | dev_err(dev, "failed to turn on PM domain %s: %d\n", |
660 | pg->genpd.name, err); | |
7fe5719b TR |
661 | goto out; |
662 | } | |
663 | ||
664 | reset_control_release(pg->reset); | |
a3804512 | 665 | |
7fe5719b | 666 | out: |
a3804512 JH |
667 | return err; |
668 | } | |
669 | ||
670 | static int tegra_genpd_power_off(struct generic_pm_domain *domain) | |
671 | { | |
672 | struct tegra_powergate *pg = to_powergate(domain); | |
589997a1 | 673 | struct device *dev = pg->pmc->dev; |
a3804512 JH |
674 | int err; |
675 | ||
7fe5719b TR |
676 | err = reset_control_acquire(pg->reset); |
677 | if (err < 0) { | |
678 | pr_err("failed to acquire resets: %d\n", err); | |
679 | return err; | |
680 | } | |
681 | ||
a3804512 | 682 | err = tegra_powergate_power_down(pg); |
7fe5719b | 683 | if (err) { |
589997a1 TR |
684 | dev_err(dev, "failed to turn off PM domain %s: %d\n", |
685 | pg->genpd.name, err); | |
7fe5719b TR |
686 | reset_control_release(pg->reset); |
687 | } | |
a3804512 JH |
688 | |
689 | return err; | |
690 | } | |
691 | ||
7232398a TR |
692 | /** |
693 | * tegra_powergate_power_on() - power on partition | |
694 | * @id: partition ID | |
695 | */ | |
70293ed0 | 696 | int tegra_powergate_power_on(unsigned int id) |
7232398a | 697 | { |
589997a1 | 698 | if (!tegra_powergate_is_available(pmc, id)) |
7232398a TR |
699 | return -EINVAL; |
700 | ||
589997a1 | 701 | return tegra_powergate_set(pmc, id, true); |
7232398a TR |
702 | } |
703 | ||
704 | /** | |
705 | * tegra_powergate_power_off() - power off partition | |
706 | * @id: partition ID | |
707 | */ | |
70293ed0 | 708 | int tegra_powergate_power_off(unsigned int id) |
7232398a | 709 | { |
589997a1 | 710 | if (!tegra_powergate_is_available(pmc, id)) |
7232398a TR |
711 | return -EINVAL; |
712 | ||
589997a1 | 713 | return tegra_powergate_set(pmc, id, false); |
7232398a TR |
714 | } |
715 | EXPORT_SYMBOL(tegra_powergate_power_off); | |
716 | ||
717 | /** | |
718 | * tegra_powergate_is_powered() - check if partition is powered | |
589997a1 | 719 | * @pmc: power management controller |
7232398a TR |
720 | * @id: partition ID |
721 | */ | |
589997a1 | 722 | static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) |
7232398a | 723 | { |
589997a1 | 724 | if (!tegra_powergate_is_valid(pmc, id)) |
7232398a TR |
725 | return -EINVAL; |
726 | ||
b6e1fd17 | 727 | return tegra_powergate_state(id); |
7232398a TR |
728 | } |
729 | ||
730 | /** | |
731 | * tegra_powergate_remove_clamping() - remove power clamps for partition | |
732 | * @id: partition ID | |
733 | */ | |
70293ed0 | 734 | int tegra_powergate_remove_clamping(unsigned int id) |
7232398a | 735 | { |
589997a1 | 736 | if (!tegra_powergate_is_available(pmc, id)) |
7232398a TR |
737 | return -EINVAL; |
738 | ||
589997a1 | 739 | return __tegra_powergate_remove_clamping(pmc, id); |
7232398a TR |
740 | } |
741 | EXPORT_SYMBOL(tegra_powergate_remove_clamping); | |
742 | ||
743 | /** | |
744 | * tegra_powergate_sequence_power_up() - power up partition | |
745 | * @id: partition ID | |
746 | * @clk: clock for partition | |
747 | * @rst: reset for partition | |
748 | * | |
749 | * Must be called with clk disabled, and returns with clk enabled. | |
750 | */ | |
70293ed0 | 751 | int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, |
7232398a TR |
752 | struct reset_control *rst) |
753 | { | |
495ac33a | 754 | struct tegra_powergate *pg; |
a3804512 | 755 | int err; |
7232398a | 756 | |
589997a1 | 757 | if (!tegra_powergate_is_available(pmc, id)) |
403db2d2 JH |
758 | return -EINVAL; |
759 | ||
495ac33a VK |
760 | pg = kzalloc(sizeof(*pg), GFP_KERNEL); |
761 | if (!pg) | |
762 | return -ENOMEM; | |
7232398a | 763 | |
495ac33a VK |
764 | pg->id = id; |
765 | pg->clks = &clk; | |
766 | pg->num_clks = 1; | |
767 | pg->reset = rst; | |
768 | pg->pmc = pmc; | |
769 | ||
770 | err = tegra_powergate_power_up(pg, false); | |
a3804512 | 771 | if (err) |
589997a1 TR |
772 | dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, |
773 | err); | |
7232398a | 774 | |
495ac33a VK |
775 | kfree(pg); |
776 | ||
a3804512 | 777 | return err; |
7232398a TR |
778 | } |
779 | EXPORT_SYMBOL(tegra_powergate_sequence_power_up); | |
780 | ||
7232398a TR |
781 | /** |
782 | * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID | |
589997a1 | 783 | * @pmc: power management controller |
7232398a TR |
784 | * @cpuid: CPU partition ID |
785 | * | |
786 | * Returns the partition ID corresponding to the CPU partition ID or a | |
787 | * negative error code on failure. | |
788 | */ | |
589997a1 TR |
789 | static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, |
790 | unsigned int cpuid) | |
7232398a | 791 | { |
70293ed0 | 792 | if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) |
7232398a TR |
793 | return pmc->soc->cpu_powergates[cpuid]; |
794 | ||
795 | return -EINVAL; | |
796 | } | |
797 | ||
798 | /** | |
799 | * tegra_pmc_cpu_is_powered() - check if CPU partition is powered | |
800 | * @cpuid: CPU partition ID | |
801 | */ | |
70293ed0 | 802 | bool tegra_pmc_cpu_is_powered(unsigned int cpuid) |
7232398a TR |
803 | { |
804 | int id; | |
805 | ||
589997a1 | 806 | id = tegra_get_cpu_powergate_id(pmc, cpuid); |
7232398a TR |
807 | if (id < 0) |
808 | return false; | |
809 | ||
589997a1 | 810 | return tegra_powergate_is_powered(pmc, id); |
7232398a TR |
811 | } |
812 | ||
813 | /** | |
814 | * tegra_pmc_cpu_power_on() - power on CPU partition | |
815 | * @cpuid: CPU partition ID | |
816 | */ | |
70293ed0 | 817 | int tegra_pmc_cpu_power_on(unsigned int cpuid) |
7232398a TR |
818 | { |
819 | int id; | |
820 | ||
589997a1 | 821 | id = tegra_get_cpu_powergate_id(pmc, cpuid); |
7232398a TR |
822 | if (id < 0) |
823 | return id; | |
824 | ||
589997a1 | 825 | return tegra_powergate_set(pmc, id, true); |
7232398a TR |
826 | } |
827 | ||
828 | /** | |
829 | * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition | |
830 | * @cpuid: CPU partition ID | |
831 | */ | |
70293ed0 | 832 | int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) |
7232398a TR |
833 | { |
834 | int id; | |
835 | ||
589997a1 | 836 | id = tegra_get_cpu_powergate_id(pmc, cpuid); |
7232398a TR |
837 | if (id < 0) |
838 | return id; | |
839 | ||
840 | return tegra_powergate_remove_clamping(id); | |
841 | } | |
7232398a | 842 | |
7892158a DR |
843 | static int tegra_pmc_restart_notify(struct notifier_block *this, |
844 | unsigned long action, void *data) | |
7232398a | 845 | { |
7892158a | 846 | const char *cmd = data; |
7232398a TR |
847 | u32 value; |
848 | ||
e247deae | 849 | value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); |
7232398a TR |
850 | value &= ~PMC_SCRATCH0_MODE_MASK; |
851 | ||
852 | if (cmd) { | |
853 | if (strcmp(cmd, "recovery") == 0) | |
854 | value |= PMC_SCRATCH0_MODE_RECOVERY; | |
855 | ||
856 | if (strcmp(cmd, "bootloader") == 0) | |
857 | value |= PMC_SCRATCH0_MODE_BOOTLOADER; | |
858 | ||
859 | if (strcmp(cmd, "forced-recovery") == 0) | |
860 | value |= PMC_SCRATCH0_MODE_RCM; | |
861 | } | |
862 | ||
e247deae | 863 | tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); |
7232398a | 864 | |
f5353c60 | 865 | /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ |
589997a1 | 866 | value = tegra_pmc_readl(pmc, PMC_CNTRL); |
f5353c60 | 867 | value |= PMC_CNTRL_MAIN_RST; |
589997a1 | 868 | tegra_pmc_writel(pmc, value, PMC_CNTRL); |
7892158a DR |
869 | |
870 | return NOTIFY_DONE; | |
7232398a TR |
871 | } |
872 | ||
7892158a DR |
873 | static struct notifier_block tegra_pmc_restart_handler = { |
874 | .notifier_call = tegra_pmc_restart_notify, | |
875 | .priority = 128, | |
876 | }; | |
877 | ||
7232398a TR |
878 | static int powergate_show(struct seq_file *s, void *data) |
879 | { | |
880 | unsigned int i; | |
c3ea2972 | 881 | int status; |
7232398a TR |
882 | |
883 | seq_printf(s, " powergate powered\n"); | |
884 | seq_printf(s, "------------------\n"); | |
885 | ||
886 | for (i = 0; i < pmc->soc->num_powergates; i++) { | |
589997a1 | 887 | status = tegra_powergate_is_powered(pmc, i); |
c3ea2972 | 888 | if (status < 0) |
7232398a TR |
889 | continue; |
890 | ||
891 | seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], | |
c3ea2972 | 892 | status ? "yes" : "no"); |
7232398a TR |
893 | } |
894 | ||
895 | return 0; | |
896 | } | |
897 | ||
57ba33d5 | 898 | DEFINE_SHOW_ATTRIBUTE(powergate); |
7232398a TR |
899 | |
900 | static int tegra_powergate_debugfs_init(void) | |
901 | { | |
3195ac6d JH |
902 | pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, |
903 | &powergate_fops); | |
904 | if (!pmc->debugfs) | |
7232398a TR |
905 | return -ENOMEM; |
906 | ||
907 | return 0; | |
908 | } | |
909 | ||
a3804512 JH |
910 | static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, |
911 | struct device_node *np) | |
912 | { | |
913 | struct clk *clk; | |
914 | unsigned int i, count; | |
915 | int err; | |
916 | ||
3fd0121b | 917 | count = of_clk_get_parent_count(np); |
a3804512 JH |
918 | if (count == 0) |
919 | return -ENODEV; | |
920 | ||
921 | pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); | |
922 | if (!pg->clks) | |
923 | return -ENOMEM; | |
924 | ||
925 | for (i = 0; i < count; i++) { | |
926 | pg->clks[i] = of_clk_get(np, i); | |
927 | if (IS_ERR(pg->clks[i])) { | |
928 | err = PTR_ERR(pg->clks[i]); | |
929 | goto err; | |
930 | } | |
931 | } | |
932 | ||
933 | pg->num_clks = count; | |
934 | ||
935 | return 0; | |
936 | ||
937 | err: | |
938 | while (i--) | |
939 | clk_put(pg->clks[i]); | |
da8f4b45 | 940 | |
a3804512 JH |
941 | kfree(pg->clks); |
942 | ||
943 | return err; | |
944 | } | |
945 | ||
946 | static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, | |
05cfb988 | 947 | struct device_node *np, bool off) |
a3804512 | 948 | { |
589997a1 | 949 | struct device *dev = pg->pmc->dev; |
a3804512 JH |
950 | int err; |
951 | ||
7fe5719b | 952 | pg->reset = of_reset_control_array_get_exclusive_released(np); |
4c817ccf VG |
953 | if (IS_ERR(pg->reset)) { |
954 | err = PTR_ERR(pg->reset); | |
589997a1 | 955 | dev_err(dev, "failed to get device resets: %d\n", err); |
4c817ccf | 956 | return err; |
a3804512 JH |
957 | } |
958 | ||
7fe5719b TR |
959 | err = reset_control_acquire(pg->reset); |
960 | if (err < 0) { | |
961 | pr_err("failed to acquire resets: %d\n", err); | |
962 | goto out; | |
963 | } | |
964 | ||
965 | if (off) { | |
4c817ccf | 966 | err = reset_control_assert(pg->reset); |
7fe5719b | 967 | } else { |
4c817ccf | 968 | err = reset_control_deassert(pg->reset); |
7fe5719b TR |
969 | if (err < 0) |
970 | goto out; | |
da8f4b45 | 971 | |
7fe5719b TR |
972 | reset_control_release(pg->reset); |
973 | } | |
974 | ||
975 | out: | |
976 | if (err) { | |
977 | reset_control_release(pg->reset); | |
4c817ccf | 978 | reset_control_put(pg->reset); |
7fe5719b | 979 | } |
a3804512 JH |
980 | |
981 | return err; | |
982 | } | |
983 | ||
6ac2a01d | 984 | static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) |
a3804512 | 985 | { |
589997a1 | 986 | struct device *dev = pmc->dev; |
a3804512 | 987 | struct tegra_powergate *pg; |
6ac2a01d | 988 | int id, err = 0; |
a3804512 | 989 | bool off; |
a3804512 JH |
990 | |
991 | pg = kzalloc(sizeof(*pg), GFP_KERNEL); | |
992 | if (!pg) | |
6ac2a01d | 993 | return -ENOMEM; |
a3804512 JH |
994 | |
995 | id = tegra_powergate_lookup(pmc, np->name); | |
c2710ac9 | 996 | if (id < 0) { |
589997a1 | 997 | dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id); |
6ac2a01d | 998 | err = -ENODEV; |
a3804512 | 999 | goto free_mem; |
c2710ac9 | 1000 | } |
a3804512 JH |
1001 | |
1002 | /* | |
1003 | * Clear the bit for this powergate so it cannot be managed | |
1004 | * directly via the legacy APIs for controlling powergates. | |
1005 | */ | |
1006 | clear_bit(id, pmc->powergates_available); | |
1007 | ||
1008 | pg->id = id; | |
1009 | pg->genpd.name = np->name; | |
1010 | pg->genpd.power_off = tegra_genpd_power_off; | |
1011 | pg->genpd.power_on = tegra_genpd_power_on; | |
1012 | pg->pmc = pmc; | |
1013 | ||
589997a1 | 1014 | off = !tegra_powergate_is_powered(pmc, pg->id); |
05cfb988 | 1015 | |
c2710ac9 JH |
1016 | err = tegra_powergate_of_get_clks(pg, np); |
1017 | if (err < 0) { | |
589997a1 | 1018 | dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err); |
a3804512 | 1019 | goto set_available; |
c2710ac9 | 1020 | } |
a3804512 | 1021 | |
c2710ac9 JH |
1022 | err = tegra_powergate_of_get_resets(pg, np, off); |
1023 | if (err < 0) { | |
589997a1 | 1024 | dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err); |
a3804512 | 1025 | goto remove_clks; |
c2710ac9 | 1026 | } |
a3804512 | 1027 | |
0b137340 JH |
1028 | if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { |
1029 | if (off) | |
1030 | WARN_ON(tegra_powergate_power_up(pg, true)); | |
1031 | ||
1032 | goto remove_resets; | |
1033 | } | |
e2d17960 | 1034 | |
cd5ceda2 JH |
1035 | err = pm_genpd_init(&pg->genpd, NULL, off); |
1036 | if (err < 0) { | |
589997a1 | 1037 | dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np, |
cd5ceda2 JH |
1038 | err); |
1039 | goto remove_resets; | |
1040 | } | |
a3804512 | 1041 | |
c2710ac9 JH |
1042 | err = of_genpd_add_provider_simple(np, &pg->genpd); |
1043 | if (err < 0) { | |
589997a1 TR |
1044 | dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n", |
1045 | np, err); | |
0b137340 | 1046 | goto remove_genpd; |
c2710ac9 | 1047 | } |
a3804512 | 1048 | |
589997a1 | 1049 | dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); |
a3804512 | 1050 | |
6ac2a01d | 1051 | return 0; |
a3804512 | 1052 | |
0b137340 JH |
1053 | remove_genpd: |
1054 | pm_genpd_remove(&pg->genpd); | |
e2d17960 | 1055 | |
a3804512 | 1056 | remove_resets: |
4c817ccf | 1057 | reset_control_put(pg->reset); |
a3804512 JH |
1058 | |
1059 | remove_clks: | |
1060 | while (pg->num_clks--) | |
1061 | clk_put(pg->clks[pg->num_clks]); | |
da8f4b45 | 1062 | |
a3804512 JH |
1063 | kfree(pg->clks); |
1064 | ||
1065 | set_available: | |
1066 | set_bit(id, pmc->powergates_available); | |
1067 | ||
1068 | free_mem: | |
1069 | kfree(pg); | |
6ac2a01d JH |
1070 | |
1071 | return err; | |
a3804512 JH |
1072 | } |
1073 | ||
6ac2a01d JH |
1074 | static int tegra_powergate_init(struct tegra_pmc *pmc, |
1075 | struct device_node *parent) | |
a3804512 JH |
1076 | { |
1077 | struct device_node *np, *child; | |
6ac2a01d JH |
1078 | int err = 0; |
1079 | ||
1080 | np = of_get_child_by_name(parent, "powergates"); | |
1081 | if (!np) | |
1082 | return 0; | |
a3804512 | 1083 | |
6ac2a01d JH |
1084 | for_each_child_of_node(np, child) { |
1085 | err = tegra_powergate_add(pmc, child); | |
1086 | if (err < 0) { | |
1087 | of_node_put(child); | |
1088 | break; | |
1089 | } | |
1090 | } | |
1091 | ||
1092 | of_node_put(np); | |
1093 | ||
1094 | return err; | |
1095 | } | |
1096 | ||
1097 | static void tegra_powergate_remove(struct generic_pm_domain *genpd) | |
1098 | { | |
1099 | struct tegra_powergate *pg = to_powergate(genpd); | |
1100 | ||
1101 | reset_control_put(pg->reset); | |
1102 | ||
1103 | while (pg->num_clks--) | |
1104 | clk_put(pg->clks[pg->num_clks]); | |
1105 | ||
1106 | kfree(pg->clks); | |
1107 | ||
1108 | set_bit(pg->id, pmc->powergates_available); | |
1109 | ||
1110 | kfree(pg); | |
1111 | } | |
1112 | ||
1113 | static void tegra_powergate_remove_all(struct device_node *parent) | |
1114 | { | |
1115 | struct generic_pm_domain *genpd; | |
1116 | struct device_node *np, *child; | |
e2d17960 JH |
1117 | |
1118 | np = of_get_child_by_name(parent, "powergates"); | |
a3804512 JH |
1119 | if (!np) |
1120 | return; | |
1121 | ||
6ac2a01d JH |
1122 | for_each_child_of_node(np, child) { |
1123 | of_genpd_del_provider(child); | |
1124 | ||
1125 | genpd = of_genpd_remove_last(child); | |
1126 | if (IS_ERR(genpd)) | |
1127 | continue; | |
1128 | ||
1129 | tegra_powergate_remove(genpd); | |
1130 | } | |
a3804512 JH |
1131 | |
1132 | of_node_put(np); | |
1133 | } | |
1134 | ||
21b49910 LD |
1135 | static const struct tegra_io_pad_soc * |
1136 | tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) | |
1137 | { | |
1138 | unsigned int i; | |
1139 | ||
1140 | for (i = 0; i < pmc->soc->num_io_pads; i++) | |
1141 | if (pmc->soc->io_pads[i].id == id) | |
1142 | return &pmc->soc->io_pads[i]; | |
1143 | ||
1144 | return NULL; | |
1145 | } | |
1146 | ||
589997a1 TR |
1147 | static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc, |
1148 | enum tegra_io_pad id, | |
00ead3c9 AV |
1149 | unsigned long *request, |
1150 | unsigned long *status, | |
1151 | u32 *mask) | |
7232398a | 1152 | { |
21b49910 | 1153 | const struct tegra_io_pad_soc *pad; |
7232398a | 1154 | |
21b49910 | 1155 | pad = tegra_io_pad_find(pmc, id); |
54e24721 | 1156 | if (!pad) { |
589997a1 | 1157 | dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); |
21b49910 | 1158 | return -ENOENT; |
54e24721 | 1159 | } |
7232398a | 1160 | |
21b49910 LD |
1161 | if (pad->dpd == UINT_MAX) |
1162 | return -ENOTSUPP; | |
7232398a | 1163 | |
27b12b4e | 1164 | *mask = BIT(pad->dpd % 32); |
21b49910 LD |
1165 | |
1166 | if (pad->dpd < 32) { | |
5be22556 TR |
1167 | *status = pmc->soc->regs->dpd_status; |
1168 | *request = pmc->soc->regs->dpd_req; | |
7232398a | 1169 | } else { |
5be22556 TR |
1170 | *status = pmc->soc->regs->dpd2_status; |
1171 | *request = pmc->soc->regs->dpd2_req; | |
7232398a TR |
1172 | } |
1173 | ||
00ead3c9 AV |
1174 | return 0; |
1175 | } | |
1176 | ||
589997a1 TR |
1177 | static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id, |
1178 | unsigned long *request, unsigned long *status, | |
1179 | u32 *mask) | |
00ead3c9 AV |
1180 | { |
1181 | unsigned long rate, value; | |
1182 | int err; | |
1183 | ||
589997a1 | 1184 | err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask); |
00ead3c9 AV |
1185 | if (err) |
1186 | return err; | |
1187 | ||
5be22556 TR |
1188 | if (pmc->clk) { |
1189 | rate = clk_get_rate(pmc->clk); | |
1190 | if (!rate) { | |
589997a1 | 1191 | dev_err(pmc->dev, "failed to get clock rate\n"); |
5be22556 TR |
1192 | return -ENODEV; |
1193 | } | |
7232398a | 1194 | |
589997a1 | 1195 | tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); |
7232398a | 1196 | |
5be22556 TR |
1197 | /* must be at least 200 ns, in APB (PCLK) clock cycles */ |
1198 | value = DIV_ROUND_UP(1000000000, rate); | |
1199 | value = DIV_ROUND_UP(200, value); | |
589997a1 | 1200 | tegra_pmc_writel(pmc, value, SEL_DPD_TIM); |
5be22556 | 1201 | } |
7232398a TR |
1202 | |
1203 | return 0; | |
1204 | } | |
1205 | ||
589997a1 TR |
1206 | static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, |
1207 | u32 mask, u32 val, unsigned long timeout) | |
7232398a | 1208 | { |
84cf85ea | 1209 | u32 value; |
7232398a TR |
1210 | |
1211 | timeout = jiffies + msecs_to_jiffies(timeout); | |
1212 | ||
1213 | while (time_after(timeout, jiffies)) { | |
589997a1 | 1214 | value = tegra_pmc_readl(pmc, offset); |
7232398a TR |
1215 | if ((value & mask) == val) |
1216 | return 0; | |
1217 | ||
1218 | usleep_range(250, 1000); | |
1219 | } | |
1220 | ||
1221 | return -ETIMEDOUT; | |
1222 | } | |
1223 | ||
589997a1 | 1224 | static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) |
7232398a | 1225 | { |
5be22556 | 1226 | if (pmc->clk) |
589997a1 | 1227 | tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); |
7232398a TR |
1228 | } |
1229 | ||
21b49910 LD |
1230 | /** |
1231 | * tegra_io_pad_power_enable() - enable power to I/O pad | |
1232 | * @id: Tegra I/O pad ID for which to enable power | |
1233 | * | |
1234 | * Returns: 0 on success or a negative error code on failure. | |
1235 | */ | |
1236 | int tegra_io_pad_power_enable(enum tegra_io_pad id) | |
7232398a | 1237 | { |
a9ccc123 | 1238 | unsigned long request, status; |
27b12b4e | 1239 | u32 mask; |
7232398a TR |
1240 | int err; |
1241 | ||
e8cf6616 JH |
1242 | mutex_lock(&pmc->powergates_lock); |
1243 | ||
589997a1 | 1244 | err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); |
21b49910 | 1245 | if (err < 0) { |
589997a1 | 1246 | dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); |
21b49910 LD |
1247 | goto unlock; |
1248 | } | |
7232398a | 1249 | |
589997a1 | 1250 | tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); |
7232398a | 1251 | |
589997a1 | 1252 | err = tegra_io_pad_poll(pmc, status, mask, 0, 250); |
21b49910 | 1253 | if (err < 0) { |
589997a1 | 1254 | dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); |
21b49910 | 1255 | goto unlock; |
592431b0 | 1256 | } |
7232398a | 1257 | |
589997a1 | 1258 | tegra_io_pad_unprepare(pmc); |
7232398a | 1259 | |
21b49910 | 1260 | unlock: |
e8cf6616 | 1261 | mutex_unlock(&pmc->powergates_lock); |
e8cf6616 | 1262 | return err; |
7232398a | 1263 | } |
21b49910 | 1264 | EXPORT_SYMBOL(tegra_io_pad_power_enable); |
7232398a | 1265 | |
21b49910 LD |
1266 | /** |
1267 | * tegra_io_pad_power_disable() - disable power to I/O pad | |
1268 | * @id: Tegra I/O pad ID for which to disable power | |
1269 | * | |
1270 | * Returns: 0 on success or a negative error code on failure. | |
1271 | */ | |
1272 | int tegra_io_pad_power_disable(enum tegra_io_pad id) | |
7232398a | 1273 | { |
a9ccc123 | 1274 | unsigned long request, status; |
27b12b4e | 1275 | u32 mask; |
7232398a TR |
1276 | int err; |
1277 | ||
e8cf6616 JH |
1278 | mutex_lock(&pmc->powergates_lock); |
1279 | ||
589997a1 | 1280 | err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); |
21b49910 | 1281 | if (err < 0) { |
589997a1 | 1282 | dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); |
21b49910 | 1283 | goto unlock; |
592431b0 | 1284 | } |
7232398a | 1285 | |
589997a1 | 1286 | tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); |
7232398a | 1287 | |
589997a1 | 1288 | err = tegra_io_pad_poll(pmc, status, mask, mask, 250); |
21b49910 | 1289 | if (err < 0) { |
589997a1 | 1290 | dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); |
21b49910 LD |
1291 | goto unlock; |
1292 | } | |
7232398a | 1293 | |
589997a1 | 1294 | tegra_io_pad_unprepare(pmc); |
7232398a | 1295 | |
21b49910 | 1296 | unlock: |
e8cf6616 | 1297 | mutex_unlock(&pmc->powergates_lock); |
e8cf6616 | 1298 | return err; |
7232398a | 1299 | } |
21b49910 LD |
1300 | EXPORT_SYMBOL(tegra_io_pad_power_disable); |
1301 | ||
589997a1 | 1302 | static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) |
f142b9d6 AV |
1303 | { |
1304 | unsigned long request, status; | |
1305 | u32 mask, value; | |
1306 | int err; | |
1307 | ||
589997a1 TR |
1308 | err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status, |
1309 | &mask); | |
f142b9d6 AV |
1310 | if (err) |
1311 | return err; | |
1312 | ||
589997a1 | 1313 | value = tegra_pmc_readl(pmc, status); |
f142b9d6 AV |
1314 | |
1315 | return !(value & mask); | |
1316 | } | |
1317 | ||
589997a1 TR |
1318 | static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, |
1319 | int voltage) | |
21b49910 LD |
1320 | { |
1321 | const struct tegra_io_pad_soc *pad; | |
1322 | u32 value; | |
1323 | ||
1324 | pad = tegra_io_pad_find(pmc, id); | |
1325 | if (!pad) | |
1326 | return -ENOENT; | |
1327 | ||
1328 | if (pad->voltage == UINT_MAX) | |
1329 | return -ENOTSUPP; | |
1330 | ||
1331 | mutex_lock(&pmc->powergates_lock); | |
1332 | ||
13136a47 | 1333 | if (pmc->soc->has_impl_33v_pwr) { |
589997a1 | 1334 | value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); |
21b49910 | 1335 | |
fccf0f76 | 1336 | if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) |
13136a47 AV |
1337 | value &= ~BIT(pad->voltage); |
1338 | else | |
1339 | value |= BIT(pad->voltage); | |
21b49910 | 1340 | |
589997a1 | 1341 | tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR); |
13136a47 AV |
1342 | } else { |
1343 | /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ | |
589997a1 | 1344 | value = tegra_pmc_readl(pmc, PMC_PWR_DET); |
21b49910 | 1345 | value |= BIT(pad->voltage); |
589997a1 | 1346 | tegra_pmc_writel(pmc, value, PMC_PWR_DET); |
21b49910 | 1347 | |
13136a47 | 1348 | /* update I/O voltage */ |
589997a1 | 1349 | value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); |
21b49910 | 1350 | |
fccf0f76 | 1351 | if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) |
13136a47 AV |
1352 | value &= ~BIT(pad->voltage); |
1353 | else | |
1354 | value |= BIT(pad->voltage); | |
1355 | ||
589997a1 | 1356 | tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE); |
13136a47 | 1357 | } |
21b49910 LD |
1358 | |
1359 | mutex_unlock(&pmc->powergates_lock); | |
1360 | ||
1361 | usleep_range(100, 250); | |
1362 | ||
1363 | return 0; | |
1364 | } | |
21b49910 | 1365 | |
589997a1 | 1366 | static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) |
21b49910 LD |
1367 | { |
1368 | const struct tegra_io_pad_soc *pad; | |
1369 | u32 value; | |
1370 | ||
1371 | pad = tegra_io_pad_find(pmc, id); | |
1372 | if (!pad) | |
1373 | return -ENOENT; | |
1374 | ||
1375 | if (pad->voltage == UINT_MAX) | |
1376 | return -ENOTSUPP; | |
1377 | ||
13136a47 | 1378 | if (pmc->soc->has_impl_33v_pwr) |
589997a1 | 1379 | value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); |
13136a47 | 1380 | else |
589997a1 | 1381 | value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); |
21b49910 LD |
1382 | |
1383 | if ((value & BIT(pad->voltage)) == 0) | |
fccf0f76 | 1384 | return TEGRA_IO_PAD_VOLTAGE_1V8; |
21b49910 | 1385 | |
fccf0f76 | 1386 | return TEGRA_IO_PAD_VOLTAGE_3V3; |
21b49910 | 1387 | } |
21b49910 LD |
1388 | |
1389 | /** | |
1390 | * tegra_io_rail_power_on() - enable power to I/O rail | |
1391 | * @id: Tegra I/O pad ID for which to enable power | |
1392 | * | |
1393 | * See also: tegra_io_pad_power_enable() | |
1394 | */ | |
1395 | int tegra_io_rail_power_on(unsigned int id) | |
1396 | { | |
1397 | return tegra_io_pad_power_enable(id); | |
1398 | } | |
1399 | EXPORT_SYMBOL(tegra_io_rail_power_on); | |
1400 | ||
1401 | /** | |
1402 | * tegra_io_rail_power_off() - disable power to I/O rail | |
1403 | * @id: Tegra I/O pad ID for which to disable power | |
1404 | * | |
1405 | * See also: tegra_io_pad_power_disable() | |
1406 | */ | |
1407 | int tegra_io_rail_power_off(unsigned int id) | |
1408 | { | |
1409 | return tegra_io_pad_power_disable(id); | |
1410 | } | |
7232398a TR |
1411 | EXPORT_SYMBOL(tegra_io_rail_power_off); |
1412 | ||
1413 | #ifdef CONFIG_PM_SLEEP | |
1414 | enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) | |
1415 | { | |
1416 | return pmc->suspend_mode; | |
1417 | } | |
1418 | ||
1419 | void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) | |
1420 | { | |
1421 | if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) | |
1422 | return; | |
1423 | ||
1424 | pmc->suspend_mode = mode; | |
1425 | } | |
1426 | ||
1427 | void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) | |
1428 | { | |
1429 | unsigned long long rate = 0; | |
1430 | u32 value; | |
1431 | ||
1432 | switch (mode) { | |
1433 | case TEGRA_SUSPEND_LP1: | |
1434 | rate = 32768; | |
1435 | break; | |
1436 | ||
1437 | case TEGRA_SUSPEND_LP2: | |
1438 | rate = clk_get_rate(pmc->clk); | |
1439 | break; | |
1440 | ||
1441 | default: | |
1442 | break; | |
1443 | } | |
1444 | ||
1445 | if (WARN_ON_ONCE(rate == 0)) | |
1446 | rate = 100000000; | |
1447 | ||
1448 | if (rate != pmc->rate) { | |
1449 | u64 ticks; | |
1450 | ||
1451 | ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; | |
1452 | do_div(ticks, USEC_PER_SEC); | |
589997a1 | 1453 | tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); |
7232398a TR |
1454 | |
1455 | ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; | |
1456 | do_div(ticks, USEC_PER_SEC); | |
589997a1 | 1457 | tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); |
7232398a TR |
1458 | |
1459 | wmb(); | |
1460 | ||
1461 | pmc->rate = rate; | |
1462 | } | |
1463 | ||
589997a1 | 1464 | value = tegra_pmc_readl(pmc, PMC_CNTRL); |
7232398a TR |
1465 | value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; |
1466 | value |= PMC_CNTRL_CPU_PWRREQ_OE; | |
589997a1 | 1467 | tegra_pmc_writel(pmc, value, PMC_CNTRL); |
7232398a TR |
1468 | } |
1469 | #endif | |
1470 | ||
1471 | static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) | |
1472 | { | |
1473 | u32 value, values[2]; | |
1474 | ||
1475 | if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { | |
1476 | } else { | |
1477 | switch (value) { | |
1478 | case 0: | |
1479 | pmc->suspend_mode = TEGRA_SUSPEND_LP0; | |
1480 | break; | |
1481 | ||
1482 | case 1: | |
1483 | pmc->suspend_mode = TEGRA_SUSPEND_LP1; | |
1484 | break; | |
1485 | ||
1486 | case 2: | |
1487 | pmc->suspend_mode = TEGRA_SUSPEND_LP2; | |
1488 | break; | |
1489 | ||
1490 | default: | |
1491 | pmc->suspend_mode = TEGRA_SUSPEND_NONE; | |
1492 | break; | |
1493 | } | |
1494 | } | |
1495 | ||
1496 | pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); | |
1497 | ||
1498 | if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) | |
1499 | pmc->suspend_mode = TEGRA_SUSPEND_NONE; | |
1500 | ||
1501 | pmc->cpu_good_time = value; | |
1502 | ||
1503 | if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) | |
1504 | pmc->suspend_mode = TEGRA_SUSPEND_NONE; | |
1505 | ||
1506 | pmc->cpu_off_time = value; | |
1507 | ||
1508 | if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", | |
1509 | values, ARRAY_SIZE(values))) | |
1510 | pmc->suspend_mode = TEGRA_SUSPEND_NONE; | |
1511 | ||
1512 | pmc->core_osc_time = values[0]; | |
1513 | pmc->core_pmu_time = values[1]; | |
1514 | ||
1515 | if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) | |
1516 | pmc->suspend_mode = TEGRA_SUSPEND_NONE; | |
1517 | ||
1518 | pmc->core_off_time = value; | |
1519 | ||
1520 | pmc->corereq_high = of_property_read_bool(np, | |
1521 | "nvidia,core-power-req-active-high"); | |
1522 | ||
1523 | pmc->sysclkreq_high = of_property_read_bool(np, | |
1524 | "nvidia,sys-clock-req-active-high"); | |
1525 | ||
1526 | pmc->combined_req = of_property_read_bool(np, | |
1527 | "nvidia,combined-power-req"); | |
1528 | ||
1529 | pmc->cpu_pwr_good_en = of_property_read_bool(np, | |
1530 | "nvidia,cpu-pwr-good-en"); | |
1531 | ||
1532 | if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, | |
1533 | ARRAY_SIZE(values))) | |
1534 | if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) | |
1535 | pmc->suspend_mode = TEGRA_SUSPEND_LP1; | |
1536 | ||
1537 | pmc->lp0_vec_phys = values[0]; | |
1538 | pmc->lp0_vec_size = values[1]; | |
1539 | ||
1540 | return 0; | |
1541 | } | |
1542 | ||
1543 | static void tegra_pmc_init(struct tegra_pmc *pmc) | |
1544 | { | |
5be22556 TR |
1545 | if (pmc->soc->init) |
1546 | pmc->soc->init(pmc); | |
7232398a TR |
1547 | } |
1548 | ||
1e52efdf | 1549 | static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) |
3568df3d MP |
1550 | { |
1551 | static const char disabled[] = "emergency thermal reset disabled"; | |
1552 | u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; | |
1553 | struct device *dev = pmc->dev; | |
1554 | struct device_node *np; | |
1555 | u32 value, checksum; | |
1556 | ||
1557 | if (!pmc->soc->has_tsense_reset) | |
95169cd2 | 1558 | return; |
3568df3d | 1559 | |
1dc6bd5e | 1560 | np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); |
3568df3d MP |
1561 | if (!np) { |
1562 | dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); | |
95169cd2 | 1563 | return; |
3568df3d MP |
1564 | } |
1565 | ||
1566 | if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { | |
1567 | dev_err(dev, "I2C controller ID missing, %s.\n", disabled); | |
1568 | goto out; | |
1569 | } | |
1570 | ||
1571 | if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { | |
1572 | dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); | |
1573 | goto out; | |
1574 | } | |
1575 | ||
1576 | if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { | |
1577 | dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); | |
1578 | goto out; | |
1579 | } | |
1580 | ||
1581 | if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { | |
1582 | dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); | |
1583 | goto out; | |
1584 | } | |
1585 | ||
1586 | if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) | |
1587 | pinmux = 0; | |
1588 | ||
589997a1 | 1589 | value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); |
3568df3d | 1590 | value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; |
589997a1 | 1591 | tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); |
3568df3d MP |
1592 | |
1593 | value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | | |
1594 | (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); | |
589997a1 | 1595 | tegra_pmc_writel(pmc, value, PMC_SCRATCH54); |
3568df3d MP |
1596 | |
1597 | value = PMC_SCRATCH55_RESET_TEGRA; | |
1598 | value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; | |
1599 | value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; | |
1600 | value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; | |
1601 | ||
1602 | /* | |
1603 | * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will | |
1604 | * contain the checksum and are currently zero, so they are not added. | |
1605 | */ | |
1606 | checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) | |
1607 | + ((value >> 24) & 0xff); | |
1608 | checksum &= 0xff; | |
1609 | checksum = 0x100 - checksum; | |
1610 | ||
1611 | value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; | |
1612 | ||
589997a1 | 1613 | tegra_pmc_writel(pmc, value, PMC_SCRATCH55); |
3568df3d | 1614 | |
589997a1 | 1615 | value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); |
3568df3d | 1616 | value |= PMC_SENSOR_CTRL_ENABLE_RST; |
589997a1 | 1617 | tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); |
3568df3d MP |
1618 | |
1619 | dev_info(pmc->dev, "emergency thermal reset enabled\n"); | |
1620 | ||
1621 | out: | |
1622 | of_node_put(np); | |
3568df3d MP |
1623 | } |
1624 | ||
4a37f11c AV |
1625 | static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev) |
1626 | { | |
589997a1 TR |
1627 | struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); |
1628 | ||
4a37f11c AV |
1629 | return pmc->soc->num_io_pads; |
1630 | } | |
1631 | ||
f1d91299 TR |
1632 | static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl, |
1633 | unsigned int group) | |
4a37f11c | 1634 | { |
589997a1 TR |
1635 | struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); |
1636 | ||
4a37f11c AV |
1637 | return pmc->soc->io_pads[group].name; |
1638 | } | |
1639 | ||
1640 | static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev, | |
1641 | unsigned int group, | |
1642 | const unsigned int **pins, | |
1643 | unsigned int *num_pins) | |
1644 | { | |
589997a1 TR |
1645 | struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); |
1646 | ||
4a37f11c AV |
1647 | *pins = &pmc->soc->io_pads[group].id; |
1648 | *num_pins = 1; | |
f1d91299 | 1649 | |
4a37f11c AV |
1650 | return 0; |
1651 | } | |
1652 | ||
1653 | static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = { | |
1654 | .get_groups_count = tegra_io_pad_pinctrl_get_groups_count, | |
1655 | .get_group_name = tegra_io_pad_pinctrl_get_group_name, | |
1656 | .get_group_pins = tegra_io_pad_pinctrl_get_group_pins, | |
1657 | .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, | |
1658 | .dt_free_map = pinconf_generic_dt_free_map, | |
1659 | }; | |
1660 | ||
1661 | static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, | |
1662 | unsigned int pin, unsigned long *config) | |
1663 | { | |
4a37f11c | 1664 | enum pin_config_param param = pinconf_to_config_param(*config); |
589997a1 TR |
1665 | struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); |
1666 | const struct tegra_io_pad_soc *pad; | |
4a37f11c AV |
1667 | int ret; |
1668 | u32 arg; | |
1669 | ||
589997a1 | 1670 | pad = tegra_io_pad_find(pmc, pin); |
4a37f11c AV |
1671 | if (!pad) |
1672 | return -EINVAL; | |
1673 | ||
1674 | switch (param) { | |
1675 | case PIN_CONFIG_POWER_SOURCE: | |
589997a1 | 1676 | ret = tegra_io_pad_get_voltage(pmc, pad->id); |
4a37f11c AV |
1677 | if (ret < 0) |
1678 | return ret; | |
f1d91299 | 1679 | |
4a37f11c AV |
1680 | arg = ret; |
1681 | break; | |
f1d91299 | 1682 | |
4a37f11c | 1683 | case PIN_CONFIG_LOW_POWER_MODE: |
589997a1 | 1684 | ret = tegra_io_pad_is_powered(pmc, pad->id); |
4a37f11c AV |
1685 | if (ret < 0) |
1686 | return ret; | |
f1d91299 | 1687 | |
4a37f11c AV |
1688 | arg = !ret; |
1689 | break; | |
f1d91299 | 1690 | |
4a37f11c AV |
1691 | default: |
1692 | return -EINVAL; | |
1693 | } | |
1694 | ||
1695 | *config = pinconf_to_config_packed(param, arg); | |
1696 | ||
1697 | return 0; | |
1698 | } | |
1699 | ||
1700 | static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, | |
1701 | unsigned int pin, unsigned long *configs, | |
1702 | unsigned int num_configs) | |
1703 | { | |
589997a1 TR |
1704 | struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); |
1705 | const struct tegra_io_pad_soc *pad; | |
4a37f11c AV |
1706 | enum pin_config_param param; |
1707 | unsigned int i; | |
1708 | int err; | |
1709 | u32 arg; | |
1710 | ||
589997a1 | 1711 | pad = tegra_io_pad_find(pmc, pin); |
4a37f11c AV |
1712 | if (!pad) |
1713 | return -EINVAL; | |
1714 | ||
1715 | for (i = 0; i < num_configs; ++i) { | |
1716 | param = pinconf_to_config_param(configs[i]); | |
1717 | arg = pinconf_to_config_argument(configs[i]); | |
1718 | ||
1719 | switch (param) { | |
1720 | case PIN_CONFIG_LOW_POWER_MODE: | |
1721 | if (arg) | |
1722 | err = tegra_io_pad_power_disable(pad->id); | |
1723 | else | |
1724 | err = tegra_io_pad_power_enable(pad->id); | |
1725 | if (err) | |
1726 | return err; | |
1727 | break; | |
1728 | case PIN_CONFIG_POWER_SOURCE: | |
1729 | if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 && | |
1730 | arg != TEGRA_IO_PAD_VOLTAGE_3V3) | |
1731 | return -EINVAL; | |
589997a1 | 1732 | err = tegra_io_pad_set_voltage(pmc, pad->id, arg); |
4a37f11c AV |
1733 | if (err) |
1734 | return err; | |
1735 | break; | |
1736 | default: | |
1737 | return -EINVAL; | |
1738 | } | |
1739 | } | |
1740 | ||
1741 | return 0; | |
1742 | } | |
1743 | ||
1744 | static const struct pinconf_ops tegra_io_pad_pinconf_ops = { | |
1745 | .pin_config_get = tegra_io_pad_pinconf_get, | |
1746 | .pin_config_set = tegra_io_pad_pinconf_set, | |
1747 | .is_generic = true, | |
1748 | }; | |
1749 | ||
1750 | static struct pinctrl_desc tegra_pmc_pctl_desc = { | |
1751 | .pctlops = &tegra_io_pad_pinctrl_ops, | |
1752 | .confops = &tegra_io_pad_pinconf_ops, | |
1753 | }; | |
1754 | ||
1755 | static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) | |
1756 | { | |
f1d91299 | 1757 | int err; |
4a37f11c AV |
1758 | |
1759 | if (!pmc->soc->num_pin_descs) | |
1760 | return 0; | |
1761 | ||
1762 | tegra_pmc_pctl_desc.name = dev_name(pmc->dev); | |
1763 | tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; | |
1764 | tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; | |
1765 | ||
1766 | pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, | |
1767 | pmc); | |
1768 | if (IS_ERR(pmc->pctl_dev)) { | |
1769 | err = PTR_ERR(pmc->pctl_dev); | |
f1d91299 TR |
1770 | dev_err(pmc->dev, "failed to register pin controller: %d\n", |
1771 | err); | |
1772 | return err; | |
4a37f11c AV |
1773 | } |
1774 | ||
f1d91299 | 1775 | return 0; |
4a37f11c AV |
1776 | } |
1777 | ||
5f84bb1a | 1778 | static ssize_t reset_reason_show(struct device *dev, |
f1d91299 | 1779 | struct device_attribute *attr, char *buf) |
5f84bb1a | 1780 | { |
00cdaa1b | 1781 | u32 value; |
5f84bb1a | 1782 | |
589997a1 | 1783 | value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); |
00cdaa1b JH |
1784 | value &= pmc->soc->regs->rst_source_mask; |
1785 | value >>= pmc->soc->regs->rst_source_shift; | |
1786 | ||
1787 | if (WARN_ON(value >= pmc->soc->num_reset_sources)) | |
1788 | return sprintf(buf, "%s\n", "UNKNOWN"); | |
5f84bb1a | 1789 | |
00cdaa1b | 1790 | return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); |
5f84bb1a SP |
1791 | } |
1792 | ||
1793 | static DEVICE_ATTR_RO(reset_reason); | |
1794 | ||
1795 | static ssize_t reset_level_show(struct device *dev, | |
f1d91299 | 1796 | struct device_attribute *attr, char *buf) |
5f84bb1a | 1797 | { |
00cdaa1b | 1798 | u32 value; |
5f84bb1a | 1799 | |
589997a1 | 1800 | value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); |
00cdaa1b JH |
1801 | value &= pmc->soc->regs->rst_level_mask; |
1802 | value >>= pmc->soc->regs->rst_level_shift; | |
5f84bb1a | 1803 | |
00cdaa1b JH |
1804 | if (WARN_ON(value >= pmc->soc->num_reset_levels)) |
1805 | return sprintf(buf, "%s\n", "UNKNOWN"); | |
1806 | ||
1807 | return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); | |
5f84bb1a SP |
1808 | } |
1809 | ||
1810 | static DEVICE_ATTR_RO(reset_level); | |
1811 | ||
1812 | static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) | |
1813 | { | |
1814 | struct device *dev = pmc->dev; | |
1815 | int err = 0; | |
1816 | ||
1817 | if (pmc->soc->reset_sources) { | |
1818 | err = device_create_file(dev, &dev_attr_reset_reason); | |
1819 | if (err < 0) | |
1820 | dev_warn(dev, | |
f1d91299 TR |
1821 | "failed to create attr \"reset_reason\": %d\n", |
1822 | err); | |
5f84bb1a SP |
1823 | } |
1824 | ||
1825 | if (pmc->soc->reset_levels) { | |
1826 | err = device_create_file(dev, &dev_attr_reset_level); | |
1827 | if (err < 0) | |
1828 | dev_warn(dev, | |
f1d91299 TR |
1829 | "failed to create attr \"reset_level\": %d\n", |
1830 | err); | |
5f84bb1a SP |
1831 | } |
1832 | } | |
1833 | ||
19906e6b TR |
1834 | static int tegra_pmc_irq_translate(struct irq_domain *domain, |
1835 | struct irq_fwspec *fwspec, | |
1836 | unsigned long *hwirq, | |
1837 | unsigned int *type) | |
1838 | { | |
1839 | if (WARN_ON(fwspec->param_count < 2)) | |
1840 | return -EINVAL; | |
1841 | ||
1842 | *hwirq = fwspec->param[0]; | |
1843 | *type = fwspec->param[1]; | |
1844 | ||
1845 | return 0; | |
1846 | } | |
1847 | ||
1848 | static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq, | |
1849 | unsigned int num_irqs, void *data) | |
1850 | { | |
1851 | struct tegra_pmc *pmc = domain->host_data; | |
1852 | const struct tegra_pmc_soc *soc = pmc->soc; | |
1853 | struct irq_fwspec *fwspec = data; | |
1854 | unsigned int i; | |
1855 | int err = 0; | |
1856 | ||
1857 | for (i = 0; i < soc->num_wake_events; i++) { | |
1858 | const struct tegra_wake_event *event = &soc->wake_events[i]; | |
1859 | ||
1860 | if (fwspec->param_count == 2) { | |
1861 | struct irq_fwspec spec; | |
1862 | ||
1863 | if (event->id != fwspec->param[0]) | |
1864 | continue; | |
1865 | ||
1866 | err = irq_domain_set_hwirq_and_chip(domain, virq, | |
1867 | event->id, | |
1868 | &pmc->irq, pmc); | |
1869 | if (err < 0) | |
1870 | break; | |
1871 | ||
1872 | spec.fwnode = &pmc->dev->of_node->fwnode; | |
1873 | spec.param_count = 3; | |
1874 | spec.param[0] = GIC_SPI; | |
1875 | spec.param[1] = event->irq; | |
1876 | spec.param[2] = fwspec->param[1]; | |
1877 | ||
1878 | err = irq_domain_alloc_irqs_parent(domain, virq, | |
1879 | num_irqs, &spec); | |
1880 | ||
1881 | break; | |
1882 | } | |
1883 | ||
1884 | if (fwspec->param_count == 3) { | |
1885 | if (event->gpio.instance != fwspec->param[0] || | |
1886 | event->gpio.pin != fwspec->param[1]) | |
1887 | continue; | |
1888 | ||
1889 | err = irq_domain_set_hwirq_and_chip(domain, virq, | |
1890 | event->id, | |
1891 | &pmc->irq, pmc); | |
1892 | ||
1893 | break; | |
1894 | } | |
1895 | } | |
1896 | ||
1897 | if (i == soc->num_wake_events) | |
1898 | err = irq_domain_set_hwirq_and_chip(domain, virq, ULONG_MAX, | |
1899 | &pmc->irq, pmc); | |
1900 | ||
1901 | return err; | |
1902 | } | |
1903 | ||
1904 | static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { | |
1905 | .translate = tegra_pmc_irq_translate, | |
1906 | .alloc = tegra_pmc_irq_alloc, | |
1907 | }; | |
1908 | ||
1909 | static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on) | |
1910 | { | |
1911 | struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); | |
1912 | unsigned int offset, bit; | |
1913 | u32 value; | |
1914 | ||
1915 | offset = data->hwirq / 32; | |
1916 | bit = data->hwirq % 32; | |
1917 | ||
1918 | /* clear wake status */ | |
1919 | writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); | |
1920 | ||
1921 | /* route wake to tier 2 */ | |
1922 | value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); | |
1923 | ||
1924 | if (!on) | |
1925 | value &= ~(1 << bit); | |
1926 | else | |
1927 | value |= 1 << bit; | |
1928 | ||
1929 | writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); | |
1930 | ||
1931 | /* enable wakeup event */ | |
1932 | writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); | |
1933 | ||
1934 | return 0; | |
1935 | } | |
1936 | ||
1937 | static int tegra_pmc_irq_set_type(struct irq_data *data, unsigned int type) | |
1938 | { | |
1939 | struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); | |
1940 | u32 value; | |
1941 | ||
1942 | if (data->hwirq == ULONG_MAX) | |
1943 | return 0; | |
1944 | ||
1945 | value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); | |
1946 | ||
1947 | switch (type) { | |
1948 | case IRQ_TYPE_EDGE_RISING: | |
1949 | case IRQ_TYPE_LEVEL_HIGH: | |
1950 | value |= WAKE_AOWAKE_CNTRL_LEVEL; | |
1951 | break; | |
1952 | ||
1953 | case IRQ_TYPE_EDGE_FALLING: | |
1954 | case IRQ_TYPE_LEVEL_LOW: | |
1955 | value &= ~WAKE_AOWAKE_CNTRL_LEVEL; | |
1956 | break; | |
1957 | ||
1958 | case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: | |
1959 | value ^= WAKE_AOWAKE_CNTRL_LEVEL; | |
1960 | break; | |
1961 | ||
1962 | default: | |
1963 | return -EINVAL; | |
1964 | } | |
1965 | ||
1966 | writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); | |
1967 | ||
1968 | return 0; | |
1969 | } | |
1970 | ||
1971 | static int tegra_pmc_irq_init(struct tegra_pmc *pmc) | |
1972 | { | |
1973 | struct irq_domain *parent = NULL; | |
1974 | struct device_node *np; | |
1975 | ||
1976 | np = of_irq_find_parent(pmc->dev->of_node); | |
1977 | if (np) { | |
1978 | parent = irq_find_host(np); | |
1979 | of_node_put(np); | |
1980 | } | |
1981 | ||
1982 | if (!parent) | |
1983 | return 0; | |
1984 | ||
1985 | pmc->irq.name = dev_name(pmc->dev); | |
1986 | pmc->irq.irq_mask = irq_chip_mask_parent; | |
1987 | pmc->irq.irq_unmask = irq_chip_unmask_parent; | |
1988 | pmc->irq.irq_eoi = irq_chip_eoi_parent; | |
1989 | pmc->irq.irq_set_affinity = irq_chip_set_affinity_parent; | |
1990 | pmc->irq.irq_set_type = tegra_pmc_irq_set_type; | |
1991 | pmc->irq.irq_set_wake = tegra_pmc_irq_set_wake; | |
1992 | ||
1993 | pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, | |
1994 | &tegra_pmc_irq_domain_ops, pmc); | |
1995 | if (!pmc->domain) { | |
1996 | dev_err(pmc->dev, "failed to allocate domain\n"); | |
1997 | return -ENOMEM; | |
1998 | } | |
1999 | ||
2000 | return 0; | |
2001 | } | |
2002 | ||
7232398a TR |
2003 | static int tegra_pmc_probe(struct platform_device *pdev) |
2004 | { | |
e8cf6616 | 2005 | void __iomem *base; |
7232398a TR |
2006 | struct resource *res; |
2007 | int err; | |
2008 | ||
a83f1fc3 JH |
2009 | /* |
2010 | * Early initialisation should have configured an initial | |
2011 | * register mapping and setup the soc data pointer. If these | |
2012 | * are not valid then something went badly wrong! | |
2013 | */ | |
2014 | if (WARN_ON(!pmc->base || !pmc->soc)) | |
2015 | return -ENODEV; | |
2016 | ||
7232398a TR |
2017 | err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); |
2018 | if (err < 0) | |
2019 | return err; | |
2020 | ||
2021 | /* take over the memory region from the early initialization */ | |
2022 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
0259f522 JH |
2023 | base = devm_ioremap_resource(&pdev->dev, res); |
2024 | if (IS_ERR(base)) | |
2025 | return PTR_ERR(base); | |
7232398a | 2026 | |
c641ec6e TR |
2027 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); |
2028 | if (res) { | |
2029 | pmc->wake = devm_ioremap_resource(&pdev->dev, res); | |
2030 | if (IS_ERR(pmc->wake)) | |
2031 | return PTR_ERR(pmc->wake); | |
2032 | } else { | |
2033 | pmc->wake = base; | |
2034 | } | |
2035 | ||
2036 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); | |
2037 | if (res) { | |
2038 | pmc->aotag = devm_ioremap_resource(&pdev->dev, res); | |
2039 | if (IS_ERR(pmc->aotag)) | |
2040 | return PTR_ERR(pmc->aotag); | |
2041 | } else { | |
2042 | pmc->aotag = base; | |
2043 | } | |
2044 | ||
2045 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); | |
2046 | if (res) { | |
2047 | pmc->scratch = devm_ioremap_resource(&pdev->dev, res); | |
2048 | if (IS_ERR(pmc->scratch)) | |
2049 | return PTR_ERR(pmc->scratch); | |
2050 | } else { | |
2051 | pmc->scratch = base; | |
2052 | } | |
5be22556 | 2053 | |
7232398a TR |
2054 | pmc->clk = devm_clk_get(&pdev->dev, "pclk"); |
2055 | if (IS_ERR(pmc->clk)) { | |
2056 | err = PTR_ERR(pmc->clk); | |
5be22556 TR |
2057 | |
2058 | if (err != -ENOENT) { | |
2059 | dev_err(&pdev->dev, "failed to get pclk: %d\n", err); | |
2060 | return err; | |
2061 | } | |
2062 | ||
2063 | pmc->clk = NULL; | |
7232398a TR |
2064 | } |
2065 | ||
3568df3d MP |
2066 | pmc->dev = &pdev->dev; |
2067 | ||
7232398a TR |
2068 | tegra_pmc_init(pmc); |
2069 | ||
3568df3d MP |
2070 | tegra_pmc_init_tsense_reset(pmc); |
2071 | ||
5f84bb1a SP |
2072 | tegra_pmc_reset_sysfs_init(pmc); |
2073 | ||
7232398a TR |
2074 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
2075 | err = tegra_powergate_debugfs_init(); | |
2076 | if (err < 0) | |
a46b51cd | 2077 | goto cleanup_sysfs; |
7892158a DR |
2078 | } |
2079 | ||
2080 | err = register_restart_handler(&tegra_pmc_restart_handler); | |
2081 | if (err) { | |
2082 | dev_err(&pdev->dev, "unable to register restart handler, %d\n", | |
2083 | err); | |
4a37f11c | 2084 | goto cleanup_debugfs; |
7232398a TR |
2085 | } |
2086 | ||
4a37f11c AV |
2087 | err = tegra_pmc_pinctrl_init(pmc); |
2088 | if (err) | |
2089 | goto cleanup_restart_handler; | |
2090 | ||
6ac2a01d JH |
2091 | err = tegra_powergate_init(pmc, pdev->dev.of_node); |
2092 | if (err < 0) | |
2093 | goto cleanup_powergates; | |
2094 | ||
19906e6b TR |
2095 | err = tegra_pmc_irq_init(pmc); |
2096 | if (err < 0) | |
6ac2a01d | 2097 | goto cleanup_powergates; |
19906e6b | 2098 | |
e8cf6616 JH |
2099 | mutex_lock(&pmc->powergates_lock); |
2100 | iounmap(pmc->base); | |
0259f522 | 2101 | pmc->base = base; |
e8cf6616 | 2102 | mutex_unlock(&pmc->powergates_lock); |
0259f522 | 2103 | |
589997a1 TR |
2104 | platform_set_drvdata(pdev, pmc); |
2105 | ||
7232398a | 2106 | return 0; |
4a37f11c | 2107 | |
6ac2a01d JH |
2108 | cleanup_powergates: |
2109 | tegra_powergate_remove_all(pdev->dev.of_node); | |
4a37f11c AV |
2110 | cleanup_restart_handler: |
2111 | unregister_restart_handler(&tegra_pmc_restart_handler); | |
2112 | cleanup_debugfs: | |
2113 | debugfs_remove(pmc->debugfs); | |
a46b51cd JH |
2114 | cleanup_sysfs: |
2115 | device_remove_file(&pdev->dev, &dev_attr_reset_reason); | |
2116 | device_remove_file(&pdev->dev, &dev_attr_reset_level); | |
4a37f11c | 2117 | return err; |
7232398a TR |
2118 | } |
2119 | ||
2b20b616 | 2120 | #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) |
7232398a TR |
2121 | static int tegra_pmc_suspend(struct device *dev) |
2122 | { | |
589997a1 TR |
2123 | struct tegra_pmc *pmc = dev_get_drvdata(dev); |
2124 | ||
2125 | tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); | |
7232398a TR |
2126 | |
2127 | return 0; | |
2128 | } | |
2129 | ||
2130 | static int tegra_pmc_resume(struct device *dev) | |
2131 | { | |
589997a1 TR |
2132 | struct tegra_pmc *pmc = dev_get_drvdata(dev); |
2133 | ||
2134 | tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); | |
7232398a TR |
2135 | |
2136 | return 0; | |
2137 | } | |
7232398a TR |
2138 | |
2139 | static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); | |
2140 | ||
2b20b616 PW |
2141 | #endif |
2142 | ||
7232398a TR |
2143 | static const char * const tegra20_powergates[] = { |
2144 | [TEGRA_POWERGATE_CPU] = "cpu", | |
2145 | [TEGRA_POWERGATE_3D] = "3d", | |
2146 | [TEGRA_POWERGATE_VENC] = "venc", | |
2147 | [TEGRA_POWERGATE_VDEC] = "vdec", | |
2148 | [TEGRA_POWERGATE_PCIE] = "pcie", | |
2149 | [TEGRA_POWERGATE_L2] = "l2", | |
2150 | [TEGRA_POWERGATE_MPE] = "mpe", | |
2151 | }; | |
2152 | ||
5be22556 TR |
2153 | static const struct tegra_pmc_regs tegra20_pmc_regs = { |
2154 | .scratch0 = 0x50, | |
2155 | .dpd_req = 0x1b8, | |
2156 | .dpd_status = 0x1bc, | |
2157 | .dpd2_req = 0x1c0, | |
2158 | .dpd2_status = 0x1c4, | |
5f84bb1a SP |
2159 | .rst_status = 0x1b4, |
2160 | .rst_source_shift = 0x0, | |
2161 | .rst_source_mask = 0x7, | |
2162 | .rst_level_shift = 0x0, | |
2163 | .rst_level_mask = 0x0, | |
5be22556 TR |
2164 | }; |
2165 | ||
2166 | static void tegra20_pmc_init(struct tegra_pmc *pmc) | |
2167 | { | |
2168 | u32 value; | |
2169 | ||
2170 | /* Always enable CPU power request */ | |
589997a1 | 2171 | value = tegra_pmc_readl(pmc, PMC_CNTRL); |
5be22556 | 2172 | value |= PMC_CNTRL_CPU_PWRREQ_OE; |
589997a1 | 2173 | tegra_pmc_writel(pmc, value, PMC_CNTRL); |
5be22556 | 2174 | |
589997a1 | 2175 | value = tegra_pmc_readl(pmc, PMC_CNTRL); |
5be22556 TR |
2176 | |
2177 | if (pmc->sysclkreq_high) | |
2178 | value &= ~PMC_CNTRL_SYSCLK_POLARITY; | |
2179 | else | |
2180 | value |= PMC_CNTRL_SYSCLK_POLARITY; | |
2181 | ||
2182 | /* configure the output polarity while the request is tristated */ | |
589997a1 | 2183 | tegra_pmc_writel(pmc, value, PMC_CNTRL); |
5be22556 TR |
2184 | |
2185 | /* now enable the request */ | |
589997a1 | 2186 | value = tegra_pmc_readl(pmc, PMC_CNTRL); |
5be22556 | 2187 | value |= PMC_CNTRL_SYSCLK_OE; |
589997a1 | 2188 | tegra_pmc_writel(pmc, value, PMC_CNTRL); |
5be22556 TR |
2189 | } |
2190 | ||
2191 | static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, | |
2192 | struct device_node *np, | |
2193 | bool invert) | |
2194 | { | |
2195 | u32 value; | |
2196 | ||
589997a1 | 2197 | value = tegra_pmc_readl(pmc, PMC_CNTRL); |
5be22556 TR |
2198 | |
2199 | if (invert) | |
2200 | value |= PMC_CNTRL_INTR_POLARITY; | |
2201 | else | |
2202 | value &= ~PMC_CNTRL_INTR_POLARITY; | |
2203 | ||
589997a1 | 2204 | tegra_pmc_writel(pmc, value, PMC_CNTRL); |
5be22556 TR |
2205 | } |
2206 | ||
7232398a TR |
2207 | static const struct tegra_pmc_soc tegra20_pmc_soc = { |
2208 | .num_powergates = ARRAY_SIZE(tegra20_powergates), | |
2209 | .powergates = tegra20_powergates, | |
2210 | .num_cpu_powergates = 0, | |
2211 | .cpu_powergates = NULL, | |
3568df3d | 2212 | .has_tsense_reset = false, |
a9a40a4a | 2213 | .has_gpu_clamps = false, |
fa3bc04e TR |
2214 | .needs_mbist_war = false, |
2215 | .has_impl_33v_pwr = false, | |
e247deae | 2216 | .maybe_tz_only = false, |
5be22556 TR |
2217 | .num_io_pads = 0, |
2218 | .io_pads = NULL, | |
4a37f11c AV |
2219 | .num_pin_descs = 0, |
2220 | .pin_descs = NULL, | |
5be22556 TR |
2221 | .regs = &tegra20_pmc_regs, |
2222 | .init = tegra20_pmc_init, | |
2223 | .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, | |
5f84bb1a SP |
2224 | .reset_sources = NULL, |
2225 | .num_reset_sources = 0, | |
2226 | .reset_levels = NULL, | |
2227 | .num_reset_levels = 0, | |
7232398a TR |
2228 | }; |
2229 | ||
2230 | static const char * const tegra30_powergates[] = { | |
2231 | [TEGRA_POWERGATE_CPU] = "cpu0", | |
2232 | [TEGRA_POWERGATE_3D] = "3d0", | |
2233 | [TEGRA_POWERGATE_VENC] = "venc", | |
2234 | [TEGRA_POWERGATE_VDEC] = "vdec", | |
2235 | [TEGRA_POWERGATE_PCIE] = "pcie", | |
2236 | [TEGRA_POWERGATE_L2] = "l2", | |
2237 | [TEGRA_POWERGATE_MPE] = "mpe", | |
2238 | [TEGRA_POWERGATE_HEG] = "heg", | |
2239 | [TEGRA_POWERGATE_SATA] = "sata", | |
2240 | [TEGRA_POWERGATE_CPU1] = "cpu1", | |
2241 | [TEGRA_POWERGATE_CPU2] = "cpu2", | |
2242 | [TEGRA_POWERGATE_CPU3] = "cpu3", | |
2243 | [TEGRA_POWERGATE_CELP] = "celp", | |
2244 | [TEGRA_POWERGATE_3D1] = "3d1", | |
2245 | }; | |
2246 | ||
2247 | static const u8 tegra30_cpu_powergates[] = { | |
2248 | TEGRA_POWERGATE_CPU, | |
2249 | TEGRA_POWERGATE_CPU1, | |
2250 | TEGRA_POWERGATE_CPU2, | |
2251 | TEGRA_POWERGATE_CPU3, | |
2252 | }; | |
2253 | ||
2254 | static const struct tegra_pmc_soc tegra30_pmc_soc = { | |
2255 | .num_powergates = ARRAY_SIZE(tegra30_powergates), | |
2256 | .powergates = tegra30_powergates, | |
2257 | .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), | |
2258 | .cpu_powergates = tegra30_cpu_powergates, | |
3568df3d | 2259 | .has_tsense_reset = true, |
a9a40a4a | 2260 | .has_gpu_clamps = false, |
fa3bc04e | 2261 | .needs_mbist_war = false, |
13136a47 | 2262 | .has_impl_33v_pwr = false, |
e247deae | 2263 | .maybe_tz_only = false, |
5be22556 TR |
2264 | .num_io_pads = 0, |
2265 | .io_pads = NULL, | |
4a37f11c AV |
2266 | .num_pin_descs = 0, |
2267 | .pin_descs = NULL, | |
5be22556 TR |
2268 | .regs = &tegra20_pmc_regs, |
2269 | .init = tegra20_pmc_init, | |
2270 | .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, | |
5f84bb1a | 2271 | .reset_sources = tegra30_reset_sources, |
00cdaa1b | 2272 | .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), |
5f84bb1a SP |
2273 | .reset_levels = NULL, |
2274 | .num_reset_levels = 0, | |
7232398a TR |
2275 | }; |
2276 | ||
2277 | static const char * const tegra114_powergates[] = { | |
2278 | [TEGRA_POWERGATE_CPU] = "crail", | |
2279 | [TEGRA_POWERGATE_3D] = "3d", | |
2280 | [TEGRA_POWERGATE_VENC] = "venc", | |
2281 | [TEGRA_POWERGATE_VDEC] = "vdec", | |
2282 | [TEGRA_POWERGATE_MPE] = "mpe", | |
2283 | [TEGRA_POWERGATE_HEG] = "heg", | |
2284 | [TEGRA_POWERGATE_CPU1] = "cpu1", | |
2285 | [TEGRA_POWERGATE_CPU2] = "cpu2", | |
2286 | [TEGRA_POWERGATE_CPU3] = "cpu3", | |
2287 | [TEGRA_POWERGATE_CELP] = "celp", | |
2288 | [TEGRA_POWERGATE_CPU0] = "cpu0", | |
2289 | [TEGRA_POWERGATE_C0NC] = "c0nc", | |
2290 | [TEGRA_POWERGATE_C1NC] = "c1nc", | |
2291 | [TEGRA_POWERGATE_DIS] = "dis", | |
2292 | [TEGRA_POWERGATE_DISB] = "disb", | |
2293 | [TEGRA_POWERGATE_XUSBA] = "xusba", | |
2294 | [TEGRA_POWERGATE_XUSBB] = "xusbb", | |
2295 | [TEGRA_POWERGATE_XUSBC] = "xusbc", | |
2296 | }; | |
2297 | ||
2298 | static const u8 tegra114_cpu_powergates[] = { | |
2299 | TEGRA_POWERGATE_CPU0, | |
2300 | TEGRA_POWERGATE_CPU1, | |
2301 | TEGRA_POWERGATE_CPU2, | |
2302 | TEGRA_POWERGATE_CPU3, | |
2303 | }; | |
2304 | ||
2305 | static const struct tegra_pmc_soc tegra114_pmc_soc = { | |
2306 | .num_powergates = ARRAY_SIZE(tegra114_powergates), | |
2307 | .powergates = tegra114_powergates, | |
2308 | .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), | |
2309 | .cpu_powergates = tegra114_cpu_powergates, | |
3568df3d | 2310 | .has_tsense_reset = true, |
a9a40a4a | 2311 | .has_gpu_clamps = false, |
fa3bc04e | 2312 | .needs_mbist_war = false, |
13136a47 | 2313 | .has_impl_33v_pwr = false, |
e247deae | 2314 | .maybe_tz_only = false, |
5be22556 TR |
2315 | .num_io_pads = 0, |
2316 | .io_pads = NULL, | |
4a37f11c AV |
2317 | .num_pin_descs = 0, |
2318 | .pin_descs = NULL, | |
5be22556 TR |
2319 | .regs = &tegra20_pmc_regs, |
2320 | .init = tegra20_pmc_init, | |
2321 | .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, | |
5f84bb1a | 2322 | .reset_sources = tegra30_reset_sources, |
00cdaa1b | 2323 | .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), |
5f84bb1a SP |
2324 | .reset_levels = NULL, |
2325 | .num_reset_levels = 0, | |
7232398a TR |
2326 | }; |
2327 | ||
2328 | static const char * const tegra124_powergates[] = { | |
2329 | [TEGRA_POWERGATE_CPU] = "crail", | |
2330 | [TEGRA_POWERGATE_3D] = "3d", | |
2331 | [TEGRA_POWERGATE_VENC] = "venc", | |
2332 | [TEGRA_POWERGATE_PCIE] = "pcie", | |
2333 | [TEGRA_POWERGATE_VDEC] = "vdec", | |
7232398a TR |
2334 | [TEGRA_POWERGATE_MPE] = "mpe", |
2335 | [TEGRA_POWERGATE_HEG] = "heg", | |
2336 | [TEGRA_POWERGATE_SATA] = "sata", | |
2337 | [TEGRA_POWERGATE_CPU1] = "cpu1", | |
2338 | [TEGRA_POWERGATE_CPU2] = "cpu2", | |
2339 | [TEGRA_POWERGATE_CPU3] = "cpu3", | |
2340 | [TEGRA_POWERGATE_CELP] = "celp", | |
2341 | [TEGRA_POWERGATE_CPU0] = "cpu0", | |
2342 | [TEGRA_POWERGATE_C0NC] = "c0nc", | |
2343 | [TEGRA_POWERGATE_C1NC] = "c1nc", | |
2344 | [TEGRA_POWERGATE_SOR] = "sor", | |
2345 | [TEGRA_POWERGATE_DIS] = "dis", | |
2346 | [TEGRA_POWERGATE_DISB] = "disb", | |
2347 | [TEGRA_POWERGATE_XUSBA] = "xusba", | |
2348 | [TEGRA_POWERGATE_XUSBB] = "xusbb", | |
2349 | [TEGRA_POWERGATE_XUSBC] = "xusbc", | |
2350 | [TEGRA_POWERGATE_VIC] = "vic", | |
2351 | [TEGRA_POWERGATE_IRAM] = "iram", | |
2352 | }; | |
2353 | ||
2354 | static const u8 tegra124_cpu_powergates[] = { | |
2355 | TEGRA_POWERGATE_CPU0, | |
2356 | TEGRA_POWERGATE_CPU1, | |
2357 | TEGRA_POWERGATE_CPU2, | |
2358 | TEGRA_POWERGATE_CPU3, | |
2359 | }; | |
2360 | ||
437c4f26 AV |
2361 | #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \ |
2362 | ((struct tegra_io_pad_soc) { \ | |
2363 | .id = (_id), \ | |
2364 | .dpd = (_dpd), \ | |
2365 | .voltage = (_voltage), \ | |
2366 | .name = (_name), \ | |
2367 | }) | |
2368 | ||
4a37f11c AV |
2369 | #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \ |
2370 | ((struct pinctrl_pin_desc) { \ | |
2371 | .number = (_id), \ | |
2372 | .name = (_name) \ | |
2373 | }) | |
2374 | ||
437c4f26 AV |
2375 | #define TEGRA124_IO_PAD_TABLE(_pad) \ |
2376 | /* .id .dpd .voltage .name */ \ | |
2377 | _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ | |
2378 | _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \ | |
2379 | _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \ | |
2380 | _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \ | |
2381 | _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ | |
2382 | _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \ | |
2383 | _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \ | |
2384 | _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ | |
2385 | _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ | |
2386 | _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ | |
2387 | _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ | |
2388 | _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ | |
2389 | _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ | |
2390 | _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \ | |
2391 | _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ | |
2392 | _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ | |
2393 | _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \ | |
2394 | _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ | |
2395 | _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ | |
2396 | _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ | |
2397 | _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ | |
2398 | _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \ | |
2399 | _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \ | |
2400 | _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \ | |
2401 | _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \ | |
2402 | _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ | |
2403 | _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ | |
2404 | _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ | |
2405 | _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ | |
2406 | _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias") | |
2407 | ||
21b49910 | 2408 | static const struct tegra_io_pad_soc tegra124_io_pads[] = { |
437c4f26 | 2409 | TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD) |
21b49910 LD |
2410 | }; |
2411 | ||
4a37f11c AV |
2412 | static const struct pinctrl_pin_desc tegra124_pin_descs[] = { |
2413 | TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) | |
21b49910 LD |
2414 | }; |
2415 | ||
7232398a TR |
2416 | static const struct tegra_pmc_soc tegra124_pmc_soc = { |
2417 | .num_powergates = ARRAY_SIZE(tegra124_powergates), | |
2418 | .powergates = tegra124_powergates, | |
2419 | .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), | |
2420 | .cpu_powergates = tegra124_cpu_powergates, | |
3568df3d | 2421 | .has_tsense_reset = true, |
a9a40a4a | 2422 | .has_gpu_clamps = true, |
fa3bc04e | 2423 | .needs_mbist_war = false, |
13136a47 | 2424 | .has_impl_33v_pwr = false, |
e247deae | 2425 | .maybe_tz_only = false, |
21b49910 LD |
2426 | .num_io_pads = ARRAY_SIZE(tegra124_io_pads), |
2427 | .io_pads = tegra124_io_pads, | |
4a37f11c AV |
2428 | .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs), |
2429 | .pin_descs = tegra124_pin_descs, | |
5be22556 TR |
2430 | .regs = &tegra20_pmc_regs, |
2431 | .init = tegra20_pmc_init, | |
2432 | .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, | |
5f84bb1a | 2433 | .reset_sources = tegra30_reset_sources, |
00cdaa1b | 2434 | .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), |
5f84bb1a SP |
2435 | .reset_levels = NULL, |
2436 | .num_reset_levels = 0, | |
7232398a TR |
2437 | }; |
2438 | ||
c2fe4694 TR |
2439 | static const char * const tegra210_powergates[] = { |
2440 | [TEGRA_POWERGATE_CPU] = "crail", | |
2441 | [TEGRA_POWERGATE_3D] = "3d", | |
2442 | [TEGRA_POWERGATE_VENC] = "venc", | |
2443 | [TEGRA_POWERGATE_PCIE] = "pcie", | |
c2fe4694 | 2444 | [TEGRA_POWERGATE_MPE] = "mpe", |
c2fe4694 TR |
2445 | [TEGRA_POWERGATE_SATA] = "sata", |
2446 | [TEGRA_POWERGATE_CPU1] = "cpu1", | |
2447 | [TEGRA_POWERGATE_CPU2] = "cpu2", | |
2448 | [TEGRA_POWERGATE_CPU3] = "cpu3", | |
c2fe4694 TR |
2449 | [TEGRA_POWERGATE_CPU0] = "cpu0", |
2450 | [TEGRA_POWERGATE_C0NC] = "c0nc", | |
c2fe4694 TR |
2451 | [TEGRA_POWERGATE_SOR] = "sor", |
2452 | [TEGRA_POWERGATE_DIS] = "dis", | |
2453 | [TEGRA_POWERGATE_DISB] = "disb", | |
2454 | [TEGRA_POWERGATE_XUSBA] = "xusba", | |
2455 | [TEGRA_POWERGATE_XUSBB] = "xusbb", | |
2456 | [TEGRA_POWERGATE_XUSBC] = "xusbc", | |
2457 | [TEGRA_POWERGATE_VIC] = "vic", | |
2458 | [TEGRA_POWERGATE_IRAM] = "iram", | |
2459 | [TEGRA_POWERGATE_NVDEC] = "nvdec", | |
2460 | [TEGRA_POWERGATE_NVJPG] = "nvjpg", | |
2461 | [TEGRA_POWERGATE_AUD] = "aud", | |
2462 | [TEGRA_POWERGATE_DFD] = "dfd", | |
2463 | [TEGRA_POWERGATE_VE2] = "ve2", | |
2464 | }; | |
2465 | ||
2466 | static const u8 tegra210_cpu_powergates[] = { | |
2467 | TEGRA_POWERGATE_CPU0, | |
2468 | TEGRA_POWERGATE_CPU1, | |
2469 | TEGRA_POWERGATE_CPU2, | |
2470 | TEGRA_POWERGATE_CPU3, | |
2471 | }; | |
2472 | ||
437c4f26 AV |
2473 | #define TEGRA210_IO_PAD_TABLE(_pad) \ |
2474 | /* .id .dpd .voltage .name */ \ | |
2475 | _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \ | |
2476 | _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \ | |
2477 | _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \ | |
2478 | _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ | |
2479 | _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ | |
2480 | _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \ | |
2481 | _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \ | |
2482 | _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \ | |
2483 | _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \ | |
2484 | _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \ | |
2485 | _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \ | |
2486 | _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \ | |
2487 | _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \ | |
2488 | _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ | |
2489 | _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ | |
2490 | _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ | |
2491 | _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ | |
2492 | _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \ | |
2493 | _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \ | |
2494 | _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \ | |
2495 | _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ | |
2496 | _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ | |
2497 | _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ | |
2498 | _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ | |
2499 | _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ | |
2500 | _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ | |
2501 | _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ | |
2502 | _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \ | |
2503 | _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \ | |
2504 | _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \ | |
2505 | _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \ | |
2506 | _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \ | |
2507 | _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \ | |
2508 | _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ | |
2509 | _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ | |
2510 | _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ | |
2511 | _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \ | |
2512 | _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias") | |
2513 | ||
21b49910 | 2514 | static const struct tegra_io_pad_soc tegra210_io_pads[] = { |
437c4f26 | 2515 | TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD) |
21b49910 LD |
2516 | }; |
2517 | ||
4a37f11c AV |
2518 | static const struct pinctrl_pin_desc tegra210_pin_descs[] = { |
2519 | TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) | |
21b49910 LD |
2520 | }; |
2521 | ||
c2fe4694 TR |
2522 | static const struct tegra_pmc_soc tegra210_pmc_soc = { |
2523 | .num_powergates = ARRAY_SIZE(tegra210_powergates), | |
2524 | .powergates = tegra210_powergates, | |
2525 | .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), | |
2526 | .cpu_powergates = tegra210_cpu_powergates, | |
2527 | .has_tsense_reset = true, | |
2528 | .has_gpu_clamps = true, | |
a263394a | 2529 | .needs_mbist_war = true, |
fa3bc04e | 2530 | .has_impl_33v_pwr = false, |
e247deae | 2531 | .maybe_tz_only = true, |
21b49910 LD |
2532 | .num_io_pads = ARRAY_SIZE(tegra210_io_pads), |
2533 | .io_pads = tegra210_io_pads, | |
4a37f11c AV |
2534 | .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), |
2535 | .pin_descs = tegra210_pin_descs, | |
5be22556 TR |
2536 | .regs = &tegra20_pmc_regs, |
2537 | .init = tegra20_pmc_init, | |
2538 | .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, | |
00cdaa1b JH |
2539 | .reset_sources = tegra210_reset_sources, |
2540 | .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), | |
5f84bb1a SP |
2541 | .reset_levels = NULL, |
2542 | .num_reset_levels = 0, | |
c2fe4694 TR |
2543 | }; |
2544 | ||
437c4f26 AV |
2545 | #define TEGRA186_IO_PAD_TABLE(_pad) \ |
2546 | /* .id .dpd .voltage .name */ \ | |
2547 | _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ | |
2548 | _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ | |
2549 | _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ | |
2550 | _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ | |
2551 | _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \ | |
2552 | _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \ | |
2553 | _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ | |
2554 | _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \ | |
2555 | _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ | |
2556 | _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ | |
2557 | _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ | |
2558 | _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \ | |
2559 | _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ | |
2560 | _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ | |
2561 | _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ | |
2562 | _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \ | |
2563 | _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \ | |
2564 | _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \ | |
2565 | _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ | |
2566 | _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \ | |
2567 | _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \ | |
2568 | _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \ | |
2569 | _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \ | |
2570 | _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \ | |
2571 | _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \ | |
2572 | _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \ | |
2573 | _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \ | |
2574 | _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \ | |
2575 | _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \ | |
2576 | _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \ | |
2577 | _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \ | |
2578 | _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \ | |
2579 | _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \ | |
2580 | _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \ | |
2581 | _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \ | |
2582 | _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \ | |
2583 | _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \ | |
2584 | _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv") | |
2585 | ||
c641ec6e | 2586 | static const struct tegra_io_pad_soc tegra186_io_pads[] = { |
437c4f26 | 2587 | TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD) |
c641ec6e TR |
2588 | }; |
2589 | ||
4a37f11c AV |
2590 | static const struct pinctrl_pin_desc tegra186_pin_descs[] = { |
2591 | TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) | |
c641ec6e TR |
2592 | }; |
2593 | ||
2594 | static const struct tegra_pmc_regs tegra186_pmc_regs = { | |
2595 | .scratch0 = 0x2000, | |
2596 | .dpd_req = 0x74, | |
2597 | .dpd_status = 0x78, | |
2598 | .dpd2_req = 0x7c, | |
2599 | .dpd2_status = 0x80, | |
5f84bb1a SP |
2600 | .rst_status = 0x70, |
2601 | .rst_source_shift = 0x2, | |
2602 | .rst_source_mask = 0x3C, | |
2603 | .rst_level_shift = 0x0, | |
2604 | .rst_level_mask = 0x3, | |
c641ec6e TR |
2605 | }; |
2606 | ||
2607 | static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, | |
2608 | struct device_node *np, | |
2609 | bool invert) | |
2610 | { | |
2611 | struct resource regs; | |
2612 | void __iomem *wake; | |
2613 | u32 value; | |
2614 | int index; | |
2615 | ||
2616 | index = of_property_match_string(np, "reg-names", "wake"); | |
2617 | if (index < 0) { | |
589997a1 | 2618 | dev_err(pmc->dev, "failed to find PMC wake registers\n"); |
c641ec6e TR |
2619 | return; |
2620 | } | |
2621 | ||
2622 | of_address_to_resource(np, index, ®s); | |
2623 | ||
2624 | wake = ioremap_nocache(regs.start, resource_size(®s)); | |
2625 | if (!wake) { | |
589997a1 | 2626 | dev_err(pmc->dev, "failed to map PMC wake registers\n"); |
c641ec6e TR |
2627 | return; |
2628 | } | |
2629 | ||
2630 | value = readl(wake + WAKE_AOWAKE_CTRL); | |
2631 | ||
2632 | if (invert) | |
2633 | value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; | |
2634 | else | |
2635 | value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; | |
2636 | ||
2637 | writel(value, wake + WAKE_AOWAKE_CTRL); | |
2638 | ||
2639 | iounmap(wake); | |
2640 | } | |
2641 | ||
e59333c8 | 2642 | static const struct tegra_wake_event tegra186_wake_events[] = { |
532700ed | 2643 | TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)), |
e59333c8 TR |
2644 | TEGRA_WAKE_IRQ("rtc", 73, 10), |
2645 | }; | |
2646 | ||
c641ec6e TR |
2647 | static const struct tegra_pmc_soc tegra186_pmc_soc = { |
2648 | .num_powergates = 0, | |
2649 | .powergates = NULL, | |
2650 | .num_cpu_powergates = 0, | |
2651 | .cpu_powergates = NULL, | |
2652 | .has_tsense_reset = false, | |
2653 | .has_gpu_clamps = false, | |
fa3bc04e | 2654 | .needs_mbist_war = false, |
13136a47 | 2655 | .has_impl_33v_pwr = true, |
e247deae | 2656 | .maybe_tz_only = false, |
c641ec6e TR |
2657 | .num_io_pads = ARRAY_SIZE(tegra186_io_pads), |
2658 | .io_pads = tegra186_io_pads, | |
4a37f11c AV |
2659 | .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), |
2660 | .pin_descs = tegra186_pin_descs, | |
c641ec6e TR |
2661 | .regs = &tegra186_pmc_regs, |
2662 | .init = NULL, | |
2663 | .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, | |
5f84bb1a | 2664 | .reset_sources = tegra186_reset_sources, |
00cdaa1b | 2665 | .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), |
5f84bb1a | 2666 | .reset_levels = tegra186_reset_levels, |
00cdaa1b | 2667 | .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), |
e59333c8 TR |
2668 | .num_wake_events = ARRAY_SIZE(tegra186_wake_events), |
2669 | .wake_events = tegra186_wake_events, | |
c641ec6e TR |
2670 | }; |
2671 | ||
eac9c48a TR |
2672 | static const struct tegra_io_pad_soc tegra194_io_pads[] = { |
2673 | { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, | |
2674 | { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, | |
2675 | { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, | |
2676 | { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX }, | |
2677 | { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX }, | |
2678 | { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, | |
2679 | { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX }, | |
2680 | { .id = TEGRA_IO_PAD_EQOS, .dpd = 8, .voltage = UINT_MAX }, | |
2681 | { .id = TEGRA_IO_PAD_PEX_CLK2_BIAS, .dpd = 9, .voltage = UINT_MAX }, | |
2682 | { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 10, .voltage = UINT_MAX }, | |
2683 | { .id = TEGRA_IO_PAD_DAP3, .dpd = 11, .voltage = UINT_MAX }, | |
2684 | { .id = TEGRA_IO_PAD_DAP5, .dpd = 12, .voltage = UINT_MAX }, | |
2685 | { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX }, | |
2686 | { .id = TEGRA_IO_PAD_PWR_CTL, .dpd = 15, .voltage = UINT_MAX }, | |
2687 | { .id = TEGRA_IO_PAD_SOC_GPIO53, .dpd = 16, .voltage = UINT_MAX }, | |
2688 | { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX }, | |
2689 | { .id = TEGRA_IO_PAD_GP_PWM2, .dpd = 18, .voltage = UINT_MAX }, | |
2690 | { .id = TEGRA_IO_PAD_GP_PWM3, .dpd = 19, .voltage = UINT_MAX }, | |
2691 | { .id = TEGRA_IO_PAD_SOC_GPIO12, .dpd = 20, .voltage = UINT_MAX }, | |
2692 | { .id = TEGRA_IO_PAD_SOC_GPIO13, .dpd = 21, .voltage = UINT_MAX }, | |
2693 | { .id = TEGRA_IO_PAD_SOC_GPIO10, .dpd = 22, .voltage = UINT_MAX }, | |
2694 | { .id = TEGRA_IO_PAD_UART4, .dpd = 23, .voltage = UINT_MAX }, | |
2695 | { .id = TEGRA_IO_PAD_UART5, .dpd = 24, .voltage = UINT_MAX }, | |
2696 | { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX }, | |
2697 | { .id = TEGRA_IO_PAD_HDMI_DP3, .dpd = 26, .voltage = UINT_MAX }, | |
2698 | { .id = TEGRA_IO_PAD_HDMI_DP2, .dpd = 27, .voltage = UINT_MAX }, | |
2699 | { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX }, | |
2700 | { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX }, | |
2701 | { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX }, | |
2702 | { .id = TEGRA_IO_PAD_PEX_CTL2, .dpd = 33, .voltage = UINT_MAX }, | |
2703 | { .id = TEGRA_IO_PAD_PEX_L0_RST_N, .dpd = 34, .voltage = UINT_MAX }, | |
2704 | { .id = TEGRA_IO_PAD_PEX_L1_RST_N, .dpd = 35, .voltage = UINT_MAX }, | |
2705 | { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX }, | |
2706 | { .id = TEGRA_IO_PAD_PEX_L5_RST_N, .dpd = 37, .voltage = UINT_MAX }, | |
2707 | { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX }, | |
2708 | { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX }, | |
2709 | { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX }, | |
2710 | { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX }, | |
2711 | { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX }, | |
2712 | { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX }, | |
2713 | { .id = TEGRA_IO_PAD_CSIG, .dpd = 50, .voltage = UINT_MAX }, | |
2714 | { .id = TEGRA_IO_PAD_CSIH, .dpd = 51, .voltage = UINT_MAX }, | |
2715 | { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX }, | |
2716 | { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX }, | |
2717 | { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX }, | |
2718 | { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX }, | |
2719 | { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX }, | |
2720 | }; | |
2721 | ||
e3e403c2 TR |
2722 | static const struct tegra_wake_event tegra194_wake_events[] = { |
2723 | TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)), | |
2724 | TEGRA_WAKE_IRQ("rtc", 73, 10), | |
2725 | }; | |
2726 | ||
eac9c48a TR |
2727 | static const struct tegra_pmc_soc tegra194_pmc_soc = { |
2728 | .num_powergates = 0, | |
2729 | .powergates = NULL, | |
2730 | .num_cpu_powergates = 0, | |
2731 | .cpu_powergates = NULL, | |
2732 | .has_tsense_reset = false, | |
2733 | .has_gpu_clamps = false, | |
fa3bc04e TR |
2734 | .needs_mbist_war = false, |
2735 | .has_impl_33v_pwr = false, | |
e247deae | 2736 | .maybe_tz_only = false, |
eac9c48a TR |
2737 | .num_io_pads = ARRAY_SIZE(tegra194_io_pads), |
2738 | .io_pads = tegra194_io_pads, | |
2739 | .regs = &tegra186_pmc_regs, | |
2740 | .init = NULL, | |
2741 | .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, | |
e3e403c2 TR |
2742 | .num_wake_events = ARRAY_SIZE(tegra194_wake_events), |
2743 | .wake_events = tegra194_wake_events, | |
c641ec6e TR |
2744 | }; |
2745 | ||
7232398a | 2746 | static const struct of_device_id tegra_pmc_match[] = { |
eac9c48a | 2747 | { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, |
c641ec6e | 2748 | { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, |
c2fe4694 | 2749 | { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, |
7d71e903 | 2750 | { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, |
7232398a TR |
2751 | { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, |
2752 | { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, | |
2753 | { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, | |
2754 | { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, | |
2755 | { } | |
2756 | }; | |
2757 | ||
2758 | static struct platform_driver tegra_pmc_driver = { | |
2759 | .driver = { | |
2760 | .name = "tegra-pmc", | |
2761 | .suppress_bind_attrs = true, | |
2762 | .of_match_table = tegra_pmc_match, | |
2b20b616 | 2763 | #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) |
7232398a | 2764 | .pm = &tegra_pmc_pm_ops, |
2b20b616 | 2765 | #endif |
7232398a TR |
2766 | }, |
2767 | .probe = tegra_pmc_probe, | |
2768 | }; | |
7d4d9ed6 | 2769 | builtin_platform_driver(tegra_pmc_driver); |
7232398a | 2770 | |
e247deae MP |
2771 | static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) |
2772 | { | |
2773 | u32 value, saved; | |
2774 | ||
2775 | saved = readl(pmc->base + pmc->soc->regs->scratch0); | |
2776 | value = saved ^ 0xffffffff; | |
2777 | ||
2778 | if (value == 0xffffffff) | |
2779 | value = 0xdeadbeef; | |
2780 | ||
2781 | /* write pattern and read it back */ | |
2782 | writel(value, pmc->base + pmc->soc->regs->scratch0); | |
2783 | value = readl(pmc->base + pmc->soc->regs->scratch0); | |
2784 | ||
2785 | /* if we read all-zeroes, access is restricted to TZ only */ | |
2786 | if (value == 0) { | |
2787 | pr_info("access to PMC is restricted to TZ\n"); | |
2788 | return true; | |
2789 | } | |
2790 | ||
2791 | /* restore original value */ | |
2792 | writel(saved, pmc->base + pmc->soc->regs->scratch0); | |
2793 | ||
2794 | return false; | |
2795 | } | |
2796 | ||
7232398a TR |
2797 | /* |
2798 | * Early initialization to allow access to registers in the very early boot | |
2799 | * process. | |
2800 | */ | |
2801 | static int __init tegra_pmc_early_init(void) | |
2802 | { | |
2803 | const struct of_device_id *match; | |
2804 | struct device_node *np; | |
2805 | struct resource regs; | |
6ac2a01d | 2806 | unsigned int i; |
7232398a | 2807 | bool invert; |
7232398a | 2808 | |
61fd284b JH |
2809 | mutex_init(&pmc->powergates_lock); |
2810 | ||
7232398a TR |
2811 | np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); |
2812 | if (!np) { | |
7d71e903 TR |
2813 | /* |
2814 | * Fall back to legacy initialization for 32-bit ARM only. All | |
2815 | * 64-bit ARM device tree files for Tegra are required to have | |
2816 | * a PMC node. | |
2817 | * | |
2818 | * This is for backwards-compatibility with old device trees | |
2819 | * that didn't contain a PMC node. Note that in this case the | |
2820 | * SoC data can't be matched and therefore powergating is | |
2821 | * disabled. | |
2822 | */ | |
2823 | if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { | |
2824 | pr_warn("DT node not found, powergating disabled\n"); | |
2825 | ||
2826 | regs.start = 0x7000e400; | |
2827 | regs.end = 0x7000e7ff; | |
2828 | regs.flags = IORESOURCE_MEM; | |
2829 | ||
2830 | pr_warn("Using memory region %pR\n", ®s); | |
2831 | } else { | |
2832 | /* | |
2833 | * At this point we're not running on Tegra, so play | |
2834 | * nice with multi-platform kernels. | |
2835 | */ | |
2836 | return 0; | |
2837 | } | |
7232398a | 2838 | } else { |
7d71e903 TR |
2839 | /* |
2840 | * Extract information from the device tree if we've found a | |
2841 | * matching node. | |
2842 | */ | |
2843 | if (of_address_to_resource(np, 0, ®s) < 0) { | |
2844 | pr_err("failed to get PMC registers\n"); | |
b69a6258 | 2845 | of_node_put(np); |
7d71e903 TR |
2846 | return -ENXIO; |
2847 | } | |
7232398a TR |
2848 | } |
2849 | ||
2850 | pmc->base = ioremap_nocache(regs.start, resource_size(®s)); | |
2851 | if (!pmc->base) { | |
2852 | pr_err("failed to map PMC registers\n"); | |
b69a6258 | 2853 | of_node_put(np); |
7232398a TR |
2854 | return -ENXIO; |
2855 | } | |
2856 | ||
11131895 | 2857 | if (np) { |
718a2426 JH |
2858 | pmc->soc = match->data; |
2859 | ||
e247deae MP |
2860 | if (pmc->soc->maybe_tz_only) |
2861 | pmc->tz_only = tegra_pmc_detect_tz_only(pmc); | |
2862 | ||
6ac2a01d JH |
2863 | /* Create a bitmap of the available and valid partitions */ |
2864 | for (i = 0; i < pmc->soc->num_powergates; i++) | |
2865 | if (pmc->soc->powergates[i]) | |
2866 | set_bit(i, pmc->powergates_available); | |
7232398a | 2867 | |
11131895 JH |
2868 | /* |
2869 | * Invert the interrupt polarity if a PMC device tree node | |
2870 | * exists and contains the nvidia,invert-interrupt property. | |
2871 | */ | |
2872 | invert = of_property_read_bool(np, "nvidia,invert-interrupt"); | |
7232398a | 2873 | |
5be22556 | 2874 | pmc->soc->setup_irq_polarity(pmc, np, invert); |
b69a6258 JH |
2875 | |
2876 | of_node_put(np); | |
11131895 | 2877 | } |
7232398a TR |
2878 | |
2879 | return 0; | |
2880 | } | |
2881 | early_initcall(tegra_pmc_early_init); |