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Merge tag 'nfsd-5.2-2' of git://linux-nfs.org/~bfields/linux
[mirror_ubuntu-jammy-kernel.git] / drivers / soundwire / intel.c
CommitLineData
71bb8a1b
VK		 1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2// Copyright(c) 2015-17 Intel Corporation.
3
4/*
5 * Soundwire Intel Master Driver
6 */
7
8#include <linux/acpi.h>
9#include <linux/delay.h>
4abbd783 10#include <linux/module.h>
71bb8a1b
VK		 11#include <linux/interrupt.h>
12#include <linux/platform_device.h>
37a2d22b
VK		 13#include <sound/pcm_params.h>
14#include <sound/soc.h>
71bb8a1b
VK		 15#include <linux/soundwire/sdw_registers.h>
16#include <linux/soundwire/sdw.h>
17#include <linux/soundwire/sdw_intel.h>
18#include "cadence_master.h"
19#include "intel.h"
20
21/* Intel SHIM Registers Definition */
22#define SDW_SHIM_LCAP 0x0
23#define SDW_SHIM_LCTL 0x4
24#define SDW_SHIM_IPPTR 0x8
25#define SDW_SHIM_SYNC 0xC
26
7cc6e315
PLB		 27#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
28#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
29#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
30#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
31#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
32#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
33
34#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
35#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
36#define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x))
37#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
38#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
71bb8a1b
VK		 39
40#define SDW_SHIM_WAKEEN 0x190
41#define SDW_SHIM_WAKESTS 0x192
42
43#define SDW_SHIM_LCTL_SPA BIT(0)
44#define SDW_SHIM_LCTL_CPA BIT(8)
45
46#define SDW_SHIM_SYNC_SYNCPRD_VAL 0x176F
47#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
48#define SDW_SHIM_SYNC_SYNCCPU BIT(15)
49#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
50#define SDW_SHIM_SYNC_CMDSYNC BIT(16)
51#define SDW_SHIM_SYNC_SYNCGO BIT(24)
52
53#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
54#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
55#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
56
57#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
58#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
59#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
60#define SDW_SHIM_PCMSYCM_DIR BIT(15)
61
62#define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0)
63#define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4)
64#define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8)
65#define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13)
66
67#define SDW_SHIM_IOCTL_MIF BIT(0)
68#define SDW_SHIM_IOCTL_CO BIT(1)
69#define SDW_SHIM_IOCTL_COE BIT(2)
70#define SDW_SHIM_IOCTL_DO BIT(3)
71#define SDW_SHIM_IOCTL_DOE BIT(4)
72#define SDW_SHIM_IOCTL_BKE BIT(5)
73#define SDW_SHIM_IOCTL_WPDD BIT(6)
74#define SDW_SHIM_IOCTL_CIBD BIT(8)
75#define SDW_SHIM_IOCTL_DIBD BIT(9)
76
77#define SDW_SHIM_CTMCTL_DACTQE BIT(0)
78#define SDW_SHIM_CTMCTL_DODS BIT(1)
79#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
80
81#define SDW_SHIM_WAKEEN_ENABLE BIT(0)
82#define SDW_SHIM_WAKESTS_STATUS BIT(0)
83
84/* Intel ALH Register definitions */
7cc6e315 85#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
71bb8a1b
VK		 86
87#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
88#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
89#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
90
c46302ec
VK		 91enum intel_pdi_type {
92 INTEL_PDI_IN = 0,
93 INTEL_PDI_OUT = 1,
94 INTEL_PDI_BD = 2,
95};
96
71bb8a1b
VK		 97struct sdw_intel {
98 struct sdw_cdns cdns;
99 int instance;
100 struct sdw_intel_link_res *res;
101};
102
103#define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
104
105/*
106 * Read, write helpers for HW registers
107 */
108static inline int intel_readl(void __iomem *base, int offset)
109{
110 return readl(base + offset);
111}
112
113static inline void intel_writel(void __iomem *base, int offset, int value)
114{
115 writel(value, base + offset);
116}
117
118static inline u16 intel_readw(void __iomem *base, int offset)
119{
120 return readw(base + offset);
121}
122
123static inline void intel_writew(void __iomem *base, int offset, u16 value)
124{
125 writew(value, base + offset);
126}
127
128static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
129{
130 int timeout = 10;
131 u32 reg_read;
132
133 writel(value, base + offset);
134 do {
135 reg_read = readl(base + offset);
136 if (!(reg_read & mask))
137 return 0;
138
139 timeout--;
140 udelay(50);
141 } while (timeout != 0);
142
143 return -EAGAIN;
144}
145
146static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
147{
148 int timeout = 10;
149 u32 reg_read;
150
151 writel(value, base + offset);
152 do {
153 reg_read = readl(base + offset);
154 if (reg_read & mask)
155 return 0;
156
157 timeout--;
158 udelay(50);
159 } while (timeout != 0);
160
161 return -EAGAIN;
162}
163
164/*
165 * shim ops
166 */
167
168static int intel_link_power_up(struct sdw_intel *sdw)
169{
170 unsigned int link_id = sdw->instance;
171 void __iomem *shim = sdw->res->shim;
172 int spa_mask, cpa_mask;
173 int link_control, ret;
174
175 /* Link power up sequence */
176 link_control = intel_readl(shim, SDW_SHIM_LCTL);
177 spa_mask = (SDW_SHIM_LCTL_SPA << link_id);
178 cpa_mask = (SDW_SHIM_LCTL_CPA << link_id);
179 link_control |= spa_mask;
180
181 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
182 if (ret < 0)
183 return ret;
184
185 sdw->cdns.link_up = true;
186 return 0;
187}
188
189static int intel_shim_init(struct sdw_intel *sdw)
190{
191 void __iomem *shim = sdw->res->shim;
192 unsigned int link_id = sdw->instance;
193 int sync_reg, ret;
194 u16 ioctl = 0, act = 0;
195
196 /* Initialize Shim */
197 ioctl |= SDW_SHIM_IOCTL_BKE;
198 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
199
200 ioctl |= SDW_SHIM_IOCTL_WPDD;
201 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
202
203 ioctl |= SDW_SHIM_IOCTL_DO;
204 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
205
206 ioctl |= SDW_SHIM_IOCTL_DOE;
207 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
208
209 /* Switch to MIP from Glue logic */
210 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
211
212 ioctl &= ~(SDW_SHIM_IOCTL_DOE);
213 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
214
215 ioctl &= ~(SDW_SHIM_IOCTL_DO);
216 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
217
218 ioctl |= (SDW_SHIM_IOCTL_MIF);
219 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
220
221 ioctl &= ~(SDW_SHIM_IOCTL_BKE);
222 ioctl &= ~(SDW_SHIM_IOCTL_COE);
223
224 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
225
226 act |= 0x1 << SDW_REG_SHIFT(SDW_SHIM_CTMCTL_DOAIS);
227 act |= SDW_SHIM_CTMCTL_DACTQE;
228 act |= SDW_SHIM_CTMCTL_DODS;
229 intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
230
231 /* Now set SyncPRD period */
232 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
233 sync_reg |= (SDW_SHIM_SYNC_SYNCPRD_VAL <<
234 SDW_REG_SHIFT(SDW_SHIM_SYNC_SYNCPRD));
235
236 /* Set SyncCPU bit */
237 sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
238 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
d542bc9e 239 SDW_SHIM_SYNC_SYNCCPU);
71bb8a1b 240 if (ret < 0)
17ed5bef 241 dev_err(sdw->cdns.dev, "Failed to set sync period: %d\n", ret);
71bb8a1b
VK		 242
243 return ret;
244}
245
37a2d22b
VK		 246/*
247 * PDI routines
248 */
249static void intel_pdi_init(struct sdw_intel *sdw,
d542bc9e 250 struct sdw_cdns_stream_config *config)
37a2d22b
VK		 251{
252 void __iomem *shim = sdw->res->shim;
253 unsigned int link_id = sdw->instance;
254 int pcm_cap, pdm_cap;
255
256 /* PCM Stream Capability */
257 pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
258
259 config->pcm_bd = (pcm_cap & SDW_SHIM_PCMSCAP_BSS) >>
260 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_BSS);
261 config->pcm_in = (pcm_cap & SDW_SHIM_PCMSCAP_ISS) >>
262 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_ISS);
263 config->pcm_out = (pcm_cap & SDW_SHIM_PCMSCAP_OSS) >>
264 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_OSS);
265
266 /* PDM Stream Capability */
267 pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
268
269 config->pdm_bd = (pdm_cap & SDW_SHIM_PDMSCAP_BSS) >>
270 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_BSS);
271 config->pdm_in = (pdm_cap & SDW_SHIM_PDMSCAP_ISS) >>
272 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_ISS);
273 config->pdm_out = (pdm_cap & SDW_SHIM_PDMSCAP_OSS) >>
274 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_OSS);
275}
276
277static int
278intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm)
279{
280 void __iomem *shim = sdw->res->shim;
281 unsigned int link_id = sdw->instance;
282 int count;
283
284 if (pcm) {
285 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
286 } else {
287 count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
288 count = ((count & SDW_SHIM_PDMSCAP_CPSS) >>
289 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_CPSS));
290 }
291
292 /* zero based values for channel count in register */
293 count++;
294
295 return count;
296}
297
298static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
d542bc9e
PLB		 299 struct sdw_cdns_pdi *pdi,
300 unsigned int num_pdi,
301 unsigned int *num_ch, bool pcm)
37a2d22b
VK		 302{
303 int i, ch_count = 0;
304
305 for (i = 0; i < num_pdi; i++) {
306 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm);
307 ch_count += pdi->ch_count;
308 pdi++;
309 }
310
311 *num_ch = ch_count;
312 return 0;
313}
314
315static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
d542bc9e 316 struct sdw_cdns_streams *stream, bool pcm)
37a2d22b
VK		 317{
318 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
d542bc9e 319 &stream->num_ch_bd, pcm);
37a2d22b
VK		 320
321 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
d542bc9e 322 &stream->num_ch_in, pcm);
37a2d22b
VK		 323
324 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
d542bc9e 325 &stream->num_ch_out, pcm);
37a2d22b
VK		 326
327 return 0;
328}
329
330static int intel_pdi_ch_update(struct sdw_intel *sdw)
331{
332 /* First update PCM streams followed by PDM streams */
333 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true);
334 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false);
335
336 return 0;
337}
338
339static void
340intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
341{
342 void __iomem *shim = sdw->res->shim;
343 unsigned int link_id = sdw->instance;
344 int pdi_conf = 0;
345
346 pdi->intel_alh_id = (link_id * 16) + pdi->num + 5;
347
348 /*
349 * Program stream parameters to stream SHIM register
350 * This is applicable for PCM stream only.
351 */
352 if (pdi->type != SDW_STREAM_PCM)
353 return;
354
355 if (pdi->dir == SDW_DATA_DIR_RX)
356 pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
357 else
358 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
359
360 pdi_conf |= (pdi->intel_alh_id <<
361 SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_STREAM));
362 pdi_conf |= (pdi->l_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_LCHN));
363 pdi_conf |= (pdi->h_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_HCHN));
364
365 intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
366}
367
368static void
369intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
370{
371 void __iomem *alh = sdw->res->alh;
372 unsigned int link_id = sdw->instance;
373 unsigned int conf;
374
375 pdi->intel_alh_id = (link_id * 16) + pdi->num + 5;
376
377 /* Program Stream config ALH register */
378 conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
379
380 conf |= (SDW_ALH_STRMZCFG_DMAT_VAL <<
381 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_DMAT));
382
383 conf |= ((pdi->ch_count - 1) <<
384 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_CHN));
385
386 intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
387}
388
c46302ec 389static int intel_config_stream(struct sdw_intel *sdw,
d542bc9e
PLB		 390 struct snd_pcm_substream *substream,
391 struct snd_soc_dai *dai,
392 struct snd_pcm_hw_params *hw_params, int link_id)
c46302ec
VK		 393{
394 if (sdw->res->ops && sdw->res->ops->config_stream)
395 return sdw->res->ops->config_stream(sdw->res->arg,
396 substream, dai, hw_params, link_id);
397
398 return -EIO;
399}
400
30246e2d
SN		 401/*
402 * bank switch routines
403 */
404
405static int intel_pre_bank_switch(struct sdw_bus *bus)
406{
407 struct sdw_cdns *cdns = bus_to_cdns(bus);
408 struct sdw_intel *sdw = cdns_to_intel(cdns);
409 void __iomem *shim = sdw->res->shim;
410 int sync_reg;
411
412 /* Write to register only for multi-link */
413 if (!bus->multi_link)
414 return 0;
415
416 /* Read SYNC register */
417 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
418 sync_reg |= SDW_SHIM_SYNC_CMDSYNC << sdw->instance;
419 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
420
421 return 0;
422}
423
424static int intel_post_bank_switch(struct sdw_bus *bus)
425{
426 struct sdw_cdns *cdns = bus_to_cdns(bus);
427 struct sdw_intel *sdw = cdns_to_intel(cdns);
428 void __iomem *shim = sdw->res->shim;
429 int sync_reg, ret;
430
431 /* Write to register only for multi-link */
432 if (!bus->multi_link)
433 return 0;
434
435 /* Read SYNC register */
436 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
437
438 /*
439 * post_bank_switch() ops is called from the bus in loop for
440 * all the Masters in the steam with the expectation that
441 * we trigger the bankswitch for the only first Master in the list
442 * and do nothing for the other Masters
443 *
444 * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
445 */
446 if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK))
447 return 0;
448
449 /*
450 * Set SyncGO bit to synchronously trigger a bank switch for
451 * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
452 * the Masters.
453 */
454 sync_reg |= SDW_SHIM_SYNC_SYNCGO;
455
456 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
d542bc9e 457 SDW_SHIM_SYNC_SYNCGO);
30246e2d 458 if (ret < 0)
17ed5bef 459 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
30246e2d
SN		 460
461 return ret;
462}
463
c46302ec
VK		 464/*
465 * DAI routines
466 */
467
468static struct sdw_cdns_port *intel_alloc_port(struct sdw_intel *sdw,
d542bc9e 469 u32 ch, u32 dir, bool pcm)
c46302ec
VK		 470{
471 struct sdw_cdns *cdns = &sdw->cdns;
472 struct sdw_cdns_port *port = NULL;
473 int i, ret = 0;
474
475 for (i = 0; i < cdns->num_ports; i++) {
2890a636 476 if (cdns->ports[i].assigned)
c46302ec
VK		 477 continue;
478
479 port = &cdns->ports[i];
480 port->assigned = true;
481 port->direction = dir;
482 port->ch = ch;
483 break;
484 }
485
486 if (!port) {
487 dev_err(cdns->dev, "Unable to find a free port\n");
488 return NULL;
489 }
490
491 if (pcm) {
492 ret = sdw_cdns_alloc_stream(cdns, &cdns->pcm, port, ch, dir);
493 if (ret)
494 goto out;
495
496 intel_pdi_shim_configure(sdw, port->pdi);
497 sdw_cdns_config_stream(cdns, port, ch, dir, port->pdi);
498
499 intel_pdi_alh_configure(sdw, port->pdi);
500
501 } else {
502 ret = sdw_cdns_alloc_stream(cdns, &cdns->pdm, port, ch, dir);
503 }
504
505out:
506 if (ret) {
507 port->assigned = false;
508 port = NULL;
509 }
510
511 return port;
512}
513
514static void intel_port_cleanup(struct sdw_cdns_dma_data *dma)
515{
516 int i;
517
518 for (i = 0; i < dma->nr_ports; i++) {
519 if (dma->port[i]) {
520 dma->port[i]->pdi->assigned = false;
521 dma->port[i]->pdi = NULL;
522 dma->port[i]->assigned = false;
523 dma->port[i] = NULL;
524 }
525 }
526}
527
528static int intel_hw_params(struct snd_pcm_substream *substream,
d542bc9e
PLB		 529 struct snd_pcm_hw_params *params,
530 struct snd_soc_dai *dai)
c46302ec
VK		 531{
532 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
533 struct sdw_intel *sdw = cdns_to_intel(cdns);
534 struct sdw_cdns_dma_data *dma;
535 struct sdw_stream_config sconfig;
536 struct sdw_port_config *pconfig;
537 int ret, i, ch, dir;
538 bool pcm = true;
539
540 dma = snd_soc_dai_get_dma_data(dai, substream);
541 if (!dma)
542 return -EIO;
543
544 ch = params_channels(params);
545 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
546 dir = SDW_DATA_DIR_RX;
547 else
548 dir = SDW_DATA_DIR_TX;
549
550 if (dma->stream_type == SDW_STREAM_PDM) {
551 /* TODO: Check whether PDM decimator is already in use */
552 dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pdm, ch, dir);
553 pcm = false;
554 } else {
555 dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pcm, ch, dir);
556 }
557
558 if (!dma->nr_ports) {
17ed5bef 559 dev_err(dai->dev, "ports/resources not available\n");
c46302ec
VK		 560 return -EINVAL;
561 }
562
563 dma->port = kcalloc(dma->nr_ports, sizeof(*dma->port), GFP_KERNEL);
564 if (!dma->port)
565 return -ENOMEM;
566
567 for (i = 0; i < dma->nr_ports; i++) {
568 dma->port[i] = intel_alloc_port(sdw, ch, dir, pcm);
569 if (!dma->port[i]) {
570 ret = -EINVAL;
571 goto port_error;
572 }
573 }
574
575 /* Inform DSP about PDI stream number */
576 for (i = 0; i < dma->nr_ports; i++) {
577 ret = intel_config_stream(sdw, substream, dai, params,
d542bc9e 578 dma->port[i]->pdi->intel_alh_id);
c46302ec
VK		 579 if (ret)
580 goto port_error;
581 }
582
583 sconfig.direction = dir;
584 sconfig.ch_count = ch;
585 sconfig.frame_rate = params_rate(params);
586 sconfig.type = dma->stream_type;
587
588 if (dma->stream_type == SDW_STREAM_PDM) {
589 sconfig.frame_rate *= 50;
590 sconfig.bps = 1;
591 } else {
592 sconfig.bps = snd_pcm_format_width(params_format(params));
593 }
594
595 /* Port configuration */
596 pconfig = kcalloc(dma->nr_ports, sizeof(*pconfig), GFP_KERNEL);
597 if (!pconfig) {
598 ret = -ENOMEM;
599 goto port_error;
600 }
601
602 for (i = 0; i < dma->nr_ports; i++) {
603 pconfig[i].num = dma->port[i]->num;
604 pconfig[i].ch_mask = (1 << ch) - 1;
605 }
606
607 ret = sdw_stream_add_master(&cdns->bus, &sconfig,
d542bc9e 608 pconfig, dma->nr_ports, dma->stream);
c46302ec 609 if (ret) {
17ed5bef 610 dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
c46302ec
VK		 611 goto stream_error;
612 }
613
614 kfree(pconfig);
615 return ret;
616
617stream_error:
618 kfree(pconfig);
619port_error:
620 intel_port_cleanup(dma);
621 kfree(dma->port);
622 return ret;
623}
624
625static int
626intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
627{
628 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
629 struct sdw_cdns_dma_data *dma;
630 int ret;
631
632 dma = snd_soc_dai_get_dma_data(dai, substream);
633 if (!dma)
634 return -EIO;
635
636 ret = sdw_stream_remove_master(&cdns->bus, dma->stream);
637 if (ret < 0)
17ed5bef 638 dev_err(dai->dev, "remove master from stream %s failed: %d\n",
d542bc9e 639 dma->stream->name, ret);
c46302ec
VK		 640
641 intel_port_cleanup(dma);
642 kfree(dma->port);
643 return ret;
644}
645
646static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
d542bc9e 647 void *stream, int direction)
c46302ec
VK		 648{
649 return cdns_set_sdw_stream(dai, stream, true, direction);
650}
651
652static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai,
d542bc9e 653 void *stream, int direction)
c46302ec
VK		 654{
655 return cdns_set_sdw_stream(dai, stream, false, direction);
656}
657
b1635596 658static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
c46302ec
VK		 659 .hw_params = intel_hw_params,
660 .hw_free = intel_hw_free,
661 .shutdown = sdw_cdns_shutdown,
662 .set_sdw_stream = intel_pcm_set_sdw_stream,
663};
664
b1635596 665static const struct snd_soc_dai_ops intel_pdm_dai_ops = {
c46302ec
VK		 666 .hw_params = intel_hw_params,
667 .hw_free = intel_hw_free,
668 .shutdown = sdw_cdns_shutdown,
669 .set_sdw_stream = intel_pdm_set_sdw_stream,
670};
671
672static const struct snd_soc_component_driver dai_component = {
673 .name = "soundwire",
674};
675
676static int intel_create_dai(struct sdw_cdns *cdns,
d542bc9e
PLB		 677 struct snd_soc_dai_driver *dais,
678 enum intel_pdi_type type,
679 u32 num, u32 off, u32 max_ch, bool pcm)
c46302ec
VK		 680{
681 int i;
682
683 if (num == 0)
684 return 0;
685
686 /* TODO: Read supported rates/formats from hardware */
687 for (i = off; i < (off + num); i++) {
688 dais[i].name = kasprintf(GFP_KERNEL, "SDW%d Pin%d",
d542bc9e 689 cdns->instance, i);
c46302ec
VK		 690 if (!dais[i].name)
691 return -ENOMEM;
692
693 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
1215daee
VK		 694 dais[i].playback.stream_name =
695 kasprintf(GFP_KERNEL, "SDW%d Tx%d",
696 cdns->instance, i);
c46302ec
VK		 697 if (!dais[i].playback.stream_name) {
698 kfree(dais[i].name);
699 return -ENOMEM;
700 }
701
702 dais[i].playback.channels_min = 1;
703 dais[i].playback.channels_max = max_ch;
704 dais[i].playback.rates = SNDRV_PCM_RATE_48000;
705 dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
706 }
707
708 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
1215daee
VK		 709 dais[i].capture.stream_name =
710 kasprintf(GFP_KERNEL, "SDW%d Rx%d",
711 cdns->instance, i);
c46302ec
VK		 712 if (!dais[i].capture.stream_name) {
713 kfree(dais[i].name);
714 kfree(dais[i].playback.stream_name);
715 return -ENOMEM;
716 }
717
39194128
SK		 718 dais[i].capture.channels_min = 1;
719 dais[i].capture.channels_max = max_ch;
c46302ec
VK		 720 dais[i].capture.rates = SNDRV_PCM_RATE_48000;
721 dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
722 }
723
724 dais[i].id = SDW_DAI_ID_RANGE_START + i;
725
726 if (pcm)
727 dais[i].ops = &intel_pcm_dai_ops;
728 else
729 dais[i].ops = &intel_pdm_dai_ops;
730 }
731
732 return 0;
733}
734
735static int intel_register_dai(struct sdw_intel *sdw)
736{
737 struct sdw_cdns *cdns = &sdw->cdns;
738 struct sdw_cdns_streams *stream;
739 struct snd_soc_dai_driver *dais;
740 int num_dai, ret, off = 0;
741
742 /* DAIs are created based on total number of PDIs supported */
743 num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi;
744
745 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
746 if (!dais)
747 return -ENOMEM;
748
749 /* Create PCM DAIs */
750 stream = &cdns->pcm;
751
1215daee
VK		 752 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, stream->num_in,
753 off, stream->num_ch_in, true);
c46302ec
VK		 754 if (ret)
755 return ret;
756
757 off += cdns->pcm.num_in;
1215daee
VK		 758 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
759 off, stream->num_ch_out, true);
c46302ec
VK		 760 if (ret)
761 return ret;
762
763 off += cdns->pcm.num_out;
1215daee
VK		 764 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
765 off, stream->num_ch_bd, true);
c46302ec
VK		 766 if (ret)
767 return ret;
768
769 /* Create PDM DAIs */
770 stream = &cdns->pdm;
771 off += cdns->pcm.num_bd;
1215daee
VK		 772 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in,
773 off, stream->num_ch_in, false);
c46302ec
VK		 774 if (ret)
775 return ret;
776
777 off += cdns->pdm.num_in;
1215daee
VK		 778 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out,
779 off, stream->num_ch_out, false);
c46302ec
VK		 780 if (ret)
781 return ret;
782
783 off += cdns->pdm.num_bd;
1215daee
VK		 784 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd,
785 off, stream->num_ch_bd, false);
c46302ec
VK		 786 if (ret)
787 return ret;
788
789 return snd_soc_register_component(cdns->dev, &dai_component,
d542bc9e 790 dais, num_dai);
c46302ec
VK		 791}
792
71bb8a1b
VK		 793static int intel_prop_read(struct sdw_bus *bus)
794{
795 /* Initialize with default handler to read all DisCo properties */
796 sdw_master_read_prop(bus);
797
798 /* BIOS is not giving some values correctly. So, lets override them */
799 bus->prop.num_freq = 1;
4ac5627a
PLB		 800 bus->prop.freq = devm_kcalloc(bus->dev, bus->prop.num_freq,
801 sizeof(*bus->prop.freq), GFP_KERNEL);
71bb8a1b
VK		 802 if (!bus->prop.freq)
803 return -ENOMEM;
804
805 bus->prop.freq[0] = bus->prop.max_freq;
806 bus->prop.err_threshold = 5;
807
808 return 0;
809}
810
c91605f4
SN		 811static struct sdw_master_ops sdw_intel_ops = {
812 .read_prop = sdw_master_read_prop,
813 .xfer_msg = cdns_xfer_msg,
814 .xfer_msg_defer = cdns_xfer_msg_defer,
815 .reset_page_addr = cdns_reset_page_addr,
07abeff1 816 .set_bus_conf = cdns_bus_conf,
30246e2d
SN		 817 .pre_bank_switch = intel_pre_bank_switch,
818 .post_bank_switch = intel_post_bank_switch,
c91605f4
SN		 819};
820
71bb8a1b
VK		 821/*
822 * probe and init
823 */
824static int intel_probe(struct platform_device *pdev)
825{
37a2d22b 826 struct sdw_cdns_stream_config config;
71bb8a1b
VK		 827 struct sdw_intel *sdw;
828 int ret;
829
830 sdw = devm_kzalloc(&pdev->dev, sizeof(*sdw), GFP_KERNEL);
831 if (!sdw)
832 return -ENOMEM;
833
834 sdw->instance = pdev->id;
835 sdw->res = dev_get_platdata(&pdev->dev);
836 sdw->cdns.dev = &pdev->dev;
837 sdw->cdns.registers = sdw->res->registers;
838 sdw->cdns.instance = sdw->instance;
839 sdw->cdns.msg_count = 0;
840 sdw->cdns.bus.dev = &pdev->dev;
841 sdw->cdns.bus.link_id = pdev->id;
842
843 sdw_cdns_probe(&sdw->cdns);
844
845 /* Set property read ops */
c91605f4
SN		 846 sdw_intel_ops.read_prop = intel_prop_read;
847 sdw->cdns.bus.ops = &sdw_intel_ops;
71bb8a1b
VK		 848
849 platform_set_drvdata(pdev, sdw);
850
851 ret = sdw_add_bus_master(&sdw->cdns.bus);
852 if (ret) {
853 dev_err(&pdev->dev, "sdw_add_bus_master fail: %d\n", ret);
854 goto err_master_reg;
855 }
856
857 /* Initialize shim and controller */
858 intel_link_power_up(sdw);
859 intel_shim_init(sdw);
860
861 ret = sdw_cdns_init(&sdw->cdns);
862 if (ret)
863 goto err_init;
864
7094dc2b 865 ret = sdw_cdns_enable_interrupt(&sdw->cdns);
37a2d22b
VK		 866
867 /* Read the PDI config and initialize cadence PDI */
868 intel_pdi_init(sdw, &config);
869 ret = sdw_cdns_pdi_init(&sdw->cdns, config);
71bb8a1b
VK		 870 if (ret)
871 goto err_init;
872
37a2d22b
VK		 873 intel_pdi_ch_update(sdw);
874
71bb8a1b 875 /* Acquire IRQ */
d542bc9e
PLB		 876 ret = request_threaded_irq(sdw->res->irq, sdw_cdns_irq, sdw_cdns_thread,
877 IRQF_SHARED, KBUILD_MODNAME, &sdw->cdns);
71bb8a1b
VK		 878 if (ret < 0) {
879 dev_err(sdw->cdns.dev, "unable to grab IRQ %d, disabling device\n",
d542bc9e 880 sdw->res->irq);
71bb8a1b
VK		 881 goto err_init;
882 }
883
c46302ec
VK		 884 /* Register DAIs */
885 ret = intel_register_dai(sdw);
886 if (ret) {
17ed5bef 887 dev_err(sdw->cdns.dev, "DAI registration failed: %d\n", ret);
c46302ec
VK		 888 snd_soc_unregister_component(sdw->cdns.dev);
889 goto err_dai;
890 }
891
71bb8a1b
VK		 892 return 0;
893
c46302ec
VK		 894err_dai:
895 free_irq(sdw->res->irq, sdw);
71bb8a1b
VK		 896err_init:
897 sdw_delete_bus_master(&sdw->cdns.bus);
898err_master_reg:
899 return ret;
900}
901
902static int intel_remove(struct platform_device *pdev)
903{
904 struct sdw_intel *sdw;
905
906 sdw = platform_get_drvdata(pdev);
907
908 free_irq(sdw->res->irq, sdw);
c46302ec 909 snd_soc_unregister_component(sdw->cdns.dev);
71bb8a1b
VK		 910 sdw_delete_bus_master(&sdw->cdns.bus);
911
912 return 0;
913}
914
915static struct platform_driver sdw_intel_drv = {
916 .probe = intel_probe,
917 .remove = intel_remove,
918 .driver = {
919 .name = "int-sdw",
920
921 },
922};
923
924module_platform_driver(sdw_intel_drv);
925
926MODULE_LICENSE("Dual BSD/GPL");
927MODULE_ALIAS("platform:int-sdw");
928MODULE_DESCRIPTION("Intel Soundwire Master Driver");
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