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71bb8a1b VK |
1 | // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) |
2 | // Copyright(c) 2015-17 Intel Corporation. | |
3 | ||
4 | /* | |
5 | * Soundwire Intel Master Driver | |
6 | */ | |
7 | ||
8 | #include <linux/acpi.h> | |
79ee6631 | 9 | #include <linux/debugfs.h> |
71bb8a1b | 10 | #include <linux/delay.h> |
4abbd783 | 11 | #include <linux/module.h> |
71bb8a1b | 12 | #include <linux/interrupt.h> |
df72b719 | 13 | #include <linux/io.h> |
71bb8a1b | 14 | #include <linux/platform_device.h> |
37a2d22b | 15 | #include <sound/pcm_params.h> |
ab2c9132 | 16 | #include <linux/pm_runtime.h> |
37a2d22b | 17 | #include <sound/soc.h> |
71bb8a1b VK |
18 | #include <linux/soundwire/sdw_registers.h> |
19 | #include <linux/soundwire/sdw.h> | |
20 | #include <linux/soundwire/sdw_intel.h> | |
21 | #include "cadence_master.h" | |
79ee6631 | 22 | #include "bus.h" |
71bb8a1b VK |
23 | #include "intel.h" |
24 | ||
ebf878ed PLB |
25 | #define INTEL_MASTER_SUSPEND_DELAY_MS 3000 |
26 | ||
27 | /* | |
28 | * debug/config flags for the Intel SoundWire Master. | |
29 | * | |
30 | * Since we may have multiple masters active, we can have up to 8 | |
31 | * flags reused in each byte, with master0 using the ls-byte, etc. | |
32 | */ | |
33 | ||
a2d9c161 PLB |
34 | #define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME BIT(0) |
35 | #define SDW_INTEL_MASTER_DISABLE_CLOCK_STOP BIT(1) | |
36 | #define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE BIT(2) | |
857a7c42 | 37 | #define SDW_INTEL_MASTER_DISABLE_MULTI_LINK BIT(3) |
ebf878ed PLB |
38 | |
39 | static int md_flags; | |
40 | module_param_named(sdw_md_flags, md_flags, int, 0444); | |
41 | MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)"); | |
42 | ||
71bb8a1b VK |
43 | /* Intel SHIM Registers Definition */ |
44 | #define SDW_SHIM_LCAP 0x0 | |
45 | #define SDW_SHIM_LCTL 0x4 | |
46 | #define SDW_SHIM_IPPTR 0x8 | |
47 | #define SDW_SHIM_SYNC 0xC | |
48 | ||
7cc6e315 PLB |
49 | #define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x)) |
50 | #define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x)) | |
51 | #define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x)) | |
52 | #define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x)) | |
53 | #define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x)) | |
54 | #define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x)) | |
55 | ||
56 | #define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y))) | |
57 | #define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y))) | |
58 | #define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x)) | |
59 | #define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x)) | |
60 | #define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x)) | |
71bb8a1b VK |
61 | |
62 | #define SDW_SHIM_WAKEEN 0x190 | |
63 | #define SDW_SHIM_WAKESTS 0x192 | |
64 | ||
65 | #define SDW_SHIM_LCTL_SPA BIT(0) | |
5ee74eb2 | 66 | #define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0) |
71bb8a1b | 67 | #define SDW_SHIM_LCTL_CPA BIT(8) |
5ee74eb2 | 68 | #define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8) |
71bb8a1b | 69 | |
4a17c441 PLB |
70 | #define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1) |
71 | #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1) | |
71bb8a1b VK |
72 | #define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0) |
73 | #define SDW_SHIM_SYNC_SYNCCPU BIT(15) | |
74 | #define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16) | |
75 | #define SDW_SHIM_SYNC_CMDSYNC BIT(16) | |
76 | #define SDW_SHIM_SYNC_SYNCGO BIT(24) | |
77 | ||
78 | #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0) | |
79 | #define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4) | |
80 | #define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8) | |
81 | ||
82 | #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0) | |
83 | #define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4) | |
84 | #define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8) | |
85 | #define SDW_SHIM_PCMSYCM_DIR BIT(15) | |
86 | ||
87 | #define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0) | |
88 | #define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4) | |
89 | #define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8) | |
90 | #define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13) | |
91 | ||
92 | #define SDW_SHIM_IOCTL_MIF BIT(0) | |
93 | #define SDW_SHIM_IOCTL_CO BIT(1) | |
94 | #define SDW_SHIM_IOCTL_COE BIT(2) | |
95 | #define SDW_SHIM_IOCTL_DO BIT(3) | |
96 | #define SDW_SHIM_IOCTL_DOE BIT(4) | |
97 | #define SDW_SHIM_IOCTL_BKE BIT(5) | |
98 | #define SDW_SHIM_IOCTL_WPDD BIT(6) | |
99 | #define SDW_SHIM_IOCTL_CIBD BIT(8) | |
100 | #define SDW_SHIM_IOCTL_DIBD BIT(9) | |
101 | ||
102 | #define SDW_SHIM_CTMCTL_DACTQE BIT(0) | |
103 | #define SDW_SHIM_CTMCTL_DODS BIT(1) | |
104 | #define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3) | |
105 | ||
106 | #define SDW_SHIM_WAKEEN_ENABLE BIT(0) | |
107 | #define SDW_SHIM_WAKESTS_STATUS BIT(0) | |
108 | ||
109 | /* Intel ALH Register definitions */ | |
7cc6e315 | 110 | #define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x))) |
79ee6631 | 111 | #define SDW_ALH_NUM_STREAMS 64 |
71bb8a1b VK |
112 | |
113 | #define SDW_ALH_STRMZCFG_DMAT_VAL 0x3 | |
114 | #define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0) | |
115 | #define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16) | |
116 | ||
c46302ec VK |
117 | enum intel_pdi_type { |
118 | INTEL_PDI_IN = 0, | |
119 | INTEL_PDI_OUT = 1, | |
120 | INTEL_PDI_BD = 2, | |
121 | }; | |
122 | ||
71bb8a1b VK |
123 | #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns) |
124 | ||
125 | /* | |
126 | * Read, write helpers for HW registers | |
127 | */ | |
128 | static inline int intel_readl(void __iomem *base, int offset) | |
129 | { | |
130 | return readl(base + offset); | |
131 | } | |
132 | ||
133 | static inline void intel_writel(void __iomem *base, int offset, int value) | |
134 | { | |
135 | writel(value, base + offset); | |
136 | } | |
137 | ||
138 | static inline u16 intel_readw(void __iomem *base, int offset) | |
139 | { | |
140 | return readw(base + offset); | |
141 | } | |
142 | ||
143 | static inline void intel_writew(void __iomem *base, int offset, u16 value) | |
144 | { | |
145 | writew(value, base + offset); | |
146 | } | |
147 | ||
7d2845d5 | 148 | static int intel_wait_bit(void __iomem *base, int offset, u32 mask, u32 target) |
71bb8a1b VK |
149 | { |
150 | int timeout = 10; | |
151 | u32 reg_read; | |
152 | ||
71bb8a1b VK |
153 | do { |
154 | reg_read = readl(base + offset); | |
7d2845d5 | 155 | if ((reg_read & mask) == target) |
71bb8a1b VK |
156 | return 0; |
157 | ||
158 | timeout--; | |
7d2845d5 | 159 | usleep_range(50, 100); |
71bb8a1b VK |
160 | } while (timeout != 0); |
161 | ||
162 | return -EAGAIN; | |
163 | } | |
164 | ||
7d2845d5 | 165 | static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask) |
71bb8a1b | 166 | { |
71bb8a1b | 167 | writel(value, base + offset); |
7d2845d5 PLB |
168 | return intel_wait_bit(base, offset, mask, 0); |
169 | } | |
71bb8a1b | 170 | |
7d2845d5 PLB |
171 | static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask) |
172 | { | |
173 | writel(value, base + offset); | |
174 | return intel_wait_bit(base, offset, mask, mask); | |
71bb8a1b VK |
175 | } |
176 | ||
79ee6631 PLB |
177 | /* |
178 | * debugfs | |
179 | */ | |
180 | #ifdef CONFIG_DEBUG_FS | |
181 | ||
182 | #define RD_BUF (2 * PAGE_SIZE) | |
183 | ||
184 | static ssize_t intel_sprintf(void __iomem *mem, bool l, | |
185 | char *buf, size_t pos, unsigned int reg) | |
186 | { | |
187 | int value; | |
188 | ||
189 | if (l) | |
190 | value = intel_readl(mem, reg); | |
191 | else | |
192 | value = intel_readw(mem, reg); | |
193 | ||
194 | return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value); | |
195 | } | |
196 | ||
197 | static int intel_reg_show(struct seq_file *s_file, void *data) | |
198 | { | |
199 | struct sdw_intel *sdw = s_file->private; | |
2523486b PLB |
200 | void __iomem *s = sdw->link_res->shim; |
201 | void __iomem *a = sdw->link_res->alh; | |
79ee6631 PLB |
202 | char *buf; |
203 | ssize_t ret; | |
204 | int i, j; | |
205 | unsigned int links, reg; | |
206 | ||
207 | buf = kzalloc(RD_BUF, GFP_KERNEL); | |
208 | if (!buf) | |
209 | return -ENOMEM; | |
210 | ||
211 | links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0); | |
212 | ||
213 | ret = scnprintf(buf, RD_BUF, "Register Value\n"); | |
214 | ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n"); | |
215 | ||
216 | for (i = 0; i < links; i++) { | |
217 | reg = SDW_SHIM_LCAP + i * 4; | |
218 | ret += intel_sprintf(s, true, buf, ret, reg); | |
219 | } | |
220 | ||
221 | for (i = 0; i < links; i++) { | |
222 | ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i); | |
223 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i)); | |
224 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i)); | |
225 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i)); | |
226 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i)); | |
227 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i)); | |
228 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i)); | |
229 | ||
230 | ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n"); | |
231 | ||
232 | /* | |
233 | * the value 10 is the number of PDIs. We will need a | |
234 | * cleanup to remove hard-coded Intel configurations | |
235 | * from cadence_master.c | |
236 | */ | |
237 | for (j = 0; j < 10; j++) { | |
238 | ret += intel_sprintf(s, false, buf, ret, | |
239 | SDW_SHIM_PCMSYCHM(i, j)); | |
240 | ret += intel_sprintf(s, false, buf, ret, | |
241 | SDW_SHIM_PCMSYCHC(i, j)); | |
242 | } | |
243 | ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n"); | |
244 | ||
245 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i)); | |
246 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i)); | |
247 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i)); | |
248 | } | |
249 | ||
250 | ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n"); | |
251 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN); | |
252 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS); | |
253 | ||
254 | ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n"); | |
255 | for (i = 0; i < SDW_ALH_NUM_STREAMS; i++) | |
256 | ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i)); | |
257 | ||
258 | seq_printf(s_file, "%s", buf); | |
259 | kfree(buf); | |
260 | ||
261 | return 0; | |
262 | } | |
263 | DEFINE_SHOW_ATTRIBUTE(intel_reg); | |
264 | ||
0f9138e7 PLB |
265 | static int intel_set_m_datamode(void *data, u64 value) |
266 | { | |
267 | struct sdw_intel *sdw = data; | |
268 | struct sdw_bus *bus = &sdw->cdns.bus; | |
269 | ||
270 | if (value > SDW_PORT_DATA_MODE_STATIC_1) | |
271 | return -EINVAL; | |
272 | ||
273 | /* Userspace changed the hardware state behind the kernel's back */ | |
274 | add_taint(TAINT_USER, LOCKDEP_STILL_OK); | |
275 | ||
276 | bus->params.m_data_mode = value; | |
277 | ||
278 | return 0; | |
279 | } | |
280 | DEFINE_DEBUGFS_ATTRIBUTE(intel_set_m_datamode_fops, NULL, | |
281 | intel_set_m_datamode, "%llu\n"); | |
282 | ||
283 | static int intel_set_s_datamode(void *data, u64 value) | |
284 | { | |
285 | struct sdw_intel *sdw = data; | |
286 | struct sdw_bus *bus = &sdw->cdns.bus; | |
287 | ||
288 | if (value > SDW_PORT_DATA_MODE_STATIC_1) | |
289 | return -EINVAL; | |
290 | ||
291 | /* Userspace changed the hardware state behind the kernel's back */ | |
292 | add_taint(TAINT_USER, LOCKDEP_STILL_OK); | |
293 | ||
294 | bus->params.s_data_mode = value; | |
295 | ||
296 | return 0; | |
297 | } | |
298 | DEFINE_DEBUGFS_ATTRIBUTE(intel_set_s_datamode_fops, NULL, | |
299 | intel_set_s_datamode, "%llu\n"); | |
300 | ||
79ee6631 PLB |
301 | static void intel_debugfs_init(struct sdw_intel *sdw) |
302 | { | |
303 | struct dentry *root = sdw->cdns.bus.debugfs; | |
304 | ||
305 | if (!root) | |
306 | return; | |
307 | ||
308 | sdw->debugfs = debugfs_create_dir("intel-sdw", root); | |
309 | ||
310 | debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw, | |
311 | &intel_reg_fops); | |
312 | ||
0f9138e7 PLB |
313 | debugfs_create_file("intel-m-datamode", 0200, sdw->debugfs, sdw, |
314 | &intel_set_m_datamode_fops); | |
315 | ||
316 | debugfs_create_file("intel-s-datamode", 0200, sdw->debugfs, sdw, | |
317 | &intel_set_s_datamode_fops); | |
318 | ||
79ee6631 PLB |
319 | sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs); |
320 | } | |
321 | ||
322 | static void intel_debugfs_exit(struct sdw_intel *sdw) | |
323 | { | |
324 | debugfs_remove_recursive(sdw->debugfs); | |
325 | } | |
326 | #else | |
327 | static void intel_debugfs_init(struct sdw_intel *sdw) {} | |
328 | static void intel_debugfs_exit(struct sdw_intel *sdw) {} | |
329 | #endif /* CONFIG_DEBUG_FS */ | |
330 | ||
71bb8a1b VK |
331 | /* |
332 | * shim ops | |
333 | */ | |
334 | ||
335 | static int intel_link_power_up(struct sdw_intel *sdw) | |
336 | { | |
337 | unsigned int link_id = sdw->instance; | |
2523486b | 338 | void __iomem *shim = sdw->link_res->shim; |
4a17c441 PLB |
339 | u32 *shim_mask = sdw->link_res->shim_mask; |
340 | struct sdw_bus *bus = &sdw->cdns.bus; | |
341 | struct sdw_master_prop *prop = &bus->prop; | |
5ee74eb2 PLB |
342 | u32 spa_mask, cpa_mask; |
343 | u32 link_control; | |
4a17c441 PLB |
344 | int ret = 0; |
345 | u32 syncprd; | |
346 | u32 sync_reg; | |
347 | ||
348 | mutex_lock(sdw->link_res->shim_lock); | |
349 | ||
350 | /* | |
351 | * The hardware relies on an internal counter, typically 4kHz, | |
352 | * to generate the SoundWire SSP - which defines a 'safe' | |
353 | * synchronization point between commands and audio transport | |
354 | * and allows for multi link synchronization. The SYNCPRD value | |
355 | * is only dependent on the oscillator clock provided to | |
356 | * the IP, so adjust based on _DSD properties reported in DSDT | |
357 | * tables. The values reported are based on either 24MHz | |
358 | * (CNL/CML) or 38.4 MHz (ICL/TGL+). | |
359 | */ | |
360 | if (prop->mclk_freq % 6000000) | |
361 | syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4; | |
362 | else | |
363 | syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24; | |
364 | ||
365 | if (!*shim_mask) { | |
5ee74eb2 PLB |
366 | dev_dbg(sdw->cdns.dev, "%s: powering up all links\n", __func__); |
367 | ||
4a17c441 PLB |
368 | /* we first need to program the SyncPRD/CPU registers */ |
369 | dev_dbg(sdw->cdns.dev, | |
370 | "%s: first link up, programming SYNCPRD\n", __func__); | |
371 | ||
372 | /* set SyncPRD period */ | |
373 | sync_reg = intel_readl(shim, SDW_SHIM_SYNC); | |
f067c925 | 374 | u32p_replace_bits(&sync_reg, syncprd, SDW_SHIM_SYNC_SYNCPRD); |
4a17c441 PLB |
375 | |
376 | /* Set SyncCPU bit */ | |
377 | sync_reg |= SDW_SHIM_SYNC_SYNCCPU; | |
378 | intel_writel(shim, SDW_SHIM_SYNC, sync_reg); | |
71bb8a1b | 379 | |
5ee74eb2 PLB |
380 | /* Link power up sequence */ |
381 | link_control = intel_readl(shim, SDW_SHIM_LCTL); | |
71bb8a1b | 382 | |
5ee74eb2 | 383 | /* only power-up enabled links */ |
3b4979ca VK |
384 | spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, sdw->link_res->link_mask); |
385 | cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask); | |
5ee74eb2 PLB |
386 | |
387 | link_control |= spa_mask; | |
388 | ||
389 | ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask); | |
390 | if (ret < 0) { | |
391 | dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret); | |
392 | goto out; | |
393 | } | |
4a17c441 | 394 | |
4a17c441 PLB |
395 | /* SyncCPU will change once link is active */ |
396 | ret = intel_wait_bit(shim, SDW_SHIM_SYNC, | |
397 | SDW_SHIM_SYNC_SYNCCPU, 0); | |
398 | if (ret < 0) { | |
399 | dev_err(sdw->cdns.dev, | |
400 | "Failed to set SHIM_SYNC: %d\n", ret); | |
401 | goto out; | |
402 | } | |
403 | } | |
404 | ||
405 | *shim_mask |= BIT(link_id); | |
71bb8a1b VK |
406 | |
407 | sdw->cdns.link_up = true; | |
4a17c441 PLB |
408 | out: |
409 | mutex_unlock(sdw->link_res->shim_lock); | |
410 | ||
411 | return ret; | |
71bb8a1b VK |
412 | } |
413 | ||
4a17c441 PLB |
414 | /* this needs to be called with shim_lock */ |
415 | static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw) | |
71bb8a1b | 416 | { |
2523486b | 417 | void __iomem *shim = sdw->link_res->shim; |
71bb8a1b | 418 | unsigned int link_id = sdw->instance; |
4a17c441 | 419 | u16 ioctl; |
71bb8a1b | 420 | |
4a17c441 PLB |
421 | /* Switch to MIP from Glue logic */ |
422 | ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id)); | |
423 | ||
424 | ioctl &= ~(SDW_SHIM_IOCTL_DOE); | |
71bb8a1b | 425 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); |
4a17c441 | 426 | usleep_range(10, 15); |
71bb8a1b | 427 | |
4a17c441 | 428 | ioctl &= ~(SDW_SHIM_IOCTL_DO); |
71bb8a1b | 429 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); |
4a17c441 | 430 | usleep_range(10, 15); |
71bb8a1b | 431 | |
4a17c441 | 432 | ioctl |= (SDW_SHIM_IOCTL_MIF); |
71bb8a1b | 433 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); |
4a17c441 | 434 | usleep_range(10, 15); |
71bb8a1b | 435 | |
4a17c441 PLB |
436 | ioctl &= ~(SDW_SHIM_IOCTL_BKE); |
437 | ioctl &= ~(SDW_SHIM_IOCTL_COE); | |
71bb8a1b | 438 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); |
4a17c441 | 439 | usleep_range(10, 15); |
71bb8a1b | 440 | |
4a17c441 PLB |
441 | /* at this point Master IP has full control of the I/Os */ |
442 | } | |
71bb8a1b | 443 | |
4a17c441 PLB |
444 | /* this needs to be called with shim_lock */ |
445 | static void intel_shim_master_ip_to_glue(struct sdw_intel *sdw) | |
446 | { | |
447 | unsigned int link_id = sdw->instance; | |
448 | void __iomem *shim = sdw->link_res->shim; | |
449 | u16 ioctl; | |
450 | ||
451 | /* Glue logic */ | |
452 | ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id)); | |
453 | ioctl |= SDW_SHIM_IOCTL_BKE; | |
454 | ioctl |= SDW_SHIM_IOCTL_COE; | |
71bb8a1b | 455 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); |
4a17c441 | 456 | usleep_range(10, 15); |
71bb8a1b | 457 | |
4a17c441 | 458 | ioctl &= ~(SDW_SHIM_IOCTL_MIF); |
71bb8a1b | 459 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); |
4a17c441 | 460 | usleep_range(10, 15); |
71bb8a1b | 461 | |
4a17c441 PLB |
462 | /* at this point Integration Glue has full control of the I/Os */ |
463 | } | |
464 | ||
465 | static int intel_shim_init(struct sdw_intel *sdw, bool clock_stop) | |
466 | { | |
467 | void __iomem *shim = sdw->link_res->shim; | |
468 | unsigned int link_id = sdw->instance; | |
469 | int ret = 0; | |
470 | u16 ioctl = 0, act = 0; | |
471 | ||
472 | mutex_lock(sdw->link_res->shim_lock); | |
473 | ||
474 | /* Initialize Shim */ | |
475 | ioctl |= SDW_SHIM_IOCTL_BKE; | |
71bb8a1b | 476 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); |
4a17c441 | 477 | usleep_range(10, 15); |
71bb8a1b | 478 | |
4a17c441 PLB |
479 | ioctl |= SDW_SHIM_IOCTL_WPDD; |
480 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); | |
481 | usleep_range(10, 15); | |
71bb8a1b | 482 | |
4a17c441 | 483 | ioctl |= SDW_SHIM_IOCTL_DO; |
71bb8a1b | 484 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); |
4a17c441 PLB |
485 | usleep_range(10, 15); |
486 | ||
487 | ioctl |= SDW_SHIM_IOCTL_DOE; | |
71bb8a1b | 488 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); |
4a17c441 PLB |
489 | usleep_range(10, 15); |
490 | ||
491 | intel_shim_glue_to_master_ip(sdw); | |
71bb8a1b | 492 | |
f067c925 | 493 | u16p_replace_bits(&act, 0x1, SDW_SHIM_CTMCTL_DOAIS); |
71bb8a1b VK |
494 | act |= SDW_SHIM_CTMCTL_DACTQE; |
495 | act |= SDW_SHIM_CTMCTL_DODS; | |
496 | intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act); | |
4a17c441 | 497 | usleep_range(10, 15); |
71bb8a1b | 498 | |
4a17c441 PLB |
499 | mutex_unlock(sdw->link_res->shim_lock); |
500 | ||
501 | return ret; | |
502 | } | |
503 | ||
ab2c9132 | 504 | static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable) |
4a17c441 PLB |
505 | { |
506 | void __iomem *shim = sdw->link_res->shim; | |
507 | unsigned int link_id = sdw->instance; | |
508 | u16 wake_en, wake_sts; | |
509 | ||
510 | mutex_lock(sdw->link_res->shim_lock); | |
511 | wake_en = intel_readw(shim, SDW_SHIM_WAKEEN); | |
512 | ||
513 | if (wake_enable) { | |
514 | /* Enable the wakeup */ | |
515 | wake_en |= (SDW_SHIM_WAKEEN_ENABLE << link_id); | |
516 | intel_writew(shim, SDW_SHIM_WAKEEN, wake_en); | |
517 | } else { | |
518 | /* Disable the wake up interrupt */ | |
519 | wake_en &= ~(SDW_SHIM_WAKEEN_ENABLE << link_id); | |
520 | intel_writew(shim, SDW_SHIM_WAKEEN, wake_en); | |
521 | ||
522 | /* Clear wake status */ | |
523 | wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS); | |
524 | wake_sts |= (SDW_SHIM_WAKEEN_ENABLE << link_id); | |
525 | intel_writew(shim, SDW_SHIM_WAKESTS_STATUS, wake_sts); | |
526 | } | |
527 | mutex_unlock(sdw->link_res->shim_lock); | |
528 | } | |
529 | ||
9b3b4b3f | 530 | static int intel_link_power_down(struct sdw_intel *sdw) |
4a17c441 | 531 | { |
5ee74eb2 | 532 | u32 link_control, spa_mask, cpa_mask; |
4a17c441 PLB |
533 | unsigned int link_id = sdw->instance; |
534 | void __iomem *shim = sdw->link_res->shim; | |
535 | u32 *shim_mask = sdw->link_res->shim_mask; | |
536 | int ret = 0; | |
537 | ||
538 | mutex_lock(sdw->link_res->shim_lock); | |
539 | ||
540 | intel_shim_master_ip_to_glue(sdw); | |
541 | ||
4a17c441 PLB |
542 | if (!(*shim_mask & BIT(link_id))) |
543 | dev_err(sdw->cdns.dev, | |
544 | "%s: Unbalanced power-up/down calls\n", __func__); | |
545 | ||
546 | *shim_mask &= ~BIT(link_id); | |
547 | ||
5ee74eb2 PLB |
548 | if (!*shim_mask) { |
549 | ||
550 | dev_dbg(sdw->cdns.dev, "%s: powering down all links\n", __func__); | |
551 | ||
552 | /* Link power down sequence */ | |
553 | link_control = intel_readl(shim, SDW_SHIM_LCTL); | |
554 | ||
555 | /* only power-down enabled links */ | |
3b4979ca VK |
556 | spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, ~sdw->link_res->link_mask); |
557 | cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask); | |
5ee74eb2 PLB |
558 | |
559 | link_control &= spa_mask; | |
560 | ||
561 | ret = intel_clear_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask); | |
562 | } | |
563 | ||
564 | link_control = intel_readl(shim, SDW_SHIM_LCTL); | |
565 | ||
4a17c441 | 566 | mutex_unlock(sdw->link_res->shim_lock); |
71bb8a1b | 567 | |
5ee74eb2 PLB |
568 | if (ret < 0) { |
569 | dev_err(sdw->cdns.dev, "%s: could not power down link\n", __func__); | |
570 | ||
4a17c441 | 571 | return ret; |
5ee74eb2 | 572 | } |
71bb8a1b | 573 | |
4a17c441 PLB |
574 | sdw->cdns.link_up = false; |
575 | return 0; | |
71bb8a1b VK |
576 | } |
577 | ||
02629e45 PLB |
578 | static void intel_shim_sync_arm(struct sdw_intel *sdw) |
579 | { | |
580 | void __iomem *shim = sdw->link_res->shim; | |
581 | u32 sync_reg; | |
582 | ||
583 | mutex_lock(sdw->link_res->shim_lock); | |
584 | ||
585 | /* update SYNC register */ | |
586 | sync_reg = intel_readl(shim, SDW_SHIM_SYNC); | |
587 | sync_reg |= (SDW_SHIM_SYNC_CMDSYNC << sdw->instance); | |
588 | intel_writel(shim, SDW_SHIM_SYNC, sync_reg); | |
589 | ||
590 | mutex_unlock(sdw->link_res->shim_lock); | |
591 | } | |
592 | ||
437e3289 PLB |
593 | static int intel_shim_sync_go_unlocked(struct sdw_intel *sdw) |
594 | { | |
595 | void __iomem *shim = sdw->link_res->shim; | |
596 | u32 sync_reg; | |
597 | int ret; | |
71bb8a1b | 598 | |
437e3289 | 599 | /* Read SYNC register */ |
71bb8a1b | 600 | sync_reg = intel_readl(shim, SDW_SHIM_SYNC); |
71bb8a1b | 601 | |
437e3289 PLB |
602 | /* |
603 | * Set SyncGO bit to synchronously trigger a bank switch for | |
604 | * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all | |
605 | * the Masters. | |
606 | */ | |
607 | sync_reg |= SDW_SHIM_SYNC_SYNCGO; | |
608 | ||
71bb8a1b | 609 | ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg, |
437e3289 PLB |
610 | SDW_SHIM_SYNC_SYNCGO); |
611 | ||
71bb8a1b | 612 | if (ret < 0) |
437e3289 | 613 | dev_err(sdw->cdns.dev, "SyncGO clear failed: %d\n", ret); |
71bb8a1b VK |
614 | |
615 | return ret; | |
616 | } | |
617 | ||
857a7c42 PLB |
618 | static int intel_shim_sync_go(struct sdw_intel *sdw) |
619 | { | |
620 | int ret; | |
621 | ||
622 | mutex_lock(sdw->link_res->shim_lock); | |
623 | ||
624 | ret = intel_shim_sync_go_unlocked(sdw); | |
625 | ||
626 | mutex_unlock(sdw->link_res->shim_lock); | |
627 | ||
628 | return ret; | |
629 | } | |
630 | ||
37a2d22b VK |
631 | /* |
632 | * PDI routines | |
633 | */ | |
634 | static void intel_pdi_init(struct sdw_intel *sdw, | |
d542bc9e | 635 | struct sdw_cdns_stream_config *config) |
37a2d22b | 636 | { |
2523486b | 637 | void __iomem *shim = sdw->link_res->shim; |
37a2d22b VK |
638 | unsigned int link_id = sdw->instance; |
639 | int pcm_cap, pdm_cap; | |
640 | ||
641 | /* PCM Stream Capability */ | |
642 | pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id)); | |
643 | ||
3b4979ca VK |
644 | config->pcm_bd = FIELD_GET(SDW_SHIM_PCMSCAP_BSS, pcm_cap); |
645 | config->pcm_in = FIELD_GET(SDW_SHIM_PCMSCAP_ISS, pcm_cap); | |
646 | config->pcm_out = FIELD_GET(SDW_SHIM_PCMSCAP_OSS, pcm_cap); | |
37a2d22b | 647 | |
121f4361 PLB |
648 | dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n", |
649 | config->pcm_bd, config->pcm_in, config->pcm_out); | |
650 | ||
37a2d22b VK |
651 | /* PDM Stream Capability */ |
652 | pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id)); | |
653 | ||
3b4979ca VK |
654 | config->pdm_bd = FIELD_GET(SDW_SHIM_PDMSCAP_BSS, pdm_cap); |
655 | config->pdm_in = FIELD_GET(SDW_SHIM_PDMSCAP_ISS, pdm_cap); | |
656 | config->pdm_out = FIELD_GET(SDW_SHIM_PDMSCAP_OSS, pdm_cap); | |
121f4361 PLB |
657 | |
658 | dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n", | |
659 | config->pdm_bd, config->pdm_in, config->pdm_out); | |
37a2d22b VK |
660 | } |
661 | ||
662 | static int | |
663 | intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm) | |
664 | { | |
2523486b | 665 | void __iomem *shim = sdw->link_res->shim; |
37a2d22b VK |
666 | unsigned int link_id = sdw->instance; |
667 | int count; | |
668 | ||
669 | if (pcm) { | |
670 | count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num)); | |
18046335 PLB |
671 | |
672 | /* | |
673 | * WORKAROUND: on all existing Intel controllers, pdi | |
674 | * number 2 reports channel count as 1 even though it | |
675 | * supports 8 channels. Performing hardcoding for pdi | |
676 | * number 2. | |
677 | */ | |
678 | if (pdi_num == 2) | |
679 | count = 7; | |
680 | ||
37a2d22b VK |
681 | } else { |
682 | count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id)); | |
3b4979ca | 683 | count = FIELD_GET(SDW_SHIM_PDMSCAP_CPSS, count); |
37a2d22b VK |
684 | } |
685 | ||
686 | /* zero based values for channel count in register */ | |
687 | count++; | |
688 | ||
689 | return count; | |
690 | } | |
691 | ||
692 | static int intel_pdi_get_ch_update(struct sdw_intel *sdw, | |
d542bc9e PLB |
693 | struct sdw_cdns_pdi *pdi, |
694 | unsigned int num_pdi, | |
695 | unsigned int *num_ch, bool pcm) | |
37a2d22b VK |
696 | { |
697 | int i, ch_count = 0; | |
698 | ||
699 | for (i = 0; i < num_pdi; i++) { | |
700 | pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm); | |
701 | ch_count += pdi->ch_count; | |
702 | pdi++; | |
703 | } | |
704 | ||
705 | *num_ch = ch_count; | |
706 | return 0; | |
707 | } | |
708 | ||
709 | static int intel_pdi_stream_ch_update(struct sdw_intel *sdw, | |
d542bc9e | 710 | struct sdw_cdns_streams *stream, bool pcm) |
37a2d22b VK |
711 | { |
712 | intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd, | |
d542bc9e | 713 | &stream->num_ch_bd, pcm); |
37a2d22b VK |
714 | |
715 | intel_pdi_get_ch_update(sdw, stream->in, stream->num_in, | |
d542bc9e | 716 | &stream->num_ch_in, pcm); |
37a2d22b VK |
717 | |
718 | intel_pdi_get_ch_update(sdw, stream->out, stream->num_out, | |
d542bc9e | 719 | &stream->num_ch_out, pcm); |
37a2d22b VK |
720 | |
721 | return 0; | |
722 | } | |
723 | ||
724 | static int intel_pdi_ch_update(struct sdw_intel *sdw) | |
725 | { | |
726 | /* First update PCM streams followed by PDM streams */ | |
727 | intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true); | |
728 | intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false); | |
729 | ||
730 | return 0; | |
731 | } | |
732 | ||
733 | static void | |
734 | intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi) | |
735 | { | |
2523486b | 736 | void __iomem *shim = sdw->link_res->shim; |
37a2d22b VK |
737 | unsigned int link_id = sdw->instance; |
738 | int pdi_conf = 0; | |
739 | ||
c134f914 PLB |
740 | /* the Bulk and PCM streams are not contiguous */ |
741 | pdi->intel_alh_id = (link_id * 16) + pdi->num + 3; | |
742 | if (pdi->num >= 2) | |
743 | pdi->intel_alh_id += 2; | |
37a2d22b VK |
744 | |
745 | /* | |
746 | * Program stream parameters to stream SHIM register | |
747 | * This is applicable for PCM stream only. | |
748 | */ | |
749 | if (pdi->type != SDW_STREAM_PCM) | |
750 | return; | |
751 | ||
752 | if (pdi->dir == SDW_DATA_DIR_RX) | |
753 | pdi_conf |= SDW_SHIM_PCMSYCM_DIR; | |
754 | else | |
755 | pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR); | |
756 | ||
f067c925 VK |
757 | u32p_replace_bits(&pdi_conf, pdi->intel_alh_id, SDW_SHIM_PCMSYCM_STREAM); |
758 | u32p_replace_bits(&pdi_conf, pdi->l_ch_num, SDW_SHIM_PCMSYCM_LCHN); | |
759 | u32p_replace_bits(&pdi_conf, pdi->h_ch_num, SDW_SHIM_PCMSYCM_HCHN); | |
37a2d22b VK |
760 | |
761 | intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf); | |
762 | } | |
763 | ||
764 | static void | |
765 | intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi) | |
766 | { | |
2523486b | 767 | void __iomem *alh = sdw->link_res->alh; |
37a2d22b VK |
768 | unsigned int link_id = sdw->instance; |
769 | unsigned int conf; | |
770 | ||
c134f914 PLB |
771 | /* the Bulk and PCM streams are not contiguous */ |
772 | pdi->intel_alh_id = (link_id * 16) + pdi->num + 3; | |
773 | if (pdi->num >= 2) | |
774 | pdi->intel_alh_id += 2; | |
37a2d22b VK |
775 | |
776 | /* Program Stream config ALH register */ | |
777 | conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id)); | |
778 | ||
f067c925 VK |
779 | u32p_replace_bits(&conf, SDW_ALH_STRMZCFG_DMAT_VAL, SDW_ALH_STRMZCFG_DMAT); |
780 | u32p_replace_bits(&conf, pdi->ch_count - 1, SDW_ALH_STRMZCFG_CHN); | |
37a2d22b VK |
781 | |
782 | intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf); | |
783 | } | |
784 | ||
4b206d34 | 785 | static int intel_params_stream(struct sdw_intel *sdw, |
d542bc9e PLB |
786 | struct snd_pcm_substream *substream, |
787 | struct snd_soc_dai *dai, | |
4b206d34 RW |
788 | struct snd_pcm_hw_params *hw_params, |
789 | int link_id, int alh_stream_id) | |
c46302ec | 790 | { |
2523486b | 791 | struct sdw_intel_link_res *res = sdw->link_res; |
4b206d34 | 792 | struct sdw_intel_stream_params_data params_data; |
05c8afe4 | 793 | |
4b206d34 RW |
794 | params_data.substream = substream; |
795 | params_data.dai = dai; | |
796 | params_data.hw_params = hw_params; | |
797 | params_data.link_id = link_id; | |
798 | params_data.alh_stream_id = alh_stream_id; | |
c46302ec | 799 | |
4b206d34 RW |
800 | if (res->ops && res->ops->params_stream && res->dev) |
801 | return res->ops->params_stream(res->dev, | |
802 | ¶ms_data); | |
c46302ec VK |
803 | return -EIO; |
804 | } | |
805 | ||
eff346f2 PLB |
806 | static int intel_free_stream(struct sdw_intel *sdw, |
807 | struct snd_pcm_substream *substream, | |
808 | struct snd_soc_dai *dai, | |
809 | int link_id) | |
810 | { | |
811 | struct sdw_intel_link_res *res = sdw->link_res; | |
812 | struct sdw_intel_stream_free_data free_data; | |
813 | ||
814 | free_data.substream = substream; | |
815 | free_data.dai = dai; | |
816 | free_data.link_id = link_id; | |
817 | ||
818 | if (res->ops && res->ops->free_stream && res->dev) | |
819 | return res->ops->free_stream(res->dev, | |
820 | &free_data); | |
821 | ||
822 | return 0; | |
823 | } | |
824 | ||
30246e2d SN |
825 | /* |
826 | * bank switch routines | |
827 | */ | |
828 | ||
829 | static int intel_pre_bank_switch(struct sdw_bus *bus) | |
830 | { | |
831 | struct sdw_cdns *cdns = bus_to_cdns(bus); | |
832 | struct sdw_intel *sdw = cdns_to_intel(cdns); | |
30246e2d SN |
833 | |
834 | /* Write to register only for multi-link */ | |
835 | if (!bus->multi_link) | |
836 | return 0; | |
837 | ||
02629e45 | 838 | intel_shim_sync_arm(sdw); |
30246e2d SN |
839 | |
840 | return 0; | |
841 | } | |
842 | ||
843 | static int intel_post_bank_switch(struct sdw_bus *bus) | |
844 | { | |
845 | struct sdw_cdns *cdns = bus_to_cdns(bus); | |
846 | struct sdw_intel *sdw = cdns_to_intel(cdns); | |
2523486b | 847 | void __iomem *shim = sdw->link_res->shim; |
30246e2d SN |
848 | int sync_reg, ret; |
849 | ||
850 | /* Write to register only for multi-link */ | |
851 | if (!bus->multi_link) | |
852 | return 0; | |
853 | ||
4a17c441 PLB |
854 | mutex_lock(sdw->link_res->shim_lock); |
855 | ||
30246e2d SN |
856 | /* Read SYNC register */ |
857 | sync_reg = intel_readl(shim, SDW_SHIM_SYNC); | |
858 | ||
859 | /* | |
860 | * post_bank_switch() ops is called from the bus in loop for | |
861 | * all the Masters in the steam with the expectation that | |
862 | * we trigger the bankswitch for the only first Master in the list | |
863 | * and do nothing for the other Masters | |
864 | * | |
865 | * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master. | |
866 | */ | |
4a17c441 PLB |
867 | if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK)) { |
868 | ret = 0; | |
869 | goto unlock; | |
870 | } | |
30246e2d | 871 | |
437e3289 | 872 | ret = intel_shim_sync_go_unlocked(sdw); |
4a17c441 PLB |
873 | unlock: |
874 | mutex_unlock(sdw->link_res->shim_lock); | |
30246e2d | 875 | |
30246e2d | 876 | if (ret < 0) |
17ed5bef | 877 | dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret); |
30246e2d SN |
878 | |
879 | return ret; | |
880 | } | |
881 | ||
c46302ec VK |
882 | /* |
883 | * DAI routines | |
884 | */ | |
885 | ||
5e7484d0 RW |
886 | static int intel_startup(struct snd_pcm_substream *substream, |
887 | struct snd_soc_dai *dai) | |
888 | { | |
ebf878ed PLB |
889 | struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); |
890 | int ret; | |
891 | ||
892 | ret = pm_runtime_get_sync(cdns->dev); | |
893 | if (ret < 0 && ret != -EACCES) { | |
894 | dev_err_ratelimited(cdns->dev, | |
895 | "pm_runtime_get_sync failed in %s, ret %d\n", | |
896 | __func__, ret); | |
897 | pm_runtime_put_noidle(cdns->dev); | |
898 | return ret; | |
899 | } | |
ff16d1e5 | 900 | return 0; |
5e7484d0 RW |
901 | } |
902 | ||
c46302ec | 903 | static int intel_hw_params(struct snd_pcm_substream *substream, |
d542bc9e PLB |
904 | struct snd_pcm_hw_params *params, |
905 | struct snd_soc_dai *dai) | |
c46302ec VK |
906 | { |
907 | struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); | |
908 | struct sdw_intel *sdw = cdns_to_intel(cdns); | |
909 | struct sdw_cdns_dma_data *dma; | |
57a34790 | 910 | struct sdw_cdns_pdi *pdi; |
c46302ec VK |
911 | struct sdw_stream_config sconfig; |
912 | struct sdw_port_config *pconfig; | |
57a34790 PLB |
913 | int ch, dir; |
914 | int ret; | |
c46302ec VK |
915 | bool pcm = true; |
916 | ||
917 | dma = snd_soc_dai_get_dma_data(dai, substream); | |
918 | if (!dma) | |
919 | return -EIO; | |
920 | ||
921 | ch = params_channels(params); | |
922 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
923 | dir = SDW_DATA_DIR_RX; | |
924 | else | |
925 | dir = SDW_DATA_DIR_TX; | |
926 | ||
57a34790 | 927 | if (dma->stream_type == SDW_STREAM_PDM) |
c46302ec | 928 | pcm = false; |
c46302ec | 929 | |
57a34790 | 930 | if (pcm) |
1b53385e | 931 | pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id); |
57a34790 | 932 | else |
1b53385e | 933 | pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pdm, ch, dir, dai->id); |
57a34790 PLB |
934 | |
935 | if (!pdi) { | |
936 | ret = -EINVAL; | |
937 | goto error; | |
c46302ec VK |
938 | } |
939 | ||
57a34790 PLB |
940 | /* do run-time configurations for SHIM, ALH and PDI/PORT */ |
941 | intel_pdi_shim_configure(sdw, pdi); | |
942 | intel_pdi_alh_configure(sdw, pdi); | |
943 | sdw_cdns_config_stream(cdns, ch, dir, pdi); | |
c46302ec | 944 | |
a5a0239c BL |
945 | /* store pdi and hw_params, may be needed in prepare step */ |
946 | dma->suspended = false; | |
947 | dma->pdi = pdi; | |
948 | dma->hw_params = params; | |
c46302ec VK |
949 | |
950 | /* Inform DSP about PDI stream number */ | |
4b206d34 RW |
951 | ret = intel_params_stream(sdw, substream, dai, params, |
952 | sdw->instance, | |
57a34790 PLB |
953 | pdi->intel_alh_id); |
954 | if (ret) | |
955 | goto error; | |
c46302ec VK |
956 | |
957 | sconfig.direction = dir; | |
958 | sconfig.ch_count = ch; | |
959 | sconfig.frame_rate = params_rate(params); | |
960 | sconfig.type = dma->stream_type; | |
961 | ||
962 | if (dma->stream_type == SDW_STREAM_PDM) { | |
963 | sconfig.frame_rate *= 50; | |
964 | sconfig.bps = 1; | |
965 | } else { | |
966 | sconfig.bps = snd_pcm_format_width(params_format(params)); | |
967 | } | |
968 | ||
969 | /* Port configuration */ | |
57a34790 | 970 | pconfig = kcalloc(1, sizeof(*pconfig), GFP_KERNEL); |
c46302ec VK |
971 | if (!pconfig) { |
972 | ret = -ENOMEM; | |
57a34790 | 973 | goto error; |
c46302ec VK |
974 | } |
975 | ||
57a34790 PLB |
976 | pconfig->num = pdi->num; |
977 | pconfig->ch_mask = (1 << ch) - 1; | |
c46302ec VK |
978 | |
979 | ret = sdw_stream_add_master(&cdns->bus, &sconfig, | |
57a34790 PLB |
980 | pconfig, 1, dma->stream); |
981 | if (ret) | |
17ed5bef | 982 | dev_err(cdns->dev, "add master to stream failed:%d\n", ret); |
c46302ec | 983 | |
c46302ec | 984 | kfree(pconfig); |
57a34790 | 985 | error: |
c46302ec VK |
986 | return ret; |
987 | } | |
988 | ||
27b198f4 RW |
989 | static int intel_prepare(struct snd_pcm_substream *substream, |
990 | struct snd_soc_dai *dai) | |
991 | { | |
a5a0239c BL |
992 | struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); |
993 | struct sdw_intel *sdw = cdns_to_intel(cdns); | |
27b198f4 | 994 | struct sdw_cdns_dma_data *dma; |
a5a0239c | 995 | int ch, dir; |
244eb888 | 996 | int ret = 0; |
27b198f4 RW |
997 | |
998 | dma = snd_soc_dai_get_dma_data(dai, substream); | |
999 | if (!dma) { | |
1000 | dev_err(dai->dev, "failed to get dma data in %s", | |
1001 | __func__); | |
1002 | return -EIO; | |
1003 | } | |
1004 | ||
a5a0239c BL |
1005 | if (dma->suspended) { |
1006 | dma->suspended = false; | |
1007 | ||
1008 | /* | |
1009 | * .prepare() is called after system resume, where we | |
1010 | * need to reinitialize the SHIM/ALH/Cadence IP. | |
1011 | * .prepare() is also called to deal with underflows, | |
1012 | * but in those cases we cannot touch ALH/SHIM | |
1013 | * registers | |
1014 | */ | |
1015 | ||
1016 | /* configure stream */ | |
1017 | ch = params_channels(dma->hw_params); | |
1018 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
1019 | dir = SDW_DATA_DIR_RX; | |
1020 | else | |
1021 | dir = SDW_DATA_DIR_TX; | |
1022 | ||
1023 | intel_pdi_shim_configure(sdw, dma->pdi); | |
1024 | intel_pdi_alh_configure(sdw, dma->pdi); | |
1025 | sdw_cdns_config_stream(cdns, ch, dir, dma->pdi); | |
1026 | ||
1027 | /* Inform DSP about PDI stream number */ | |
1028 | ret = intel_params_stream(sdw, substream, dai, | |
1029 | dma->hw_params, | |
1030 | sdw->instance, | |
1031 | dma->pdi->intel_alh_id); | |
a5a0239c BL |
1032 | } |
1033 | ||
a5a0239c | 1034 | return ret; |
27b198f4 RW |
1035 | } |
1036 | ||
c46302ec VK |
1037 | static int |
1038 | intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) | |
1039 | { | |
1040 | struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); | |
eff346f2 | 1041 | struct sdw_intel *sdw = cdns_to_intel(cdns); |
c46302ec VK |
1042 | struct sdw_cdns_dma_data *dma; |
1043 | int ret; | |
1044 | ||
1045 | dma = snd_soc_dai_get_dma_data(dai, substream); | |
1046 | if (!dma) | |
1047 | return -EIO; | |
1048 | ||
244eb888 PLB |
1049 | /* |
1050 | * The sdw stream state will transition to RELEASED when stream-> | |
1051 | * master_list is empty. So the stream state will transition to | |
1052 | * DEPREPARED for the first cpu-dai and to RELEASED for the last | |
1053 | * cpu-dai. | |
1054 | */ | |
c46302ec | 1055 | ret = sdw_stream_remove_master(&cdns->bus, dma->stream); |
eff346f2 | 1056 | if (ret < 0) { |
17ed5bef | 1057 | dev_err(dai->dev, "remove master from stream %s failed: %d\n", |
d542bc9e | 1058 | dma->stream->name, ret); |
eff346f2 PLB |
1059 | return ret; |
1060 | } | |
c46302ec | 1061 | |
eff346f2 PLB |
1062 | ret = intel_free_stream(sdw, substream, dai, sdw->instance); |
1063 | if (ret < 0) { | |
1064 | dev_err(dai->dev, "intel_free_stream: failed %d", ret); | |
1065 | return ret; | |
1066 | } | |
1067 | ||
a5a0239c BL |
1068 | dma->hw_params = NULL; |
1069 | dma->pdi = NULL; | |
1070 | ||
eff346f2 | 1071 | return 0; |
c46302ec VK |
1072 | } |
1073 | ||
183c7687 PLB |
1074 | static void intel_shutdown(struct snd_pcm_substream *substream, |
1075 | struct snd_soc_dai *dai) | |
1076 | { | |
ebf878ed | 1077 | struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); |
183c7687 | 1078 | |
ebf878ed PLB |
1079 | pm_runtime_mark_last_busy(cdns->dev); |
1080 | pm_runtime_put_autosuspend(cdns->dev); | |
183c7687 PLB |
1081 | } |
1082 | ||
a5a0239c BL |
1083 | static int intel_component_dais_suspend(struct snd_soc_component *component) |
1084 | { | |
1085 | struct sdw_cdns_dma_data *dma; | |
1086 | struct snd_soc_dai *dai; | |
1087 | ||
1088 | for_each_component_dais(component, dai) { | |
1089 | /* | |
1090 | * we don't have a .suspend dai_ops, and we don't have access | |
1091 | * to the substream, so let's mark both capture and playback | |
1092 | * DMA contexts as suspended | |
1093 | */ | |
1094 | dma = dai->playback_dma_data; | |
1095 | if (dma) | |
1096 | dma->suspended = true; | |
1097 | ||
1098 | dma = dai->capture_dma_data; | |
1099 | if (dma) | |
1100 | dma->suspended = true; | |
1101 | } | |
1102 | ||
1103 | return 0; | |
1104 | } | |
1105 | ||
c46302ec | 1106 | static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai, |
d542bc9e | 1107 | void *stream, int direction) |
c46302ec VK |
1108 | { |
1109 | return cdns_set_sdw_stream(dai, stream, true, direction); | |
1110 | } | |
1111 | ||
1112 | static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai, | |
d542bc9e | 1113 | void *stream, int direction) |
c46302ec VK |
1114 | { |
1115 | return cdns_set_sdw_stream(dai, stream, false, direction); | |
1116 | } | |
1117 | ||
09553140 PLB |
1118 | static void *intel_get_sdw_stream(struct snd_soc_dai *dai, |
1119 | int direction) | |
1120 | { | |
1121 | struct sdw_cdns_dma_data *dma; | |
1122 | ||
1123 | if (direction == SNDRV_PCM_STREAM_PLAYBACK) | |
1124 | dma = dai->playback_dma_data; | |
1125 | else | |
1126 | dma = dai->capture_dma_data; | |
1127 | ||
1128 | if (!dma) | |
06dcb4e4 | 1129 | return ERR_PTR(-EINVAL); |
09553140 PLB |
1130 | |
1131 | return dma->stream; | |
1132 | } | |
1133 | ||
b1635596 | 1134 | static const struct snd_soc_dai_ops intel_pcm_dai_ops = { |
5e7484d0 | 1135 | .startup = intel_startup, |
c46302ec | 1136 | .hw_params = intel_hw_params, |
27b198f4 | 1137 | .prepare = intel_prepare, |
c46302ec | 1138 | .hw_free = intel_hw_free, |
183c7687 | 1139 | .shutdown = intel_shutdown, |
c46302ec | 1140 | .set_sdw_stream = intel_pcm_set_sdw_stream, |
09553140 | 1141 | .get_sdw_stream = intel_get_sdw_stream, |
c46302ec VK |
1142 | }; |
1143 | ||
b1635596 | 1144 | static const struct snd_soc_dai_ops intel_pdm_dai_ops = { |
5e7484d0 | 1145 | .startup = intel_startup, |
c46302ec | 1146 | .hw_params = intel_hw_params, |
27b198f4 | 1147 | .prepare = intel_prepare, |
c46302ec | 1148 | .hw_free = intel_hw_free, |
183c7687 | 1149 | .shutdown = intel_shutdown, |
c46302ec | 1150 | .set_sdw_stream = intel_pdm_set_sdw_stream, |
09553140 | 1151 | .get_sdw_stream = intel_get_sdw_stream, |
c46302ec VK |
1152 | }; |
1153 | ||
1154 | static const struct snd_soc_component_driver dai_component = { | |
1155 | .name = "soundwire", | |
a5a0239c | 1156 | .suspend = intel_component_dais_suspend |
c46302ec VK |
1157 | }; |
1158 | ||
1159 | static int intel_create_dai(struct sdw_cdns *cdns, | |
d542bc9e PLB |
1160 | struct snd_soc_dai_driver *dais, |
1161 | enum intel_pdi_type type, | |
1162 | u32 num, u32 off, u32 max_ch, bool pcm) | |
c46302ec VK |
1163 | { |
1164 | int i; | |
1165 | ||
1166 | if (num == 0) | |
1167 | return 0; | |
1168 | ||
1169 | /* TODO: Read supported rates/formats from hardware */ | |
1170 | for (i = off; i < (off + num); i++) { | |
bf6d6e68 PLB |
1171 | dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL, |
1172 | "SDW%d Pin%d", | |
1173 | cdns->instance, i); | |
c46302ec VK |
1174 | if (!dais[i].name) |
1175 | return -ENOMEM; | |
1176 | ||
1177 | if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) { | |
c46302ec VK |
1178 | dais[i].playback.channels_min = 1; |
1179 | dais[i].playback.channels_max = max_ch; | |
1180 | dais[i].playback.rates = SNDRV_PCM_RATE_48000; | |
1181 | dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE; | |
1182 | } | |
1183 | ||
1184 | if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) { | |
39194128 SK |
1185 | dais[i].capture.channels_min = 1; |
1186 | dais[i].capture.channels_max = max_ch; | |
c46302ec VK |
1187 | dais[i].capture.rates = SNDRV_PCM_RATE_48000; |
1188 | dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE; | |
1189 | } | |
1190 | ||
c46302ec VK |
1191 | if (pcm) |
1192 | dais[i].ops = &intel_pcm_dai_ops; | |
1193 | else | |
1194 | dais[i].ops = &intel_pdm_dai_ops; | |
1195 | } | |
1196 | ||
1197 | return 0; | |
1198 | } | |
1199 | ||
1200 | static int intel_register_dai(struct sdw_intel *sdw) | |
1201 | { | |
1202 | struct sdw_cdns *cdns = &sdw->cdns; | |
1203 | struct sdw_cdns_streams *stream; | |
1204 | struct snd_soc_dai_driver *dais; | |
1205 | int num_dai, ret, off = 0; | |
1206 | ||
1207 | /* DAIs are created based on total number of PDIs supported */ | |
1208 | num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi; | |
1209 | ||
1210 | dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL); | |
1211 | if (!dais) | |
1212 | return -ENOMEM; | |
1213 | ||
1214 | /* Create PCM DAIs */ | |
1215 | stream = &cdns->pcm; | |
1216 | ||
cf924962 | 1217 | ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in, |
1215daee | 1218 | off, stream->num_ch_in, true); |
c46302ec VK |
1219 | if (ret) |
1220 | return ret; | |
1221 | ||
1222 | off += cdns->pcm.num_in; | |
1215daee VK |
1223 | ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out, |
1224 | off, stream->num_ch_out, true); | |
c46302ec VK |
1225 | if (ret) |
1226 | return ret; | |
1227 | ||
1228 | off += cdns->pcm.num_out; | |
1215daee VK |
1229 | ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd, |
1230 | off, stream->num_ch_bd, true); | |
c46302ec VK |
1231 | if (ret) |
1232 | return ret; | |
1233 | ||
1234 | /* Create PDM DAIs */ | |
1235 | stream = &cdns->pdm; | |
1236 | off += cdns->pcm.num_bd; | |
1215daee VK |
1237 | ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in, |
1238 | off, stream->num_ch_in, false); | |
c46302ec VK |
1239 | if (ret) |
1240 | return ret; | |
1241 | ||
1242 | off += cdns->pdm.num_in; | |
1215daee VK |
1243 | ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out, |
1244 | off, stream->num_ch_out, false); | |
c46302ec VK |
1245 | if (ret) |
1246 | return ret; | |
1247 | ||
cf924962 | 1248 | off += cdns->pdm.num_out; |
1215daee VK |
1249 | ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd, |
1250 | off, stream->num_ch_bd, false); | |
c46302ec VK |
1251 | if (ret) |
1252 | return ret; | |
1253 | ||
1254 | return snd_soc_register_component(cdns->dev, &dai_component, | |
d542bc9e | 1255 | dais, num_dai); |
c46302ec VK |
1256 | } |
1257 | ||
085f4ace PLB |
1258 | static int sdw_master_read_intel_prop(struct sdw_bus *bus) |
1259 | { | |
1260 | struct sdw_master_prop *prop = &bus->prop; | |
1261 | struct fwnode_handle *link; | |
1262 | char name[32]; | |
395713d8 | 1263 | u32 quirk_mask; |
085f4ace PLB |
1264 | |
1265 | /* Find master handle */ | |
1266 | snprintf(name, sizeof(name), | |
1267 | "mipi-sdw-link-%d-subproperties", bus->link_id); | |
1268 | ||
1269 | link = device_get_named_child_node(bus->dev, name); | |
1270 | if (!link) { | |
1271 | dev_err(bus->dev, "Master node %s not found\n", name); | |
1272 | return -EIO; | |
1273 | } | |
1274 | ||
1275 | fwnode_property_read_u32(link, | |
1276 | "intel-sdw-ip-clock", | |
1277 | &prop->mclk_freq); | |
395713d8 | 1278 | |
a19efb52 BL |
1279 | /* the values reported by BIOS are the 2x clock, not the bus clock */ |
1280 | prop->mclk_freq /= 2; | |
1281 | ||
395713d8 PLB |
1282 | fwnode_property_read_u32(link, |
1283 | "intel-quirk-mask", | |
1284 | &quirk_mask); | |
1285 | ||
1286 | if (quirk_mask & SDW_INTEL_QUIRK_MASK_BUS_DISABLE) | |
1287 | prop->hw_disabled = true; | |
1288 | ||
085f4ace PLB |
1289 | return 0; |
1290 | } | |
1291 | ||
71bb8a1b VK |
1292 | static int intel_prop_read(struct sdw_bus *bus) |
1293 | { | |
1294 | /* Initialize with default handler to read all DisCo properties */ | |
1295 | sdw_master_read_prop(bus); | |
1296 | ||
085f4ace PLB |
1297 | /* read Intel-specific properties */ |
1298 | sdw_master_read_intel_prop(bus); | |
1299 | ||
71bb8a1b VK |
1300 | return 0; |
1301 | } | |
1302 | ||
c91605f4 SN |
1303 | static struct sdw_master_ops sdw_intel_ops = { |
1304 | .read_prop = sdw_master_read_prop, | |
1305 | .xfer_msg = cdns_xfer_msg, | |
1306 | .xfer_msg_defer = cdns_xfer_msg_defer, | |
1307 | .reset_page_addr = cdns_reset_page_addr, | |
07abeff1 | 1308 | .set_bus_conf = cdns_bus_conf, |
30246e2d SN |
1309 | .pre_bank_switch = intel_pre_bank_switch, |
1310 | .post_bank_switch = intel_post_bank_switch, | |
c91605f4 SN |
1311 | }; |
1312 | ||
dfbe642d PLB |
1313 | static int intel_init(struct sdw_intel *sdw) |
1314 | { | |
4a17c441 PLB |
1315 | bool clock_stop; |
1316 | ||
dfbe642d PLB |
1317 | /* Initialize shim and controller */ |
1318 | intel_link_power_up(sdw); | |
4a17c441 PLB |
1319 | |
1320 | clock_stop = sdw_cdns_is_clock_stop(&sdw->cdns); | |
1321 | ||
1322 | intel_shim_init(sdw, clock_stop); | |
1323 | ||
857a7c42 | 1324 | return 0; |
dfbe642d PLB |
1325 | } |
1326 | ||
71bb8a1b VK |
1327 | /* |
1328 | * probe and init | |
1329 | */ | |
b6109dd6 | 1330 | static int intel_master_probe(struct platform_device *pdev) |
71bb8a1b | 1331 | { |
b6109dd6 | 1332 | struct device *dev = &pdev->dev; |
71bb8a1b | 1333 | struct sdw_intel *sdw; |
83e129af | 1334 | struct sdw_cdns *cdns; |
b6109dd6 | 1335 | struct sdw_bus *bus; |
71bb8a1b VK |
1336 | int ret; |
1337 | ||
b6109dd6 | 1338 | sdw = devm_kzalloc(dev, sizeof(*sdw), GFP_KERNEL); |
71bb8a1b VK |
1339 | if (!sdw) |
1340 | return -ENOMEM; | |
1341 | ||
83e129af PLB |
1342 | cdns = &sdw->cdns; |
1343 | bus = &cdns->bus; | |
b6109dd6 | 1344 | |
71bb8a1b | 1345 | sdw->instance = pdev->id; |
b6109dd6 | 1346 | sdw->link_res = dev_get_platdata(dev); |
83e129af PLB |
1347 | cdns->dev = dev; |
1348 | cdns->registers = sdw->link_res->registers; | |
1349 | cdns->instance = sdw->instance; | |
1350 | cdns->msg_count = 0; | |
1351 | ||
b6109dd6 | 1352 | bus->link_id = pdev->id; |
71bb8a1b | 1353 | |
83e129af | 1354 | sdw_cdns_probe(cdns); |
71bb8a1b VK |
1355 | |
1356 | /* Set property read ops */ | |
c91605f4 | 1357 | sdw_intel_ops.read_prop = intel_prop_read; |
b6109dd6 | 1358 | bus->ops = &sdw_intel_ops; |
71bb8a1b | 1359 | |
b6109dd6 | 1360 | /* set driver data, accessed by snd_soc_dai_get_drvdata() */ |
83e129af | 1361 | dev_set_drvdata(dev, cdns); |
71bb8a1b | 1362 | |
9026118f BL |
1363 | /* use generic bandwidth allocation algorithm */ |
1364 | sdw->cdns.bus.compute_params = sdw_compute_params; | |
1365 | ||
b6109dd6 | 1366 | ret = sdw_bus_master_add(bus, dev, dev->fwnode); |
71bb8a1b | 1367 | if (ret) { |
b6109dd6 | 1368 | dev_err(dev, "sdw_bus_master_add fail: %d\n", ret); |
9e3d47fb | 1369 | return ret; |
71bb8a1b VK |
1370 | } |
1371 | ||
6d2c6669 | 1372 | if (bus->prop.hw_disabled) |
b6109dd6 PLB |
1373 | dev_info(dev, |
1374 | "SoundWire master %d is disabled, will be ignored\n", | |
1375 | bus->link_id); | |
0ef2986e PLB |
1376 | /* |
1377 | * Ignore BIOS err_threshold, it's a really bad idea when dealing | |
1378 | * with multiple hardware synchronized links | |
1379 | */ | |
1380 | bus->prop.err_threshold = 0; | |
6d2c6669 | 1381 | |
6d2c6669 | 1382 | return 0; |
6d2c6669 PLB |
1383 | } |
1384 | ||
1385 | int intel_master_startup(struct platform_device *pdev) | |
1386 | { | |
1387 | struct sdw_cdns_stream_config config; | |
1388 | struct device *dev = &pdev->dev; | |
1389 | struct sdw_cdns *cdns = dev_get_drvdata(dev); | |
1390 | struct sdw_intel *sdw = cdns_to_intel(cdns); | |
1391 | struct sdw_bus *bus = &cdns->bus; | |
ebf878ed | 1392 | int link_flags; |
857a7c42 | 1393 | bool multi_link; |
caf68819 | 1394 | u32 clock_stop_quirks; |
6d2c6669 PLB |
1395 | int ret; |
1396 | ||
1397 | if (bus->prop.hw_disabled) { | |
1398 | dev_info(dev, | |
1399 | "SoundWire master %d is disabled, ignoring\n", | |
1400 | sdw->instance); | |
395713d8 PLB |
1401 | return 0; |
1402 | } | |
1403 | ||
857a7c42 PLB |
1404 | link_flags = md_flags >> (bus->link_id * 8); |
1405 | multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK); | |
1406 | if (!multi_link) { | |
1407 | dev_dbg(dev, "Multi-link is disabled\n"); | |
1408 | bus->multi_link = false; | |
1409 | } else { | |
94eed661 PLB |
1410 | /* |
1411 | * hardware-based synchronization is required regardless | |
1412 | * of the number of segments used by a stream: SSP-based | |
1413 | * synchronization is gated by gsync when the multi-master | |
1414 | * mode is set. | |
1415 | */ | |
857a7c42 | 1416 | bus->multi_link = true; |
94eed661 | 1417 | bus->hw_sync_min_links = 1; |
857a7c42 PLB |
1418 | } |
1419 | ||
1420 | /* Initialize shim, controller */ | |
dfbe642d | 1421 | ret = intel_init(sdw); |
71bb8a1b VK |
1422 | if (ret) |
1423 | goto err_init; | |
1424 | ||
37a2d22b VK |
1425 | /* Read the PDI config and initialize cadence PDI */ |
1426 | intel_pdi_init(sdw, &config); | |
83e129af | 1427 | ret = sdw_cdns_pdi_init(cdns, config); |
71bb8a1b VK |
1428 | if (ret) |
1429 | goto err_init; | |
1430 | ||
37a2d22b VK |
1431 | intel_pdi_ch_update(sdw); |
1432 | ||
83e129af | 1433 | ret = sdw_cdns_enable_interrupt(cdns, true); |
71bb8a1b | 1434 | if (ret < 0) { |
b6109dd6 | 1435 | dev_err(dev, "cannot enable interrupts\n"); |
71bb8a1b VK |
1436 | goto err_init; |
1437 | } | |
1438 | ||
857a7c42 PLB |
1439 | /* |
1440 | * follow recommended programming flows to avoid timeouts when | |
1441 | * gsync is enabled | |
1442 | */ | |
1443 | if (multi_link) | |
1444 | intel_shim_sync_arm(sdw); | |
1445 | ||
1446 | ret = sdw_cdns_init(cdns); | |
1447 | if (ret < 0) { | |
1448 | dev_err(dev, "unable to initialize Cadence IP\n"); | |
1449 | goto err_interrupt; | |
1450 | } | |
1451 | ||
83e129af | 1452 | ret = sdw_cdns_exit_reset(cdns); |
49ea07d3 | 1453 | if (ret < 0) { |
b6109dd6 | 1454 | dev_err(dev, "unable to exit bus reset sequence\n"); |
9e3d47fb | 1455 | goto err_interrupt; |
49ea07d3 PLB |
1456 | } |
1457 | ||
857a7c42 PLB |
1458 | if (multi_link) { |
1459 | ret = intel_shim_sync_go(sdw); | |
1460 | if (ret < 0) { | |
1461 | dev_err(dev, "sync go failed: %d\n", ret); | |
1462 | goto err_interrupt; | |
1463 | } | |
1464 | } | |
1465 | ||
c46302ec VK |
1466 | /* Register DAIs */ |
1467 | ret = intel_register_dai(sdw); | |
1468 | if (ret) { | |
b6109dd6 PLB |
1469 | dev_err(dev, "DAI registration failed: %d\n", ret); |
1470 | snd_soc_unregister_component(dev); | |
9e3d47fb | 1471 | goto err_interrupt; |
c46302ec VK |
1472 | } |
1473 | ||
79ee6631 PLB |
1474 | intel_debugfs_init(sdw); |
1475 | ||
ebf878ed | 1476 | /* Enable runtime PM */ |
ebf878ed PLB |
1477 | if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME)) { |
1478 | pm_runtime_set_autosuspend_delay(dev, | |
1479 | INTEL_MASTER_SUSPEND_DELAY_MS); | |
1480 | pm_runtime_use_autosuspend(dev); | |
1481 | pm_runtime_mark_last_busy(dev); | |
1482 | ||
1483 | pm_runtime_set_active(dev); | |
1484 | pm_runtime_enable(dev); | |
1485 | } | |
1486 | ||
caf68819 PLB |
1487 | clock_stop_quirks = sdw->link_res->clock_stop_quirks; |
1488 | if (clock_stop_quirks & SDW_INTEL_CLK_STOP_NOT_ALLOWED) { | |
1489 | /* | |
1490 | * To keep the clock running we need to prevent | |
1491 | * pm_runtime suspend from happening by increasing the | |
1492 | * reference count. | |
1493 | * This quirk is specified by the parent PCI device in | |
1494 | * case of specific latency requirements. It will have | |
1495 | * no effect if pm_runtime is disabled by the user via | |
1496 | * a module parameter for testing purposes. | |
1497 | */ | |
1498 | pm_runtime_get_noresume(dev); | |
1499 | } | |
1500 | ||
a2d9c161 PLB |
1501 | /* |
1502 | * The runtime PM status of Slave devices is "Unsupported" | |
1503 | * until they report as ATTACHED. If they don't, e.g. because | |
1504 | * there are no Slave devices populated or if the power-on is | |
1505 | * delayed or dependent on a power switch, the Master will | |
1506 | * remain active and prevent its parent from suspending. | |
1507 | * | |
1508 | * Conditionally force the pm_runtime core to re-evaluate the | |
1509 | * Master status in the absence of any Slave activity. A quirk | |
1510 | * is provided to e.g. deal with Slaves that may be powered on | |
1511 | * with a delay. A more complete solution would require the | |
1512 | * definition of Master properties. | |
1513 | */ | |
1514 | if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE)) | |
1515 | pm_runtime_idle(dev); | |
1516 | ||
71bb8a1b VK |
1517 | return 0; |
1518 | ||
9e3d47fb | 1519 | err_interrupt: |
83e129af | 1520 | sdw_cdns_enable_interrupt(cdns, false); |
71bb8a1b | 1521 | err_init: |
71bb8a1b VK |
1522 | return ret; |
1523 | } | |
1524 | ||
b6109dd6 | 1525 | static int intel_master_remove(struct platform_device *pdev) |
71bb8a1b | 1526 | { |
b6109dd6 | 1527 | struct device *dev = &pdev->dev; |
83e129af PLB |
1528 | struct sdw_cdns *cdns = dev_get_drvdata(dev); |
1529 | struct sdw_intel *sdw = cdns_to_intel(cdns); | |
1530 | struct sdw_bus *bus = &cdns->bus; | |
b6109dd6 | 1531 | |
caf68819 PLB |
1532 | /* |
1533 | * Since pm_runtime is already disabled, we don't decrease | |
1534 | * the refcount when the clock_stop_quirk is | |
1535 | * SDW_INTEL_CLK_STOP_NOT_ALLOWED | |
1536 | */ | |
b6109dd6 | 1537 | if (!bus->prop.hw_disabled) { |
395713d8 | 1538 | intel_debugfs_exit(sdw); |
83e129af | 1539 | sdw_cdns_enable_interrupt(cdns, false); |
b6109dd6 | 1540 | snd_soc_unregister_component(dev); |
395713d8 | 1541 | } |
b6109dd6 | 1542 | sdw_bus_master_delete(bus); |
71bb8a1b VK |
1543 | |
1544 | return 0; | |
1545 | } | |
1546 | ||
ab2c9132 RW |
1547 | int intel_master_process_wakeen_event(struct platform_device *pdev) |
1548 | { | |
1549 | struct device *dev = &pdev->dev; | |
71bb8a1b | 1550 | struct sdw_intel *sdw; |
ab2c9132 RW |
1551 | struct sdw_bus *bus; |
1552 | void __iomem *shim; | |
1553 | u16 wake_sts; | |
71bb8a1b VK |
1554 | |
1555 | sdw = platform_get_drvdata(pdev); | |
ab2c9132 | 1556 | bus = &sdw->cdns.bus; |
71bb8a1b | 1557 | |
ab2c9132 RW |
1558 | if (bus->prop.hw_disabled) { |
1559 | dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", bus->link_id); | |
1560 | return 0; | |
395713d8 | 1561 | } |
ab2c9132 RW |
1562 | |
1563 | shim = sdw->link_res->shim; | |
1564 | wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS); | |
1565 | ||
1566 | if (!(wake_sts & BIT(sdw->instance))) | |
1567 | return 0; | |
1568 | ||
1569 | /* disable WAKEEN interrupt ASAP to prevent interrupt flood */ | |
1570 | intel_shim_wake(sdw, false); | |
1571 | ||
1572 | /* | |
1573 | * resume the Master, which will generate a bus reset and result in | |
1574 | * Slaves re-attaching and be re-enumerated. The SoundWire physical | |
1575 | * device which generated the wake will trigger an interrupt, which | |
1576 | * will in turn cause the corresponding Linux Slave device to be | |
1577 | * resumed and the Slave codec driver to check the status. | |
1578 | */ | |
1579 | pm_request_resume(dev); | |
71bb8a1b VK |
1580 | |
1581 | return 0; | |
1582 | } | |
1583 | ||
9b3b4b3f PLB |
1584 | /* |
1585 | * PM calls | |
1586 | */ | |
1587 | ||
f046b233 | 1588 | static int __maybe_unused intel_suspend(struct device *dev) |
9b3b4b3f PLB |
1589 | { |
1590 | struct sdw_cdns *cdns = dev_get_drvdata(dev); | |
1591 | struct sdw_intel *sdw = cdns_to_intel(cdns); | |
1592 | struct sdw_bus *bus = &cdns->bus; | |
e4be9fac | 1593 | u32 clock_stop_quirks; |
9b3b4b3f PLB |
1594 | int ret; |
1595 | ||
1596 | if (bus->prop.hw_disabled) { | |
1597 | dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", | |
1598 | bus->link_id); | |
1599 | return 0; | |
1600 | } | |
1601 | ||
b61b8b37 PLB |
1602 | if (pm_runtime_suspended(dev)) { |
1603 | dev_dbg(dev, "%s: pm_runtime status: suspended\n", __func__); | |
1604 | ||
e4be9fac PLB |
1605 | clock_stop_quirks = sdw->link_res->clock_stop_quirks; |
1606 | ||
1607 | if ((clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET || | |
1608 | !clock_stop_quirks) && | |
1609 | !pm_runtime_suspended(dev->parent)) { | |
1610 | ||
1611 | /* | |
1612 | * if we've enabled clock stop, and the parent | |
1613 | * is still active, disable shim wake. The | |
1614 | * SHIM registers are not accessible if the | |
1615 | * parent is already pm_runtime suspended so | |
1616 | * it's too late to change that configuration | |
1617 | */ | |
1618 | ||
1619 | intel_shim_wake(sdw, false); | |
1620 | } | |
1621 | ||
b61b8b37 PLB |
1622 | return 0; |
1623 | } | |
1624 | ||
9b3b4b3f PLB |
1625 | ret = sdw_cdns_enable_interrupt(cdns, false); |
1626 | if (ret < 0) { | |
1627 | dev_err(dev, "cannot disable interrupts on suspend\n"); | |
1628 | return ret; | |
1629 | } | |
1630 | ||
1631 | ret = intel_link_power_down(sdw); | |
1632 | if (ret) { | |
1633 | dev_err(dev, "Link power down failed: %d", ret); | |
1634 | return ret; | |
1635 | } | |
1636 | ||
1637 | intel_shim_wake(sdw, false); | |
1638 | ||
1639 | return 0; | |
1640 | } | |
1641 | ||
17e0da0b | 1642 | static int __maybe_unused intel_suspend_runtime(struct device *dev) |
ebf878ed PLB |
1643 | { |
1644 | struct sdw_cdns *cdns = dev_get_drvdata(dev); | |
1645 | struct sdw_intel *sdw = cdns_to_intel(cdns); | |
1646 | struct sdw_bus *bus = &cdns->bus; | |
a320f41e | 1647 | u32 clock_stop_quirks; |
ebf878ed PLB |
1648 | int ret; |
1649 | ||
1650 | if (bus->prop.hw_disabled) { | |
1651 | dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", | |
1652 | bus->link_id); | |
1653 | return 0; | |
1654 | } | |
1655 | ||
a320f41e | 1656 | clock_stop_quirks = sdw->link_res->clock_stop_quirks; |
ebf878ed | 1657 | |
a320f41e | 1658 | if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) { |
ebf878ed | 1659 | |
a320f41e PLB |
1660 | ret = sdw_cdns_enable_interrupt(cdns, false); |
1661 | if (ret < 0) { | |
1662 | dev_err(dev, "cannot disable interrupts on suspend\n"); | |
1663 | return ret; | |
1664 | } | |
ebf878ed | 1665 | |
a320f41e PLB |
1666 | ret = intel_link_power_down(sdw); |
1667 | if (ret) { | |
1668 | dev_err(dev, "Link power down failed: %d", ret); | |
1669 | return ret; | |
1670 | } | |
1671 | ||
1672 | intel_shim_wake(sdw, false); | |
1673 | ||
61fb830b PLB |
1674 | } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET || |
1675 | !clock_stop_quirks) { | |
6626a616 RW |
1676 | ret = sdw_cdns_clock_stop(cdns, true); |
1677 | if (ret < 0) { | |
1678 | dev_err(dev, "cannot enable clock stop on suspend\n"); | |
1679 | return ret; | |
1680 | } | |
1681 | ||
1682 | ret = sdw_cdns_enable_interrupt(cdns, false); | |
1683 | if (ret < 0) { | |
1684 | dev_err(dev, "cannot disable interrupts on suspend\n"); | |
1685 | return ret; | |
1686 | } | |
1687 | ||
1688 | ret = intel_link_power_down(sdw); | |
1689 | if (ret) { | |
1690 | dev_err(dev, "Link power down failed: %d", ret); | |
1691 | return ret; | |
1692 | } | |
1693 | ||
1694 | intel_shim_wake(sdw, true); | |
a320f41e PLB |
1695 | } else { |
1696 | dev_err(dev, "%s clock_stop_quirks %x unsupported\n", | |
1697 | __func__, clock_stop_quirks); | |
1698 | ret = -EINVAL; | |
1699 | } | |
1700 | ||
1701 | return ret; | |
ebf878ed PLB |
1702 | } |
1703 | ||
f046b233 | 1704 | static int __maybe_unused intel_resume(struct device *dev) |
9b3b4b3f PLB |
1705 | { |
1706 | struct sdw_cdns *cdns = dev_get_drvdata(dev); | |
1707 | struct sdw_intel *sdw = cdns_to_intel(cdns); | |
1708 | struct sdw_bus *bus = &cdns->bus; | |
a2d9c161 | 1709 | int link_flags; |
857a7c42 | 1710 | bool multi_link; |
9b3b4b3f PLB |
1711 | int ret; |
1712 | ||
1713 | if (bus->prop.hw_disabled) { | |
1714 | dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", | |
1715 | bus->link_id); | |
1716 | return 0; | |
1717 | } | |
1718 | ||
857a7c42 PLB |
1719 | link_flags = md_flags >> (bus->link_id * 8); |
1720 | multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK); | |
1721 | ||
b61b8b37 PLB |
1722 | if (pm_runtime_suspended(dev)) { |
1723 | dev_dbg(dev, "%s: pm_runtime status was suspended, forcing active\n", __func__); | |
1724 | ||
1725 | /* follow required sequence from runtime_pm.rst */ | |
1726 | pm_runtime_disable(dev); | |
1727 | pm_runtime_set_active(dev); | |
1728 | pm_runtime_mark_last_busy(dev); | |
1729 | pm_runtime_enable(dev); | |
a2d9c161 PLB |
1730 | |
1731 | link_flags = md_flags >> (bus->link_id * 8); | |
857a7c42 | 1732 | |
a2d9c161 PLB |
1733 | if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE)) |
1734 | pm_runtime_idle(dev); | |
b61b8b37 PLB |
1735 | } |
1736 | ||
9b3b4b3f PLB |
1737 | ret = intel_init(sdw); |
1738 | if (ret) { | |
1739 | dev_err(dev, "%s failed: %d", __func__, ret); | |
1740 | return ret; | |
1741 | } | |
1742 | ||
99b6a30f PLB |
1743 | /* |
1744 | * make sure all Slaves are tagged as UNATTACHED and provide | |
1745 | * reason for reinitialization | |
1746 | */ | |
1747 | sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET); | |
1748 | ||
9b3b4b3f PLB |
1749 | ret = sdw_cdns_enable_interrupt(cdns, true); |
1750 | if (ret < 0) { | |
1751 | dev_err(dev, "cannot enable interrupts during resume\n"); | |
1752 | return ret; | |
1753 | } | |
1754 | ||
857a7c42 PLB |
1755 | /* |
1756 | * follow recommended programming flows to avoid timeouts when | |
1757 | * gsync is enabled | |
1758 | */ | |
1759 | if (multi_link) | |
1760 | intel_shim_sync_arm(sdw); | |
1761 | ||
1762 | ret = sdw_cdns_init(&sdw->cdns); | |
1763 | if (ret < 0) { | |
1764 | dev_err(dev, "unable to initialize Cadence IP during resume\n"); | |
1765 | return ret; | |
1766 | } | |
1767 | ||
9b3b4b3f PLB |
1768 | ret = sdw_cdns_exit_reset(cdns); |
1769 | if (ret < 0) { | |
1770 | dev_err(dev, "unable to exit bus reset sequence during resume\n"); | |
1771 | return ret; | |
1772 | } | |
1773 | ||
857a7c42 PLB |
1774 | if (multi_link) { |
1775 | ret = intel_shim_sync_go(sdw); | |
1776 | if (ret < 0) { | |
1777 | dev_err(dev, "sync go failed during resume\n"); | |
1778 | return ret; | |
1779 | } | |
1780 | } | |
1781 | ||
cb1e6d59 PLB |
1782 | /* |
1783 | * after system resume, the pm_runtime suspend() may kick in | |
1784 | * during the enumeration, before any children device force the | |
1785 | * master device to remain active. Using pm_runtime_get() | |
1786 | * routines is not really possible, since it'd prevent the | |
1787 | * master from suspending. | |
1788 | * A reasonable compromise is to update the pm_runtime | |
1789 | * counters and delay the pm_runtime suspend by several | |
1790 | * seconds, by when all enumeration should be complete. | |
1791 | */ | |
1792 | pm_runtime_mark_last_busy(dev); | |
1793 | ||
9b3b4b3f PLB |
1794 | return ret; |
1795 | } | |
1796 | ||
17e0da0b | 1797 | static int __maybe_unused intel_resume_runtime(struct device *dev) |
ebf878ed PLB |
1798 | { |
1799 | struct sdw_cdns *cdns = dev_get_drvdata(dev); | |
1800 | struct sdw_intel *sdw = cdns_to_intel(cdns); | |
1801 | struct sdw_bus *bus = &cdns->bus; | |
a320f41e | 1802 | u32 clock_stop_quirks; |
08abad9f | 1803 | bool clock_stop0; |
857a7c42 PLB |
1804 | int link_flags; |
1805 | bool multi_link; | |
08abad9f | 1806 | int status; |
ebf878ed PLB |
1807 | int ret; |
1808 | ||
1809 | if (bus->prop.hw_disabled) { | |
1810 | dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", | |
1811 | bus->link_id); | |
1812 | return 0; | |
1813 | } | |
1814 | ||
857a7c42 PLB |
1815 | link_flags = md_flags >> (bus->link_id * 8); |
1816 | multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK); | |
1817 | ||
a320f41e | 1818 | clock_stop_quirks = sdw->link_res->clock_stop_quirks; |
ebf878ed | 1819 | |
a320f41e PLB |
1820 | if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) { |
1821 | ret = intel_init(sdw); | |
1822 | if (ret) { | |
1823 | dev_err(dev, "%s failed: %d", __func__, ret); | |
1824 | return ret; | |
1825 | } | |
99b6a30f | 1826 | |
a320f41e PLB |
1827 | /* |
1828 | * make sure all Slaves are tagged as UNATTACHED and provide | |
1829 | * reason for reinitialization | |
1830 | */ | |
1831 | sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET); | |
ebf878ed | 1832 | |
a320f41e PLB |
1833 | ret = sdw_cdns_enable_interrupt(cdns, true); |
1834 | if (ret < 0) { | |
1835 | dev_err(dev, "cannot enable interrupts during resume\n"); | |
1836 | return ret; | |
1837 | } | |
1838 | ||
857a7c42 PLB |
1839 | /* |
1840 | * follow recommended programming flows to avoid | |
1841 | * timeouts when gsync is enabled | |
1842 | */ | |
1843 | if (multi_link) | |
1844 | intel_shim_sync_arm(sdw); | |
1845 | ||
1846 | ret = sdw_cdns_init(&sdw->cdns); | |
1847 | if (ret < 0) { | |
1848 | dev_err(dev, "unable to initialize Cadence IP during resume\n"); | |
1849 | return ret; | |
1850 | } | |
1851 | ||
a320f41e PLB |
1852 | ret = sdw_cdns_exit_reset(cdns); |
1853 | if (ret < 0) { | |
1854 | dev_err(dev, "unable to exit bus reset sequence during resume\n"); | |
1855 | return ret; | |
1856 | } | |
857a7c42 PLB |
1857 | |
1858 | if (multi_link) { | |
1859 | ret = intel_shim_sync_go(sdw); | |
1860 | if (ret < 0) { | |
1861 | dev_err(dev, "sync go failed during resume\n"); | |
1862 | return ret; | |
1863 | } | |
1864 | } | |
6626a616 RW |
1865 | } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) { |
1866 | ret = intel_init(sdw); | |
1867 | if (ret) { | |
1868 | dev_err(dev, "%s failed: %d", __func__, ret); | |
1869 | return ret; | |
1870 | } | |
1871 | ||
08abad9f RW |
1872 | /* |
1873 | * An exception condition occurs for the CLK_STOP_BUS_RESET | |
1874 | * case if one or more masters remain active. In this condition, | |
1875 | * all the masters are powered on for they are in the same power | |
1876 | * domain. Master can preserve its context for clock stop0, so | |
1877 | * there is no need to clear slave status and reset bus. | |
1878 | */ | |
1879 | clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns); | |
1880 | ||
08abad9f | 1881 | if (!clock_stop0) { |
857a7c42 | 1882 | |
857a7c42 PLB |
1883 | /* |
1884 | * make sure all Slaves are tagged as UNATTACHED and | |
1885 | * provide reason for reinitialization | |
1886 | */ | |
1887 | ||
08abad9f RW |
1888 | status = SDW_UNATTACH_REQUEST_MASTER_RESET; |
1889 | sdw_clear_slave_status(bus, status); | |
08abad9f | 1890 | |
d78071b4 PLB |
1891 | ret = sdw_cdns_enable_interrupt(cdns, true); |
1892 | if (ret < 0) { | |
1893 | dev_err(dev, "cannot enable interrupts during resume\n"); | |
1894 | return ret; | |
1895 | } | |
1896 | ||
1897 | /* | |
1898 | * follow recommended programming flows to avoid | |
1899 | * timeouts when gsync is enabled | |
1900 | */ | |
1901 | if (multi_link) | |
1902 | intel_shim_sync_arm(sdw); | |
6626a616 | 1903 | |
d78071b4 PLB |
1904 | /* |
1905 | * Re-initialize the IP since it was powered-off | |
1906 | */ | |
1907 | sdw_cdns_init(&sdw->cdns); | |
1908 | ||
1909 | } else { | |
1910 | ret = sdw_cdns_enable_interrupt(cdns, true); | |
1911 | if (ret < 0) { | |
1912 | dev_err(dev, "cannot enable interrupts during resume\n"); | |
1913 | return ret; | |
1914 | } | |
6626a616 RW |
1915 | } |
1916 | ||
08abad9f | 1917 | ret = sdw_cdns_clock_restart(cdns, !clock_stop0); |
6626a616 RW |
1918 | if (ret < 0) { |
1919 | dev_err(dev, "unable to restart clock during resume\n"); | |
1920 | return ret; | |
1921 | } | |
d78071b4 PLB |
1922 | |
1923 | if (!clock_stop0) { | |
1924 | ret = sdw_cdns_exit_reset(cdns); | |
1925 | if (ret < 0) { | |
1926 | dev_err(dev, "unable to exit bus reset sequence during resume\n"); | |
1927 | return ret; | |
1928 | } | |
1929 | ||
1930 | if (multi_link) { | |
1931 | ret = intel_shim_sync_go(sdw); | |
1932 | if (ret < 0) { | |
1933 | dev_err(sdw->cdns.dev, "sync go failed during resume\n"); | |
1934 | return ret; | |
1935 | } | |
1936 | } | |
1937 | } | |
61fb830b | 1938 | } else if (!clock_stop_quirks) { |
f748f34e PLB |
1939 | |
1940 | clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns); | |
1941 | if (!clock_stop0) | |
1942 | dev_err(dev, "%s invalid configuration, clock was not stopped", __func__); | |
1943 | ||
61fb830b PLB |
1944 | ret = intel_init(sdw); |
1945 | if (ret) { | |
1946 | dev_err(dev, "%s failed: %d", __func__, ret); | |
1947 | return ret; | |
1948 | } | |
1949 | ||
1950 | ret = sdw_cdns_enable_interrupt(cdns, true); | |
1951 | if (ret < 0) { | |
1952 | dev_err(dev, "cannot enable interrupts during resume\n"); | |
1953 | return ret; | |
1954 | } | |
1955 | ||
1956 | ret = sdw_cdns_clock_restart(cdns, false); | |
1957 | if (ret < 0) { | |
1958 | dev_err(dev, "unable to resume master during resume\n"); | |
1959 | return ret; | |
1960 | } | |
a320f41e PLB |
1961 | } else { |
1962 | dev_err(dev, "%s clock_stop_quirks %x unsupported\n", | |
1963 | __func__, clock_stop_quirks); | |
1964 | ret = -EINVAL; | |
ebf878ed PLB |
1965 | } |
1966 | ||
1967 | return ret; | |
1968 | } | |
1969 | ||
9b3b4b3f PLB |
1970 | static const struct dev_pm_ops intel_pm = { |
1971 | SET_SYSTEM_SLEEP_PM_OPS(intel_suspend, intel_resume) | |
ebf878ed | 1972 | SET_RUNTIME_PM_OPS(intel_suspend_runtime, intel_resume_runtime, NULL) |
9b3b4b3f PLB |
1973 | }; |
1974 | ||
71bb8a1b | 1975 | static struct platform_driver sdw_intel_drv = { |
b6109dd6 PLB |
1976 | .probe = intel_master_probe, |
1977 | .remove = intel_master_remove, | |
71bb8a1b | 1978 | .driver = { |
6d2c6669 | 1979 | .name = "intel-sdw", |
9b3b4b3f PLB |
1980 | .pm = &intel_pm, |
1981 | } | |
71bb8a1b VK |
1982 | }; |
1983 | ||
1984 | module_platform_driver(sdw_intel_drv); | |
1985 | ||
1986 | MODULE_LICENSE("Dual BSD/GPL"); | |
6d2c6669 | 1987 | MODULE_ALIAS("platform:intel-sdw"); |
71bb8a1b | 1988 | MODULE_DESCRIPTION("Intel Soundwire Master Driver"); |