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71bb8a1b VK |
1 | // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) |
2 | // Copyright(c) 2015-17 Intel Corporation. | |
3 | ||
4 | /* | |
5 | * Soundwire Intel Master Driver | |
6 | */ | |
7 | ||
8 | #include <linux/acpi.h> | |
79ee6631 | 9 | #include <linux/debugfs.h> |
71bb8a1b | 10 | #include <linux/delay.h> |
4abbd783 | 11 | #include <linux/module.h> |
71bb8a1b VK |
12 | #include <linux/interrupt.h> |
13 | #include <linux/platform_device.h> | |
37a2d22b VK |
14 | #include <sound/pcm_params.h> |
15 | #include <sound/soc.h> | |
71bb8a1b VK |
16 | #include <linux/soundwire/sdw_registers.h> |
17 | #include <linux/soundwire/sdw.h> | |
18 | #include <linux/soundwire/sdw_intel.h> | |
19 | #include "cadence_master.h" | |
79ee6631 | 20 | #include "bus.h" |
71bb8a1b VK |
21 | #include "intel.h" |
22 | ||
23 | /* Intel SHIM Registers Definition */ | |
24 | #define SDW_SHIM_LCAP 0x0 | |
25 | #define SDW_SHIM_LCTL 0x4 | |
26 | #define SDW_SHIM_IPPTR 0x8 | |
27 | #define SDW_SHIM_SYNC 0xC | |
28 | ||
7cc6e315 PLB |
29 | #define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x)) |
30 | #define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x)) | |
31 | #define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x)) | |
32 | #define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x)) | |
33 | #define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x)) | |
34 | #define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x)) | |
35 | ||
36 | #define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y))) | |
37 | #define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y))) | |
38 | #define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x)) | |
39 | #define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x)) | |
40 | #define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x)) | |
71bb8a1b VK |
41 | |
42 | #define SDW_SHIM_WAKEEN 0x190 | |
43 | #define SDW_SHIM_WAKESTS 0x192 | |
44 | ||
45 | #define SDW_SHIM_LCTL_SPA BIT(0) | |
46 | #define SDW_SHIM_LCTL_CPA BIT(8) | |
47 | ||
48 | #define SDW_SHIM_SYNC_SYNCPRD_VAL 0x176F | |
49 | #define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0) | |
50 | #define SDW_SHIM_SYNC_SYNCCPU BIT(15) | |
51 | #define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16) | |
52 | #define SDW_SHIM_SYNC_CMDSYNC BIT(16) | |
53 | #define SDW_SHIM_SYNC_SYNCGO BIT(24) | |
54 | ||
55 | #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0) | |
56 | #define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4) | |
57 | #define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8) | |
58 | ||
59 | #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0) | |
60 | #define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4) | |
61 | #define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8) | |
62 | #define SDW_SHIM_PCMSYCM_DIR BIT(15) | |
63 | ||
64 | #define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0) | |
65 | #define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4) | |
66 | #define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8) | |
67 | #define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13) | |
68 | ||
69 | #define SDW_SHIM_IOCTL_MIF BIT(0) | |
70 | #define SDW_SHIM_IOCTL_CO BIT(1) | |
71 | #define SDW_SHIM_IOCTL_COE BIT(2) | |
72 | #define SDW_SHIM_IOCTL_DO BIT(3) | |
73 | #define SDW_SHIM_IOCTL_DOE BIT(4) | |
74 | #define SDW_SHIM_IOCTL_BKE BIT(5) | |
75 | #define SDW_SHIM_IOCTL_WPDD BIT(6) | |
76 | #define SDW_SHIM_IOCTL_CIBD BIT(8) | |
77 | #define SDW_SHIM_IOCTL_DIBD BIT(9) | |
78 | ||
79 | #define SDW_SHIM_CTMCTL_DACTQE BIT(0) | |
80 | #define SDW_SHIM_CTMCTL_DODS BIT(1) | |
81 | #define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3) | |
82 | ||
83 | #define SDW_SHIM_WAKEEN_ENABLE BIT(0) | |
84 | #define SDW_SHIM_WAKESTS_STATUS BIT(0) | |
85 | ||
86 | /* Intel ALH Register definitions */ | |
7cc6e315 | 87 | #define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x))) |
79ee6631 | 88 | #define SDW_ALH_NUM_STREAMS 64 |
71bb8a1b VK |
89 | |
90 | #define SDW_ALH_STRMZCFG_DMAT_VAL 0x3 | |
91 | #define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0) | |
92 | #define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16) | |
93 | ||
395713d8 PLB |
94 | #define SDW_INTEL_QUIRK_MASK_BUS_DISABLE BIT(1) |
95 | ||
c46302ec VK |
96 | enum intel_pdi_type { |
97 | INTEL_PDI_IN = 0, | |
98 | INTEL_PDI_OUT = 1, | |
99 | INTEL_PDI_BD = 2, | |
100 | }; | |
101 | ||
71bb8a1b VK |
102 | struct sdw_intel { |
103 | struct sdw_cdns cdns; | |
104 | int instance; | |
105 | struct sdw_intel_link_res *res; | |
79ee6631 PLB |
106 | #ifdef CONFIG_DEBUG_FS |
107 | struct dentry *debugfs; | |
108 | #endif | |
71bb8a1b VK |
109 | }; |
110 | ||
111 | #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns) | |
112 | ||
113 | /* | |
114 | * Read, write helpers for HW registers | |
115 | */ | |
116 | static inline int intel_readl(void __iomem *base, int offset) | |
117 | { | |
118 | return readl(base + offset); | |
119 | } | |
120 | ||
121 | static inline void intel_writel(void __iomem *base, int offset, int value) | |
122 | { | |
123 | writel(value, base + offset); | |
124 | } | |
125 | ||
126 | static inline u16 intel_readw(void __iomem *base, int offset) | |
127 | { | |
128 | return readw(base + offset); | |
129 | } | |
130 | ||
131 | static inline void intel_writew(void __iomem *base, int offset, u16 value) | |
132 | { | |
133 | writew(value, base + offset); | |
134 | } | |
135 | ||
136 | static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask) | |
137 | { | |
138 | int timeout = 10; | |
139 | u32 reg_read; | |
140 | ||
141 | writel(value, base + offset); | |
142 | do { | |
143 | reg_read = readl(base + offset); | |
144 | if (!(reg_read & mask)) | |
145 | return 0; | |
146 | ||
147 | timeout--; | |
148 | udelay(50); | |
149 | } while (timeout != 0); | |
150 | ||
151 | return -EAGAIN; | |
152 | } | |
153 | ||
154 | static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask) | |
155 | { | |
156 | int timeout = 10; | |
157 | u32 reg_read; | |
158 | ||
159 | writel(value, base + offset); | |
160 | do { | |
161 | reg_read = readl(base + offset); | |
162 | if (reg_read & mask) | |
163 | return 0; | |
164 | ||
165 | timeout--; | |
166 | udelay(50); | |
167 | } while (timeout != 0); | |
168 | ||
169 | return -EAGAIN; | |
170 | } | |
171 | ||
79ee6631 PLB |
172 | /* |
173 | * debugfs | |
174 | */ | |
175 | #ifdef CONFIG_DEBUG_FS | |
176 | ||
177 | #define RD_BUF (2 * PAGE_SIZE) | |
178 | ||
179 | static ssize_t intel_sprintf(void __iomem *mem, bool l, | |
180 | char *buf, size_t pos, unsigned int reg) | |
181 | { | |
182 | int value; | |
183 | ||
184 | if (l) | |
185 | value = intel_readl(mem, reg); | |
186 | else | |
187 | value = intel_readw(mem, reg); | |
188 | ||
189 | return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value); | |
190 | } | |
191 | ||
192 | static int intel_reg_show(struct seq_file *s_file, void *data) | |
193 | { | |
194 | struct sdw_intel *sdw = s_file->private; | |
195 | void __iomem *s = sdw->res->shim; | |
196 | void __iomem *a = sdw->res->alh; | |
197 | char *buf; | |
198 | ssize_t ret; | |
199 | int i, j; | |
200 | unsigned int links, reg; | |
201 | ||
202 | buf = kzalloc(RD_BUF, GFP_KERNEL); | |
203 | if (!buf) | |
204 | return -ENOMEM; | |
205 | ||
206 | links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0); | |
207 | ||
208 | ret = scnprintf(buf, RD_BUF, "Register Value\n"); | |
209 | ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n"); | |
210 | ||
211 | for (i = 0; i < links; i++) { | |
212 | reg = SDW_SHIM_LCAP + i * 4; | |
213 | ret += intel_sprintf(s, true, buf, ret, reg); | |
214 | } | |
215 | ||
216 | for (i = 0; i < links; i++) { | |
217 | ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i); | |
218 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i)); | |
219 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i)); | |
220 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i)); | |
221 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i)); | |
222 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i)); | |
223 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i)); | |
224 | ||
225 | ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n"); | |
226 | ||
227 | /* | |
228 | * the value 10 is the number of PDIs. We will need a | |
229 | * cleanup to remove hard-coded Intel configurations | |
230 | * from cadence_master.c | |
231 | */ | |
232 | for (j = 0; j < 10; j++) { | |
233 | ret += intel_sprintf(s, false, buf, ret, | |
234 | SDW_SHIM_PCMSYCHM(i, j)); | |
235 | ret += intel_sprintf(s, false, buf, ret, | |
236 | SDW_SHIM_PCMSYCHC(i, j)); | |
237 | } | |
238 | ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n"); | |
239 | ||
240 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i)); | |
241 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i)); | |
242 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i)); | |
243 | } | |
244 | ||
245 | ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n"); | |
246 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN); | |
247 | ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS); | |
248 | ||
249 | ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n"); | |
250 | for (i = 0; i < SDW_ALH_NUM_STREAMS; i++) | |
251 | ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i)); | |
252 | ||
253 | seq_printf(s_file, "%s", buf); | |
254 | kfree(buf); | |
255 | ||
256 | return 0; | |
257 | } | |
258 | DEFINE_SHOW_ATTRIBUTE(intel_reg); | |
259 | ||
260 | static void intel_debugfs_init(struct sdw_intel *sdw) | |
261 | { | |
262 | struct dentry *root = sdw->cdns.bus.debugfs; | |
263 | ||
264 | if (!root) | |
265 | return; | |
266 | ||
267 | sdw->debugfs = debugfs_create_dir("intel-sdw", root); | |
268 | ||
269 | debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw, | |
270 | &intel_reg_fops); | |
271 | ||
272 | sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs); | |
273 | } | |
274 | ||
275 | static void intel_debugfs_exit(struct sdw_intel *sdw) | |
276 | { | |
277 | debugfs_remove_recursive(sdw->debugfs); | |
278 | } | |
279 | #else | |
280 | static void intel_debugfs_init(struct sdw_intel *sdw) {} | |
281 | static void intel_debugfs_exit(struct sdw_intel *sdw) {} | |
282 | #endif /* CONFIG_DEBUG_FS */ | |
283 | ||
71bb8a1b VK |
284 | /* |
285 | * shim ops | |
286 | */ | |
287 | ||
288 | static int intel_link_power_up(struct sdw_intel *sdw) | |
289 | { | |
290 | unsigned int link_id = sdw->instance; | |
291 | void __iomem *shim = sdw->res->shim; | |
292 | int spa_mask, cpa_mask; | |
293 | int link_control, ret; | |
294 | ||
295 | /* Link power up sequence */ | |
296 | link_control = intel_readl(shim, SDW_SHIM_LCTL); | |
297 | spa_mask = (SDW_SHIM_LCTL_SPA << link_id); | |
298 | cpa_mask = (SDW_SHIM_LCTL_CPA << link_id); | |
299 | link_control |= spa_mask; | |
300 | ||
301 | ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask); | |
302 | if (ret < 0) | |
303 | return ret; | |
304 | ||
305 | sdw->cdns.link_up = true; | |
306 | return 0; | |
307 | } | |
308 | ||
309 | static int intel_shim_init(struct sdw_intel *sdw) | |
310 | { | |
311 | void __iomem *shim = sdw->res->shim; | |
312 | unsigned int link_id = sdw->instance; | |
313 | int sync_reg, ret; | |
314 | u16 ioctl = 0, act = 0; | |
315 | ||
316 | /* Initialize Shim */ | |
317 | ioctl |= SDW_SHIM_IOCTL_BKE; | |
318 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); | |
319 | ||
320 | ioctl |= SDW_SHIM_IOCTL_WPDD; | |
321 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); | |
322 | ||
323 | ioctl |= SDW_SHIM_IOCTL_DO; | |
324 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); | |
325 | ||
326 | ioctl |= SDW_SHIM_IOCTL_DOE; | |
327 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); | |
328 | ||
329 | /* Switch to MIP from Glue logic */ | |
330 | ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id)); | |
331 | ||
332 | ioctl &= ~(SDW_SHIM_IOCTL_DOE); | |
333 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); | |
334 | ||
335 | ioctl &= ~(SDW_SHIM_IOCTL_DO); | |
336 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); | |
337 | ||
338 | ioctl |= (SDW_SHIM_IOCTL_MIF); | |
339 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); | |
340 | ||
341 | ioctl &= ~(SDW_SHIM_IOCTL_BKE); | |
342 | ioctl &= ~(SDW_SHIM_IOCTL_COE); | |
343 | ||
344 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); | |
345 | ||
346 | act |= 0x1 << SDW_REG_SHIFT(SDW_SHIM_CTMCTL_DOAIS); | |
347 | act |= SDW_SHIM_CTMCTL_DACTQE; | |
348 | act |= SDW_SHIM_CTMCTL_DODS; | |
349 | intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act); | |
350 | ||
351 | /* Now set SyncPRD period */ | |
352 | sync_reg = intel_readl(shim, SDW_SHIM_SYNC); | |
353 | sync_reg |= (SDW_SHIM_SYNC_SYNCPRD_VAL << | |
354 | SDW_REG_SHIFT(SDW_SHIM_SYNC_SYNCPRD)); | |
355 | ||
356 | /* Set SyncCPU bit */ | |
357 | sync_reg |= SDW_SHIM_SYNC_SYNCCPU; | |
358 | ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg, | |
d542bc9e | 359 | SDW_SHIM_SYNC_SYNCCPU); |
71bb8a1b | 360 | if (ret < 0) |
17ed5bef | 361 | dev_err(sdw->cdns.dev, "Failed to set sync period: %d\n", ret); |
71bb8a1b VK |
362 | |
363 | return ret; | |
364 | } | |
365 | ||
37a2d22b VK |
366 | /* |
367 | * PDI routines | |
368 | */ | |
369 | static void intel_pdi_init(struct sdw_intel *sdw, | |
d542bc9e | 370 | struct sdw_cdns_stream_config *config) |
37a2d22b VK |
371 | { |
372 | void __iomem *shim = sdw->res->shim; | |
373 | unsigned int link_id = sdw->instance; | |
374 | int pcm_cap, pdm_cap; | |
375 | ||
376 | /* PCM Stream Capability */ | |
377 | pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id)); | |
378 | ||
379 | config->pcm_bd = (pcm_cap & SDW_SHIM_PCMSCAP_BSS) >> | |
380 | SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_BSS); | |
381 | config->pcm_in = (pcm_cap & SDW_SHIM_PCMSCAP_ISS) >> | |
382 | SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_ISS); | |
383 | config->pcm_out = (pcm_cap & SDW_SHIM_PCMSCAP_OSS) >> | |
384 | SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_OSS); | |
385 | ||
121f4361 PLB |
386 | dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n", |
387 | config->pcm_bd, config->pcm_in, config->pcm_out); | |
388 | ||
37a2d22b VK |
389 | /* PDM Stream Capability */ |
390 | pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id)); | |
391 | ||
392 | config->pdm_bd = (pdm_cap & SDW_SHIM_PDMSCAP_BSS) >> | |
393 | SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_BSS); | |
394 | config->pdm_in = (pdm_cap & SDW_SHIM_PDMSCAP_ISS) >> | |
395 | SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_ISS); | |
396 | config->pdm_out = (pdm_cap & SDW_SHIM_PDMSCAP_OSS) >> | |
397 | SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_OSS); | |
121f4361 PLB |
398 | |
399 | dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n", | |
400 | config->pdm_bd, config->pdm_in, config->pdm_out); | |
37a2d22b VK |
401 | } |
402 | ||
403 | static int | |
404 | intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm) | |
405 | { | |
406 | void __iomem *shim = sdw->res->shim; | |
407 | unsigned int link_id = sdw->instance; | |
408 | int count; | |
409 | ||
410 | if (pcm) { | |
411 | count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num)); | |
18046335 PLB |
412 | |
413 | /* | |
414 | * WORKAROUND: on all existing Intel controllers, pdi | |
415 | * number 2 reports channel count as 1 even though it | |
416 | * supports 8 channels. Performing hardcoding for pdi | |
417 | * number 2. | |
418 | */ | |
419 | if (pdi_num == 2) | |
420 | count = 7; | |
421 | ||
37a2d22b VK |
422 | } else { |
423 | count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id)); | |
424 | count = ((count & SDW_SHIM_PDMSCAP_CPSS) >> | |
425 | SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_CPSS)); | |
426 | } | |
427 | ||
428 | /* zero based values for channel count in register */ | |
429 | count++; | |
430 | ||
431 | return count; | |
432 | } | |
433 | ||
434 | static int intel_pdi_get_ch_update(struct sdw_intel *sdw, | |
d542bc9e PLB |
435 | struct sdw_cdns_pdi *pdi, |
436 | unsigned int num_pdi, | |
437 | unsigned int *num_ch, bool pcm) | |
37a2d22b VK |
438 | { |
439 | int i, ch_count = 0; | |
440 | ||
441 | for (i = 0; i < num_pdi; i++) { | |
442 | pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm); | |
443 | ch_count += pdi->ch_count; | |
444 | pdi++; | |
445 | } | |
446 | ||
447 | *num_ch = ch_count; | |
448 | return 0; | |
449 | } | |
450 | ||
451 | static int intel_pdi_stream_ch_update(struct sdw_intel *sdw, | |
d542bc9e | 452 | struct sdw_cdns_streams *stream, bool pcm) |
37a2d22b VK |
453 | { |
454 | intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd, | |
d542bc9e | 455 | &stream->num_ch_bd, pcm); |
37a2d22b VK |
456 | |
457 | intel_pdi_get_ch_update(sdw, stream->in, stream->num_in, | |
d542bc9e | 458 | &stream->num_ch_in, pcm); |
37a2d22b VK |
459 | |
460 | intel_pdi_get_ch_update(sdw, stream->out, stream->num_out, | |
d542bc9e | 461 | &stream->num_ch_out, pcm); |
37a2d22b VK |
462 | |
463 | return 0; | |
464 | } | |
465 | ||
466 | static int intel_pdi_ch_update(struct sdw_intel *sdw) | |
467 | { | |
468 | /* First update PCM streams followed by PDM streams */ | |
469 | intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true); | |
470 | intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false); | |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
475 | static void | |
476 | intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi) | |
477 | { | |
478 | void __iomem *shim = sdw->res->shim; | |
479 | unsigned int link_id = sdw->instance; | |
480 | int pdi_conf = 0; | |
481 | ||
482 | pdi->intel_alh_id = (link_id * 16) + pdi->num + 5; | |
483 | ||
484 | /* | |
485 | * Program stream parameters to stream SHIM register | |
486 | * This is applicable for PCM stream only. | |
487 | */ | |
488 | if (pdi->type != SDW_STREAM_PCM) | |
489 | return; | |
490 | ||
491 | if (pdi->dir == SDW_DATA_DIR_RX) | |
492 | pdi_conf |= SDW_SHIM_PCMSYCM_DIR; | |
493 | else | |
494 | pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR); | |
495 | ||
496 | pdi_conf |= (pdi->intel_alh_id << | |
497 | SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_STREAM)); | |
498 | pdi_conf |= (pdi->l_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_LCHN)); | |
499 | pdi_conf |= (pdi->h_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_HCHN)); | |
500 | ||
501 | intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf); | |
502 | } | |
503 | ||
504 | static void | |
505 | intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi) | |
506 | { | |
507 | void __iomem *alh = sdw->res->alh; | |
508 | unsigned int link_id = sdw->instance; | |
509 | unsigned int conf; | |
510 | ||
511 | pdi->intel_alh_id = (link_id * 16) + pdi->num + 5; | |
512 | ||
513 | /* Program Stream config ALH register */ | |
514 | conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id)); | |
515 | ||
516 | conf |= (SDW_ALH_STRMZCFG_DMAT_VAL << | |
517 | SDW_REG_SHIFT(SDW_ALH_STRMZCFG_DMAT)); | |
518 | ||
519 | conf |= ((pdi->ch_count - 1) << | |
520 | SDW_REG_SHIFT(SDW_ALH_STRMZCFG_CHN)); | |
521 | ||
522 | intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf); | |
523 | } | |
524 | ||
c46302ec | 525 | static int intel_config_stream(struct sdw_intel *sdw, |
d542bc9e PLB |
526 | struct snd_pcm_substream *substream, |
527 | struct snd_soc_dai *dai, | |
528 | struct snd_pcm_hw_params *hw_params, int link_id) | |
c46302ec | 529 | { |
05c8afe4 PLB |
530 | struct sdw_intel_link_res *res = sdw->res; |
531 | ||
532 | if (res->ops && res->ops->config_stream && res->arg) | |
533 | return res->ops->config_stream(res->arg, | |
c46302ec VK |
534 | substream, dai, hw_params, link_id); |
535 | ||
536 | return -EIO; | |
537 | } | |
538 | ||
30246e2d SN |
539 | /* |
540 | * bank switch routines | |
541 | */ | |
542 | ||
543 | static int intel_pre_bank_switch(struct sdw_bus *bus) | |
544 | { | |
545 | struct sdw_cdns *cdns = bus_to_cdns(bus); | |
546 | struct sdw_intel *sdw = cdns_to_intel(cdns); | |
547 | void __iomem *shim = sdw->res->shim; | |
548 | int sync_reg; | |
549 | ||
550 | /* Write to register only for multi-link */ | |
551 | if (!bus->multi_link) | |
552 | return 0; | |
553 | ||
554 | /* Read SYNC register */ | |
555 | sync_reg = intel_readl(shim, SDW_SHIM_SYNC); | |
556 | sync_reg |= SDW_SHIM_SYNC_CMDSYNC << sdw->instance; | |
557 | intel_writel(shim, SDW_SHIM_SYNC, sync_reg); | |
558 | ||
559 | return 0; | |
560 | } | |
561 | ||
562 | static int intel_post_bank_switch(struct sdw_bus *bus) | |
563 | { | |
564 | struct sdw_cdns *cdns = bus_to_cdns(bus); | |
565 | struct sdw_intel *sdw = cdns_to_intel(cdns); | |
566 | void __iomem *shim = sdw->res->shim; | |
567 | int sync_reg, ret; | |
568 | ||
569 | /* Write to register only for multi-link */ | |
570 | if (!bus->multi_link) | |
571 | return 0; | |
572 | ||
573 | /* Read SYNC register */ | |
574 | sync_reg = intel_readl(shim, SDW_SHIM_SYNC); | |
575 | ||
576 | /* | |
577 | * post_bank_switch() ops is called from the bus in loop for | |
578 | * all the Masters in the steam with the expectation that | |
579 | * we trigger the bankswitch for the only first Master in the list | |
580 | * and do nothing for the other Masters | |
581 | * | |
582 | * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master. | |
583 | */ | |
584 | if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK)) | |
585 | return 0; | |
586 | ||
587 | /* | |
588 | * Set SyncGO bit to synchronously trigger a bank switch for | |
589 | * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all | |
590 | * the Masters. | |
591 | */ | |
592 | sync_reg |= SDW_SHIM_SYNC_SYNCGO; | |
593 | ||
594 | ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg, | |
d542bc9e | 595 | SDW_SHIM_SYNC_SYNCGO); |
30246e2d | 596 | if (ret < 0) |
17ed5bef | 597 | dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret); |
30246e2d SN |
598 | |
599 | return ret; | |
600 | } | |
601 | ||
c46302ec VK |
602 | /* |
603 | * DAI routines | |
604 | */ | |
605 | ||
606 | static struct sdw_cdns_port *intel_alloc_port(struct sdw_intel *sdw, | |
d542bc9e | 607 | u32 ch, u32 dir, bool pcm) |
c46302ec VK |
608 | { |
609 | struct sdw_cdns *cdns = &sdw->cdns; | |
610 | struct sdw_cdns_port *port = NULL; | |
611 | int i, ret = 0; | |
612 | ||
613 | for (i = 0; i < cdns->num_ports; i++) { | |
2890a636 | 614 | if (cdns->ports[i].assigned) |
c46302ec VK |
615 | continue; |
616 | ||
617 | port = &cdns->ports[i]; | |
618 | port->assigned = true; | |
619 | port->direction = dir; | |
620 | port->ch = ch; | |
621 | break; | |
622 | } | |
623 | ||
624 | if (!port) { | |
625 | dev_err(cdns->dev, "Unable to find a free port\n"); | |
626 | return NULL; | |
627 | } | |
628 | ||
629 | if (pcm) { | |
630 | ret = sdw_cdns_alloc_stream(cdns, &cdns->pcm, port, ch, dir); | |
631 | if (ret) | |
632 | goto out; | |
633 | ||
634 | intel_pdi_shim_configure(sdw, port->pdi); | |
635 | sdw_cdns_config_stream(cdns, port, ch, dir, port->pdi); | |
636 | ||
637 | intel_pdi_alh_configure(sdw, port->pdi); | |
638 | ||
639 | } else { | |
640 | ret = sdw_cdns_alloc_stream(cdns, &cdns->pdm, port, ch, dir); | |
641 | } | |
642 | ||
643 | out: | |
644 | if (ret) { | |
645 | port->assigned = false; | |
646 | port = NULL; | |
647 | } | |
648 | ||
649 | return port; | |
650 | } | |
651 | ||
652 | static void intel_port_cleanup(struct sdw_cdns_dma_data *dma) | |
653 | { | |
654 | int i; | |
655 | ||
656 | for (i = 0; i < dma->nr_ports; i++) { | |
657 | if (dma->port[i]) { | |
658 | dma->port[i]->pdi->assigned = false; | |
659 | dma->port[i]->pdi = NULL; | |
660 | dma->port[i]->assigned = false; | |
661 | dma->port[i] = NULL; | |
662 | } | |
663 | } | |
664 | } | |
665 | ||
666 | static int intel_hw_params(struct snd_pcm_substream *substream, | |
d542bc9e PLB |
667 | struct snd_pcm_hw_params *params, |
668 | struct snd_soc_dai *dai) | |
c46302ec VK |
669 | { |
670 | struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); | |
671 | struct sdw_intel *sdw = cdns_to_intel(cdns); | |
672 | struct sdw_cdns_dma_data *dma; | |
673 | struct sdw_stream_config sconfig; | |
674 | struct sdw_port_config *pconfig; | |
675 | int ret, i, ch, dir; | |
676 | bool pcm = true; | |
677 | ||
678 | dma = snd_soc_dai_get_dma_data(dai, substream); | |
679 | if (!dma) | |
680 | return -EIO; | |
681 | ||
682 | ch = params_channels(params); | |
683 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
684 | dir = SDW_DATA_DIR_RX; | |
685 | else | |
686 | dir = SDW_DATA_DIR_TX; | |
687 | ||
688 | if (dma->stream_type == SDW_STREAM_PDM) { | |
689 | /* TODO: Check whether PDM decimator is already in use */ | |
690 | dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pdm, ch, dir); | |
691 | pcm = false; | |
692 | } else { | |
693 | dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pcm, ch, dir); | |
694 | } | |
695 | ||
696 | if (!dma->nr_ports) { | |
17ed5bef | 697 | dev_err(dai->dev, "ports/resources not available\n"); |
c46302ec VK |
698 | return -EINVAL; |
699 | } | |
700 | ||
701 | dma->port = kcalloc(dma->nr_ports, sizeof(*dma->port), GFP_KERNEL); | |
702 | if (!dma->port) | |
703 | return -ENOMEM; | |
704 | ||
705 | for (i = 0; i < dma->nr_ports; i++) { | |
706 | dma->port[i] = intel_alloc_port(sdw, ch, dir, pcm); | |
707 | if (!dma->port[i]) { | |
708 | ret = -EINVAL; | |
709 | goto port_error; | |
710 | } | |
711 | } | |
712 | ||
713 | /* Inform DSP about PDI stream number */ | |
714 | for (i = 0; i < dma->nr_ports; i++) { | |
715 | ret = intel_config_stream(sdw, substream, dai, params, | |
d542bc9e | 716 | dma->port[i]->pdi->intel_alh_id); |
c46302ec VK |
717 | if (ret) |
718 | goto port_error; | |
719 | } | |
720 | ||
721 | sconfig.direction = dir; | |
722 | sconfig.ch_count = ch; | |
723 | sconfig.frame_rate = params_rate(params); | |
724 | sconfig.type = dma->stream_type; | |
725 | ||
726 | if (dma->stream_type == SDW_STREAM_PDM) { | |
727 | sconfig.frame_rate *= 50; | |
728 | sconfig.bps = 1; | |
729 | } else { | |
730 | sconfig.bps = snd_pcm_format_width(params_format(params)); | |
731 | } | |
732 | ||
733 | /* Port configuration */ | |
734 | pconfig = kcalloc(dma->nr_ports, sizeof(*pconfig), GFP_KERNEL); | |
735 | if (!pconfig) { | |
736 | ret = -ENOMEM; | |
737 | goto port_error; | |
738 | } | |
739 | ||
740 | for (i = 0; i < dma->nr_ports; i++) { | |
741 | pconfig[i].num = dma->port[i]->num; | |
742 | pconfig[i].ch_mask = (1 << ch) - 1; | |
743 | } | |
744 | ||
745 | ret = sdw_stream_add_master(&cdns->bus, &sconfig, | |
d542bc9e | 746 | pconfig, dma->nr_ports, dma->stream); |
c46302ec | 747 | if (ret) { |
17ed5bef | 748 | dev_err(cdns->dev, "add master to stream failed:%d\n", ret); |
c46302ec VK |
749 | goto stream_error; |
750 | } | |
751 | ||
752 | kfree(pconfig); | |
753 | return ret; | |
754 | ||
755 | stream_error: | |
756 | kfree(pconfig); | |
757 | port_error: | |
758 | intel_port_cleanup(dma); | |
759 | kfree(dma->port); | |
760 | return ret; | |
761 | } | |
762 | ||
763 | static int | |
764 | intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) | |
765 | { | |
766 | struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); | |
767 | struct sdw_cdns_dma_data *dma; | |
768 | int ret; | |
769 | ||
770 | dma = snd_soc_dai_get_dma_data(dai, substream); | |
771 | if (!dma) | |
772 | return -EIO; | |
773 | ||
774 | ret = sdw_stream_remove_master(&cdns->bus, dma->stream); | |
775 | if (ret < 0) | |
17ed5bef | 776 | dev_err(dai->dev, "remove master from stream %s failed: %d\n", |
d542bc9e | 777 | dma->stream->name, ret); |
c46302ec VK |
778 | |
779 | intel_port_cleanup(dma); | |
780 | kfree(dma->port); | |
781 | return ret; | |
782 | } | |
783 | ||
183c7687 PLB |
784 | static void intel_shutdown(struct snd_pcm_substream *substream, |
785 | struct snd_soc_dai *dai) | |
786 | { | |
787 | struct sdw_cdns_dma_data *dma; | |
788 | ||
789 | dma = snd_soc_dai_get_dma_data(dai, substream); | |
790 | if (!dma) | |
791 | return; | |
792 | ||
793 | snd_soc_dai_set_dma_data(dai, substream, NULL); | |
794 | kfree(dma); | |
795 | } | |
796 | ||
c46302ec | 797 | static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai, |
d542bc9e | 798 | void *stream, int direction) |
c46302ec VK |
799 | { |
800 | return cdns_set_sdw_stream(dai, stream, true, direction); | |
801 | } | |
802 | ||
803 | static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai, | |
d542bc9e | 804 | void *stream, int direction) |
c46302ec VK |
805 | { |
806 | return cdns_set_sdw_stream(dai, stream, false, direction); | |
807 | } | |
808 | ||
b1635596 | 809 | static const struct snd_soc_dai_ops intel_pcm_dai_ops = { |
c46302ec VK |
810 | .hw_params = intel_hw_params, |
811 | .hw_free = intel_hw_free, | |
183c7687 | 812 | .shutdown = intel_shutdown, |
c46302ec VK |
813 | .set_sdw_stream = intel_pcm_set_sdw_stream, |
814 | }; | |
815 | ||
b1635596 | 816 | static const struct snd_soc_dai_ops intel_pdm_dai_ops = { |
c46302ec VK |
817 | .hw_params = intel_hw_params, |
818 | .hw_free = intel_hw_free, | |
183c7687 | 819 | .shutdown = intel_shutdown, |
c46302ec VK |
820 | .set_sdw_stream = intel_pdm_set_sdw_stream, |
821 | }; | |
822 | ||
823 | static const struct snd_soc_component_driver dai_component = { | |
824 | .name = "soundwire", | |
825 | }; | |
826 | ||
827 | static int intel_create_dai(struct sdw_cdns *cdns, | |
d542bc9e PLB |
828 | struct snd_soc_dai_driver *dais, |
829 | enum intel_pdi_type type, | |
830 | u32 num, u32 off, u32 max_ch, bool pcm) | |
c46302ec VK |
831 | { |
832 | int i; | |
833 | ||
834 | if (num == 0) | |
835 | return 0; | |
836 | ||
837 | /* TODO: Read supported rates/formats from hardware */ | |
838 | for (i = off; i < (off + num); i++) { | |
839 | dais[i].name = kasprintf(GFP_KERNEL, "SDW%d Pin%d", | |
d542bc9e | 840 | cdns->instance, i); |
c46302ec VK |
841 | if (!dais[i].name) |
842 | return -ENOMEM; | |
843 | ||
844 | if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) { | |
1215daee VK |
845 | dais[i].playback.stream_name = |
846 | kasprintf(GFP_KERNEL, "SDW%d Tx%d", | |
847 | cdns->instance, i); | |
c46302ec VK |
848 | if (!dais[i].playback.stream_name) { |
849 | kfree(dais[i].name); | |
850 | return -ENOMEM; | |
851 | } | |
852 | ||
853 | dais[i].playback.channels_min = 1; | |
854 | dais[i].playback.channels_max = max_ch; | |
855 | dais[i].playback.rates = SNDRV_PCM_RATE_48000; | |
856 | dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE; | |
857 | } | |
858 | ||
859 | if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) { | |
1215daee VK |
860 | dais[i].capture.stream_name = |
861 | kasprintf(GFP_KERNEL, "SDW%d Rx%d", | |
862 | cdns->instance, i); | |
c46302ec VK |
863 | if (!dais[i].capture.stream_name) { |
864 | kfree(dais[i].name); | |
865 | kfree(dais[i].playback.stream_name); | |
866 | return -ENOMEM; | |
867 | } | |
868 | ||
39194128 SK |
869 | dais[i].capture.channels_min = 1; |
870 | dais[i].capture.channels_max = max_ch; | |
c46302ec VK |
871 | dais[i].capture.rates = SNDRV_PCM_RATE_48000; |
872 | dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE; | |
873 | } | |
874 | ||
875 | dais[i].id = SDW_DAI_ID_RANGE_START + i; | |
876 | ||
877 | if (pcm) | |
878 | dais[i].ops = &intel_pcm_dai_ops; | |
879 | else | |
880 | dais[i].ops = &intel_pdm_dai_ops; | |
881 | } | |
882 | ||
883 | return 0; | |
884 | } | |
885 | ||
886 | static int intel_register_dai(struct sdw_intel *sdw) | |
887 | { | |
888 | struct sdw_cdns *cdns = &sdw->cdns; | |
889 | struct sdw_cdns_streams *stream; | |
890 | struct snd_soc_dai_driver *dais; | |
891 | int num_dai, ret, off = 0; | |
892 | ||
893 | /* DAIs are created based on total number of PDIs supported */ | |
894 | num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi; | |
895 | ||
896 | dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL); | |
897 | if (!dais) | |
898 | return -ENOMEM; | |
899 | ||
900 | /* Create PCM DAIs */ | |
901 | stream = &cdns->pcm; | |
902 | ||
1215daee VK |
903 | ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, stream->num_in, |
904 | off, stream->num_ch_in, true); | |
c46302ec VK |
905 | if (ret) |
906 | return ret; | |
907 | ||
908 | off += cdns->pcm.num_in; | |
1215daee VK |
909 | ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out, |
910 | off, stream->num_ch_out, true); | |
c46302ec VK |
911 | if (ret) |
912 | return ret; | |
913 | ||
914 | off += cdns->pcm.num_out; | |
1215daee VK |
915 | ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd, |
916 | off, stream->num_ch_bd, true); | |
c46302ec VK |
917 | if (ret) |
918 | return ret; | |
919 | ||
920 | /* Create PDM DAIs */ | |
921 | stream = &cdns->pdm; | |
922 | off += cdns->pcm.num_bd; | |
1215daee VK |
923 | ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in, |
924 | off, stream->num_ch_in, false); | |
c46302ec VK |
925 | if (ret) |
926 | return ret; | |
927 | ||
928 | off += cdns->pdm.num_in; | |
1215daee VK |
929 | ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out, |
930 | off, stream->num_ch_out, false); | |
c46302ec VK |
931 | if (ret) |
932 | return ret; | |
933 | ||
934 | off += cdns->pdm.num_bd; | |
1215daee VK |
935 | ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd, |
936 | off, stream->num_ch_bd, false); | |
c46302ec VK |
937 | if (ret) |
938 | return ret; | |
939 | ||
940 | return snd_soc_register_component(cdns->dev, &dai_component, | |
d542bc9e | 941 | dais, num_dai); |
c46302ec VK |
942 | } |
943 | ||
085f4ace PLB |
944 | static int sdw_master_read_intel_prop(struct sdw_bus *bus) |
945 | { | |
946 | struct sdw_master_prop *prop = &bus->prop; | |
947 | struct fwnode_handle *link; | |
948 | char name[32]; | |
395713d8 | 949 | u32 quirk_mask; |
085f4ace PLB |
950 | |
951 | /* Find master handle */ | |
952 | snprintf(name, sizeof(name), | |
953 | "mipi-sdw-link-%d-subproperties", bus->link_id); | |
954 | ||
955 | link = device_get_named_child_node(bus->dev, name); | |
956 | if (!link) { | |
957 | dev_err(bus->dev, "Master node %s not found\n", name); | |
958 | return -EIO; | |
959 | } | |
960 | ||
961 | fwnode_property_read_u32(link, | |
962 | "intel-sdw-ip-clock", | |
963 | &prop->mclk_freq); | |
395713d8 PLB |
964 | |
965 | fwnode_property_read_u32(link, | |
966 | "intel-quirk-mask", | |
967 | &quirk_mask); | |
968 | ||
969 | if (quirk_mask & SDW_INTEL_QUIRK_MASK_BUS_DISABLE) | |
970 | prop->hw_disabled = true; | |
971 | ||
085f4ace PLB |
972 | return 0; |
973 | } | |
974 | ||
71bb8a1b VK |
975 | static int intel_prop_read(struct sdw_bus *bus) |
976 | { | |
977 | /* Initialize with default handler to read all DisCo properties */ | |
978 | sdw_master_read_prop(bus); | |
979 | ||
085f4ace PLB |
980 | /* read Intel-specific properties */ |
981 | sdw_master_read_intel_prop(bus); | |
982 | ||
71bb8a1b VK |
983 | return 0; |
984 | } | |
985 | ||
c91605f4 SN |
986 | static struct sdw_master_ops sdw_intel_ops = { |
987 | .read_prop = sdw_master_read_prop, | |
988 | .xfer_msg = cdns_xfer_msg, | |
989 | .xfer_msg_defer = cdns_xfer_msg_defer, | |
990 | .reset_page_addr = cdns_reset_page_addr, | |
07abeff1 | 991 | .set_bus_conf = cdns_bus_conf, |
30246e2d SN |
992 | .pre_bank_switch = intel_pre_bank_switch, |
993 | .post_bank_switch = intel_post_bank_switch, | |
c91605f4 SN |
994 | }; |
995 | ||
71bb8a1b VK |
996 | /* |
997 | * probe and init | |
998 | */ | |
999 | static int intel_probe(struct platform_device *pdev) | |
1000 | { | |
37a2d22b | 1001 | struct sdw_cdns_stream_config config; |
71bb8a1b VK |
1002 | struct sdw_intel *sdw; |
1003 | int ret; | |
1004 | ||
1005 | sdw = devm_kzalloc(&pdev->dev, sizeof(*sdw), GFP_KERNEL); | |
1006 | if (!sdw) | |
1007 | return -ENOMEM; | |
1008 | ||
1009 | sdw->instance = pdev->id; | |
1010 | sdw->res = dev_get_platdata(&pdev->dev); | |
1011 | sdw->cdns.dev = &pdev->dev; | |
1012 | sdw->cdns.registers = sdw->res->registers; | |
1013 | sdw->cdns.instance = sdw->instance; | |
1014 | sdw->cdns.msg_count = 0; | |
1015 | sdw->cdns.bus.dev = &pdev->dev; | |
1016 | sdw->cdns.bus.link_id = pdev->id; | |
1017 | ||
1018 | sdw_cdns_probe(&sdw->cdns); | |
1019 | ||
1020 | /* Set property read ops */ | |
c91605f4 SN |
1021 | sdw_intel_ops.read_prop = intel_prop_read; |
1022 | sdw->cdns.bus.ops = &sdw_intel_ops; | |
71bb8a1b VK |
1023 | |
1024 | platform_set_drvdata(pdev, sdw); | |
1025 | ||
1026 | ret = sdw_add_bus_master(&sdw->cdns.bus); | |
1027 | if (ret) { | |
1028 | dev_err(&pdev->dev, "sdw_add_bus_master fail: %d\n", ret); | |
1029 | goto err_master_reg; | |
1030 | } | |
1031 | ||
395713d8 PLB |
1032 | if (sdw->cdns.bus.prop.hw_disabled) { |
1033 | dev_info(&pdev->dev, "SoundWire master %d is disabled, ignoring\n", | |
1034 | sdw->cdns.bus.link_id); | |
1035 | return 0; | |
1036 | } | |
1037 | ||
71bb8a1b VK |
1038 | /* Initialize shim and controller */ |
1039 | intel_link_power_up(sdw); | |
1040 | intel_shim_init(sdw); | |
1041 | ||
1042 | ret = sdw_cdns_init(&sdw->cdns); | |
1043 | if (ret) | |
1044 | goto err_init; | |
1045 | ||
7094dc2b | 1046 | ret = sdw_cdns_enable_interrupt(&sdw->cdns); |
37a2d22b VK |
1047 | |
1048 | /* Read the PDI config and initialize cadence PDI */ | |
1049 | intel_pdi_init(sdw, &config); | |
1050 | ret = sdw_cdns_pdi_init(&sdw->cdns, config); | |
71bb8a1b VK |
1051 | if (ret) |
1052 | goto err_init; | |
1053 | ||
37a2d22b VK |
1054 | intel_pdi_ch_update(sdw); |
1055 | ||
71bb8a1b | 1056 | /* Acquire IRQ */ |
d542bc9e PLB |
1057 | ret = request_threaded_irq(sdw->res->irq, sdw_cdns_irq, sdw_cdns_thread, |
1058 | IRQF_SHARED, KBUILD_MODNAME, &sdw->cdns); | |
71bb8a1b VK |
1059 | if (ret < 0) { |
1060 | dev_err(sdw->cdns.dev, "unable to grab IRQ %d, disabling device\n", | |
d542bc9e | 1061 | sdw->res->irq); |
71bb8a1b VK |
1062 | goto err_init; |
1063 | } | |
1064 | ||
c46302ec VK |
1065 | /* Register DAIs */ |
1066 | ret = intel_register_dai(sdw); | |
1067 | if (ret) { | |
17ed5bef | 1068 | dev_err(sdw->cdns.dev, "DAI registration failed: %d\n", ret); |
c46302ec VK |
1069 | snd_soc_unregister_component(sdw->cdns.dev); |
1070 | goto err_dai; | |
1071 | } | |
1072 | ||
79ee6631 PLB |
1073 | intel_debugfs_init(sdw); |
1074 | ||
71bb8a1b VK |
1075 | return 0; |
1076 | ||
c46302ec VK |
1077 | err_dai: |
1078 | free_irq(sdw->res->irq, sdw); | |
71bb8a1b VK |
1079 | err_init: |
1080 | sdw_delete_bus_master(&sdw->cdns.bus); | |
1081 | err_master_reg: | |
1082 | return ret; | |
1083 | } | |
1084 | ||
1085 | static int intel_remove(struct platform_device *pdev) | |
1086 | { | |
1087 | struct sdw_intel *sdw; | |
1088 | ||
1089 | sdw = platform_get_drvdata(pdev); | |
1090 | ||
395713d8 PLB |
1091 | if (!sdw->cdns.bus.prop.hw_disabled) { |
1092 | intel_debugfs_exit(sdw); | |
1093 | free_irq(sdw->res->irq, sdw); | |
1094 | snd_soc_unregister_component(sdw->cdns.dev); | |
1095 | } | |
71bb8a1b VK |
1096 | sdw_delete_bus_master(&sdw->cdns.bus); |
1097 | ||
1098 | return 0; | |
1099 | } | |
1100 | ||
1101 | static struct platform_driver sdw_intel_drv = { | |
1102 | .probe = intel_probe, | |
1103 | .remove = intel_remove, | |
1104 | .driver = { | |
1105 | .name = "int-sdw", | |
1106 | ||
1107 | }, | |
1108 | }; | |
1109 | ||
1110 | module_platform_driver(sdw_intel_drv); | |
1111 | ||
1112 | MODULE_LICENSE("Dual BSD/GPL"); | |
1113 | MODULE_ALIAS("platform:int-sdw"); | |
1114 | MODULE_DESCRIPTION("Intel Soundwire Master Driver"); |