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754ce4f2 HS |
1 | /* |
2 | * Driver for Atmel AT32 and AT91 SPI Controllers | |
3 | * | |
4 | * Copyright (C) 2006 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/clk.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/spi/spi.h> | |
21 | ||
22 | #include <asm/io.h> | |
a09e64fb RK |
23 | #include <mach/board.h> |
24 | #include <mach/gpio.h> | |
25 | #include <mach/cpu.h> | |
bb2d1c36 | 26 | |
754ce4f2 HS |
27 | #include "atmel_spi.h" |
28 | ||
29 | /* | |
30 | * The core SPI transfer engine just talks to a register bank to set up | |
31 | * DMA transfers; transfer queue progress is driven by IRQs. The clock | |
32 | * framework provides the base clock, subdivided for each spi_device. | |
754ce4f2 HS |
33 | */ |
34 | struct atmel_spi { | |
35 | spinlock_t lock; | |
36 | ||
37 | void __iomem *regs; | |
38 | int irq; | |
39 | struct clk *clk; | |
40 | struct platform_device *pdev; | |
defbd3b4 | 41 | struct spi_device *stay; |
754ce4f2 HS |
42 | |
43 | u8 stopping; | |
44 | struct list_head queue; | |
45 | struct spi_transfer *current_transfer; | |
154443c7 SE |
46 | unsigned long current_remaining_bytes; |
47 | struct spi_transfer *next_transfer; | |
48 | unsigned long next_remaining_bytes; | |
754ce4f2 HS |
49 | |
50 | void *buffer; | |
51 | dma_addr_t buffer_dma; | |
52 | }; | |
53 | ||
5ee36c98 HS |
54 | /* Controller-specific per-slave state */ |
55 | struct atmel_spi_device { | |
56 | unsigned int npcs_pin; | |
57 | u32 csr; | |
58 | }; | |
59 | ||
754ce4f2 HS |
60 | #define BUFFER_SIZE PAGE_SIZE |
61 | #define INVALID_DMA_ADDRESS 0xffffffff | |
62 | ||
5bfa26ca HS |
63 | /* |
64 | * Version 2 of the SPI controller has | |
65 | * - CR.LASTXFER | |
66 | * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero) | |
67 | * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs) | |
68 | * - SPI_CSRx.CSAAT | |
69 | * - SPI_CSRx.SBCR allows faster clocking | |
70 | * | |
71 | * We can determine the controller version by reading the VERSION | |
72 | * register, but I haven't checked that it exists on all chips, and | |
73 | * this is cheaper anyway. | |
74 | */ | |
75 | static bool atmel_spi_is_v2(void) | |
76 | { | |
77 | return !cpu_is_at91rm9200(); | |
78 | } | |
79 | ||
754ce4f2 HS |
80 | /* |
81 | * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby | |
82 | * they assume that spi slave device state will not change on deselect, so | |
defbd3b4 DB |
83 | * that automagic deselection is OK. ("NPCSx rises if no data is to be |
84 | * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer | |
85 | * controllers have CSAAT and friends. | |
754ce4f2 | 86 | * |
defbd3b4 DB |
87 | * Since the CSAAT functionality is a bit weird on newer controllers as |
88 | * well, we use GPIO to control nCSx pins on all controllers, updating | |
89 | * MR.PCS to avoid confusing the controller. Using GPIOs also lets us | |
90 | * support active-high chipselects despite the controller's belief that | |
91 | * only active-low devices/systems exists. | |
92 | * | |
93 | * However, at91rm9200 has a second erratum whereby nCS0 doesn't work | |
94 | * right when driven with GPIO. ("Mode Fault does not allow more than one | |
95 | * Master on Chip Select 0.") No workaround exists for that ... so for | |
96 | * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH, | |
97 | * and (c) will trigger that first erratum in some cases. | |
5ee36c98 HS |
98 | * |
99 | * TODO: Test if the atmel_spi_is_v2() branch below works on | |
100 | * AT91RM9200 if we use some other register than CSR0. However, don't | |
101 | * do this unconditionally since AP7000 has an errata where the BITS | |
102 | * field in CSR0 overrides all other CSRs. | |
754ce4f2 HS |
103 | */ |
104 | ||
defbd3b4 | 105 | static void cs_activate(struct atmel_spi *as, struct spi_device *spi) |
754ce4f2 | 106 | { |
5ee36c98 | 107 | struct atmel_spi_device *asd = spi->controller_state; |
754ce4f2 | 108 | unsigned active = spi->mode & SPI_CS_HIGH; |
defbd3b4 DB |
109 | u32 mr; |
110 | ||
5ee36c98 HS |
111 | if (atmel_spi_is_v2()) { |
112 | /* | |
113 | * Always use CSR0. This ensures that the clock | |
114 | * switches to the correct idle polarity before we | |
115 | * toggle the CS. | |
116 | */ | |
117 | spi_writel(as, CSR0, asd->csr); | |
118 | spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(MODFDIS) | |
119 | | SPI_BIT(MSTR)); | |
120 | mr = spi_readl(as, MR); | |
121 | gpio_set_value(asd->npcs_pin, active); | |
122 | } else { | |
123 | u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0; | |
124 | int i; | |
125 | u32 csr; | |
126 | ||
127 | /* Make sure clock polarity is correct */ | |
128 | for (i = 0; i < spi->master->num_chipselect; i++) { | |
129 | csr = spi_readl(as, CSR0 + 4 * i); | |
130 | if ((csr ^ cpol) & SPI_BIT(CPOL)) | |
131 | spi_writel(as, CSR0 + 4 * i, | |
132 | csr ^ SPI_BIT(CPOL)); | |
133 | } | |
134 | ||
135 | mr = spi_readl(as, MR); | |
136 | mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr); | |
137 | if (spi->chip_select != 0) | |
138 | gpio_set_value(asd->npcs_pin, active); | |
139 | spi_writel(as, MR, mr); | |
140 | } | |
defbd3b4 DB |
141 | |
142 | dev_dbg(&spi->dev, "activate %u%s, mr %08x\n", | |
5ee36c98 | 143 | asd->npcs_pin, active ? " (high)" : "", |
defbd3b4 | 144 | mr); |
754ce4f2 HS |
145 | } |
146 | ||
defbd3b4 | 147 | static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi) |
754ce4f2 | 148 | { |
5ee36c98 | 149 | struct atmel_spi_device *asd = spi->controller_state; |
754ce4f2 | 150 | unsigned active = spi->mode & SPI_CS_HIGH; |
defbd3b4 DB |
151 | u32 mr; |
152 | ||
153 | /* only deactivate *this* device; sometimes transfers to | |
154 | * another device may be active when this routine is called. | |
155 | */ | |
156 | mr = spi_readl(as, MR); | |
157 | if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) { | |
158 | mr = SPI_BFINS(PCS, 0xf, mr); | |
159 | spi_writel(as, MR, mr); | |
160 | } | |
754ce4f2 | 161 | |
defbd3b4 | 162 | dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n", |
5ee36c98 | 163 | asd->npcs_pin, active ? " (low)" : "", |
defbd3b4 DB |
164 | mr); |
165 | ||
5bfa26ca | 166 | if (atmel_spi_is_v2() || spi->chip_select != 0) |
5ee36c98 | 167 | gpio_set_value(asd->npcs_pin, !active); |
754ce4f2 HS |
168 | } |
169 | ||
154443c7 SE |
170 | static inline int atmel_spi_xfer_is_last(struct spi_message *msg, |
171 | struct spi_transfer *xfer) | |
172 | { | |
173 | return msg->transfers.prev == &xfer->transfer_list; | |
174 | } | |
175 | ||
176 | static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer) | |
177 | { | |
178 | return xfer->delay_usecs == 0 && !xfer->cs_change; | |
179 | } | |
180 | ||
181 | static void atmel_spi_next_xfer_data(struct spi_master *master, | |
182 | struct spi_transfer *xfer, | |
183 | dma_addr_t *tx_dma, | |
184 | dma_addr_t *rx_dma, | |
185 | u32 *plen) | |
186 | { | |
187 | struct atmel_spi *as = spi_master_get_devdata(master); | |
188 | u32 len = *plen; | |
189 | ||
190 | /* use scratch buffer only when rx or tx data is unspecified */ | |
191 | if (xfer->rx_buf) | |
192 | *rx_dma = xfer->rx_dma + xfer->len - len; | |
193 | else { | |
194 | *rx_dma = as->buffer_dma; | |
195 | if (len > BUFFER_SIZE) | |
196 | len = BUFFER_SIZE; | |
197 | } | |
198 | if (xfer->tx_buf) | |
199 | *tx_dma = xfer->tx_dma + xfer->len - len; | |
200 | else { | |
201 | *tx_dma = as->buffer_dma; | |
202 | if (len > BUFFER_SIZE) | |
203 | len = BUFFER_SIZE; | |
204 | memset(as->buffer, 0, len); | |
205 | dma_sync_single_for_device(&as->pdev->dev, | |
206 | as->buffer_dma, len, DMA_TO_DEVICE); | |
207 | } | |
208 | ||
209 | *plen = len; | |
210 | } | |
211 | ||
754ce4f2 HS |
212 | /* |
213 | * Submit next transfer for DMA. | |
214 | * lock is held, spi irq is blocked | |
215 | */ | |
216 | static void atmel_spi_next_xfer(struct spi_master *master, | |
217 | struct spi_message *msg) | |
218 | { | |
219 | struct atmel_spi *as = spi_master_get_devdata(master); | |
220 | struct spi_transfer *xfer; | |
dc329442 GK |
221 | u32 len, remaining; |
222 | u32 ieval; | |
754ce4f2 HS |
223 | dma_addr_t tx_dma, rx_dma; |
224 | ||
154443c7 SE |
225 | if (!as->current_transfer) |
226 | xfer = list_entry(msg->transfers.next, | |
227 | struct spi_transfer, transfer_list); | |
228 | else if (!as->next_transfer) | |
229 | xfer = list_entry(as->current_transfer->transfer_list.next, | |
230 | struct spi_transfer, transfer_list); | |
231 | else | |
232 | xfer = NULL; | |
233 | ||
234 | if (xfer) { | |
dc329442 GK |
235 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); |
236 | ||
154443c7 SE |
237 | len = xfer->len; |
238 | atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); | |
239 | remaining = xfer->len - len; | |
240 | ||
241 | spi_writel(as, RPR, rx_dma); | |
242 | spi_writel(as, TPR, tx_dma); | |
243 | ||
244 | if (msg->spi->bits_per_word > 8) | |
245 | len >>= 1; | |
246 | spi_writel(as, RCR, len); | |
247 | spi_writel(as, TCR, len); | |
8bacb219 HS |
248 | |
249 | dev_dbg(&msg->spi->dev, | |
250 | " start xfer %p: len %u tx %p/%08x rx %p/%08x\n", | |
251 | xfer, xfer->len, xfer->tx_buf, xfer->tx_dma, | |
252 | xfer->rx_buf, xfer->rx_dma); | |
154443c7 SE |
253 | } else { |
254 | xfer = as->next_transfer; | |
255 | remaining = as->next_remaining_bytes; | |
754ce4f2 HS |
256 | } |
257 | ||
154443c7 SE |
258 | as->current_transfer = xfer; |
259 | as->current_remaining_bytes = remaining; | |
754ce4f2 | 260 | |
154443c7 SE |
261 | if (remaining > 0) |
262 | len = remaining; | |
8bacb219 HS |
263 | else if (!atmel_spi_xfer_is_last(msg, xfer) |
264 | && atmel_spi_xfer_can_be_chained(xfer)) { | |
154443c7 SE |
265 | xfer = list_entry(xfer->transfer_list.next, |
266 | struct spi_transfer, transfer_list); | |
267 | len = xfer->len; | |
268 | } else | |
269 | xfer = NULL; | |
754ce4f2 | 270 | |
154443c7 | 271 | as->next_transfer = xfer; |
754ce4f2 | 272 | |
154443c7 | 273 | if (xfer) { |
dc329442 GK |
274 | u32 total; |
275 | ||
154443c7 SE |
276 | total = len; |
277 | atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); | |
278 | as->next_remaining_bytes = total - len; | |
754ce4f2 | 279 | |
154443c7 SE |
280 | spi_writel(as, RNPR, rx_dma); |
281 | spi_writel(as, TNPR, tx_dma); | |
754ce4f2 | 282 | |
154443c7 SE |
283 | if (msg->spi->bits_per_word > 8) |
284 | len >>= 1; | |
285 | spi_writel(as, RNCR, len); | |
286 | spi_writel(as, TNCR, len); | |
8bacb219 HS |
287 | |
288 | dev_dbg(&msg->spi->dev, | |
289 | " next xfer %p: len %u tx %p/%08x rx %p/%08x\n", | |
290 | xfer, xfer->len, xfer->tx_buf, xfer->tx_dma, | |
291 | xfer->rx_buf, xfer->rx_dma); | |
dc329442 | 292 | ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES); |
154443c7 SE |
293 | } else { |
294 | spi_writel(as, RNCR, 0); | |
295 | spi_writel(as, TNCR, 0); | |
dc329442 | 296 | ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES); |
154443c7 SE |
297 | } |
298 | ||
299 | /* REVISIT: We're waiting for ENDRX before we start the next | |
754ce4f2 HS |
300 | * transfer because we need to handle some difficult timing |
301 | * issues otherwise. If we wait for ENDTX in one transfer and | |
302 | * then starts waiting for ENDRX in the next, it's difficult | |
303 | * to tell the difference between the ENDRX interrupt we're | |
304 | * actually waiting for and the ENDRX interrupt of the | |
305 | * previous transfer. | |
306 | * | |
307 | * It should be doable, though. Just not now... | |
308 | */ | |
dc329442 | 309 | spi_writel(as, IER, ieval); |
754ce4f2 HS |
310 | spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); |
311 | } | |
312 | ||
313 | static void atmel_spi_next_message(struct spi_master *master) | |
314 | { | |
315 | struct atmel_spi *as = spi_master_get_devdata(master); | |
316 | struct spi_message *msg; | |
defbd3b4 | 317 | struct spi_device *spi; |
754ce4f2 HS |
318 | |
319 | BUG_ON(as->current_transfer); | |
320 | ||
321 | msg = list_entry(as->queue.next, struct spi_message, queue); | |
defbd3b4 | 322 | spi = msg->spi; |
754ce4f2 | 323 | |
49dce689 | 324 | dev_dbg(master->dev.parent, "start message %p for %s\n", |
defbd3b4 DB |
325 | msg, spi->dev.bus_id); |
326 | ||
327 | /* select chip if it's not still active */ | |
328 | if (as->stay) { | |
329 | if (as->stay != spi) { | |
330 | cs_deactivate(as, as->stay); | |
331 | cs_activate(as, spi); | |
332 | } | |
333 | as->stay = NULL; | |
334 | } else | |
335 | cs_activate(as, spi); | |
754ce4f2 HS |
336 | |
337 | atmel_spi_next_xfer(master, msg); | |
338 | } | |
339 | ||
8da0859a DB |
340 | /* |
341 | * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma: | |
342 | * - The buffer is either valid for CPU access, else NULL | |
343 | * - If the buffer is valid, so is its DMA addresss | |
344 | * | |
345 | * This driver manages the dma addresss unless message->is_dma_mapped. | |
346 | */ | |
347 | static int | |
754ce4f2 HS |
348 | atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer) |
349 | { | |
8da0859a DB |
350 | struct device *dev = &as->pdev->dev; |
351 | ||
754ce4f2 | 352 | xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS; |
8da0859a DB |
353 | if (xfer->tx_buf) { |
354 | xfer->tx_dma = dma_map_single(dev, | |
754ce4f2 HS |
355 | (void *) xfer->tx_buf, xfer->len, |
356 | DMA_TO_DEVICE); | |
8d8bb39b | 357 | if (dma_mapping_error(dev, xfer->tx_dma)) |
8da0859a DB |
358 | return -ENOMEM; |
359 | } | |
360 | if (xfer->rx_buf) { | |
361 | xfer->rx_dma = dma_map_single(dev, | |
754ce4f2 HS |
362 | xfer->rx_buf, xfer->len, |
363 | DMA_FROM_DEVICE); | |
8d8bb39b | 364 | if (dma_mapping_error(dev, xfer->rx_dma)) { |
8da0859a DB |
365 | if (xfer->tx_buf) |
366 | dma_unmap_single(dev, | |
367 | xfer->tx_dma, xfer->len, | |
368 | DMA_TO_DEVICE); | |
369 | return -ENOMEM; | |
370 | } | |
371 | } | |
372 | return 0; | |
754ce4f2 HS |
373 | } |
374 | ||
375 | static void atmel_spi_dma_unmap_xfer(struct spi_master *master, | |
376 | struct spi_transfer *xfer) | |
377 | { | |
378 | if (xfer->tx_dma != INVALID_DMA_ADDRESS) | |
49dce689 | 379 | dma_unmap_single(master->dev.parent, xfer->tx_dma, |
754ce4f2 HS |
380 | xfer->len, DMA_TO_DEVICE); |
381 | if (xfer->rx_dma != INVALID_DMA_ADDRESS) | |
49dce689 | 382 | dma_unmap_single(master->dev.parent, xfer->rx_dma, |
754ce4f2 HS |
383 | xfer->len, DMA_FROM_DEVICE); |
384 | } | |
385 | ||
386 | static void | |
387 | atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as, | |
defbd3b4 | 388 | struct spi_message *msg, int status, int stay) |
754ce4f2 | 389 | { |
defbd3b4 DB |
390 | if (!stay || status < 0) |
391 | cs_deactivate(as, msg->spi); | |
392 | else | |
393 | as->stay = msg->spi; | |
394 | ||
754ce4f2 HS |
395 | list_del(&msg->queue); |
396 | msg->status = status; | |
397 | ||
49dce689 | 398 | dev_dbg(master->dev.parent, |
754ce4f2 HS |
399 | "xfer complete: %u bytes transferred\n", |
400 | msg->actual_length); | |
401 | ||
402 | spin_unlock(&as->lock); | |
403 | msg->complete(msg->context); | |
404 | spin_lock(&as->lock); | |
405 | ||
406 | as->current_transfer = NULL; | |
154443c7 | 407 | as->next_transfer = NULL; |
754ce4f2 HS |
408 | |
409 | /* continue if needed */ | |
410 | if (list_empty(&as->queue) || as->stopping) | |
411 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
412 | else | |
413 | atmel_spi_next_message(master); | |
414 | } | |
415 | ||
416 | static irqreturn_t | |
417 | atmel_spi_interrupt(int irq, void *dev_id) | |
418 | { | |
419 | struct spi_master *master = dev_id; | |
420 | struct atmel_spi *as = spi_master_get_devdata(master); | |
421 | struct spi_message *msg; | |
422 | struct spi_transfer *xfer; | |
423 | u32 status, pending, imr; | |
424 | int ret = IRQ_NONE; | |
425 | ||
426 | spin_lock(&as->lock); | |
427 | ||
428 | xfer = as->current_transfer; | |
429 | msg = list_entry(as->queue.next, struct spi_message, queue); | |
430 | ||
431 | imr = spi_readl(as, IMR); | |
432 | status = spi_readl(as, SR); | |
433 | pending = status & imr; | |
434 | ||
435 | if (pending & SPI_BIT(OVRES)) { | |
436 | int timeout; | |
437 | ||
438 | ret = IRQ_HANDLED; | |
439 | ||
dc329442 | 440 | spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) |
754ce4f2 HS |
441 | | SPI_BIT(OVRES))); |
442 | ||
443 | /* | |
444 | * When we get an overrun, we disregard the current | |
445 | * transfer. Data will not be copied back from any | |
446 | * bounce buffer and msg->actual_len will not be | |
447 | * updated with the last xfer. | |
448 | * | |
449 | * We will also not process any remaning transfers in | |
450 | * the message. | |
451 | * | |
452 | * First, stop the transfer and unmap the DMA buffers. | |
453 | */ | |
454 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
455 | if (!msg->is_dma_mapped) | |
456 | atmel_spi_dma_unmap_xfer(master, xfer); | |
457 | ||
458 | /* REVISIT: udelay in irq is unfriendly */ | |
459 | if (xfer->delay_usecs) | |
460 | udelay(xfer->delay_usecs); | |
461 | ||
dc329442 | 462 | dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n", |
754ce4f2 HS |
463 | spi_readl(as, TCR), spi_readl(as, RCR)); |
464 | ||
465 | /* | |
466 | * Clean up DMA registers and make sure the data | |
467 | * registers are empty. | |
468 | */ | |
469 | spi_writel(as, RNCR, 0); | |
470 | spi_writel(as, TNCR, 0); | |
471 | spi_writel(as, RCR, 0); | |
472 | spi_writel(as, TCR, 0); | |
473 | for (timeout = 1000; timeout; timeout--) | |
474 | if (spi_readl(as, SR) & SPI_BIT(TXEMPTY)) | |
475 | break; | |
476 | if (!timeout) | |
49dce689 | 477 | dev_warn(master->dev.parent, |
754ce4f2 HS |
478 | "timeout waiting for TXEMPTY"); |
479 | while (spi_readl(as, SR) & SPI_BIT(RDRF)) | |
480 | spi_readl(as, RDR); | |
481 | ||
482 | /* Clear any overrun happening while cleaning up */ | |
483 | spi_readl(as, SR); | |
484 | ||
defbd3b4 | 485 | atmel_spi_msg_done(master, as, msg, -EIO, 0); |
dc329442 | 486 | } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) { |
754ce4f2 HS |
487 | ret = IRQ_HANDLED; |
488 | ||
489 | spi_writel(as, IDR, pending); | |
490 | ||
154443c7 | 491 | if (as->current_remaining_bytes == 0) { |
754ce4f2 HS |
492 | msg->actual_length += xfer->len; |
493 | ||
494 | if (!msg->is_dma_mapped) | |
495 | atmel_spi_dma_unmap_xfer(master, xfer); | |
496 | ||
497 | /* REVISIT: udelay in irq is unfriendly */ | |
498 | if (xfer->delay_usecs) | |
499 | udelay(xfer->delay_usecs); | |
500 | ||
154443c7 | 501 | if (atmel_spi_xfer_is_last(msg, xfer)) { |
754ce4f2 | 502 | /* report completed message */ |
defbd3b4 DB |
503 | atmel_spi_msg_done(master, as, msg, 0, |
504 | xfer->cs_change); | |
754ce4f2 HS |
505 | } else { |
506 | if (xfer->cs_change) { | |
defbd3b4 | 507 | cs_deactivate(as, msg->spi); |
754ce4f2 | 508 | udelay(1); |
defbd3b4 | 509 | cs_activate(as, msg->spi); |
754ce4f2 HS |
510 | } |
511 | ||
512 | /* | |
513 | * Not done yet. Submit the next transfer. | |
514 | * | |
515 | * FIXME handle protocol options for xfer | |
516 | */ | |
517 | atmel_spi_next_xfer(master, msg); | |
518 | } | |
519 | } else { | |
520 | /* | |
521 | * Keep going, we still have data to send in | |
522 | * the current transfer. | |
523 | */ | |
524 | atmel_spi_next_xfer(master, msg); | |
525 | } | |
526 | } | |
527 | ||
528 | spin_unlock(&as->lock); | |
529 | ||
530 | return ret; | |
531 | } | |
532 | ||
dccd573b | 533 | /* the spi->mode bits understood by this driver: */ |
754ce4f2 HS |
534 | #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH) |
535 | ||
536 | static int atmel_spi_setup(struct spi_device *spi) | |
537 | { | |
538 | struct atmel_spi *as; | |
5ee36c98 | 539 | struct atmel_spi_device *asd; |
754ce4f2 HS |
540 | u32 scbr, csr; |
541 | unsigned int bits = spi->bits_per_word; | |
592e7bf8 | 542 | unsigned long bus_hz; |
754ce4f2 HS |
543 | unsigned int npcs_pin; |
544 | int ret; | |
545 | ||
546 | as = spi_master_get_devdata(spi->master); | |
547 | ||
548 | if (as->stopping) | |
549 | return -ESHUTDOWN; | |
550 | ||
551 | if (spi->chip_select > spi->master->num_chipselect) { | |
552 | dev_dbg(&spi->dev, | |
553 | "setup: invalid chipselect %u (%u defined)\n", | |
554 | spi->chip_select, spi->master->num_chipselect); | |
555 | return -EINVAL; | |
556 | } | |
557 | ||
558 | if (bits == 0) | |
559 | bits = 8; | |
560 | if (bits < 8 || bits > 16) { | |
561 | dev_dbg(&spi->dev, | |
562 | "setup: invalid bits_per_word %u (8 to 16)\n", | |
563 | bits); | |
564 | return -EINVAL; | |
565 | } | |
566 | ||
567 | if (spi->mode & ~MODEBITS) { | |
568 | dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", | |
569 | spi->mode & ~MODEBITS); | |
570 | return -EINVAL; | |
571 | } | |
572 | ||
defbd3b4 | 573 | /* see notes above re chipselect */ |
5bfa26ca | 574 | if (!atmel_spi_is_v2() |
defbd3b4 DB |
575 | && spi->chip_select == 0 |
576 | && (spi->mode & SPI_CS_HIGH)) { | |
577 | dev_dbg(&spi->dev, "setup: can't be active-high\n"); | |
578 | return -EINVAL; | |
579 | } | |
580 | ||
5bfa26ca | 581 | /* v1 chips start out at half the peripheral bus speed. */ |
754ce4f2 | 582 | bus_hz = clk_get_rate(as->clk); |
5bfa26ca | 583 | if (!atmel_spi_is_v2()) |
592e7bf8 HS |
584 | bus_hz /= 2; |
585 | ||
754ce4f2 | 586 | if (spi->max_speed_hz) { |
592e7bf8 HS |
587 | /* |
588 | * Calculate the lowest divider that satisfies the | |
589 | * constraint, assuming div32/fdiv/mbz == 0. | |
590 | */ | |
591 | scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz); | |
592 | ||
593 | /* | |
594 | * If the resulting divider doesn't fit into the | |
595 | * register bitfield, we can't satisfy the constraint. | |
596 | */ | |
754ce4f2 | 597 | if (scbr >= (1 << SPI_SCBR_SIZE)) { |
8da0859a DB |
598 | dev_dbg(&spi->dev, |
599 | "setup: %d Hz too slow, scbr %u; min %ld Hz\n", | |
600 | spi->max_speed_hz, scbr, bus_hz/255); | |
754ce4f2 HS |
601 | return -EINVAL; |
602 | } | |
603 | } else | |
592e7bf8 | 604 | /* speed zero means "as slow as possible" */ |
754ce4f2 | 605 | scbr = 0xff; |
754ce4f2 HS |
606 | |
607 | csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8); | |
608 | if (spi->mode & SPI_CPOL) | |
609 | csr |= SPI_BIT(CPOL); | |
610 | if (!(spi->mode & SPI_CPHA)) | |
611 | csr |= SPI_BIT(NCPHA); | |
612 | ||
1eed29df HS |
613 | /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs. |
614 | * | |
615 | * DLYBCT would add delays between words, slowing down transfers. | |
616 | * It could potentially be useful to cope with DMA bottlenecks, but | |
617 | * in those cases it's probably best to just use a lower bitrate. | |
618 | */ | |
619 | csr |= SPI_BF(DLYBS, 0); | |
620 | csr |= SPI_BF(DLYBCT, 0); | |
754ce4f2 HS |
621 | |
622 | /* chipselect must have been muxed as GPIO (e.g. in board setup) */ | |
623 | npcs_pin = (unsigned int)spi->controller_data; | |
5ee36c98 HS |
624 | asd = spi->controller_state; |
625 | if (!asd) { | |
626 | asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL); | |
627 | if (!asd) | |
628 | return -ENOMEM; | |
629 | ||
65f97a56 | 630 | ret = gpio_request(npcs_pin, spi->dev.bus_id); |
5ee36c98 HS |
631 | if (ret) { |
632 | kfree(asd); | |
754ce4f2 | 633 | return ret; |
5ee36c98 HS |
634 | } |
635 | ||
636 | asd->npcs_pin = npcs_pin; | |
637 | spi->controller_state = asd; | |
28735a72 | 638 | gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH)); |
defbd3b4 DB |
639 | } else { |
640 | unsigned long flags; | |
641 | ||
642 | spin_lock_irqsave(&as->lock, flags); | |
643 | if (as->stay == spi) | |
644 | as->stay = NULL; | |
645 | cs_deactivate(as, spi); | |
646 | spin_unlock_irqrestore(&as->lock, flags); | |
754ce4f2 HS |
647 | } |
648 | ||
5ee36c98 HS |
649 | asd->csr = csr; |
650 | ||
754ce4f2 HS |
651 | dev_dbg(&spi->dev, |
652 | "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n", | |
592e7bf8 | 653 | bus_hz / scbr, bits, spi->mode, spi->chip_select, csr); |
754ce4f2 | 654 | |
5ee36c98 HS |
655 | if (!atmel_spi_is_v2()) |
656 | spi_writel(as, CSR0 + 4 * spi->chip_select, csr); | |
754ce4f2 HS |
657 | |
658 | return 0; | |
659 | } | |
660 | ||
661 | static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg) | |
662 | { | |
663 | struct atmel_spi *as; | |
664 | struct spi_transfer *xfer; | |
665 | unsigned long flags; | |
49dce689 | 666 | struct device *controller = spi->master->dev.parent; |
754ce4f2 HS |
667 | |
668 | as = spi_master_get_devdata(spi->master); | |
669 | ||
670 | dev_dbg(controller, "new message %p submitted for %s\n", | |
671 | msg, spi->dev.bus_id); | |
672 | ||
673 | if (unlikely(list_empty(&msg->transfers) | |
674 | || !spi->max_speed_hz)) | |
675 | return -EINVAL; | |
676 | ||
677 | if (as->stopping) | |
678 | return -ESHUTDOWN; | |
679 | ||
680 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
06719814 | 681 | if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) { |
754ce4f2 HS |
682 | dev_dbg(&spi->dev, "missing rx or tx buf\n"); |
683 | return -EINVAL; | |
684 | } | |
685 | ||
686 | /* FIXME implement these protocol options!! */ | |
687 | if (xfer->bits_per_word || xfer->speed_hz) { | |
688 | dev_dbg(&spi->dev, "no protocol options yet\n"); | |
689 | return -ENOPROTOOPT; | |
690 | } | |
754ce4f2 | 691 | |
8da0859a DB |
692 | /* |
693 | * DMA map early, for performance (empties dcache ASAP) and | |
694 | * better fault reporting. This is a DMA-only driver. | |
695 | * | |
696 | * NOTE that if dma_unmap_single() ever starts to do work on | |
697 | * platforms supported by this driver, we would need to clean | |
698 | * up mappings for previously-mapped transfers. | |
699 | */ | |
700 | if (!msg->is_dma_mapped) { | |
701 | if (atmel_spi_dma_map_xfer(as, xfer) < 0) | |
702 | return -ENOMEM; | |
703 | } | |
754ce4f2 HS |
704 | } |
705 | ||
defbd3b4 | 706 | #ifdef VERBOSE |
754ce4f2 HS |
707 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
708 | dev_dbg(controller, | |
709 | " xfer %p: len %u tx %p/%08x rx %p/%08x\n", | |
710 | xfer, xfer->len, | |
711 | xfer->tx_buf, xfer->tx_dma, | |
712 | xfer->rx_buf, xfer->rx_dma); | |
713 | } | |
defbd3b4 | 714 | #endif |
754ce4f2 HS |
715 | |
716 | msg->status = -EINPROGRESS; | |
717 | msg->actual_length = 0; | |
718 | ||
719 | spin_lock_irqsave(&as->lock, flags); | |
720 | list_add_tail(&msg->queue, &as->queue); | |
721 | if (!as->current_transfer) | |
722 | atmel_spi_next_message(spi->master); | |
723 | spin_unlock_irqrestore(&as->lock, flags); | |
724 | ||
725 | return 0; | |
726 | } | |
727 | ||
bb2d1c36 | 728 | static void atmel_spi_cleanup(struct spi_device *spi) |
754ce4f2 | 729 | { |
defbd3b4 | 730 | struct atmel_spi *as = spi_master_get_devdata(spi->master); |
5ee36c98 | 731 | struct atmel_spi_device *asd = spi->controller_state; |
defbd3b4 DB |
732 | unsigned gpio = (unsigned) spi->controller_data; |
733 | unsigned long flags; | |
734 | ||
5ee36c98 | 735 | if (!asd) |
defbd3b4 DB |
736 | return; |
737 | ||
738 | spin_lock_irqsave(&as->lock, flags); | |
739 | if (as->stay == spi) { | |
740 | as->stay = NULL; | |
741 | cs_deactivate(as, spi); | |
742 | } | |
743 | spin_unlock_irqrestore(&as->lock, flags); | |
744 | ||
5ee36c98 | 745 | spi->controller_state = NULL; |
defbd3b4 | 746 | gpio_free(gpio); |
5ee36c98 | 747 | kfree(asd); |
754ce4f2 HS |
748 | } |
749 | ||
750 | /*-------------------------------------------------------------------------*/ | |
751 | ||
752 | static int __init atmel_spi_probe(struct platform_device *pdev) | |
753 | { | |
754 | struct resource *regs; | |
755 | int irq; | |
756 | struct clk *clk; | |
757 | int ret; | |
758 | struct spi_master *master; | |
759 | struct atmel_spi *as; | |
760 | ||
761 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
762 | if (!regs) | |
763 | return -ENXIO; | |
764 | ||
765 | irq = platform_get_irq(pdev, 0); | |
766 | if (irq < 0) | |
767 | return irq; | |
768 | ||
769 | clk = clk_get(&pdev->dev, "spi_clk"); | |
770 | if (IS_ERR(clk)) | |
771 | return PTR_ERR(clk); | |
772 | ||
773 | /* setup spi core then atmel-specific driver state */ | |
774 | ret = -ENOMEM; | |
775 | master = spi_alloc_master(&pdev->dev, sizeof *as); | |
776 | if (!master) | |
777 | goto out_free; | |
778 | ||
779 | master->bus_num = pdev->id; | |
780 | master->num_chipselect = 4; | |
781 | master->setup = atmel_spi_setup; | |
782 | master->transfer = atmel_spi_transfer; | |
783 | master->cleanup = atmel_spi_cleanup; | |
784 | platform_set_drvdata(pdev, master); | |
785 | ||
786 | as = spi_master_get_devdata(master); | |
787 | ||
8da0859a DB |
788 | /* |
789 | * Scratch buffer is used for throwaway rx and tx data. | |
790 | * It's coherent to minimize dcache pollution. | |
791 | */ | |
754ce4f2 HS |
792 | as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE, |
793 | &as->buffer_dma, GFP_KERNEL); | |
794 | if (!as->buffer) | |
795 | goto out_free; | |
796 | ||
797 | spin_lock_init(&as->lock); | |
798 | INIT_LIST_HEAD(&as->queue); | |
799 | as->pdev = pdev; | |
800 | as->regs = ioremap(regs->start, (regs->end - regs->start) + 1); | |
801 | if (!as->regs) | |
802 | goto out_free_buffer; | |
803 | as->irq = irq; | |
804 | as->clk = clk; | |
754ce4f2 HS |
805 | |
806 | ret = request_irq(irq, atmel_spi_interrupt, 0, | |
807 | pdev->dev.bus_id, master); | |
808 | if (ret) | |
809 | goto out_unmap_regs; | |
810 | ||
811 | /* Initialize the hardware */ | |
812 | clk_enable(clk); | |
813 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
50d7d5bf | 814 | spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ |
754ce4f2 HS |
815 | spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); |
816 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
817 | spi_writel(as, CR, SPI_BIT(SPIEN)); | |
818 | ||
819 | /* go! */ | |
820 | dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n", | |
821 | (unsigned long)regs->start, irq); | |
822 | ||
823 | ret = spi_register_master(master); | |
824 | if (ret) | |
825 | goto out_reset_hw; | |
826 | ||
827 | return 0; | |
828 | ||
829 | out_reset_hw: | |
830 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
50d7d5bf | 831 | spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ |
754ce4f2 HS |
832 | clk_disable(clk); |
833 | free_irq(irq, master); | |
834 | out_unmap_regs: | |
835 | iounmap(as->regs); | |
836 | out_free_buffer: | |
837 | dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, | |
838 | as->buffer_dma); | |
839 | out_free: | |
840 | clk_put(clk); | |
841 | spi_master_put(master); | |
842 | return ret; | |
843 | } | |
844 | ||
845 | static int __exit atmel_spi_remove(struct platform_device *pdev) | |
846 | { | |
847 | struct spi_master *master = platform_get_drvdata(pdev); | |
848 | struct atmel_spi *as = spi_master_get_devdata(master); | |
849 | struct spi_message *msg; | |
850 | ||
851 | /* reset the hardware and block queue progress */ | |
852 | spin_lock_irq(&as->lock); | |
853 | as->stopping = 1; | |
854 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
50d7d5bf | 855 | spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ |
754ce4f2 HS |
856 | spi_readl(as, SR); |
857 | spin_unlock_irq(&as->lock); | |
858 | ||
859 | /* Terminate remaining queued transfers */ | |
860 | list_for_each_entry(msg, &as->queue, queue) { | |
861 | /* REVISIT unmapping the dma is a NOP on ARM and AVR32 | |
862 | * but we shouldn't depend on that... | |
863 | */ | |
864 | msg->status = -ESHUTDOWN; | |
865 | msg->complete(msg->context); | |
866 | } | |
867 | ||
868 | dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, | |
869 | as->buffer_dma); | |
870 | ||
871 | clk_disable(as->clk); | |
872 | clk_put(as->clk); | |
873 | free_irq(as->irq, master); | |
874 | iounmap(as->regs); | |
875 | ||
876 | spi_unregister_master(master); | |
877 | ||
878 | return 0; | |
879 | } | |
880 | ||
881 | #ifdef CONFIG_PM | |
882 | ||
883 | static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg) | |
884 | { | |
885 | struct spi_master *master = platform_get_drvdata(pdev); | |
886 | struct atmel_spi *as = spi_master_get_devdata(master); | |
887 | ||
888 | clk_disable(as->clk); | |
889 | return 0; | |
890 | } | |
891 | ||
892 | static int atmel_spi_resume(struct platform_device *pdev) | |
893 | { | |
894 | struct spi_master *master = platform_get_drvdata(pdev); | |
895 | struct atmel_spi *as = spi_master_get_devdata(master); | |
896 | ||
897 | clk_enable(as->clk); | |
898 | return 0; | |
899 | } | |
900 | ||
901 | #else | |
902 | #define atmel_spi_suspend NULL | |
903 | #define atmel_spi_resume NULL | |
904 | #endif | |
905 | ||
906 | ||
907 | static struct platform_driver atmel_spi_driver = { | |
908 | .driver = { | |
909 | .name = "atmel_spi", | |
910 | .owner = THIS_MODULE, | |
911 | }, | |
912 | .suspend = atmel_spi_suspend, | |
913 | .resume = atmel_spi_resume, | |
914 | .remove = __exit_p(atmel_spi_remove), | |
915 | }; | |
916 | ||
917 | static int __init atmel_spi_init(void) | |
918 | { | |
919 | return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe); | |
920 | } | |
921 | module_init(atmel_spi_init); | |
922 | ||
923 | static void __exit atmel_spi_exit(void) | |
924 | { | |
925 | platform_driver_unregister(&atmel_spi_driver); | |
926 | } | |
927 | module_exit(atmel_spi_exit); | |
928 | ||
929 | MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver"); | |
930 | MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>"); | |
931 | MODULE_LICENSE("GPL"); | |
7e38c3c4 | 932 | MODULE_ALIAS("platform:atmel_spi"); |