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[mirror_ubuntu-zesty-kernel.git] / drivers / spi / au1550_spi.c
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63bd2359
JN		 1/*
2 * au1550_spi.c - au1550 psc spi controller driver
3 * may work also with au1200, au1210, au1250
4 * will not work on au1000, au1100 and au1500 (no full spi controller there)
5 *
6 * Copyright (c) 2006 ATRON electronic GmbH
7 * Author: Jan Nikitenko <jan.nikitenko@gmail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/errno.h>
27#include <linux/device.h>
28#include <linux/platform_device.h>
3a93a159 29#include <linux/resource.h>
63bd2359
JN		 30#include <linux/spi/spi.h>
31#include <linux/spi/spi_bitbang.h>
32#include <linux/dma-mapping.h>
33#include <linux/completion.h>
34#include <asm/mach-au1x00/au1000.h>
35#include <asm/mach-au1x00/au1xxx_psc.h>
36#include <asm/mach-au1x00/au1xxx_dbdma.h>
37
38#include <asm/mach-au1x00/au1550_spi.h>
39
40static unsigned usedma = 1;
41module_param(usedma, uint, 0644);
42
43/*
44#define AU1550_SPI_DEBUG_LOOPBACK
45*/
46
47
48#define AU1550_SPI_DBDMA_DESCRIPTORS 1
49#define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
50
51struct au1550_spi {
52 struct spi_bitbang bitbang;
53
54 volatile psc_spi_t __iomem *regs;
55 int irq;
56 unsigned freq_max;
57 unsigned freq_min;
58
59 unsigned len;
60 unsigned tx_count;
61 unsigned rx_count;
62 const u8 *tx;
63 u8 *rx;
64
65 void (*rx_word)(struct au1550_spi *hw);
66 void (*tx_word)(struct au1550_spi *hw);
67 int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
68 irqreturn_t (*irq_callback)(struct au1550_spi *hw);
69
70 struct completion master_done;
71
72 unsigned usedma;
73 u32 dma_tx_id;
74 u32 dma_rx_id;
75 u32 dma_tx_ch;
76 u32 dma_rx_ch;
77
78 u8 *dma_rx_tmpbuf;
79 unsigned dma_rx_tmpbuf_size;
80 u32 dma_rx_tmpbuf_addr;
81
82 struct spi_master *master;
83 struct device *dev;
84 struct au1550_spi_info *pdata;
3a93a159 85 struct resource *ioarea;
63bd2359
JN		 86};
87
88
89/* we use an 8-bit memory device for dma transfers to/from spi fifo */
90static dbdev_tab_t au1550_spi_mem_dbdev =
91{
92 .dev_id = DBDMA_MEM_CHAN,
93 .dev_flags = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
94 .dev_tsize = 0,
95 .dev_devwidth = 8,
96 .dev_physaddr = 0x00000000,
97 .dev_intlevel = 0,
98 .dev_intpolarity = 0
99};
100
3a93a159
ML		 101static int ddma_memid; /* id to above mem dma device */
102
63bd2359
JN		 103static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
104
105
40369e1c 106/*
63bd2359
JN		 107 * compute BRG and DIV bits to setup spi clock based on main input clock rate
108 * that was specified in platform data structure
109 * according to au1550 datasheet:
110 * psc_tempclk = psc_mainclk / (2 << DIV)
111 * spiclk = psc_tempclk / (2 * (BRG + 1))
112 * BRG valid range is 4..63
113 * DIV valid range is 0..3
114 */
115static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
116{
117 u32 mainclk_hz = hw->pdata->mainclk_hz;
118 u32 div, brg;
119
120 for (div = 0; div < 4; div++) {
121 brg = mainclk_hz / speed_hz / (4 << div);
122 /* now we have BRG+1 in brg, so count with that */
123 if (brg < (4 + 1)) {
124 brg = (4 + 1); /* speed_hz too big */
125 break; /* set lowest brg (div is == 0) */
126 }
127 if (brg <= (63 + 1))
128 break; /* we have valid brg and div */
129 }
130 if (div == 4) {
131 div = 3; /* speed_hz too small */
132 brg = (63 + 1); /* set highest brg and div */
133 }
134 brg--;
135 return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
136}
137
138static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
139{
140 hw->regs->psc_spimsk =
141 PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
142 | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
143 | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
144 au_sync();
145
146 hw->regs->psc_spievent =
147 PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
148 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
149 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
150 au_sync();
151}
152
153static void au1550_spi_reset_fifos(struct au1550_spi *hw)
154{
155 u32 pcr;
156
157 hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
158 au_sync();
159 do {
160 pcr = hw->regs->psc_spipcr;
161 au_sync();
162 } while (pcr != 0);
163}
164
165/*
166 * dma transfers are used for the most common spi word size of 8-bits
167 * we cannot easily change already set up dma channels' width, so if we wanted
168 * dma support for more than 8-bit words (up to 24 bits), we would need to
169 * setup dma channels from scratch on each spi transfer, based on bits_per_word
170 * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
171 * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
172 * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
173 */
174static void au1550_spi_chipsel(struct spi_device *spi, int value)
175{
176 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
177 unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
178 u32 cfg, stat;
179
180 switch (value) {
181 case BITBANG_CS_INACTIVE:
182 if (hw->pdata->deactivate_cs)
183 hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
184 cspol);
185 break;
186
187 case BITBANG_CS_ACTIVE:
188 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
189
190 cfg = hw->regs->psc_spicfg;
191 au_sync();
192 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
193 au_sync();
194
195 if (spi->mode & SPI_CPOL)
196 cfg |= PSC_SPICFG_BI;
197 else
198 cfg &= ~PSC_SPICFG_BI;
199 if (spi->mode & SPI_CPHA)
200 cfg &= ~PSC_SPICFG_CDE;
201 else
202 cfg |= PSC_SPICFG_CDE;
203
204 if (spi->mode & SPI_LSB_FIRST)
205 cfg |= PSC_SPICFG_MLF;
206 else
207 cfg &= ~PSC_SPICFG_MLF;
208
209 if (hw->usedma && spi->bits_per_word <= 8)
210 cfg &= ~PSC_SPICFG_DD_DISABLE;
211 else
212 cfg |= PSC_SPICFG_DD_DISABLE;
213 cfg = PSC_SPICFG_CLR_LEN(cfg);
214 cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
215
216 cfg = PSC_SPICFG_CLR_BAUD(cfg);
217 cfg &= ~PSC_SPICFG_SET_DIV(3);
218 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
219
220 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
221 au_sync();
222 do {
223 stat = hw->regs->psc_spistat;
224 au_sync();
225 } while ((stat & PSC_SPISTAT_DR) == 0);
226
227 if (hw->pdata->activate_cs)
228 hw->pdata->activate_cs(hw->pdata, spi->chip_select,
229 cspol);
230 break;
231 }
232}
233
234static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
235{
236 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
237 unsigned bpw, hz;
238 u32 cfg, stat;
239
04ba24b3
JN		 240 bpw = spi->bits_per_word;
241 hz = spi->max_speed_hz;
242 if (t) {
243 if (t->bits_per_word)
244 bpw = t->bits_per_word;
245 if (t->speed_hz)
246 hz = t->speed_hz;
247 }
63bd2359
JN		 248
249 if (bpw < 4 || bpw > 24) {
250 dev_err(&spi->dev, "setupxfer: invalid bits_per_word=%d\n",
251 bpw);
252 return -EINVAL;
253 }
254 if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) {
255 dev_err(&spi->dev, "setupxfer: clock rate=%d out of range\n",
256 hz);
257 return -EINVAL;
258 }
259
260 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
261
262 cfg = hw->regs->psc_spicfg;
263 au_sync();
264 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
265 au_sync();
266
267 if (hw->usedma && bpw <= 8)
268 cfg &= ~PSC_SPICFG_DD_DISABLE;
269 else
270 cfg |= PSC_SPICFG_DD_DISABLE;
271 cfg = PSC_SPICFG_CLR_LEN(cfg);
272 cfg |= PSC_SPICFG_SET_LEN(bpw);
273
274 cfg = PSC_SPICFG_CLR_BAUD(cfg);
275 cfg &= ~PSC_SPICFG_SET_DIV(3);
276 cfg |= au1550_spi_baudcfg(hw, hz);
277
278 hw->regs->psc_spicfg = cfg;
279 au_sync();
280
281 if (cfg & PSC_SPICFG_DE_ENABLE) {
282 do {
283 stat = hw->regs->psc_spistat;
284 au_sync();
285 } while ((stat & PSC_SPISTAT_DR) == 0);
286 }
287
288 au1550_spi_reset_fifos(hw);
289 au1550_spi_mask_ack_all(hw);
290 return 0;
291}
292
293static int au1550_spi_setup(struct spi_device *spi)
294{
295 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
296
63bd2359
JN		 297 if (spi->bits_per_word < 4 || spi->bits_per_word > 24) {
298 dev_err(&spi->dev, "setup: invalid bits_per_word=%d\n",
299 spi->bits_per_word);
300 return -EINVAL;
301 }
302
303 if (spi->max_speed_hz == 0)
304 spi->max_speed_hz = hw->freq_max;
305 if (spi->max_speed_hz > hw->freq_max
306 || spi->max_speed_hz < hw->freq_min)
307 return -EINVAL;
308 /*
309 * NOTE: cannot change speed and other hw settings immediately,
310 * otherwise sharing of spi bus is not possible,
311 * so do not call setupxfer(spi, NULL) here
312 */
313 return 0;
314}
315
316/*
317 * for dma spi transfers, we have to setup rx channel, otherwise there is
318 * no reliable way how to recognize that spi transfer is done
319 * dma complete callbacks are called before real spi transfer is finished
320 * and if only tx dma channel is set up (and rx fifo overflow event masked)
321 * spi master done event irq is not generated unless rx fifo is empty (emptied)
322 * so we need rx tmp buffer to use for rx dma if user does not provide one
323 */
324static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
325{
326 hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
327 if (!hw->dma_rx_tmpbuf)
328 return -ENOMEM;
329 hw->dma_rx_tmpbuf_size = size;
330 hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
331 size, DMA_FROM_DEVICE);
8d8bb39b 332 if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) {
63bd2359
JN		 333 kfree(hw->dma_rx_tmpbuf);
334 hw->dma_rx_tmpbuf = 0;
335 hw->dma_rx_tmpbuf_size = 0;
336 return -EFAULT;
337 }
338 return 0;
339}
340
341static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
342{
343 dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
344 hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
345 kfree(hw->dma_rx_tmpbuf);
346 hw->dma_rx_tmpbuf = 0;
347 hw->dma_rx_tmpbuf_size = 0;
348}
349
350static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
351{
352 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
353 dma_addr_t dma_tx_addr;
354 dma_addr_t dma_rx_addr;
355 u32 res;
356
357 hw->len = t->len;
358 hw->tx_count = 0;
359 hw->rx_count = 0;
360
361 hw->tx = t->tx_buf;
362 hw->rx = t->rx_buf;
363 dma_tx_addr = t->tx_dma;
364 dma_rx_addr = t->rx_dma;
365
366 /*
4e253d23
JN		 367 * check if buffers are already dma mapped, map them otherwise:
368 * - first map the TX buffer, so cache data gets written to memory
369 * - then map the RX buffer, so that cache entries (with
370 * soon-to-be-stale data) get removed
63bd2359
JN		 371 * use rx buffer in place of tx if tx buffer was not provided
372 * use temp rx buffer (preallocated or realloc to fit) for rx dma
373 */
4e253d23
JN		 374 if (t->tx_buf) {
375 if (t->tx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
376 dma_tx_addr = dma_map_single(hw->dev,
377 (void *)t->tx_buf,
378 t->len, DMA_TO_DEVICE);
379 if (dma_mapping_error(hw->dev, dma_tx_addr))
380 dev_err(hw->dev, "tx dma map error\n");
381 }
382 }
383
63bd2359
JN		 384 if (t->rx_buf) {
385 if (t->rx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
386 dma_rx_addr = dma_map_single(hw->dev,
387 (void *)t->rx_buf,
388 t->len, DMA_FROM_DEVICE);
8d8bb39b 389 if (dma_mapping_error(hw->dev, dma_rx_addr))
63bd2359
JN		 390 dev_err(hw->dev, "rx dma map error\n");
391 }
392 } else {
393 if (t->len > hw->dma_rx_tmpbuf_size) {
394 int ret;
395
396 au1550_spi_dma_rxtmp_free(hw);
397 ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
398 AU1550_SPI_DMA_RXTMP_MINSIZE));
399 if (ret < 0)
400 return ret;
401 }
402 hw->rx = hw->dma_rx_tmpbuf;
403 dma_rx_addr = hw->dma_rx_tmpbuf_addr;
404 dma_sync_single_for_device(hw->dev, dma_rx_addr,
405 t->len, DMA_FROM_DEVICE);
406 }
4e253d23
JN		 407
408 if (!t->tx_buf) {
63bd2359
JN		 409 dma_sync_single_for_device(hw->dev, dma_rx_addr,
410 t->len, DMA_BIDIRECTIONAL);
411 hw->tx = hw->rx;
412 }
413
414 /* put buffers on the ring */
415 res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, hw->rx, t->len);
416 if (!res)
417 dev_err(hw->dev, "rx dma put dest error\n");
418
419 res = au1xxx_dbdma_put_source(hw->dma_tx_ch, (void *)hw->tx, t->len);
420 if (!res)
421 dev_err(hw->dev, "tx dma put source error\n");
422
423 au1xxx_dbdma_start(hw->dma_rx_ch);
424 au1xxx_dbdma_start(hw->dma_tx_ch);
425
426 /* by default enable nearly all events interrupt */
427 hw->regs->psc_spimsk = PSC_SPIMSK_SD;
428 au_sync();
429
430 /* start the transfer */
431 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
432 au_sync();
433
434 wait_for_completion(&hw->master_done);
435
436 au1xxx_dbdma_stop(hw->dma_tx_ch);
437 au1xxx_dbdma_stop(hw->dma_rx_ch);
438
439 if (!t->rx_buf) {
440 /* using the temporal preallocated and premapped buffer */
441 dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
442 DMA_FROM_DEVICE);
443 }
444 /* unmap buffers if mapped above */
445 if (t->rx_buf && t->rx_dma == 0 )
446 dma_unmap_single(hw->dev, dma_rx_addr, t->len,
447 DMA_FROM_DEVICE);
448 if (t->tx_buf && t->tx_dma == 0 )
449 dma_unmap_single(hw->dev, dma_tx_addr, t->len,
450 DMA_TO_DEVICE);
451
452 return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
453}
454
455static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
456{
457 u32 stat, evnt;
458
459 stat = hw->regs->psc_spistat;
460 evnt = hw->regs->psc_spievent;
461 au_sync();
462 if ((stat & PSC_SPISTAT_DI) == 0) {
463 dev_err(hw->dev, "Unexpected IRQ!\n");
464 return IRQ_NONE;
465 }
466
467 if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
468 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
469 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
470 != 0) {
471 /*
472 * due to an spi error we consider transfer as done,
473 * so mask all events until before next transfer start
474 * and stop the possibly running dma immediatelly
475 */
476 au1550_spi_mask_ack_all(hw);
477 au1xxx_dbdma_stop(hw->dma_rx_ch);
478 au1xxx_dbdma_stop(hw->dma_tx_ch);
479
480 /* get number of transfered bytes */
481 hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
482 hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
483
484 au1xxx_dbdma_reset(hw->dma_rx_ch);
485 au1xxx_dbdma_reset(hw->dma_tx_ch);
486 au1550_spi_reset_fifos(hw);
487
bbe48ecc
JN		 488 if (evnt == PSC_SPIEVNT_RO)
489 dev_err(hw->dev,
490 "dma transfer: receive FIFO overflow!\n");
491 else
492 dev_err(hw->dev,
493 "dma transfer: unexpected SPI error "
494 "(event=0x%x stat=0x%x)!\n", evnt, stat);
63bd2359
JN		 495
496 complete(&hw->master_done);
497 return IRQ_HANDLED;
498 }
499
500 if ((evnt & PSC_SPIEVNT_MD) != 0) {
501 /* transfer completed successfully */
502 au1550_spi_mask_ack_all(hw);
503 hw->rx_count = hw->len;
504 hw->tx_count = hw->len;
505 complete(&hw->master_done);
506 }
507 return IRQ_HANDLED;
508}
509
510
511/* routines to handle different word sizes in pio mode */
512#define AU1550_SPI_RX_WORD(size, mask) \
513static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \
514{ \
515 u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \
516 au_sync(); \
517 if (hw->rx) { \
518 *(u##size *)hw->rx = (u##size)fifoword; \
519 hw->rx += (size) / 8; \
520 } \
521 hw->rx_count += (size) / 8; \
522}
523
524#define AU1550_SPI_TX_WORD(size, mask) \
525static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \
526{ \
527 u32 fifoword = 0; \
528 if (hw->tx) { \
529 fifoword = *(u##size *)hw->tx & (u32)(mask); \
530 hw->tx += (size) / 8; \
531 } \
532 hw->tx_count += (size) / 8; \
533 if (hw->tx_count >= hw->len) \
534 fifoword |= PSC_SPITXRX_LC; \
535 hw->regs->psc_spitxrx = fifoword; \
536 au_sync(); \
537}
538
539AU1550_SPI_RX_WORD(8,0xff)
540AU1550_SPI_RX_WORD(16,0xffff)
541AU1550_SPI_RX_WORD(32,0xffffff)
542AU1550_SPI_TX_WORD(8,0xff)
543AU1550_SPI_TX_WORD(16,0xffff)
544AU1550_SPI_TX_WORD(32,0xffffff)
545
546static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
547{
548 u32 stat, mask;
549 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
550
551 hw->tx = t->tx_buf;
552 hw->rx = t->rx_buf;
553 hw->len = t->len;
554 hw->tx_count = 0;
555 hw->rx_count = 0;
556
557 /* by default enable nearly all events after filling tx fifo */
558 mask = PSC_SPIMSK_SD;
559
560 /* fill the transmit FIFO */
561 while (hw->tx_count < hw->len) {
562
563 hw->tx_word(hw);
564
565 if (hw->tx_count >= hw->len) {
566 /* mask tx fifo request interrupt as we are done */
567 mask |= PSC_SPIMSK_TR;
568 }
569
570 stat = hw->regs->psc_spistat;
571 au_sync();
572 if (stat & PSC_SPISTAT_TF)
573 break;
574 }
575
576 /* enable event interrupts */
577 hw->regs->psc_spimsk = mask;
578 au_sync();
579
580 /* start the transfer */
581 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
582 au_sync();
583
584 wait_for_completion(&hw->master_done);
585
586 return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
587}
588
589static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
590{
591 int busy;
592 u32 stat, evnt;
593
594 stat = hw->regs->psc_spistat;
595 evnt = hw->regs->psc_spievent;
596 au_sync();
597 if ((stat & PSC_SPISTAT_DI) == 0) {
598 dev_err(hw->dev, "Unexpected IRQ!\n");
599 return IRQ_NONE;
600 }
601
602 if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
603 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
bbe48ecc 604 | PSC_SPIEVNT_SD))
63bd2359 605 != 0) {
63bd2359
JN		 606 /*
607 * due to an error we consider transfer as done,
608 * so mask all events until before next transfer start
609 */
610 au1550_spi_mask_ack_all(hw);
611 au1550_spi_reset_fifos(hw);
bbe48ecc
JN		 612 dev_err(hw->dev,
613 "pio transfer: unexpected SPI error "
614 "(event=0x%x stat=0x%x)!\n", evnt, stat);
63bd2359
JN		 615 complete(&hw->master_done);
616 return IRQ_HANDLED;
617 }
618
619 /*
620 * while there is something to read from rx fifo
621 * or there is a space to write to tx fifo:
622 */
623 do {
624 busy = 0;
625 stat = hw->regs->psc_spistat;
626 au_sync();
627
bbe48ecc
JN		 628 /*
629 * Take care to not let the Rx FIFO overflow.
630 *
631 * We only write a byte if we have read one at least. Initially,
632 * the write fifo is full, so we should read from the read fifo
633 * first.
634 * In case we miss a word from the read fifo, we should get a
635 * RO event and should back out.
636 */
637 if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
63bd2359 638 hw->rx_word(hw);
63bd2359 639 busy = 1;
63bd2359 640
bbe48ecc
JN		 641 if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
642 hw->tx_word(hw);
63bd2359
JN		 643 }
644 } while (busy);
645
bbe48ecc 646 hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
63bd2359
JN		 647 au_sync();
648
bbe48ecc
JN		 649 /*
650 * Restart the SPI transmission in case of a transmit underflow.
651 * This seems to work despite the notes in the Au1550 data book
652 * of Figure 8-4 with flowchart for SPI master operation:
653 *
654 * """Note 1: An XFR Error Interrupt occurs, unless masked,
655 * for any of the following events: Tx FIFO Underflow,
656 * Rx FIFO Overflow, or Multiple-master Error
657 * Note 2: In case of a Tx Underflow Error, all zeroes are
658 * transmitted."""
659 *
660 * By simply restarting the spi transfer on Tx Underflow Error,
661 * we assume that spi transfer was paused instead of zeroes
662 * transmittion mentioned in the Note 2 of Au1550 data book.
663 */
664 if (evnt & PSC_SPIEVNT_TU) {
665 hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
666 au_sync();
667 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
668 au_sync();
669 }
670
671 if (hw->rx_count >= hw->len) {
63bd2359
JN		 672 /* transfer completed successfully */
673 au1550_spi_mask_ack_all(hw);
674 complete(&hw->master_done);
675 }
676 return IRQ_HANDLED;
677}
678
679static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
680{
681 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
682 return hw->txrx_bufs(spi, t);
683}
684
40369e1c 685static irqreturn_t au1550_spi_irq(int irq, void *dev)
63bd2359
JN		 686{
687 struct au1550_spi *hw = dev;
688 return hw->irq_callback(hw);
689}
690
691static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
692{
693 if (bpw <= 8) {
694 if (hw->usedma) {
695 hw->txrx_bufs = &au1550_spi_dma_txrxb;
696 hw->irq_callback = &au1550_spi_dma_irq_callback;
697 } else {
698 hw->rx_word = &au1550_spi_rx_word_8;
699 hw->tx_word = &au1550_spi_tx_word_8;
700 hw->txrx_bufs = &au1550_spi_pio_txrxb;
701 hw->irq_callback = &au1550_spi_pio_irq_callback;
702 }
703 } else if (bpw <= 16) {
704 hw->rx_word = &au1550_spi_rx_word_16;
705 hw->tx_word = &au1550_spi_tx_word_16;
706 hw->txrx_bufs = &au1550_spi_pio_txrxb;
707 hw->irq_callback = &au1550_spi_pio_irq_callback;
708 } else {
709 hw->rx_word = &au1550_spi_rx_word_32;
710 hw->tx_word = &au1550_spi_tx_word_32;
711 hw->txrx_bufs = &au1550_spi_pio_txrxb;
712 hw->irq_callback = &au1550_spi_pio_irq_callback;
713 }
714}
715
716static void __init au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
717{
718 u32 stat, cfg;
719
720 /* set up the PSC for SPI mode */
721 hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
722 au_sync();
723 hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
724 au_sync();
725
726 hw->regs->psc_spicfg = 0;
727 au_sync();
728
729 hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
730 au_sync();
731
732 do {
733 stat = hw->regs->psc_spistat;
734 au_sync();
735 } while ((stat & PSC_SPISTAT_SR) == 0);
736
737
738 cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
739 cfg |= PSC_SPICFG_SET_LEN(8);
740 cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
741 /* use minimal allowed brg and div values as initial setting: */
742 cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
743
744#ifdef AU1550_SPI_DEBUG_LOOPBACK
745 cfg |= PSC_SPICFG_LB;
746#endif
747
748 hw->regs->psc_spicfg = cfg;
749 au_sync();
750
751 au1550_spi_mask_ack_all(hw);
752
753 hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
754 au_sync();
755
756 do {
757 stat = hw->regs->psc_spistat;
758 au_sync();
759 } while ((stat & PSC_SPISTAT_DR) == 0);
bbe48ecc
JN		 760
761 au1550_spi_reset_fifos(hw);
63bd2359
JN		 762}
763
764
765static int __init au1550_spi_probe(struct platform_device *pdev)
766{
767 struct au1550_spi *hw;
768 struct spi_master *master;
3a93a159 769 struct resource *r;
63bd2359
JN		 770 int err = 0;
771
772 master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
773 if (master == NULL) {
774 dev_err(&pdev->dev, "No memory for spi_master\n");
775 err = -ENOMEM;
776 goto err_nomem;
777 }
778
e7db06b5
DB		 779 /* the spi->mode bits understood by this driver: */
780 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
781
63bd2359
JN		 782 hw = spi_master_get_devdata(master);
783
784 hw->master = spi_master_get(master);
785 hw->pdata = pdev->dev.platform_data;
786 hw->dev = &pdev->dev;
787
788 if (hw->pdata == NULL) {
789 dev_err(&pdev->dev, "No platform data supplied\n");
790 err = -ENOENT;
791 goto err_no_pdata;
792 }
793
3a93a159
ML		 794 r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
795 if (!r) {
796 dev_err(&pdev->dev, "no IRQ\n");
797 err = -ENODEV;
798 goto err_no_iores;
799 }
800 hw->irq = r->start;
801
802 hw->usedma = 0;
803 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
804 if (r) {
805 hw->dma_tx_id = r->start;
806 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
807 if (r) {
808 hw->dma_rx_id = r->start;
809 if (usedma && ddma_memid) {
810 if (pdev->dev.dma_mask == NULL)
811 dev_warn(&pdev->dev, "no dma mask\n");
812 else
813 hw->usedma = 1;
814 }
815 }
816 }
63bd2359 817
3a93a159
ML		 818 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
819 if (!r) {
820 dev_err(&pdev->dev, "no mmio resource\n");
821 err = -ENODEV;
822 goto err_no_iores;
63bd2359
JN		 823 }
824
3a93a159
ML		 825 hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
826 pdev->name);
827 if (!hw->ioarea) {
63bd2359
JN		 828 dev_err(&pdev->dev, "Cannot reserve iomem region\n");
829 err = -ENXIO;
830 goto err_no_iores;
831 }
832
3a93a159
ML		 833 hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
834 if (!hw->regs) {
835 dev_err(&pdev->dev, "cannot ioremap\n");
836 err = -ENXIO;
837 goto err_ioremap;
63bd2359
JN		 838 }
839
3a93a159 840 platform_set_drvdata(pdev, hw);
63bd2359 841
3a93a159
ML		 842 init_completion(&hw->master_done);
843
844 hw->bitbang.master = hw->master;
845 hw->bitbang.setup_transfer = au1550_spi_setupxfer;
846 hw->bitbang.chipselect = au1550_spi_chipsel;
847 hw->bitbang.master->setup = au1550_spi_setup;
848 hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
849
850 if (hw->usedma) {
851 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
63bd2359
JN		 852 hw->dma_tx_id, NULL, (void *)hw);
853 if (hw->dma_tx_ch == 0) {
854 dev_err(&pdev->dev,
855 "Cannot allocate tx dma channel\n");
856 err = -ENXIO;
857 goto err_no_txdma;
858 }
859 au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
860 if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
861 AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
862 dev_err(&pdev->dev,
863 "Cannot allocate tx dma descriptors\n");
864 err = -ENXIO;
865 goto err_no_txdma_descr;
866 }
867
868
869 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
3a93a159 870 ddma_memid, NULL, (void *)hw);
63bd2359
JN		 871 if (hw->dma_rx_ch == 0) {
872 dev_err(&pdev->dev,
873 "Cannot allocate rx dma channel\n");
874 err = -ENXIO;
875 goto err_no_rxdma;
876 }
877 au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
878 if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
879 AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
880 dev_err(&pdev->dev,
881 "Cannot allocate rx dma descriptors\n");
882 err = -ENXIO;
883 goto err_no_rxdma_descr;
884 }
885
886 err = au1550_spi_dma_rxtmp_alloc(hw,
887 AU1550_SPI_DMA_RXTMP_MINSIZE);
888 if (err < 0) {
889 dev_err(&pdev->dev,
890 "Cannot allocate initial rx dma tmp buffer\n");
891 goto err_dma_rxtmp_alloc;
892 }
893 }
894
895 au1550_spi_bits_handlers_set(hw, 8);
896
897 err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
898 if (err) {
899 dev_err(&pdev->dev, "Cannot claim IRQ\n");
900 goto err_no_irq;
901 }
902
3a93a159 903 master->bus_num = pdev->id;
63bd2359
JN		 904 master->num_chipselect = hw->pdata->num_chipselect;
905
906 /*
907 * precompute valid range for spi freq - from au1550 datasheet:
908 * psc_tempclk = psc_mainclk / (2 << DIV)
909 * spiclk = psc_tempclk / (2 * (BRG + 1))
910 * BRG valid range is 4..63
911 * DIV valid range is 0..3
912 * round the min and max frequencies to values that would still
913 * produce valid brg and div
914 */
915 {
916 int min_div = (2 << 0) * (2 * (4 + 1));
917 int max_div = (2 << 3) * (2 * (63 + 1));
918 hw->freq_max = hw->pdata->mainclk_hz / min_div;
919 hw->freq_min = hw->pdata->mainclk_hz / (max_div + 1) + 1;
920 }
921
922 au1550_spi_setup_psc_as_spi(hw);
923
924 err = spi_bitbang_start(&hw->bitbang);
925 if (err) {
926 dev_err(&pdev->dev, "Failed to register SPI master\n");
927 goto err_register;
928 }
929
930 dev_info(&pdev->dev,
931 "spi master registered: bus_num=%d num_chipselect=%d\n",
932 master->bus_num, master->num_chipselect);
933
934 return 0;
935
936err_register:
937 free_irq(hw->irq, hw);
938
939err_no_irq:
940 au1550_spi_dma_rxtmp_free(hw);
941
942err_dma_rxtmp_alloc:
943err_no_rxdma_descr:
944 if (hw->usedma)
945 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
946
947err_no_rxdma:
948err_no_txdma_descr:
949 if (hw->usedma)
950 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
951
952err_no_txdma:
3a93a159
ML		 953 iounmap((void __iomem *)hw->regs);
954
955err_ioremap:
956 release_resource(hw->ioarea);
957 kfree(hw->ioarea);
63bd2359
JN		 958
959err_no_iores:
960err_no_pdata:
961 spi_master_put(hw->master);
962
963err_nomem:
964 return err;
965}
966
967static int __exit au1550_spi_remove(struct platform_device *pdev)
968{
969 struct au1550_spi *hw = platform_get_drvdata(pdev);
970
971 dev_info(&pdev->dev, "spi master remove: bus_num=%d\n",
972 hw->master->bus_num);
973
974 spi_bitbang_stop(&hw->bitbang);
975 free_irq(hw->irq, hw);
3a93a159
ML		 976 iounmap((void __iomem *)hw->regs);
977 release_resource(hw->ioarea);
978 kfree(hw->ioarea);
63bd2359
JN		 979
980 if (hw->usedma) {
981 au1550_spi_dma_rxtmp_free(hw);
982 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
983 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
984 }
985
986 platform_set_drvdata(pdev, NULL);
987
988 spi_master_put(hw->master);
989 return 0;
990}
991
7e38c3c4
KS		 992/* work with hotplug and coldplug */
993MODULE_ALIAS("platform:au1550-spi");
994
63bd2359
JN		 995static struct platform_driver au1550_spi_drv = {
996 .remove = __exit_p(au1550_spi_remove),
997 .driver = {
998 .name = "au1550-spi",
999 .owner = THIS_MODULE,
1000 },
1001};
1002
1003static int __init au1550_spi_init(void)
1004{
3a93a159
ML		 1005 /*
1006 * create memory device with 8 bits dev_devwidth
1007 * needed for proper byte ordering to spi fifo
1008 */
1009 if (usedma) {
1010 ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
1011 if (!ddma_memid)
1012 printk(KERN_ERR "au1550-spi: cannot add memory"
1013 "dbdma device\n");
1014 }
63bd2359
JN		 1015 return platform_driver_probe(&au1550_spi_drv, au1550_spi_probe);
1016}
1017module_init(au1550_spi_init);
1018
1019static void __exit au1550_spi_exit(void)
1020{
3a93a159
ML		 1021 if (usedma && ddma_memid)
1022 au1xxx_ddma_del_device(ddma_memid);
63bd2359
JN		 1023 platform_driver_unregister(&au1550_spi_drv);
1024}
1025module_exit(au1550_spi_exit);
1026
1027MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
1028MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
1029MODULE_LICENSE("GPL");
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