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358934a6 SP |
1 | /* |
2 | * Copyright (C) 2009 Texas Instruments. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
19 | #include <linux/interrupt.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/gpio.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/dma-mapping.h> | |
28 | #include <linux/spi/spi.h> | |
29 | #include <linux/spi/spi_bitbang.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
358934a6 SP |
31 | |
32 | #include <mach/spi.h> | |
33 | #include <mach/edma.h> | |
34 | ||
35 | #define SPI_NO_RESOURCE ((resource_size_t)-1) | |
36 | ||
37 | #define SPI_MAX_CHIPSELECT 2 | |
38 | ||
39 | #define CS_DEFAULT 0xFF | |
40 | ||
41 | #define SPI_BUFSIZ (SMP_CACHE_BYTES + 1) | |
358934a6 SP |
42 | |
43 | #define SPIFMT_PHASE_MASK BIT(16) | |
44 | #define SPIFMT_POLARITY_MASK BIT(17) | |
45 | #define SPIFMT_DISTIMER_MASK BIT(18) | |
46 | #define SPIFMT_SHIFTDIR_MASK BIT(20) | |
47 | #define SPIFMT_WAITENA_MASK BIT(21) | |
48 | #define SPIFMT_PARITYENA_MASK BIT(22) | |
49 | #define SPIFMT_ODD_PARITY_MASK BIT(23) | |
50 | #define SPIFMT_WDELAY_MASK 0x3f000000u | |
51 | #define SPIFMT_WDELAY_SHIFT 24 | |
7fe0092b | 52 | #define SPIFMT_PRESCALE_SHIFT 8 |
358934a6 | 53 | |
358934a6 SP |
54 | |
55 | /* SPIPC0 */ | |
56 | #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ | |
57 | #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ | |
58 | #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ | |
59 | #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ | |
358934a6 SP |
60 | |
61 | #define SPIINT_MASKALL 0x0101035F | |
358934a6 | 62 | |
cfbc5d1d BN |
63 | /* SPIDAT1 (upper 16 bit defines) */ |
64 | #define SPIDAT1_CSHOLD_MASK BIT(12) | |
65 | ||
66 | /* SPIGCR1 */ | |
358934a6 SP |
67 | #define SPIGCR1_CLKMOD_MASK BIT(1) |
68 | #define SPIGCR1_MASTER_MASK BIT(0) | |
69 | #define SPIGCR1_LOOPBACK_MASK BIT(16) | |
8e206f1c | 70 | #define SPIGCR1_SPIENA_MASK BIT(24) |
358934a6 SP |
71 | |
72 | /* SPIBUF */ | |
73 | #define SPIBUF_TXFULL_MASK BIT(29) | |
74 | #define SPIBUF_RXEMPTY_MASK BIT(31) | |
75 | ||
7abbf23c BN |
76 | /* SPIDELAY */ |
77 | #define SPIDELAY_C2TDELAY_SHIFT 24 | |
78 | #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) | |
79 | #define SPIDELAY_T2CDELAY_SHIFT 16 | |
80 | #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) | |
81 | #define SPIDELAY_T2EDELAY_SHIFT 8 | |
82 | #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) | |
83 | #define SPIDELAY_C2EDELAY_SHIFT 0 | |
84 | #define SPIDELAY_C2EDELAY_MASK 0xFF | |
85 | ||
358934a6 SP |
86 | /* Error Masks */ |
87 | #define SPIFLG_DLEN_ERR_MASK BIT(0) | |
88 | #define SPIFLG_TIMEOUT_MASK BIT(1) | |
89 | #define SPIFLG_PARERR_MASK BIT(2) | |
90 | #define SPIFLG_DESYNC_MASK BIT(3) | |
91 | #define SPIFLG_BITERR_MASK BIT(4) | |
92 | #define SPIFLG_OVRRUN_MASK BIT(6) | |
358934a6 | 93 | #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) |
839c996c BN |
94 | #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ |
95 | | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ | |
96 | | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ | |
97 | | SPIFLG_OVRRUN_MASK) | |
8e206f1c | 98 | |
358934a6 | 99 | #define SPIINT_DMA_REQ_EN BIT(16) |
358934a6 | 100 | |
358934a6 SP |
101 | /* SPI Controller registers */ |
102 | #define SPIGCR0 0x00 | |
103 | #define SPIGCR1 0x04 | |
104 | #define SPIINT 0x08 | |
105 | #define SPILVL 0x0c | |
106 | #define SPIFLG 0x10 | |
107 | #define SPIPC0 0x14 | |
358934a6 SP |
108 | #define SPIDAT1 0x3c |
109 | #define SPIBUF 0x40 | |
358934a6 SP |
110 | #define SPIDELAY 0x48 |
111 | #define SPIDEF 0x4c | |
112 | #define SPIFMT0 0x50 | |
358934a6 | 113 | |
358934a6 SP |
114 | /* We have 2 DMA channels per CS, one for RX and one for TX */ |
115 | struct davinci_spi_dma { | |
116 | int dma_tx_channel; | |
117 | int dma_rx_channel; | |
118 | int dma_tx_sync_dev; | |
119 | int dma_rx_sync_dev; | |
120 | enum dma_event_q eventq; | |
121 | ||
122 | struct completion dma_tx_completion; | |
123 | struct completion dma_rx_completion; | |
124 | }; | |
125 | ||
126 | /* SPI Controller driver's private data. */ | |
127 | struct davinci_spi { | |
128 | struct spi_bitbang bitbang; | |
129 | struct clk *clk; | |
130 | ||
131 | u8 version; | |
132 | resource_size_t pbase; | |
133 | void __iomem *base; | |
134 | size_t region_size; | |
358934a6 SP |
135 | |
136 | const void *tx; | |
137 | void *rx; | |
138 | u8 *tmp_buf; | |
358934a6 | 139 | struct davinci_spi_dma *dma_channels; |
778e261e | 140 | struct davinci_spi_platform_data *pdata; |
358934a6 SP |
141 | |
142 | void (*get_rx)(u32 rx_data, struct davinci_spi *); | |
143 | u32 (*get_tx)(struct davinci_spi *); | |
144 | ||
cda987eb | 145 | u8 bytes_per_word[SPI_MAX_CHIPSELECT]; |
358934a6 SP |
146 | }; |
147 | ||
53a31b07 BN |
148 | static struct davinci_spi_config davinci_spi_default_cfg; |
149 | ||
358934a6 SP |
150 | static unsigned use_dma; |
151 | ||
152 | static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi) | |
153 | { | |
53d454a1 BN |
154 | if (davinci_spi->rx) { |
155 | u8 *rx = davinci_spi->rx; | |
156 | *rx++ = (u8)data; | |
157 | davinci_spi->rx = rx; | |
158 | } | |
358934a6 SP |
159 | } |
160 | ||
161 | static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi) | |
162 | { | |
53d454a1 BN |
163 | if (davinci_spi->rx) { |
164 | u16 *rx = davinci_spi->rx; | |
165 | *rx++ = (u16)data; | |
166 | davinci_spi->rx = rx; | |
167 | } | |
358934a6 SP |
168 | } |
169 | ||
170 | static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi) | |
171 | { | |
53d454a1 BN |
172 | u32 data = 0; |
173 | if (davinci_spi->tx) { | |
174 | const u8 *tx = davinci_spi->tx; | |
175 | data = *tx++; | |
176 | davinci_spi->tx = tx; | |
177 | } | |
358934a6 SP |
178 | return data; |
179 | } | |
180 | ||
181 | static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi) | |
182 | { | |
53d454a1 BN |
183 | u32 data = 0; |
184 | if (davinci_spi->tx) { | |
185 | const u16 *tx = davinci_spi->tx; | |
186 | data = *tx++; | |
187 | davinci_spi->tx = tx; | |
188 | } | |
358934a6 SP |
189 | return data; |
190 | } | |
191 | ||
192 | static inline void set_io_bits(void __iomem *addr, u32 bits) | |
193 | { | |
194 | u32 v = ioread32(addr); | |
195 | ||
196 | v |= bits; | |
197 | iowrite32(v, addr); | |
198 | } | |
199 | ||
200 | static inline void clear_io_bits(void __iomem *addr, u32 bits) | |
201 | { | |
202 | u32 v = ioread32(addr); | |
203 | ||
204 | v &= ~bits; | |
205 | iowrite32(v, addr); | |
206 | } | |
207 | ||
358934a6 SP |
208 | static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable) |
209 | { | |
210 | struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); | |
211 | ||
212 | if (enable) | |
213 | set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); | |
214 | else | |
215 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); | |
216 | } | |
217 | ||
218 | /* | |
219 | * Interface to control the chip select signal | |
220 | */ | |
221 | static void davinci_spi_chipselect(struct spi_device *spi, int value) | |
222 | { | |
223 | struct davinci_spi *davinci_spi; | |
224 | struct davinci_spi_platform_data *pdata; | |
7978b8c3 | 225 | u8 chip_sel = spi->chip_select; |
cfbc5d1d | 226 | u16 spidat1_cfg = CS_DEFAULT; |
23853973 | 227 | bool gpio_chipsel = false; |
358934a6 SP |
228 | |
229 | davinci_spi = spi_master_get_devdata(spi->master); | |
230 | pdata = davinci_spi->pdata; | |
231 | ||
23853973 BN |
232 | if (pdata->chip_sel && chip_sel < pdata->num_chipselect && |
233 | pdata->chip_sel[chip_sel] != SPI_INTERN_CS) | |
234 | gpio_chipsel = true; | |
235 | ||
358934a6 SP |
236 | /* |
237 | * Board specific chip select logic decides the polarity and cs | |
238 | * line for the controller | |
239 | */ | |
23853973 BN |
240 | if (gpio_chipsel) { |
241 | if (value == BITBANG_CS_ACTIVE) | |
242 | gpio_set_value(pdata->chip_sel[chip_sel], 0); | |
243 | else | |
244 | gpio_set_value(pdata->chip_sel[chip_sel], 1); | |
245 | } else { | |
246 | if (value == BITBANG_CS_ACTIVE) { | |
247 | spidat1_cfg |= SPIDAT1_CSHOLD_MASK; | |
248 | spidat1_cfg &= ~(0x1 << chip_sel); | |
249 | } | |
7978b8c3 | 250 | |
23853973 BN |
251 | iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); |
252 | } | |
358934a6 SP |
253 | } |
254 | ||
7fe0092b BN |
255 | /** |
256 | * davinci_spi_get_prescale - Calculates the correct prescale value | |
257 | * @maxspeed_hz: the maximum rate the SPI clock can run at | |
258 | * | |
259 | * This function calculates the prescale value that generates a clock rate | |
260 | * less than or equal to the specified maximum. | |
261 | * | |
262 | * Returns: calculated prescale - 1 for easy programming into SPI registers | |
263 | * or negative error number if valid prescalar cannot be updated. | |
264 | */ | |
265 | static inline int davinci_spi_get_prescale(struct davinci_spi *davinci_spi, | |
266 | u32 max_speed_hz) | |
267 | { | |
268 | int ret; | |
269 | ||
270 | ret = DIV_ROUND_UP(clk_get_rate(davinci_spi->clk), max_speed_hz); | |
271 | ||
272 | if (ret < 3 || ret > 256) | |
273 | return -EINVAL; | |
274 | ||
275 | return ret - 1; | |
276 | } | |
277 | ||
358934a6 SP |
278 | /** |
279 | * davinci_spi_setup_transfer - This functions will determine transfer method | |
280 | * @spi: spi device on which data transfer to be done | |
281 | * @t: spi transfer in which transfer info is filled | |
282 | * | |
283 | * This function determines data transfer method (8/16/32 bit transfer). | |
284 | * It will also set the SPI Clock Control register according to | |
285 | * SPI slave device freq. | |
286 | */ | |
287 | static int davinci_spi_setup_transfer(struct spi_device *spi, | |
288 | struct spi_transfer *t) | |
289 | { | |
290 | ||
291 | struct davinci_spi *davinci_spi; | |
25f33512 | 292 | struct davinci_spi_config *spicfg; |
358934a6 | 293 | u8 bits_per_word = 0; |
25f33512 | 294 | u32 hz = 0, spifmt = 0, prescale = 0; |
358934a6 SP |
295 | |
296 | davinci_spi = spi_master_get_devdata(spi->master); | |
25f33512 BN |
297 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
298 | if (!spicfg) | |
299 | spicfg = &davinci_spi_default_cfg; | |
358934a6 SP |
300 | |
301 | if (t) { | |
302 | bits_per_word = t->bits_per_word; | |
303 | hz = t->speed_hz; | |
304 | } | |
305 | ||
306 | /* if bits_per_word is not set then set it default */ | |
307 | if (!bits_per_word) | |
308 | bits_per_word = spi->bits_per_word; | |
309 | ||
310 | /* | |
311 | * Assign function pointer to appropriate transfer method | |
312 | * 8bit, 16bit or 32bit transfer | |
313 | */ | |
314 | if (bits_per_word <= 8 && bits_per_word >= 2) { | |
315 | davinci_spi->get_rx = davinci_spi_rx_buf_u8; | |
316 | davinci_spi->get_tx = davinci_spi_tx_buf_u8; | |
cda987eb | 317 | davinci_spi->bytes_per_word[spi->chip_select] = 1; |
358934a6 SP |
318 | } else if (bits_per_word <= 16 && bits_per_word >= 2) { |
319 | davinci_spi->get_rx = davinci_spi_rx_buf_u16; | |
320 | davinci_spi->get_tx = davinci_spi_tx_buf_u16; | |
cda987eb | 321 | davinci_spi->bytes_per_word[spi->chip_select] = 2; |
358934a6 SP |
322 | } else |
323 | return -EINVAL; | |
324 | ||
325 | if (!hz) | |
326 | hz = spi->max_speed_hz; | |
327 | ||
25f33512 BN |
328 | /* Set up SPIFMTn register, unique to this chipselect. */ |
329 | ||
7fe0092b BN |
330 | prescale = davinci_spi_get_prescale(davinci_spi, hz); |
331 | if (prescale < 0) | |
332 | return prescale; | |
333 | ||
25f33512 BN |
334 | spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); |
335 | ||
336 | if (spi->mode & SPI_LSB_FIRST) | |
337 | spifmt |= SPIFMT_SHIFTDIR_MASK; | |
338 | ||
339 | if (spi->mode & SPI_CPOL) | |
340 | spifmt |= SPIFMT_POLARITY_MASK; | |
341 | ||
342 | if (!(spi->mode & SPI_CPHA)) | |
343 | spifmt |= SPIFMT_PHASE_MASK; | |
344 | ||
345 | /* | |
346 | * Version 1 hardware supports two basic SPI modes: | |
347 | * - Standard SPI mode uses 4 pins, with chipselect | |
348 | * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) | |
349 | * (distinct from SPI_3WIRE, with just one data wire; | |
350 | * or similar variants without MOSI or without MISO) | |
351 | * | |
352 | * Version 2 hardware supports an optional handshaking signal, | |
353 | * so it can support two more modes: | |
354 | * - 5 pin SPI variant is standard SPI plus SPI_READY | |
355 | * - 4 pin with enable is (SPI_READY | SPI_NO_CS) | |
356 | */ | |
357 | ||
358 | if (davinci_spi->version == SPI_VERSION_2) { | |
359 | ||
7abbf23c BN |
360 | u32 delay = 0; |
361 | ||
25f33512 BN |
362 | spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) |
363 | & SPIFMT_WDELAY_MASK); | |
358934a6 | 364 | |
25f33512 BN |
365 | if (spicfg->odd_parity) |
366 | spifmt |= SPIFMT_ODD_PARITY_MASK; | |
367 | ||
368 | if (spicfg->parity_enable) | |
369 | spifmt |= SPIFMT_PARITYENA_MASK; | |
370 | ||
7abbf23c | 371 | if (spicfg->timer_disable) { |
25f33512 | 372 | spifmt |= SPIFMT_DISTIMER_MASK; |
7abbf23c BN |
373 | } else { |
374 | delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) | |
375 | & SPIDELAY_C2TDELAY_MASK; | |
376 | delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) | |
377 | & SPIDELAY_T2CDELAY_MASK; | |
378 | } | |
25f33512 | 379 | |
7abbf23c | 380 | if (spi->mode & SPI_READY) { |
25f33512 | 381 | spifmt |= SPIFMT_WAITENA_MASK; |
7abbf23c BN |
382 | delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) |
383 | & SPIDELAY_T2EDELAY_MASK; | |
384 | delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) | |
385 | & SPIDELAY_C2EDELAY_MASK; | |
386 | } | |
387 | ||
388 | iowrite32(delay, davinci_spi->base + SPIDELAY); | |
25f33512 BN |
389 | } |
390 | ||
391 | iowrite32(spifmt, davinci_spi->base + SPIFMT0); | |
358934a6 SP |
392 | |
393 | return 0; | |
394 | } | |
395 | ||
396 | static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data) | |
397 | { | |
398 | struct spi_device *spi = (struct spi_device *)data; | |
399 | struct davinci_spi *davinci_spi; | |
400 | struct davinci_spi_dma *davinci_spi_dma; | |
358934a6 SP |
401 | |
402 | davinci_spi = spi_master_get_devdata(spi->master); | |
403 | davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); | |
358934a6 SP |
404 | |
405 | if (ch_status == DMA_COMPLETE) | |
406 | edma_stop(davinci_spi_dma->dma_rx_channel); | |
407 | else | |
408 | edma_clean_channel(davinci_spi_dma->dma_rx_channel); | |
409 | ||
410 | complete(&davinci_spi_dma->dma_rx_completion); | |
411 | /* We must disable the DMA RX request */ | |
412 | davinci_spi_set_dma_req(spi, 0); | |
413 | } | |
414 | ||
415 | static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data) | |
416 | { | |
417 | struct spi_device *spi = (struct spi_device *)data; | |
418 | struct davinci_spi *davinci_spi; | |
419 | struct davinci_spi_dma *davinci_spi_dma; | |
358934a6 SP |
420 | |
421 | davinci_spi = spi_master_get_devdata(spi->master); | |
422 | davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); | |
358934a6 SP |
423 | |
424 | if (ch_status == DMA_COMPLETE) | |
425 | edma_stop(davinci_spi_dma->dma_tx_channel); | |
426 | else | |
427 | edma_clean_channel(davinci_spi_dma->dma_tx_channel); | |
428 | ||
429 | complete(&davinci_spi_dma->dma_tx_completion); | |
430 | /* We must disable the DMA TX request */ | |
431 | davinci_spi_set_dma_req(spi, 0); | |
432 | } | |
433 | ||
434 | static int davinci_spi_request_dma(struct spi_device *spi) | |
435 | { | |
436 | struct davinci_spi *davinci_spi; | |
437 | struct davinci_spi_dma *davinci_spi_dma; | |
358934a6 SP |
438 | struct device *sdev; |
439 | int r; | |
440 | ||
441 | davinci_spi = spi_master_get_devdata(spi->master); | |
442 | davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; | |
358934a6 SP |
443 | sdev = davinci_spi->bitbang.master->dev.parent; |
444 | ||
445 | r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev, | |
446 | davinci_spi_dma_rx_callback, spi, | |
447 | davinci_spi_dma->eventq); | |
448 | if (r < 0) { | |
449 | dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n"); | |
450 | return -EAGAIN; | |
451 | } | |
452 | davinci_spi_dma->dma_rx_channel = r; | |
453 | r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev, | |
454 | davinci_spi_dma_tx_callback, spi, | |
455 | davinci_spi_dma->eventq); | |
456 | if (r < 0) { | |
457 | edma_free_channel(davinci_spi_dma->dma_rx_channel); | |
458 | davinci_spi_dma->dma_rx_channel = -1; | |
459 | dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n"); | |
460 | return -EAGAIN; | |
461 | } | |
462 | davinci_spi_dma->dma_tx_channel = r; | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
467 | /** | |
468 | * davinci_spi_setup - This functions will set default transfer method | |
469 | * @spi: spi device on which data transfer to be done | |
470 | * | |
471 | * This functions sets the default transfer method. | |
472 | */ | |
358934a6 SP |
473 | static int davinci_spi_setup(struct spi_device *spi) |
474 | { | |
475 | int retval; | |
476 | struct davinci_spi *davinci_spi; | |
477 | struct davinci_spi_dma *davinci_spi_dma; | |
358934a6 SP |
478 | |
479 | davinci_spi = spi_master_get_devdata(spi->master); | |
358934a6 SP |
480 | |
481 | /* if bits per word length is zero then set it default 8 */ | |
482 | if (!spi->bits_per_word) | |
483 | spi->bits_per_word = 8; | |
484 | ||
358934a6 SP |
485 | if (use_dma && davinci_spi->dma_channels) { |
486 | davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; | |
487 | ||
488 | if ((davinci_spi_dma->dma_rx_channel == -1) | |
489 | || (davinci_spi_dma->dma_tx_channel == -1)) { | |
490 | retval = davinci_spi_request_dma(spi); | |
491 | if (retval < 0) | |
492 | return retval; | |
493 | } | |
494 | } | |
495 | ||
358934a6 SP |
496 | retval = davinci_spi_setup_transfer(spi, NULL); |
497 | ||
498 | return retval; | |
499 | } | |
500 | ||
501 | static void davinci_spi_cleanup(struct spi_device *spi) | |
502 | { | |
503 | struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); | |
504 | struct davinci_spi_dma *davinci_spi_dma; | |
505 | ||
506 | davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; | |
507 | ||
508 | if (use_dma && davinci_spi->dma_channels) { | |
509 | davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; | |
510 | ||
511 | if ((davinci_spi_dma->dma_rx_channel != -1) | |
512 | && (davinci_spi_dma->dma_tx_channel != -1)) { | |
513 | edma_free_channel(davinci_spi_dma->dma_tx_channel); | |
514 | edma_free_channel(davinci_spi_dma->dma_rx_channel); | |
515 | } | |
516 | } | |
517 | } | |
518 | ||
519 | static int davinci_spi_bufs_prep(struct spi_device *spi, | |
520 | struct davinci_spi *davinci_spi) | |
521 | { | |
23853973 | 522 | struct davinci_spi_platform_data *pdata; |
358934a6 SP |
523 | int op_mode = 0; |
524 | ||
525 | /* | |
526 | * REVISIT unless devices disagree about SPI_LOOP or | |
527 | * SPI_READY (SPI_NO_CS only allows one device!), this | |
528 | * should not need to be done before each message... | |
529 | * optimize for both flags staying cleared. | |
530 | */ | |
531 | ||
532 | op_mode = SPIPC0_DIFUN_MASK | |
533 | | SPIPC0_DOFUN_MASK | |
534 | | SPIPC0_CLKFUN_MASK; | |
23853973 BN |
535 | if (!(spi->mode & SPI_NO_CS)) { |
536 | pdata = davinci_spi->pdata; | |
537 | if (!pdata->chip_sel || | |
538 | pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS) | |
539 | op_mode |= 1 << spi->chip_select; | |
540 | } | |
358934a6 SP |
541 | if (spi->mode & SPI_READY) |
542 | op_mode |= SPIPC0_SPIENA_MASK; | |
543 | ||
544 | iowrite32(op_mode, davinci_spi->base + SPIPC0); | |
545 | ||
546 | if (spi->mode & SPI_LOOP) | |
547 | set_io_bits(davinci_spi->base + SPIGCR1, | |
548 | SPIGCR1_LOOPBACK_MASK); | |
549 | else | |
550 | clear_io_bits(davinci_spi->base + SPIGCR1, | |
551 | SPIGCR1_LOOPBACK_MASK); | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
556 | static int davinci_spi_check_error(struct davinci_spi *davinci_spi, | |
557 | int int_status) | |
558 | { | |
559 | struct device *sdev = davinci_spi->bitbang.master->dev.parent; | |
560 | ||
561 | if (int_status & SPIFLG_TIMEOUT_MASK) { | |
562 | dev_dbg(sdev, "SPI Time-out Error\n"); | |
563 | return -ETIMEDOUT; | |
564 | } | |
565 | if (int_status & SPIFLG_DESYNC_MASK) { | |
566 | dev_dbg(sdev, "SPI Desynchronization Error\n"); | |
567 | return -EIO; | |
568 | } | |
569 | if (int_status & SPIFLG_BITERR_MASK) { | |
570 | dev_dbg(sdev, "SPI Bit error\n"); | |
571 | return -EIO; | |
572 | } | |
573 | ||
574 | if (davinci_spi->version == SPI_VERSION_2) { | |
575 | if (int_status & SPIFLG_DLEN_ERR_MASK) { | |
576 | dev_dbg(sdev, "SPI Data Length Error\n"); | |
577 | return -EIO; | |
578 | } | |
579 | if (int_status & SPIFLG_PARERR_MASK) { | |
580 | dev_dbg(sdev, "SPI Parity Error\n"); | |
581 | return -EIO; | |
582 | } | |
583 | if (int_status & SPIFLG_OVRRUN_MASK) { | |
584 | dev_dbg(sdev, "SPI Data Overrun error\n"); | |
585 | return -EIO; | |
586 | } | |
358934a6 SP |
587 | if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { |
588 | dev_dbg(sdev, "SPI Buffer Init Active\n"); | |
589 | return -EBUSY; | |
590 | } | |
591 | } | |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
596 | /** | |
597 | * davinci_spi_bufs - functions which will handle transfer data | |
598 | * @spi: spi device on which data transfer to be done | |
599 | * @t: spi transfer in which transfer info is filled | |
600 | * | |
601 | * This function will put data to be transferred into data register | |
602 | * of SPI controller and then wait until the completion will be marked | |
603 | * by the IRQ Handler. | |
604 | */ | |
605 | static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t) | |
606 | { | |
607 | struct davinci_spi *davinci_spi; | |
839c996c BN |
608 | int ret; |
609 | int rcount, wcount; | |
358934a6 | 610 | u32 tx_data, data1_reg_val; |
839c996c | 611 | u32 errors = 0; |
358934a6 SP |
612 | struct davinci_spi_platform_data *pdata; |
613 | ||
614 | davinci_spi = spi_master_get_devdata(spi->master); | |
615 | pdata = davinci_spi->pdata; | |
616 | ||
617 | davinci_spi->tx = t->tx_buf; | |
618 | davinci_spi->rx = t->rx_buf; | |
839c996c BN |
619 | wcount = t->len / davinci_spi->bytes_per_word[spi->chip_select]; |
620 | rcount = wcount; | |
7978b8c3 | 621 | |
358934a6 SP |
622 | ret = davinci_spi_bufs_prep(spi, davinci_spi); |
623 | if (ret) | |
624 | return ret; | |
625 | ||
839c996c BN |
626 | data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); |
627 | ||
358934a6 SP |
628 | /* Enable SPI */ |
629 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | |
630 | ||
cf90fe73 BN |
631 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); |
632 | ||
839c996c BN |
633 | /* start the transfer */ |
634 | wcount--; | |
635 | tx_data = davinci_spi->get_tx(davinci_spi); | |
636 | data1_reg_val &= 0xFFFF0000; | |
637 | data1_reg_val |= tx_data & 0xFFFF; | |
638 | iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); | |
358934a6 | 639 | |
839c996c | 640 | while (rcount > 0 || wcount > 0) { |
358934a6 | 641 | |
839c996c | 642 | u32 buf, status; |
358934a6 | 643 | |
839c996c BN |
644 | buf = ioread32(davinci_spi->base + SPIBUF); |
645 | ||
646 | if (!(buf & SPIBUF_RXEMPTY_MASK)) { | |
647 | davinci_spi->get_rx(buf & 0xFFFF, davinci_spi); | |
648 | rcount--; | |
649 | } | |
358934a6 | 650 | |
839c996c | 651 | status = ioread32(davinci_spi->base + SPIFLG); |
358934a6 | 652 | |
839c996c BN |
653 | if (unlikely(status & SPIFLG_ERROR_MASK)) { |
654 | errors = status & SPIFLG_ERROR_MASK; | |
655 | break; | |
656 | } | |
358934a6 | 657 | |
839c996c BN |
658 | if (wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { |
659 | wcount--; | |
660 | tx_data = davinci_spi->get_tx(davinci_spi); | |
661 | data1_reg_val &= ~0xFFFF; | |
662 | data1_reg_val |= 0xFFFF & tx_data; | |
663 | iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); | |
358934a6 SP |
664 | } |
665 | } | |
666 | ||
667 | /* | |
668 | * Check for bit error, desync error,parity error,timeout error and | |
669 | * receive overflow errors | |
670 | */ | |
839c996c BN |
671 | if (errors) { |
672 | ret = davinci_spi_check_error(davinci_spi, errors); | |
673 | WARN(!ret, "%s: error reported but no error found!\n", | |
674 | dev_name(&spi->dev)); | |
358934a6 | 675 | return ret; |
839c996c | 676 | } |
358934a6 | 677 | |
358934a6 SP |
678 | return t->len; |
679 | } | |
680 | ||
358934a6 SP |
681 | static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t) |
682 | { | |
683 | struct davinci_spi *davinci_spi; | |
684 | int int_status = 0; | |
685 | int count, temp_count; | |
358934a6 SP |
686 | u32 data1_reg_val; |
687 | struct davinci_spi_dma *davinci_spi_dma; | |
b7ab24a0 | 688 | int data_type, ret; |
358934a6 | 689 | unsigned long tx_reg, rx_reg; |
358934a6 SP |
690 | struct device *sdev; |
691 | ||
692 | davinci_spi = spi_master_get_devdata(spi->master); | |
358934a6 SP |
693 | sdev = davinci_spi->bitbang.master->dev.parent; |
694 | ||
695 | davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; | |
696 | ||
697 | tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1; | |
698 | rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF; | |
699 | ||
700 | davinci_spi->tx = t->tx_buf; | |
701 | davinci_spi->rx = t->rx_buf; | |
702 | ||
703 | /* convert len to words based on bits_per_word */ | |
b7ab24a0 | 704 | data_type = davinci_spi->bytes_per_word[spi->chip_select]; |
358934a6 | 705 | |
7978b8c3 BN |
706 | data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); |
707 | ||
358934a6 SP |
708 | init_completion(&davinci_spi_dma->dma_rx_completion); |
709 | init_completion(&davinci_spi_dma->dma_tx_completion); | |
710 | ||
358934a6 SP |
711 | ret = davinci_spi_bufs_prep(spi, davinci_spi); |
712 | if (ret) | |
713 | return ret; | |
714 | ||
f2bf4e84 | 715 | count = t->len / data_type; /* the number of elements */ |
358934a6 SP |
716 | |
717 | /* disable all interrupts for dma transfers */ | |
718 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); | |
358934a6 SP |
719 | /* Enable SPI */ |
720 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | |
721 | ||
358934a6 SP |
722 | if (t->tx_buf) { |
723 | t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count, | |
724 | DMA_TO_DEVICE); | |
725 | if (dma_mapping_error(&spi->dev, t->tx_dma)) { | |
726 | dev_dbg(sdev, "Unable to DMA map a %d bytes" | |
727 | " TX buffer\n", count); | |
728 | return -ENOMEM; | |
729 | } | |
730 | temp_count = count; | |
731 | } else { | |
732 | /* We need TX clocking for RX transaction */ | |
733 | t->tx_dma = dma_map_single(&spi->dev, | |
734 | (void *)davinci_spi->tmp_buf, count + 1, | |
735 | DMA_TO_DEVICE); | |
736 | if (dma_mapping_error(&spi->dev, t->tx_dma)) { | |
737 | dev_dbg(sdev, "Unable to DMA map a %d bytes" | |
738 | " TX tmp buffer\n", count); | |
739 | return -ENOMEM; | |
740 | } | |
741 | temp_count = count + 1; | |
742 | } | |
743 | ||
744 | edma_set_transfer_params(davinci_spi_dma->dma_tx_channel, | |
745 | data_type, temp_count, 1, 0, ASYNC); | |
746 | edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT); | |
747 | edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT); | |
748 | edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0); | |
749 | edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0); | |
750 | ||
751 | if (t->rx_buf) { | |
752 | /* initiate transaction */ | |
753 | iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); | |
754 | ||
755 | t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count, | |
756 | DMA_FROM_DEVICE); | |
757 | if (dma_mapping_error(&spi->dev, t->rx_dma)) { | |
758 | dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", | |
759 | count); | |
760 | if (t->tx_buf != NULL) | |
761 | dma_unmap_single(NULL, t->tx_dma, | |
762 | count, DMA_TO_DEVICE); | |
763 | return -ENOMEM; | |
764 | } | |
765 | edma_set_transfer_params(davinci_spi_dma->dma_rx_channel, | |
766 | data_type, count, 1, 0, ASYNC); | |
767 | edma_set_src(davinci_spi_dma->dma_rx_channel, | |
768 | rx_reg, INCR, W8BIT); | |
769 | edma_set_dest(davinci_spi_dma->dma_rx_channel, | |
770 | t->rx_dma, INCR, W8BIT); | |
771 | edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0); | |
772 | edma_set_dest_index(davinci_spi_dma->dma_rx_channel, | |
773 | data_type, 0); | |
774 | } | |
775 | ||
776 | if ((t->tx_buf) || (t->rx_buf)) | |
777 | edma_start(davinci_spi_dma->dma_tx_channel); | |
778 | ||
779 | if (t->rx_buf) | |
780 | edma_start(davinci_spi_dma->dma_rx_channel); | |
781 | ||
782 | if ((t->rx_buf) || (t->tx_buf)) | |
783 | davinci_spi_set_dma_req(spi, 1); | |
784 | ||
785 | if (t->tx_buf) | |
786 | wait_for_completion_interruptible( | |
787 | &davinci_spi_dma->dma_tx_completion); | |
788 | ||
789 | if (t->rx_buf) | |
790 | wait_for_completion_interruptible( | |
791 | &davinci_spi_dma->dma_rx_completion); | |
792 | ||
793 | dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE); | |
794 | ||
795 | if (t->rx_buf) | |
796 | dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE); | |
797 | ||
798 | /* | |
799 | * Check for bit error, desync error,parity error,timeout error and | |
800 | * receive overflow errors | |
801 | */ | |
802 | int_status = ioread32(davinci_spi->base + SPIFLG); | |
803 | ||
804 | ret = davinci_spi_check_error(davinci_spi, int_status); | |
805 | if (ret != 0) | |
806 | return ret; | |
807 | ||
358934a6 SP |
808 | return t->len; |
809 | } | |
810 | ||
358934a6 SP |
811 | /** |
812 | * davinci_spi_probe - probe function for SPI Master Controller | |
813 | * @pdev: platform_device structure which contains plateform specific data | |
814 | */ | |
815 | static int davinci_spi_probe(struct platform_device *pdev) | |
816 | { | |
817 | struct spi_master *master; | |
818 | struct davinci_spi *davinci_spi; | |
819 | struct davinci_spi_platform_data *pdata; | |
820 | struct resource *r, *mem; | |
821 | resource_size_t dma_rx_chan = SPI_NO_RESOURCE; | |
822 | resource_size_t dma_tx_chan = SPI_NO_RESOURCE; | |
823 | resource_size_t dma_eventq = SPI_NO_RESOURCE; | |
824 | int i = 0, ret = 0; | |
825 | ||
826 | pdata = pdev->dev.platform_data; | |
827 | if (pdata == NULL) { | |
828 | ret = -ENODEV; | |
829 | goto err; | |
830 | } | |
831 | ||
832 | master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); | |
833 | if (master == NULL) { | |
834 | ret = -ENOMEM; | |
835 | goto err; | |
836 | } | |
837 | ||
838 | dev_set_drvdata(&pdev->dev, master); | |
839 | ||
840 | davinci_spi = spi_master_get_devdata(master); | |
841 | if (davinci_spi == NULL) { | |
842 | ret = -ENOENT; | |
843 | goto free_master; | |
844 | } | |
845 | ||
846 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
847 | if (r == NULL) { | |
848 | ret = -ENOENT; | |
849 | goto free_master; | |
850 | } | |
851 | ||
852 | davinci_spi->pbase = r->start; | |
853 | davinci_spi->region_size = resource_size(r); | |
854 | davinci_spi->pdata = pdata; | |
855 | ||
856 | mem = request_mem_region(r->start, davinci_spi->region_size, | |
857 | pdev->name); | |
858 | if (mem == NULL) { | |
859 | ret = -EBUSY; | |
860 | goto free_master; | |
861 | } | |
862 | ||
50356dd7 | 863 | davinci_spi->base = ioremap(r->start, davinci_spi->region_size); |
358934a6 SP |
864 | if (davinci_spi->base == NULL) { |
865 | ret = -ENOMEM; | |
866 | goto release_region; | |
867 | } | |
868 | ||
358934a6 SP |
869 | /* Allocate tmp_buf for tx_buf */ |
870 | davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL); | |
871 | if (davinci_spi->tmp_buf == NULL) { | |
872 | ret = -ENOMEM; | |
cf90fe73 | 873 | goto unmap_io; |
358934a6 SP |
874 | } |
875 | ||
876 | davinci_spi->bitbang.master = spi_master_get(master); | |
877 | if (davinci_spi->bitbang.master == NULL) { | |
878 | ret = -ENODEV; | |
879 | goto free_tmp_buf; | |
880 | } | |
881 | ||
882 | davinci_spi->clk = clk_get(&pdev->dev, NULL); | |
883 | if (IS_ERR(davinci_spi->clk)) { | |
884 | ret = -ENODEV; | |
885 | goto put_master; | |
886 | } | |
887 | clk_enable(davinci_spi->clk); | |
888 | ||
358934a6 SP |
889 | master->bus_num = pdev->id; |
890 | master->num_chipselect = pdata->num_chipselect; | |
891 | master->setup = davinci_spi_setup; | |
892 | master->cleanup = davinci_spi_cleanup; | |
893 | ||
894 | davinci_spi->bitbang.chipselect = davinci_spi_chipselect; | |
895 | davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer; | |
896 | ||
897 | davinci_spi->version = pdata->version; | |
898 | use_dma = pdata->use_dma; | |
899 | ||
900 | davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; | |
901 | if (davinci_spi->version == SPI_VERSION_2) | |
902 | davinci_spi->bitbang.flags |= SPI_READY; | |
903 | ||
904 | if (use_dma) { | |
778e261e BN |
905 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
906 | if (r) | |
907 | dma_rx_chan = r->start; | |
908 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
909 | if (r) | |
910 | dma_tx_chan = r->start; | |
911 | r = platform_get_resource(pdev, IORESOURCE_DMA, 2); | |
912 | if (r) | |
913 | dma_eventq = r->start; | |
358934a6 SP |
914 | } |
915 | ||
916 | if (!use_dma || | |
917 | dma_rx_chan == SPI_NO_RESOURCE || | |
918 | dma_tx_chan == SPI_NO_RESOURCE || | |
919 | dma_eventq == SPI_NO_RESOURCE) { | |
920 | davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio; | |
921 | use_dma = 0; | |
922 | } else { | |
923 | davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma; | |
924 | davinci_spi->dma_channels = kzalloc(master->num_chipselect | |
925 | * sizeof(struct davinci_spi_dma), GFP_KERNEL); | |
926 | if (davinci_spi->dma_channels == NULL) { | |
927 | ret = -ENOMEM; | |
928 | goto free_clk; | |
929 | } | |
930 | ||
931 | for (i = 0; i < master->num_chipselect; i++) { | |
932 | davinci_spi->dma_channels[i].dma_rx_channel = -1; | |
933 | davinci_spi->dma_channels[i].dma_rx_sync_dev = | |
934 | dma_rx_chan; | |
935 | davinci_spi->dma_channels[i].dma_tx_channel = -1; | |
936 | davinci_spi->dma_channels[i].dma_tx_sync_dev = | |
937 | dma_tx_chan; | |
938 | davinci_spi->dma_channels[i].eventq = dma_eventq; | |
939 | } | |
940 | dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n" | |
941 | "Using RX channel = %d , TX channel = %d and " | |
942 | "event queue = %d", dma_rx_chan, dma_tx_chan, | |
943 | dma_eventq); | |
944 | } | |
945 | ||
946 | davinci_spi->get_rx = davinci_spi_rx_buf_u8; | |
947 | davinci_spi->get_tx = davinci_spi_tx_buf_u8; | |
948 | ||
358934a6 SP |
949 | /* Reset In/OUT SPI module */ |
950 | iowrite32(0, davinci_spi->base + SPIGCR0); | |
951 | udelay(100); | |
952 | iowrite32(1, davinci_spi->base + SPIGCR0); | |
953 | ||
23853973 BN |
954 | /* initialize chip selects */ |
955 | if (pdata->chip_sel) { | |
956 | for (i = 0; i < pdata->num_chipselect; i++) { | |
957 | if (pdata->chip_sel[i] != SPI_INTERN_CS) | |
958 | gpio_direction_output(pdata->chip_sel[i], 1); | |
959 | } | |
960 | } | |
961 | ||
358934a6 SP |
962 | /* Clock internal */ |
963 | if (davinci_spi->pdata->clk_internal) | |
964 | set_io_bits(davinci_spi->base + SPIGCR1, | |
965 | SPIGCR1_CLKMOD_MASK); | |
966 | else | |
967 | clear_io_bits(davinci_spi->base + SPIGCR1, | |
968 | SPIGCR1_CLKMOD_MASK); | |
969 | ||
843a713b BN |
970 | iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF); |
971 | ||
358934a6 SP |
972 | /* master mode default */ |
973 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); | |
974 | ||
358934a6 SP |
975 | ret = spi_bitbang_start(&davinci_spi->bitbang); |
976 | if (ret) | |
977 | goto free_clk; | |
978 | ||
3b740b10 | 979 | dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base); |
358934a6 | 980 | |
358934a6 SP |
981 | return ret; |
982 | ||
983 | free_clk: | |
984 | clk_disable(davinci_spi->clk); | |
985 | clk_put(davinci_spi->clk); | |
986 | put_master: | |
987 | spi_master_put(master); | |
988 | free_tmp_buf: | |
989 | kfree(davinci_spi->tmp_buf); | |
358934a6 SP |
990 | unmap_io: |
991 | iounmap(davinci_spi->base); | |
992 | release_region: | |
993 | release_mem_region(davinci_spi->pbase, davinci_spi->region_size); | |
994 | free_master: | |
995 | kfree(master); | |
996 | err: | |
997 | return ret; | |
998 | } | |
999 | ||
1000 | /** | |
1001 | * davinci_spi_remove - remove function for SPI Master Controller | |
1002 | * @pdev: platform_device structure which contains plateform specific data | |
1003 | * | |
1004 | * This function will do the reverse action of davinci_spi_probe function | |
1005 | * It will free the IRQ and SPI controller's memory region. | |
1006 | * It will also call spi_bitbang_stop to destroy the work queue which was | |
1007 | * created by spi_bitbang_start. | |
1008 | */ | |
1009 | static int __exit davinci_spi_remove(struct platform_device *pdev) | |
1010 | { | |
1011 | struct davinci_spi *davinci_spi; | |
1012 | struct spi_master *master; | |
1013 | ||
1014 | master = dev_get_drvdata(&pdev->dev); | |
1015 | davinci_spi = spi_master_get_devdata(master); | |
1016 | ||
1017 | spi_bitbang_stop(&davinci_spi->bitbang); | |
1018 | ||
1019 | clk_disable(davinci_spi->clk); | |
1020 | clk_put(davinci_spi->clk); | |
1021 | spi_master_put(master); | |
1022 | kfree(davinci_spi->tmp_buf); | |
358934a6 SP |
1023 | iounmap(davinci_spi->base); |
1024 | release_mem_region(davinci_spi->pbase, davinci_spi->region_size); | |
1025 | ||
1026 | return 0; | |
1027 | } | |
1028 | ||
1029 | static struct platform_driver davinci_spi_driver = { | |
1030 | .driver.name = "spi_davinci", | |
1031 | .remove = __exit_p(davinci_spi_remove), | |
1032 | }; | |
1033 | ||
1034 | static int __init davinci_spi_init(void) | |
1035 | { | |
1036 | return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe); | |
1037 | } | |
1038 | module_init(davinci_spi_init); | |
1039 | ||
1040 | static void __exit davinci_spi_exit(void) | |
1041 | { | |
1042 | platform_driver_unregister(&davinci_spi_driver); | |
1043 | } | |
1044 | module_exit(davinci_spi_exit); | |
1045 | ||
1046 | MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); | |
1047 | MODULE_LICENSE("GPL"); |