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358934a6 SP |
1 | /* |
2 | * Copyright (C) 2009 Texas Instruments. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
19 | #include <linux/interrupt.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/gpio.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/dma-mapping.h> | |
28 | #include <linux/spi/spi.h> | |
29 | #include <linux/spi/spi_bitbang.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
358934a6 SP |
31 | |
32 | #include <mach/spi.h> | |
33 | #include <mach/edma.h> | |
34 | ||
35 | #define SPI_NO_RESOURCE ((resource_size_t)-1) | |
36 | ||
37 | #define SPI_MAX_CHIPSELECT 2 | |
38 | ||
39 | #define CS_DEFAULT 0xFF | |
40 | ||
41 | #define SPI_BUFSIZ (SMP_CACHE_BYTES + 1) | |
358934a6 SP |
42 | |
43 | #define SPIFMT_PHASE_MASK BIT(16) | |
44 | #define SPIFMT_POLARITY_MASK BIT(17) | |
45 | #define SPIFMT_DISTIMER_MASK BIT(18) | |
46 | #define SPIFMT_SHIFTDIR_MASK BIT(20) | |
47 | #define SPIFMT_WAITENA_MASK BIT(21) | |
48 | #define SPIFMT_PARITYENA_MASK BIT(22) | |
49 | #define SPIFMT_ODD_PARITY_MASK BIT(23) | |
50 | #define SPIFMT_WDELAY_MASK 0x3f000000u | |
51 | #define SPIFMT_WDELAY_SHIFT 24 | |
7fe0092b | 52 | #define SPIFMT_PRESCALE_SHIFT 8 |
358934a6 | 53 | |
358934a6 SP |
54 | |
55 | /* SPIPC0 */ | |
56 | #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ | |
57 | #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ | |
58 | #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ | |
59 | #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ | |
358934a6 SP |
60 | |
61 | #define SPIINT_MASKALL 0x0101035F | |
e0d205e9 BN |
62 | #define SPIINT_MASKINT 0x0000015F |
63 | #define SPI_INTLVL_1 0x000001FF | |
64 | #define SPI_INTLVL_0 0x00000000 | |
358934a6 | 65 | |
cfbc5d1d BN |
66 | /* SPIDAT1 (upper 16 bit defines) */ |
67 | #define SPIDAT1_CSHOLD_MASK BIT(12) | |
68 | ||
69 | /* SPIGCR1 */ | |
358934a6 SP |
70 | #define SPIGCR1_CLKMOD_MASK BIT(1) |
71 | #define SPIGCR1_MASTER_MASK BIT(0) | |
72 | #define SPIGCR1_LOOPBACK_MASK BIT(16) | |
8e206f1c | 73 | #define SPIGCR1_SPIENA_MASK BIT(24) |
358934a6 SP |
74 | |
75 | /* SPIBUF */ | |
76 | #define SPIBUF_TXFULL_MASK BIT(29) | |
77 | #define SPIBUF_RXEMPTY_MASK BIT(31) | |
78 | ||
7abbf23c BN |
79 | /* SPIDELAY */ |
80 | #define SPIDELAY_C2TDELAY_SHIFT 24 | |
81 | #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) | |
82 | #define SPIDELAY_T2CDELAY_SHIFT 16 | |
83 | #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) | |
84 | #define SPIDELAY_T2EDELAY_SHIFT 8 | |
85 | #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) | |
86 | #define SPIDELAY_C2EDELAY_SHIFT 0 | |
87 | #define SPIDELAY_C2EDELAY_MASK 0xFF | |
88 | ||
358934a6 SP |
89 | /* Error Masks */ |
90 | #define SPIFLG_DLEN_ERR_MASK BIT(0) | |
91 | #define SPIFLG_TIMEOUT_MASK BIT(1) | |
92 | #define SPIFLG_PARERR_MASK BIT(2) | |
93 | #define SPIFLG_DESYNC_MASK BIT(3) | |
94 | #define SPIFLG_BITERR_MASK BIT(4) | |
95 | #define SPIFLG_OVRRUN_MASK BIT(6) | |
358934a6 | 96 | #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) |
839c996c BN |
97 | #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ |
98 | | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ | |
99 | | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ | |
100 | | SPIFLG_OVRRUN_MASK) | |
8e206f1c | 101 | |
358934a6 | 102 | #define SPIINT_DMA_REQ_EN BIT(16) |
358934a6 | 103 | |
358934a6 SP |
104 | /* SPI Controller registers */ |
105 | #define SPIGCR0 0x00 | |
106 | #define SPIGCR1 0x04 | |
107 | #define SPIINT 0x08 | |
108 | #define SPILVL 0x0c | |
109 | #define SPIFLG 0x10 | |
110 | #define SPIPC0 0x14 | |
358934a6 SP |
111 | #define SPIDAT1 0x3c |
112 | #define SPIBUF 0x40 | |
358934a6 SP |
113 | #define SPIDELAY 0x48 |
114 | #define SPIDEF 0x4c | |
115 | #define SPIFMT0 0x50 | |
358934a6 | 116 | |
358934a6 SP |
117 | /* We have 2 DMA channels per CS, one for RX and one for TX */ |
118 | struct davinci_spi_dma { | |
119 | int dma_tx_channel; | |
120 | int dma_rx_channel; | |
121 | int dma_tx_sync_dev; | |
122 | int dma_rx_sync_dev; | |
123 | enum dma_event_q eventq; | |
124 | ||
125 | struct completion dma_tx_completion; | |
126 | struct completion dma_rx_completion; | |
127 | }; | |
128 | ||
129 | /* SPI Controller driver's private data. */ | |
130 | struct davinci_spi { | |
131 | struct spi_bitbang bitbang; | |
132 | struct clk *clk; | |
133 | ||
134 | u8 version; | |
135 | resource_size_t pbase; | |
136 | void __iomem *base; | |
137 | size_t region_size; | |
e0d205e9 BN |
138 | u32 irq; |
139 | struct completion done; | |
358934a6 SP |
140 | |
141 | const void *tx; | |
142 | void *rx; | |
143 | u8 *tmp_buf; | |
e0d205e9 BN |
144 | int rcount; |
145 | int wcount; | |
358934a6 | 146 | struct davinci_spi_dma *dma_channels; |
778e261e | 147 | struct davinci_spi_platform_data *pdata; |
358934a6 SP |
148 | |
149 | void (*get_rx)(u32 rx_data, struct davinci_spi *); | |
150 | u32 (*get_tx)(struct davinci_spi *); | |
151 | ||
cda987eb | 152 | u8 bytes_per_word[SPI_MAX_CHIPSELECT]; |
358934a6 SP |
153 | }; |
154 | ||
53a31b07 BN |
155 | static struct davinci_spi_config davinci_spi_default_cfg; |
156 | ||
358934a6 SP |
157 | static unsigned use_dma; |
158 | ||
159 | static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi) | |
160 | { | |
53d454a1 BN |
161 | if (davinci_spi->rx) { |
162 | u8 *rx = davinci_spi->rx; | |
163 | *rx++ = (u8)data; | |
164 | davinci_spi->rx = rx; | |
165 | } | |
358934a6 SP |
166 | } |
167 | ||
168 | static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi) | |
169 | { | |
53d454a1 BN |
170 | if (davinci_spi->rx) { |
171 | u16 *rx = davinci_spi->rx; | |
172 | *rx++ = (u16)data; | |
173 | davinci_spi->rx = rx; | |
174 | } | |
358934a6 SP |
175 | } |
176 | ||
177 | static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi) | |
178 | { | |
53d454a1 BN |
179 | u32 data = 0; |
180 | if (davinci_spi->tx) { | |
181 | const u8 *tx = davinci_spi->tx; | |
182 | data = *tx++; | |
183 | davinci_spi->tx = tx; | |
184 | } | |
358934a6 SP |
185 | return data; |
186 | } | |
187 | ||
188 | static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi) | |
189 | { | |
53d454a1 BN |
190 | u32 data = 0; |
191 | if (davinci_spi->tx) { | |
192 | const u16 *tx = davinci_spi->tx; | |
193 | data = *tx++; | |
194 | davinci_spi->tx = tx; | |
195 | } | |
358934a6 SP |
196 | return data; |
197 | } | |
198 | ||
199 | static inline void set_io_bits(void __iomem *addr, u32 bits) | |
200 | { | |
201 | u32 v = ioread32(addr); | |
202 | ||
203 | v |= bits; | |
204 | iowrite32(v, addr); | |
205 | } | |
206 | ||
207 | static inline void clear_io_bits(void __iomem *addr, u32 bits) | |
208 | { | |
209 | u32 v = ioread32(addr); | |
210 | ||
211 | v &= ~bits; | |
212 | iowrite32(v, addr); | |
213 | } | |
214 | ||
358934a6 SP |
215 | static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable) |
216 | { | |
217 | struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); | |
218 | ||
219 | if (enable) | |
220 | set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); | |
221 | else | |
222 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); | |
223 | } | |
224 | ||
225 | /* | |
226 | * Interface to control the chip select signal | |
227 | */ | |
228 | static void davinci_spi_chipselect(struct spi_device *spi, int value) | |
229 | { | |
230 | struct davinci_spi *davinci_spi; | |
231 | struct davinci_spi_platform_data *pdata; | |
7978b8c3 | 232 | u8 chip_sel = spi->chip_select; |
cfbc5d1d | 233 | u16 spidat1_cfg = CS_DEFAULT; |
23853973 | 234 | bool gpio_chipsel = false; |
358934a6 SP |
235 | |
236 | davinci_spi = spi_master_get_devdata(spi->master); | |
237 | pdata = davinci_spi->pdata; | |
238 | ||
23853973 BN |
239 | if (pdata->chip_sel && chip_sel < pdata->num_chipselect && |
240 | pdata->chip_sel[chip_sel] != SPI_INTERN_CS) | |
241 | gpio_chipsel = true; | |
242 | ||
358934a6 SP |
243 | /* |
244 | * Board specific chip select logic decides the polarity and cs | |
245 | * line for the controller | |
246 | */ | |
23853973 BN |
247 | if (gpio_chipsel) { |
248 | if (value == BITBANG_CS_ACTIVE) | |
249 | gpio_set_value(pdata->chip_sel[chip_sel], 0); | |
250 | else | |
251 | gpio_set_value(pdata->chip_sel[chip_sel], 1); | |
252 | } else { | |
253 | if (value == BITBANG_CS_ACTIVE) { | |
254 | spidat1_cfg |= SPIDAT1_CSHOLD_MASK; | |
255 | spidat1_cfg &= ~(0x1 << chip_sel); | |
256 | } | |
7978b8c3 | 257 | |
23853973 BN |
258 | iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); |
259 | } | |
358934a6 SP |
260 | } |
261 | ||
7fe0092b BN |
262 | /** |
263 | * davinci_spi_get_prescale - Calculates the correct prescale value | |
264 | * @maxspeed_hz: the maximum rate the SPI clock can run at | |
265 | * | |
266 | * This function calculates the prescale value that generates a clock rate | |
267 | * less than or equal to the specified maximum. | |
268 | * | |
269 | * Returns: calculated prescale - 1 for easy programming into SPI registers | |
270 | * or negative error number if valid prescalar cannot be updated. | |
271 | */ | |
272 | static inline int davinci_spi_get_prescale(struct davinci_spi *davinci_spi, | |
273 | u32 max_speed_hz) | |
274 | { | |
275 | int ret; | |
276 | ||
277 | ret = DIV_ROUND_UP(clk_get_rate(davinci_spi->clk), max_speed_hz); | |
278 | ||
279 | if (ret < 3 || ret > 256) | |
280 | return -EINVAL; | |
281 | ||
282 | return ret - 1; | |
283 | } | |
284 | ||
358934a6 SP |
285 | /** |
286 | * davinci_spi_setup_transfer - This functions will determine transfer method | |
287 | * @spi: spi device on which data transfer to be done | |
288 | * @t: spi transfer in which transfer info is filled | |
289 | * | |
290 | * This function determines data transfer method (8/16/32 bit transfer). | |
291 | * It will also set the SPI Clock Control register according to | |
292 | * SPI slave device freq. | |
293 | */ | |
294 | static int davinci_spi_setup_transfer(struct spi_device *spi, | |
295 | struct spi_transfer *t) | |
296 | { | |
297 | ||
298 | struct davinci_spi *davinci_spi; | |
25f33512 | 299 | struct davinci_spi_config *spicfg; |
358934a6 | 300 | u8 bits_per_word = 0; |
25f33512 | 301 | u32 hz = 0, spifmt = 0, prescale = 0; |
358934a6 SP |
302 | |
303 | davinci_spi = spi_master_get_devdata(spi->master); | |
25f33512 BN |
304 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
305 | if (!spicfg) | |
306 | spicfg = &davinci_spi_default_cfg; | |
358934a6 SP |
307 | |
308 | if (t) { | |
309 | bits_per_word = t->bits_per_word; | |
310 | hz = t->speed_hz; | |
311 | } | |
312 | ||
313 | /* if bits_per_word is not set then set it default */ | |
314 | if (!bits_per_word) | |
315 | bits_per_word = spi->bits_per_word; | |
316 | ||
317 | /* | |
318 | * Assign function pointer to appropriate transfer method | |
319 | * 8bit, 16bit or 32bit transfer | |
320 | */ | |
321 | if (bits_per_word <= 8 && bits_per_word >= 2) { | |
322 | davinci_spi->get_rx = davinci_spi_rx_buf_u8; | |
323 | davinci_spi->get_tx = davinci_spi_tx_buf_u8; | |
cda987eb | 324 | davinci_spi->bytes_per_word[spi->chip_select] = 1; |
358934a6 SP |
325 | } else if (bits_per_word <= 16 && bits_per_word >= 2) { |
326 | davinci_spi->get_rx = davinci_spi_rx_buf_u16; | |
327 | davinci_spi->get_tx = davinci_spi_tx_buf_u16; | |
cda987eb | 328 | davinci_spi->bytes_per_word[spi->chip_select] = 2; |
358934a6 SP |
329 | } else |
330 | return -EINVAL; | |
331 | ||
332 | if (!hz) | |
333 | hz = spi->max_speed_hz; | |
334 | ||
25f33512 BN |
335 | /* Set up SPIFMTn register, unique to this chipselect. */ |
336 | ||
7fe0092b BN |
337 | prescale = davinci_spi_get_prescale(davinci_spi, hz); |
338 | if (prescale < 0) | |
339 | return prescale; | |
340 | ||
25f33512 BN |
341 | spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); |
342 | ||
343 | if (spi->mode & SPI_LSB_FIRST) | |
344 | spifmt |= SPIFMT_SHIFTDIR_MASK; | |
345 | ||
346 | if (spi->mode & SPI_CPOL) | |
347 | spifmt |= SPIFMT_POLARITY_MASK; | |
348 | ||
349 | if (!(spi->mode & SPI_CPHA)) | |
350 | spifmt |= SPIFMT_PHASE_MASK; | |
351 | ||
352 | /* | |
353 | * Version 1 hardware supports two basic SPI modes: | |
354 | * - Standard SPI mode uses 4 pins, with chipselect | |
355 | * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) | |
356 | * (distinct from SPI_3WIRE, with just one data wire; | |
357 | * or similar variants without MOSI or without MISO) | |
358 | * | |
359 | * Version 2 hardware supports an optional handshaking signal, | |
360 | * so it can support two more modes: | |
361 | * - 5 pin SPI variant is standard SPI plus SPI_READY | |
362 | * - 4 pin with enable is (SPI_READY | SPI_NO_CS) | |
363 | */ | |
364 | ||
365 | if (davinci_spi->version == SPI_VERSION_2) { | |
366 | ||
7abbf23c BN |
367 | u32 delay = 0; |
368 | ||
25f33512 BN |
369 | spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) |
370 | & SPIFMT_WDELAY_MASK); | |
358934a6 | 371 | |
25f33512 BN |
372 | if (spicfg->odd_parity) |
373 | spifmt |= SPIFMT_ODD_PARITY_MASK; | |
374 | ||
375 | if (spicfg->parity_enable) | |
376 | spifmt |= SPIFMT_PARITYENA_MASK; | |
377 | ||
7abbf23c | 378 | if (spicfg->timer_disable) { |
25f33512 | 379 | spifmt |= SPIFMT_DISTIMER_MASK; |
7abbf23c BN |
380 | } else { |
381 | delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) | |
382 | & SPIDELAY_C2TDELAY_MASK; | |
383 | delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) | |
384 | & SPIDELAY_T2CDELAY_MASK; | |
385 | } | |
25f33512 | 386 | |
7abbf23c | 387 | if (spi->mode & SPI_READY) { |
25f33512 | 388 | spifmt |= SPIFMT_WAITENA_MASK; |
7abbf23c BN |
389 | delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) |
390 | & SPIDELAY_T2EDELAY_MASK; | |
391 | delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) | |
392 | & SPIDELAY_C2EDELAY_MASK; | |
393 | } | |
394 | ||
395 | iowrite32(delay, davinci_spi->base + SPIDELAY); | |
25f33512 BN |
396 | } |
397 | ||
398 | iowrite32(spifmt, davinci_spi->base + SPIFMT0); | |
358934a6 SP |
399 | |
400 | return 0; | |
401 | } | |
402 | ||
403 | static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data) | |
404 | { | |
405 | struct spi_device *spi = (struct spi_device *)data; | |
406 | struct davinci_spi *davinci_spi; | |
407 | struct davinci_spi_dma *davinci_spi_dma; | |
358934a6 SP |
408 | |
409 | davinci_spi = spi_master_get_devdata(spi->master); | |
410 | davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); | |
358934a6 SP |
411 | |
412 | if (ch_status == DMA_COMPLETE) | |
413 | edma_stop(davinci_spi_dma->dma_rx_channel); | |
414 | else | |
415 | edma_clean_channel(davinci_spi_dma->dma_rx_channel); | |
416 | ||
417 | complete(&davinci_spi_dma->dma_rx_completion); | |
418 | /* We must disable the DMA RX request */ | |
419 | davinci_spi_set_dma_req(spi, 0); | |
420 | } | |
421 | ||
422 | static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data) | |
423 | { | |
424 | struct spi_device *spi = (struct spi_device *)data; | |
425 | struct davinci_spi *davinci_spi; | |
426 | struct davinci_spi_dma *davinci_spi_dma; | |
358934a6 SP |
427 | |
428 | davinci_spi = spi_master_get_devdata(spi->master); | |
429 | davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); | |
358934a6 SP |
430 | |
431 | if (ch_status == DMA_COMPLETE) | |
432 | edma_stop(davinci_spi_dma->dma_tx_channel); | |
433 | else | |
434 | edma_clean_channel(davinci_spi_dma->dma_tx_channel); | |
435 | ||
436 | complete(&davinci_spi_dma->dma_tx_completion); | |
437 | /* We must disable the DMA TX request */ | |
438 | davinci_spi_set_dma_req(spi, 0); | |
439 | } | |
440 | ||
441 | static int davinci_spi_request_dma(struct spi_device *spi) | |
442 | { | |
443 | struct davinci_spi *davinci_spi; | |
444 | struct davinci_spi_dma *davinci_spi_dma; | |
358934a6 SP |
445 | struct device *sdev; |
446 | int r; | |
447 | ||
448 | davinci_spi = spi_master_get_devdata(spi->master); | |
449 | davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; | |
358934a6 SP |
450 | sdev = davinci_spi->bitbang.master->dev.parent; |
451 | ||
452 | r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev, | |
453 | davinci_spi_dma_rx_callback, spi, | |
454 | davinci_spi_dma->eventq); | |
455 | if (r < 0) { | |
456 | dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n"); | |
457 | return -EAGAIN; | |
458 | } | |
459 | davinci_spi_dma->dma_rx_channel = r; | |
460 | r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev, | |
461 | davinci_spi_dma_tx_callback, spi, | |
462 | davinci_spi_dma->eventq); | |
463 | if (r < 0) { | |
464 | edma_free_channel(davinci_spi_dma->dma_rx_channel); | |
465 | davinci_spi_dma->dma_rx_channel = -1; | |
466 | dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n"); | |
467 | return -EAGAIN; | |
468 | } | |
469 | davinci_spi_dma->dma_tx_channel = r; | |
470 | ||
471 | return 0; | |
472 | } | |
473 | ||
474 | /** | |
475 | * davinci_spi_setup - This functions will set default transfer method | |
476 | * @spi: spi device on which data transfer to be done | |
477 | * | |
478 | * This functions sets the default transfer method. | |
479 | */ | |
358934a6 SP |
480 | static int davinci_spi_setup(struct spi_device *spi) |
481 | { | |
b23a5d46 | 482 | int retval = 0; |
358934a6 SP |
483 | struct davinci_spi *davinci_spi; |
484 | struct davinci_spi_dma *davinci_spi_dma; | |
be88471b | 485 | struct davinci_spi_platform_data *pdata; |
358934a6 SP |
486 | |
487 | davinci_spi = spi_master_get_devdata(spi->master); | |
be88471b | 488 | pdata = davinci_spi->pdata; |
358934a6 SP |
489 | |
490 | /* if bits per word length is zero then set it default 8 */ | |
491 | if (!spi->bits_per_word) | |
492 | spi->bits_per_word = 8; | |
493 | ||
be88471b BN |
494 | if (!(spi->mode & SPI_NO_CS)) { |
495 | if ((pdata->chip_sel == NULL) || | |
496 | (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) | |
497 | set_io_bits(davinci_spi->base + SPIPC0, | |
498 | 1 << spi->chip_select); | |
499 | ||
500 | } | |
501 | ||
502 | if (spi->mode & SPI_READY) | |
503 | set_io_bits(davinci_spi->base + SPIPC0, SPIPC0_SPIENA_MASK); | |
504 | ||
505 | if (spi->mode & SPI_LOOP) | |
506 | set_io_bits(davinci_spi->base + SPIGCR1, | |
507 | SPIGCR1_LOOPBACK_MASK); | |
508 | else | |
509 | clear_io_bits(davinci_spi->base + SPIGCR1, | |
510 | SPIGCR1_LOOPBACK_MASK); | |
511 | ||
358934a6 SP |
512 | if (use_dma && davinci_spi->dma_channels) { |
513 | davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; | |
514 | ||
b23a5d46 BN |
515 | if ((davinci_spi_dma->dma_rx_channel == -1) || |
516 | (davinci_spi_dma->dma_tx_channel == -1)) | |
358934a6 | 517 | retval = davinci_spi_request_dma(spi); |
358934a6 SP |
518 | } |
519 | ||
358934a6 SP |
520 | return retval; |
521 | } | |
522 | ||
523 | static void davinci_spi_cleanup(struct spi_device *spi) | |
524 | { | |
525 | struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); | |
526 | struct davinci_spi_dma *davinci_spi_dma; | |
527 | ||
528 | davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; | |
529 | ||
530 | if (use_dma && davinci_spi->dma_channels) { | |
531 | davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; | |
532 | ||
533 | if ((davinci_spi_dma->dma_rx_channel != -1) | |
534 | && (davinci_spi_dma->dma_tx_channel != -1)) { | |
535 | edma_free_channel(davinci_spi_dma->dma_tx_channel); | |
536 | edma_free_channel(davinci_spi_dma->dma_rx_channel); | |
537 | } | |
538 | } | |
539 | } | |
540 | ||
358934a6 SP |
541 | static int davinci_spi_check_error(struct davinci_spi *davinci_spi, |
542 | int int_status) | |
543 | { | |
544 | struct device *sdev = davinci_spi->bitbang.master->dev.parent; | |
545 | ||
546 | if (int_status & SPIFLG_TIMEOUT_MASK) { | |
547 | dev_dbg(sdev, "SPI Time-out Error\n"); | |
548 | return -ETIMEDOUT; | |
549 | } | |
550 | if (int_status & SPIFLG_DESYNC_MASK) { | |
551 | dev_dbg(sdev, "SPI Desynchronization Error\n"); | |
552 | return -EIO; | |
553 | } | |
554 | if (int_status & SPIFLG_BITERR_MASK) { | |
555 | dev_dbg(sdev, "SPI Bit error\n"); | |
556 | return -EIO; | |
557 | } | |
558 | ||
559 | if (davinci_spi->version == SPI_VERSION_2) { | |
560 | if (int_status & SPIFLG_DLEN_ERR_MASK) { | |
561 | dev_dbg(sdev, "SPI Data Length Error\n"); | |
562 | return -EIO; | |
563 | } | |
564 | if (int_status & SPIFLG_PARERR_MASK) { | |
565 | dev_dbg(sdev, "SPI Parity Error\n"); | |
566 | return -EIO; | |
567 | } | |
568 | if (int_status & SPIFLG_OVRRUN_MASK) { | |
569 | dev_dbg(sdev, "SPI Data Overrun error\n"); | |
570 | return -EIO; | |
571 | } | |
358934a6 SP |
572 | if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { |
573 | dev_dbg(sdev, "SPI Buffer Init Active\n"); | |
574 | return -EBUSY; | |
575 | } | |
576 | } | |
577 | ||
578 | return 0; | |
579 | } | |
580 | ||
e0d205e9 BN |
581 | /** |
582 | * davinci_spi_process_events - check for and handle any SPI controller events | |
583 | * @davinci_spi: the controller data | |
584 | * | |
585 | * This function will check the SPIFLG register and handle any events that are | |
586 | * detected there | |
587 | */ | |
588 | static int davinci_spi_process_events(struct davinci_spi *davinci_spi) | |
589 | { | |
590 | u32 buf, status, errors = 0, data1_reg_val; | |
591 | ||
592 | buf = ioread32(davinci_spi->base + SPIBUF); | |
593 | ||
594 | if (davinci_spi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { | |
595 | davinci_spi->get_rx(buf & 0xFFFF, davinci_spi); | |
596 | davinci_spi->rcount--; | |
597 | } | |
598 | ||
599 | status = ioread32(davinci_spi->base + SPIFLG); | |
600 | ||
601 | if (unlikely(status & SPIFLG_ERROR_MASK)) { | |
602 | errors = status & SPIFLG_ERROR_MASK; | |
603 | goto out; | |
604 | } | |
605 | ||
606 | if (davinci_spi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { | |
607 | data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); | |
608 | davinci_spi->wcount--; | |
609 | data1_reg_val &= ~0xFFFF; | |
610 | data1_reg_val |= 0xFFFF & davinci_spi->get_tx(davinci_spi); | |
611 | iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); | |
612 | } | |
613 | ||
614 | out: | |
615 | return errors; | |
616 | } | |
617 | ||
358934a6 SP |
618 | /** |
619 | * davinci_spi_bufs - functions which will handle transfer data | |
620 | * @spi: spi device on which data transfer to be done | |
621 | * @t: spi transfer in which transfer info is filled | |
622 | * | |
623 | * This function will put data to be transferred into data register | |
624 | * of SPI controller and then wait until the completion will be marked | |
625 | * by the IRQ Handler. | |
626 | */ | |
627 | static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t) | |
628 | { | |
629 | struct davinci_spi *davinci_spi; | |
839c996c | 630 | int ret; |
358934a6 | 631 | u32 tx_data, data1_reg_val; |
839c996c | 632 | u32 errors = 0; |
e0d205e9 | 633 | struct davinci_spi_config *spicfg; |
358934a6 SP |
634 | struct davinci_spi_platform_data *pdata; |
635 | ||
636 | davinci_spi = spi_master_get_devdata(spi->master); | |
637 | pdata = davinci_spi->pdata; | |
e0d205e9 BN |
638 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
639 | if (!spicfg) | |
640 | spicfg = &davinci_spi_default_cfg; | |
358934a6 SP |
641 | |
642 | davinci_spi->tx = t->tx_buf; | |
643 | davinci_spi->rx = t->rx_buf; | |
e0d205e9 BN |
644 | davinci_spi->wcount = t->len / |
645 | davinci_spi->bytes_per_word[spi->chip_select]; | |
646 | davinci_spi->rcount = davinci_spi->wcount; | |
7978b8c3 | 647 | |
839c996c BN |
648 | data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); |
649 | ||
358934a6 SP |
650 | /* Enable SPI */ |
651 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | |
652 | ||
e0d205e9 BN |
653 | if (spicfg->io_type == SPI_IO_TYPE_INTR) { |
654 | set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); | |
655 | INIT_COMPLETION(davinci_spi->done); | |
656 | } | |
cf90fe73 | 657 | |
839c996c | 658 | /* start the transfer */ |
e0d205e9 | 659 | davinci_spi->wcount--; |
839c996c BN |
660 | tx_data = davinci_spi->get_tx(davinci_spi); |
661 | data1_reg_val &= 0xFFFF0000; | |
662 | data1_reg_val |= tx_data & 0xFFFF; | |
663 | iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); | |
358934a6 | 664 | |
e0d205e9 BN |
665 | /* Wait for the transfer to complete */ |
666 | if (spicfg->io_type == SPI_IO_TYPE_INTR) { | |
667 | wait_for_completion_interruptible(&(davinci_spi->done)); | |
668 | } else { | |
669 | while (davinci_spi->rcount > 0 || davinci_spi->wcount > 0) { | |
670 | errors = davinci_spi_process_events(davinci_spi); | |
671 | if (errors) | |
672 | break; | |
673 | cpu_relax(); | |
358934a6 SP |
674 | } |
675 | } | |
676 | ||
e0d205e9 BN |
677 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); |
678 | ||
358934a6 SP |
679 | /* |
680 | * Check for bit error, desync error,parity error,timeout error and | |
681 | * receive overflow errors | |
682 | */ | |
839c996c BN |
683 | if (errors) { |
684 | ret = davinci_spi_check_error(davinci_spi, errors); | |
685 | WARN(!ret, "%s: error reported but no error found!\n", | |
686 | dev_name(&spi->dev)); | |
358934a6 | 687 | return ret; |
839c996c | 688 | } |
358934a6 | 689 | |
358934a6 SP |
690 | return t->len; |
691 | } | |
692 | ||
e0d205e9 BN |
693 | /** |
694 | * davinci_spi_irq - Interrupt handler for SPI Master Controller | |
695 | * @irq: IRQ number for this SPI Master | |
696 | * @context_data: structure for SPI Master controller davinci_spi | |
697 | * | |
698 | * ISR will determine that interrupt arrives either for READ or WRITE command. | |
699 | * According to command it will do the appropriate action. It will check | |
700 | * transfer length and if it is not zero then dispatch transfer command again. | |
701 | * If transfer length is zero then it will indicate the COMPLETION so that | |
702 | * davinci_spi_bufs function can go ahead. | |
703 | */ | |
704 | static irqreturn_t davinci_spi_irq(s32 irq, void *context_data) | |
705 | { | |
706 | struct davinci_spi *davinci_spi = context_data; | |
707 | int status; | |
708 | ||
709 | status = davinci_spi_process_events(davinci_spi); | |
710 | if (unlikely(status != 0)) | |
711 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); | |
712 | ||
713 | if ((!davinci_spi->rcount && !davinci_spi->wcount) || status) | |
714 | complete(&davinci_spi->done); | |
715 | ||
716 | return IRQ_HANDLED; | |
717 | } | |
718 | ||
358934a6 SP |
719 | static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t) |
720 | { | |
721 | struct davinci_spi *davinci_spi; | |
722 | int int_status = 0; | |
723 | int count, temp_count; | |
358934a6 SP |
724 | u32 data1_reg_val; |
725 | struct davinci_spi_dma *davinci_spi_dma; | |
b7ab24a0 | 726 | int data_type, ret; |
358934a6 | 727 | unsigned long tx_reg, rx_reg; |
358934a6 SP |
728 | struct device *sdev; |
729 | ||
730 | davinci_spi = spi_master_get_devdata(spi->master); | |
358934a6 SP |
731 | sdev = davinci_spi->bitbang.master->dev.parent; |
732 | ||
733 | davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; | |
734 | ||
735 | tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1; | |
736 | rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF; | |
737 | ||
738 | davinci_spi->tx = t->tx_buf; | |
739 | davinci_spi->rx = t->rx_buf; | |
740 | ||
741 | /* convert len to words based on bits_per_word */ | |
b7ab24a0 | 742 | data_type = davinci_spi->bytes_per_word[spi->chip_select]; |
358934a6 | 743 | |
7978b8c3 BN |
744 | data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); |
745 | ||
358934a6 SP |
746 | init_completion(&davinci_spi_dma->dma_rx_completion); |
747 | init_completion(&davinci_spi_dma->dma_tx_completion); | |
748 | ||
f2bf4e84 | 749 | count = t->len / data_type; /* the number of elements */ |
358934a6 SP |
750 | |
751 | /* disable all interrupts for dma transfers */ | |
752 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); | |
358934a6 SP |
753 | /* Enable SPI */ |
754 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | |
755 | ||
358934a6 SP |
756 | if (t->tx_buf) { |
757 | t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count, | |
758 | DMA_TO_DEVICE); | |
759 | if (dma_mapping_error(&spi->dev, t->tx_dma)) { | |
760 | dev_dbg(sdev, "Unable to DMA map a %d bytes" | |
761 | " TX buffer\n", count); | |
762 | return -ENOMEM; | |
763 | } | |
764 | temp_count = count; | |
765 | } else { | |
766 | /* We need TX clocking for RX transaction */ | |
767 | t->tx_dma = dma_map_single(&spi->dev, | |
768 | (void *)davinci_spi->tmp_buf, count + 1, | |
769 | DMA_TO_DEVICE); | |
770 | if (dma_mapping_error(&spi->dev, t->tx_dma)) { | |
771 | dev_dbg(sdev, "Unable to DMA map a %d bytes" | |
772 | " TX tmp buffer\n", count); | |
773 | return -ENOMEM; | |
774 | } | |
775 | temp_count = count + 1; | |
776 | } | |
777 | ||
778 | edma_set_transfer_params(davinci_spi_dma->dma_tx_channel, | |
779 | data_type, temp_count, 1, 0, ASYNC); | |
780 | edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT); | |
781 | edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT); | |
782 | edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0); | |
783 | edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0); | |
784 | ||
785 | if (t->rx_buf) { | |
786 | /* initiate transaction */ | |
787 | iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); | |
788 | ||
789 | t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count, | |
790 | DMA_FROM_DEVICE); | |
791 | if (dma_mapping_error(&spi->dev, t->rx_dma)) { | |
792 | dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", | |
793 | count); | |
794 | if (t->tx_buf != NULL) | |
795 | dma_unmap_single(NULL, t->tx_dma, | |
796 | count, DMA_TO_DEVICE); | |
797 | return -ENOMEM; | |
798 | } | |
799 | edma_set_transfer_params(davinci_spi_dma->dma_rx_channel, | |
800 | data_type, count, 1, 0, ASYNC); | |
801 | edma_set_src(davinci_spi_dma->dma_rx_channel, | |
802 | rx_reg, INCR, W8BIT); | |
803 | edma_set_dest(davinci_spi_dma->dma_rx_channel, | |
804 | t->rx_dma, INCR, W8BIT); | |
805 | edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0); | |
806 | edma_set_dest_index(davinci_spi_dma->dma_rx_channel, | |
807 | data_type, 0); | |
808 | } | |
809 | ||
810 | if ((t->tx_buf) || (t->rx_buf)) | |
811 | edma_start(davinci_spi_dma->dma_tx_channel); | |
812 | ||
813 | if (t->rx_buf) | |
814 | edma_start(davinci_spi_dma->dma_rx_channel); | |
815 | ||
816 | if ((t->rx_buf) || (t->tx_buf)) | |
817 | davinci_spi_set_dma_req(spi, 1); | |
818 | ||
819 | if (t->tx_buf) | |
820 | wait_for_completion_interruptible( | |
821 | &davinci_spi_dma->dma_tx_completion); | |
822 | ||
823 | if (t->rx_buf) | |
824 | wait_for_completion_interruptible( | |
825 | &davinci_spi_dma->dma_rx_completion); | |
826 | ||
827 | dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE); | |
828 | ||
829 | if (t->rx_buf) | |
830 | dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE); | |
831 | ||
832 | /* | |
833 | * Check for bit error, desync error,parity error,timeout error and | |
834 | * receive overflow errors | |
835 | */ | |
836 | int_status = ioread32(davinci_spi->base + SPIFLG); | |
837 | ||
838 | ret = davinci_spi_check_error(davinci_spi, int_status); | |
839 | if (ret != 0) | |
840 | return ret; | |
841 | ||
358934a6 SP |
842 | return t->len; |
843 | } | |
844 | ||
358934a6 SP |
845 | /** |
846 | * davinci_spi_probe - probe function for SPI Master Controller | |
847 | * @pdev: platform_device structure which contains plateform specific data | |
848 | */ | |
849 | static int davinci_spi_probe(struct platform_device *pdev) | |
850 | { | |
851 | struct spi_master *master; | |
852 | struct davinci_spi *davinci_spi; | |
853 | struct davinci_spi_platform_data *pdata; | |
854 | struct resource *r, *mem; | |
855 | resource_size_t dma_rx_chan = SPI_NO_RESOURCE; | |
856 | resource_size_t dma_tx_chan = SPI_NO_RESOURCE; | |
857 | resource_size_t dma_eventq = SPI_NO_RESOURCE; | |
858 | int i = 0, ret = 0; | |
f34bd4cc | 859 | u32 spipc0; |
358934a6 SP |
860 | |
861 | pdata = pdev->dev.platform_data; | |
862 | if (pdata == NULL) { | |
863 | ret = -ENODEV; | |
864 | goto err; | |
865 | } | |
866 | ||
867 | master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); | |
868 | if (master == NULL) { | |
869 | ret = -ENOMEM; | |
870 | goto err; | |
871 | } | |
872 | ||
873 | dev_set_drvdata(&pdev->dev, master); | |
874 | ||
875 | davinci_spi = spi_master_get_devdata(master); | |
876 | if (davinci_spi == NULL) { | |
877 | ret = -ENOENT; | |
878 | goto free_master; | |
879 | } | |
880 | ||
881 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
882 | if (r == NULL) { | |
883 | ret = -ENOENT; | |
884 | goto free_master; | |
885 | } | |
886 | ||
887 | davinci_spi->pbase = r->start; | |
888 | davinci_spi->region_size = resource_size(r); | |
889 | davinci_spi->pdata = pdata; | |
890 | ||
891 | mem = request_mem_region(r->start, davinci_spi->region_size, | |
892 | pdev->name); | |
893 | if (mem == NULL) { | |
894 | ret = -EBUSY; | |
895 | goto free_master; | |
896 | } | |
897 | ||
50356dd7 | 898 | davinci_spi->base = ioremap(r->start, davinci_spi->region_size); |
358934a6 SP |
899 | if (davinci_spi->base == NULL) { |
900 | ret = -ENOMEM; | |
901 | goto release_region; | |
902 | } | |
903 | ||
e0d205e9 BN |
904 | davinci_spi->irq = platform_get_irq(pdev, 0); |
905 | if (davinci_spi->irq <= 0) { | |
906 | ret = -EINVAL; | |
907 | goto unmap_io; | |
908 | } | |
909 | ||
910 | ret = request_irq(davinci_spi->irq, davinci_spi_irq, 0, | |
911 | dev_name(&pdev->dev), davinci_spi); | |
912 | if (ret) | |
913 | goto unmap_io; | |
914 | ||
358934a6 SP |
915 | /* Allocate tmp_buf for tx_buf */ |
916 | davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL); | |
917 | if (davinci_spi->tmp_buf == NULL) { | |
918 | ret = -ENOMEM; | |
e0d205e9 | 919 | goto irq_free; |
358934a6 SP |
920 | } |
921 | ||
922 | davinci_spi->bitbang.master = spi_master_get(master); | |
923 | if (davinci_spi->bitbang.master == NULL) { | |
924 | ret = -ENODEV; | |
925 | goto free_tmp_buf; | |
926 | } | |
927 | ||
928 | davinci_spi->clk = clk_get(&pdev->dev, NULL); | |
929 | if (IS_ERR(davinci_spi->clk)) { | |
930 | ret = -ENODEV; | |
931 | goto put_master; | |
932 | } | |
933 | clk_enable(davinci_spi->clk); | |
934 | ||
358934a6 SP |
935 | master->bus_num = pdev->id; |
936 | master->num_chipselect = pdata->num_chipselect; | |
937 | master->setup = davinci_spi_setup; | |
938 | master->cleanup = davinci_spi_cleanup; | |
939 | ||
940 | davinci_spi->bitbang.chipselect = davinci_spi_chipselect; | |
941 | davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer; | |
942 | ||
943 | davinci_spi->version = pdata->version; | |
944 | use_dma = pdata->use_dma; | |
945 | ||
946 | davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; | |
947 | if (davinci_spi->version == SPI_VERSION_2) | |
948 | davinci_spi->bitbang.flags |= SPI_READY; | |
949 | ||
950 | if (use_dma) { | |
778e261e BN |
951 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
952 | if (r) | |
953 | dma_rx_chan = r->start; | |
954 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
955 | if (r) | |
956 | dma_tx_chan = r->start; | |
957 | r = platform_get_resource(pdev, IORESOURCE_DMA, 2); | |
958 | if (r) | |
959 | dma_eventq = r->start; | |
358934a6 SP |
960 | } |
961 | ||
962 | if (!use_dma || | |
963 | dma_rx_chan == SPI_NO_RESOURCE || | |
964 | dma_tx_chan == SPI_NO_RESOURCE || | |
965 | dma_eventq == SPI_NO_RESOURCE) { | |
966 | davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio; | |
967 | use_dma = 0; | |
968 | } else { | |
969 | davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma; | |
970 | davinci_spi->dma_channels = kzalloc(master->num_chipselect | |
971 | * sizeof(struct davinci_spi_dma), GFP_KERNEL); | |
972 | if (davinci_spi->dma_channels == NULL) { | |
973 | ret = -ENOMEM; | |
974 | goto free_clk; | |
975 | } | |
976 | ||
977 | for (i = 0; i < master->num_chipselect; i++) { | |
978 | davinci_spi->dma_channels[i].dma_rx_channel = -1; | |
979 | davinci_spi->dma_channels[i].dma_rx_sync_dev = | |
980 | dma_rx_chan; | |
981 | davinci_spi->dma_channels[i].dma_tx_channel = -1; | |
982 | davinci_spi->dma_channels[i].dma_tx_sync_dev = | |
983 | dma_tx_chan; | |
984 | davinci_spi->dma_channels[i].eventq = dma_eventq; | |
985 | } | |
986 | dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n" | |
987 | "Using RX channel = %d , TX channel = %d and " | |
988 | "event queue = %d", dma_rx_chan, dma_tx_chan, | |
989 | dma_eventq); | |
990 | } | |
991 | ||
992 | davinci_spi->get_rx = davinci_spi_rx_buf_u8; | |
993 | davinci_spi->get_tx = davinci_spi_tx_buf_u8; | |
994 | ||
e0d205e9 BN |
995 | init_completion(&davinci_spi->done); |
996 | ||
358934a6 SP |
997 | /* Reset In/OUT SPI module */ |
998 | iowrite32(0, davinci_spi->base + SPIGCR0); | |
999 | udelay(100); | |
1000 | iowrite32(1, davinci_spi->base + SPIGCR0); | |
1001 | ||
be88471b | 1002 | /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ |
f34bd4cc BN |
1003 | spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; |
1004 | iowrite32(spipc0, davinci_spi->base + SPIPC0); | |
1005 | ||
23853973 BN |
1006 | /* initialize chip selects */ |
1007 | if (pdata->chip_sel) { | |
1008 | for (i = 0; i < pdata->num_chipselect; i++) { | |
1009 | if (pdata->chip_sel[i] != SPI_INTERN_CS) | |
1010 | gpio_direction_output(pdata->chip_sel[i], 1); | |
1011 | } | |
1012 | } | |
1013 | ||
358934a6 SP |
1014 | /* Clock internal */ |
1015 | if (davinci_spi->pdata->clk_internal) | |
1016 | set_io_bits(davinci_spi->base + SPIGCR1, | |
1017 | SPIGCR1_CLKMOD_MASK); | |
1018 | else | |
1019 | clear_io_bits(davinci_spi->base + SPIGCR1, | |
1020 | SPIGCR1_CLKMOD_MASK); | |
1021 | ||
e0d205e9 BN |
1022 | if (pdata->intr_line) |
1023 | iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); | |
1024 | else | |
1025 | iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); | |
1026 | ||
843a713b BN |
1027 | iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF); |
1028 | ||
358934a6 SP |
1029 | /* master mode default */ |
1030 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); | |
1031 | ||
358934a6 SP |
1032 | ret = spi_bitbang_start(&davinci_spi->bitbang); |
1033 | if (ret) | |
1034 | goto free_clk; | |
1035 | ||
3b740b10 | 1036 | dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base); |
358934a6 | 1037 | |
358934a6 SP |
1038 | return ret; |
1039 | ||
1040 | free_clk: | |
1041 | clk_disable(davinci_spi->clk); | |
1042 | clk_put(davinci_spi->clk); | |
1043 | put_master: | |
1044 | spi_master_put(master); | |
1045 | free_tmp_buf: | |
1046 | kfree(davinci_spi->tmp_buf); | |
e0d205e9 BN |
1047 | irq_free: |
1048 | free_irq(davinci_spi->irq, davinci_spi); | |
358934a6 SP |
1049 | unmap_io: |
1050 | iounmap(davinci_spi->base); | |
1051 | release_region: | |
1052 | release_mem_region(davinci_spi->pbase, davinci_spi->region_size); | |
1053 | free_master: | |
1054 | kfree(master); | |
1055 | err: | |
1056 | return ret; | |
1057 | } | |
1058 | ||
1059 | /** | |
1060 | * davinci_spi_remove - remove function for SPI Master Controller | |
1061 | * @pdev: platform_device structure which contains plateform specific data | |
1062 | * | |
1063 | * This function will do the reverse action of davinci_spi_probe function | |
1064 | * It will free the IRQ and SPI controller's memory region. | |
1065 | * It will also call spi_bitbang_stop to destroy the work queue which was | |
1066 | * created by spi_bitbang_start. | |
1067 | */ | |
1068 | static int __exit davinci_spi_remove(struct platform_device *pdev) | |
1069 | { | |
1070 | struct davinci_spi *davinci_spi; | |
1071 | struct spi_master *master; | |
1072 | ||
1073 | master = dev_get_drvdata(&pdev->dev); | |
1074 | davinci_spi = spi_master_get_devdata(master); | |
1075 | ||
1076 | spi_bitbang_stop(&davinci_spi->bitbang); | |
1077 | ||
1078 | clk_disable(davinci_spi->clk); | |
1079 | clk_put(davinci_spi->clk); | |
1080 | spi_master_put(master); | |
1081 | kfree(davinci_spi->tmp_buf); | |
e0d205e9 | 1082 | free_irq(davinci_spi->irq, davinci_spi); |
358934a6 SP |
1083 | iounmap(davinci_spi->base); |
1084 | release_mem_region(davinci_spi->pbase, davinci_spi->region_size); | |
1085 | ||
1086 | return 0; | |
1087 | } | |
1088 | ||
1089 | static struct platform_driver davinci_spi_driver = { | |
1090 | .driver.name = "spi_davinci", | |
1091 | .remove = __exit_p(davinci_spi_remove), | |
1092 | }; | |
1093 | ||
1094 | static int __init davinci_spi_init(void) | |
1095 | { | |
1096 | return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe); | |
1097 | } | |
1098 | module_init(davinci_spi_init); | |
1099 | ||
1100 | static void __exit davinci_spi_exit(void) | |
1101 | { | |
1102 | platform_driver_unregister(&davinci_spi_driver); | |
1103 | } | |
1104 | module_exit(davinci_spi_exit); | |
1105 | ||
1106 | MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); | |
1107 | MODULE_LICENSE("GPL"); |