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358934a6 SP |
1 | /* |
2 | * Copyright (C) 2009 Texas Instruments. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
19 | #include <linux/interrupt.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/gpio.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/dma-mapping.h> | |
28 | #include <linux/spi/spi.h> | |
29 | #include <linux/spi/spi_bitbang.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
358934a6 SP |
31 | |
32 | #include <mach/spi.h> | |
33 | #include <mach/edma.h> | |
34 | ||
35 | #define SPI_NO_RESOURCE ((resource_size_t)-1) | |
36 | ||
37 | #define SPI_MAX_CHIPSELECT 2 | |
38 | ||
39 | #define CS_DEFAULT 0xFF | |
40 | ||
41 | #define SPI_BUFSIZ (SMP_CACHE_BYTES + 1) | |
358934a6 SP |
42 | |
43 | #define SPIFMT_PHASE_MASK BIT(16) | |
44 | #define SPIFMT_POLARITY_MASK BIT(17) | |
45 | #define SPIFMT_DISTIMER_MASK BIT(18) | |
46 | #define SPIFMT_SHIFTDIR_MASK BIT(20) | |
47 | #define SPIFMT_WAITENA_MASK BIT(21) | |
48 | #define SPIFMT_PARITYENA_MASK BIT(22) | |
49 | #define SPIFMT_ODD_PARITY_MASK BIT(23) | |
50 | #define SPIFMT_WDELAY_MASK 0x3f000000u | |
51 | #define SPIFMT_WDELAY_SHIFT 24 | |
7fe0092b | 52 | #define SPIFMT_PRESCALE_SHIFT 8 |
358934a6 | 53 | |
358934a6 SP |
54 | |
55 | /* SPIPC0 */ | |
56 | #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ | |
57 | #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ | |
58 | #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ | |
59 | #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ | |
358934a6 SP |
60 | |
61 | #define SPIINT_MASKALL 0x0101035F | |
358934a6 | 62 | |
cfbc5d1d BN |
63 | /* SPIDAT1 (upper 16 bit defines) */ |
64 | #define SPIDAT1_CSHOLD_MASK BIT(12) | |
65 | ||
66 | /* SPIGCR1 */ | |
358934a6 SP |
67 | #define SPIGCR1_CLKMOD_MASK BIT(1) |
68 | #define SPIGCR1_MASTER_MASK BIT(0) | |
69 | #define SPIGCR1_LOOPBACK_MASK BIT(16) | |
8e206f1c | 70 | #define SPIGCR1_SPIENA_MASK BIT(24) |
358934a6 SP |
71 | |
72 | /* SPIBUF */ | |
73 | #define SPIBUF_TXFULL_MASK BIT(29) | |
74 | #define SPIBUF_RXEMPTY_MASK BIT(31) | |
75 | ||
7abbf23c BN |
76 | /* SPIDELAY */ |
77 | #define SPIDELAY_C2TDELAY_SHIFT 24 | |
78 | #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) | |
79 | #define SPIDELAY_T2CDELAY_SHIFT 16 | |
80 | #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) | |
81 | #define SPIDELAY_T2EDELAY_SHIFT 8 | |
82 | #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) | |
83 | #define SPIDELAY_C2EDELAY_SHIFT 0 | |
84 | #define SPIDELAY_C2EDELAY_MASK 0xFF | |
85 | ||
358934a6 SP |
86 | /* Error Masks */ |
87 | #define SPIFLG_DLEN_ERR_MASK BIT(0) | |
88 | #define SPIFLG_TIMEOUT_MASK BIT(1) | |
89 | #define SPIFLG_PARERR_MASK BIT(2) | |
90 | #define SPIFLG_DESYNC_MASK BIT(3) | |
91 | #define SPIFLG_BITERR_MASK BIT(4) | |
92 | #define SPIFLG_OVRRUN_MASK BIT(6) | |
358934a6 | 93 | #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) |
8e206f1c | 94 | |
358934a6 | 95 | #define SPIINT_DMA_REQ_EN BIT(16) |
358934a6 | 96 | |
358934a6 SP |
97 | /* SPI Controller registers */ |
98 | #define SPIGCR0 0x00 | |
99 | #define SPIGCR1 0x04 | |
100 | #define SPIINT 0x08 | |
101 | #define SPILVL 0x0c | |
102 | #define SPIFLG 0x10 | |
103 | #define SPIPC0 0x14 | |
358934a6 SP |
104 | #define SPIDAT1 0x3c |
105 | #define SPIBUF 0x40 | |
358934a6 SP |
106 | #define SPIDELAY 0x48 |
107 | #define SPIDEF 0x4c | |
108 | #define SPIFMT0 0x50 | |
358934a6 | 109 | |
358934a6 SP |
110 | /* We have 2 DMA channels per CS, one for RX and one for TX */ |
111 | struct davinci_spi_dma { | |
112 | int dma_tx_channel; | |
113 | int dma_rx_channel; | |
114 | int dma_tx_sync_dev; | |
115 | int dma_rx_sync_dev; | |
116 | enum dma_event_q eventq; | |
117 | ||
118 | struct completion dma_tx_completion; | |
119 | struct completion dma_rx_completion; | |
120 | }; | |
121 | ||
122 | /* SPI Controller driver's private data. */ | |
123 | struct davinci_spi { | |
124 | struct spi_bitbang bitbang; | |
125 | struct clk *clk; | |
126 | ||
127 | u8 version; | |
128 | resource_size_t pbase; | |
129 | void __iomem *base; | |
130 | size_t region_size; | |
358934a6 SP |
131 | |
132 | const void *tx; | |
133 | void *rx; | |
134 | u8 *tmp_buf; | |
358934a6 | 135 | struct davinci_spi_dma *dma_channels; |
778e261e | 136 | struct davinci_spi_platform_data *pdata; |
358934a6 SP |
137 | |
138 | void (*get_rx)(u32 rx_data, struct davinci_spi *); | |
139 | u32 (*get_tx)(struct davinci_spi *); | |
140 | ||
cda987eb | 141 | u8 bytes_per_word[SPI_MAX_CHIPSELECT]; |
358934a6 SP |
142 | }; |
143 | ||
53a31b07 BN |
144 | static struct davinci_spi_config davinci_spi_default_cfg; |
145 | ||
358934a6 SP |
146 | static unsigned use_dma; |
147 | ||
148 | static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi) | |
149 | { | |
53d454a1 BN |
150 | if (davinci_spi->rx) { |
151 | u8 *rx = davinci_spi->rx; | |
152 | *rx++ = (u8)data; | |
153 | davinci_spi->rx = rx; | |
154 | } | |
358934a6 SP |
155 | } |
156 | ||
157 | static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi) | |
158 | { | |
53d454a1 BN |
159 | if (davinci_spi->rx) { |
160 | u16 *rx = davinci_spi->rx; | |
161 | *rx++ = (u16)data; | |
162 | davinci_spi->rx = rx; | |
163 | } | |
358934a6 SP |
164 | } |
165 | ||
166 | static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi) | |
167 | { | |
53d454a1 BN |
168 | u32 data = 0; |
169 | if (davinci_spi->tx) { | |
170 | const u8 *tx = davinci_spi->tx; | |
171 | data = *tx++; | |
172 | davinci_spi->tx = tx; | |
173 | } | |
358934a6 SP |
174 | return data; |
175 | } | |
176 | ||
177 | static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi) | |
178 | { | |
53d454a1 BN |
179 | u32 data = 0; |
180 | if (davinci_spi->tx) { | |
181 | const u16 *tx = davinci_spi->tx; | |
182 | data = *tx++; | |
183 | davinci_spi->tx = tx; | |
184 | } | |
358934a6 SP |
185 | return data; |
186 | } | |
187 | ||
188 | static inline void set_io_bits(void __iomem *addr, u32 bits) | |
189 | { | |
190 | u32 v = ioread32(addr); | |
191 | ||
192 | v |= bits; | |
193 | iowrite32(v, addr); | |
194 | } | |
195 | ||
196 | static inline void clear_io_bits(void __iomem *addr, u32 bits) | |
197 | { | |
198 | u32 v = ioread32(addr); | |
199 | ||
200 | v &= ~bits; | |
201 | iowrite32(v, addr); | |
202 | } | |
203 | ||
358934a6 SP |
204 | static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable) |
205 | { | |
206 | struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); | |
207 | ||
208 | if (enable) | |
209 | set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); | |
210 | else | |
211 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); | |
212 | } | |
213 | ||
214 | /* | |
215 | * Interface to control the chip select signal | |
216 | */ | |
217 | static void davinci_spi_chipselect(struct spi_device *spi, int value) | |
218 | { | |
219 | struct davinci_spi *davinci_spi; | |
220 | struct davinci_spi_platform_data *pdata; | |
7978b8c3 | 221 | u8 chip_sel = spi->chip_select; |
cfbc5d1d | 222 | u16 spidat1_cfg = CS_DEFAULT; |
23853973 | 223 | bool gpio_chipsel = false; |
358934a6 SP |
224 | |
225 | davinci_spi = spi_master_get_devdata(spi->master); | |
226 | pdata = davinci_spi->pdata; | |
227 | ||
23853973 BN |
228 | if (pdata->chip_sel && chip_sel < pdata->num_chipselect && |
229 | pdata->chip_sel[chip_sel] != SPI_INTERN_CS) | |
230 | gpio_chipsel = true; | |
231 | ||
358934a6 SP |
232 | /* |
233 | * Board specific chip select logic decides the polarity and cs | |
234 | * line for the controller | |
235 | */ | |
23853973 BN |
236 | if (gpio_chipsel) { |
237 | if (value == BITBANG_CS_ACTIVE) | |
238 | gpio_set_value(pdata->chip_sel[chip_sel], 0); | |
239 | else | |
240 | gpio_set_value(pdata->chip_sel[chip_sel], 1); | |
241 | } else { | |
242 | if (value == BITBANG_CS_ACTIVE) { | |
243 | spidat1_cfg |= SPIDAT1_CSHOLD_MASK; | |
244 | spidat1_cfg &= ~(0x1 << chip_sel); | |
245 | } | |
7978b8c3 | 246 | |
23853973 BN |
247 | iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); |
248 | } | |
358934a6 SP |
249 | } |
250 | ||
7fe0092b BN |
251 | /** |
252 | * davinci_spi_get_prescale - Calculates the correct prescale value | |
253 | * @maxspeed_hz: the maximum rate the SPI clock can run at | |
254 | * | |
255 | * This function calculates the prescale value that generates a clock rate | |
256 | * less than or equal to the specified maximum. | |
257 | * | |
258 | * Returns: calculated prescale - 1 for easy programming into SPI registers | |
259 | * or negative error number if valid prescalar cannot be updated. | |
260 | */ | |
261 | static inline int davinci_spi_get_prescale(struct davinci_spi *davinci_spi, | |
262 | u32 max_speed_hz) | |
263 | { | |
264 | int ret; | |
265 | ||
266 | ret = DIV_ROUND_UP(clk_get_rate(davinci_spi->clk), max_speed_hz); | |
267 | ||
268 | if (ret < 3 || ret > 256) | |
269 | return -EINVAL; | |
270 | ||
271 | return ret - 1; | |
272 | } | |
273 | ||
358934a6 SP |
274 | /** |
275 | * davinci_spi_setup_transfer - This functions will determine transfer method | |
276 | * @spi: spi device on which data transfer to be done | |
277 | * @t: spi transfer in which transfer info is filled | |
278 | * | |
279 | * This function determines data transfer method (8/16/32 bit transfer). | |
280 | * It will also set the SPI Clock Control register according to | |
281 | * SPI slave device freq. | |
282 | */ | |
283 | static int davinci_spi_setup_transfer(struct spi_device *spi, | |
284 | struct spi_transfer *t) | |
285 | { | |
286 | ||
287 | struct davinci_spi *davinci_spi; | |
25f33512 | 288 | struct davinci_spi_config *spicfg; |
358934a6 | 289 | u8 bits_per_word = 0; |
25f33512 | 290 | u32 hz = 0, spifmt = 0, prescale = 0; |
358934a6 SP |
291 | |
292 | davinci_spi = spi_master_get_devdata(spi->master); | |
25f33512 BN |
293 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
294 | if (!spicfg) | |
295 | spicfg = &davinci_spi_default_cfg; | |
358934a6 SP |
296 | |
297 | if (t) { | |
298 | bits_per_word = t->bits_per_word; | |
299 | hz = t->speed_hz; | |
300 | } | |
301 | ||
302 | /* if bits_per_word is not set then set it default */ | |
303 | if (!bits_per_word) | |
304 | bits_per_word = spi->bits_per_word; | |
305 | ||
306 | /* | |
307 | * Assign function pointer to appropriate transfer method | |
308 | * 8bit, 16bit or 32bit transfer | |
309 | */ | |
310 | if (bits_per_word <= 8 && bits_per_word >= 2) { | |
311 | davinci_spi->get_rx = davinci_spi_rx_buf_u8; | |
312 | davinci_spi->get_tx = davinci_spi_tx_buf_u8; | |
cda987eb | 313 | davinci_spi->bytes_per_word[spi->chip_select] = 1; |
358934a6 SP |
314 | } else if (bits_per_word <= 16 && bits_per_word >= 2) { |
315 | davinci_spi->get_rx = davinci_spi_rx_buf_u16; | |
316 | davinci_spi->get_tx = davinci_spi_tx_buf_u16; | |
cda987eb | 317 | davinci_spi->bytes_per_word[spi->chip_select] = 2; |
358934a6 SP |
318 | } else |
319 | return -EINVAL; | |
320 | ||
321 | if (!hz) | |
322 | hz = spi->max_speed_hz; | |
323 | ||
25f33512 BN |
324 | /* Set up SPIFMTn register, unique to this chipselect. */ |
325 | ||
7fe0092b BN |
326 | prescale = davinci_spi_get_prescale(davinci_spi, hz); |
327 | if (prescale < 0) | |
328 | return prescale; | |
329 | ||
25f33512 BN |
330 | spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); |
331 | ||
332 | if (spi->mode & SPI_LSB_FIRST) | |
333 | spifmt |= SPIFMT_SHIFTDIR_MASK; | |
334 | ||
335 | if (spi->mode & SPI_CPOL) | |
336 | spifmt |= SPIFMT_POLARITY_MASK; | |
337 | ||
338 | if (!(spi->mode & SPI_CPHA)) | |
339 | spifmt |= SPIFMT_PHASE_MASK; | |
340 | ||
341 | /* | |
342 | * Version 1 hardware supports two basic SPI modes: | |
343 | * - Standard SPI mode uses 4 pins, with chipselect | |
344 | * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) | |
345 | * (distinct from SPI_3WIRE, with just one data wire; | |
346 | * or similar variants without MOSI or without MISO) | |
347 | * | |
348 | * Version 2 hardware supports an optional handshaking signal, | |
349 | * so it can support two more modes: | |
350 | * - 5 pin SPI variant is standard SPI plus SPI_READY | |
351 | * - 4 pin with enable is (SPI_READY | SPI_NO_CS) | |
352 | */ | |
353 | ||
354 | if (davinci_spi->version == SPI_VERSION_2) { | |
355 | ||
7abbf23c BN |
356 | u32 delay = 0; |
357 | ||
25f33512 BN |
358 | spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) |
359 | & SPIFMT_WDELAY_MASK); | |
358934a6 | 360 | |
25f33512 BN |
361 | if (spicfg->odd_parity) |
362 | spifmt |= SPIFMT_ODD_PARITY_MASK; | |
363 | ||
364 | if (spicfg->parity_enable) | |
365 | spifmt |= SPIFMT_PARITYENA_MASK; | |
366 | ||
7abbf23c | 367 | if (spicfg->timer_disable) { |
25f33512 | 368 | spifmt |= SPIFMT_DISTIMER_MASK; |
7abbf23c BN |
369 | } else { |
370 | delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) | |
371 | & SPIDELAY_C2TDELAY_MASK; | |
372 | delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) | |
373 | & SPIDELAY_T2CDELAY_MASK; | |
374 | } | |
25f33512 | 375 | |
7abbf23c | 376 | if (spi->mode & SPI_READY) { |
25f33512 | 377 | spifmt |= SPIFMT_WAITENA_MASK; |
7abbf23c BN |
378 | delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) |
379 | & SPIDELAY_T2EDELAY_MASK; | |
380 | delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) | |
381 | & SPIDELAY_C2EDELAY_MASK; | |
382 | } | |
383 | ||
384 | iowrite32(delay, davinci_spi->base + SPIDELAY); | |
25f33512 BN |
385 | } |
386 | ||
387 | iowrite32(spifmt, davinci_spi->base + SPIFMT0); | |
358934a6 SP |
388 | |
389 | return 0; | |
390 | } | |
391 | ||
392 | static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data) | |
393 | { | |
394 | struct spi_device *spi = (struct spi_device *)data; | |
395 | struct davinci_spi *davinci_spi; | |
396 | struct davinci_spi_dma *davinci_spi_dma; | |
358934a6 SP |
397 | |
398 | davinci_spi = spi_master_get_devdata(spi->master); | |
399 | davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); | |
358934a6 SP |
400 | |
401 | if (ch_status == DMA_COMPLETE) | |
402 | edma_stop(davinci_spi_dma->dma_rx_channel); | |
403 | else | |
404 | edma_clean_channel(davinci_spi_dma->dma_rx_channel); | |
405 | ||
406 | complete(&davinci_spi_dma->dma_rx_completion); | |
407 | /* We must disable the DMA RX request */ | |
408 | davinci_spi_set_dma_req(spi, 0); | |
409 | } | |
410 | ||
411 | static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data) | |
412 | { | |
413 | struct spi_device *spi = (struct spi_device *)data; | |
414 | struct davinci_spi *davinci_spi; | |
415 | struct davinci_spi_dma *davinci_spi_dma; | |
358934a6 SP |
416 | |
417 | davinci_spi = spi_master_get_devdata(spi->master); | |
418 | davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); | |
358934a6 SP |
419 | |
420 | if (ch_status == DMA_COMPLETE) | |
421 | edma_stop(davinci_spi_dma->dma_tx_channel); | |
422 | else | |
423 | edma_clean_channel(davinci_spi_dma->dma_tx_channel); | |
424 | ||
425 | complete(&davinci_spi_dma->dma_tx_completion); | |
426 | /* We must disable the DMA TX request */ | |
427 | davinci_spi_set_dma_req(spi, 0); | |
428 | } | |
429 | ||
430 | static int davinci_spi_request_dma(struct spi_device *spi) | |
431 | { | |
432 | struct davinci_spi *davinci_spi; | |
433 | struct davinci_spi_dma *davinci_spi_dma; | |
358934a6 SP |
434 | struct device *sdev; |
435 | int r; | |
436 | ||
437 | davinci_spi = spi_master_get_devdata(spi->master); | |
438 | davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; | |
358934a6 SP |
439 | sdev = davinci_spi->bitbang.master->dev.parent; |
440 | ||
441 | r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev, | |
442 | davinci_spi_dma_rx_callback, spi, | |
443 | davinci_spi_dma->eventq); | |
444 | if (r < 0) { | |
445 | dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n"); | |
446 | return -EAGAIN; | |
447 | } | |
448 | davinci_spi_dma->dma_rx_channel = r; | |
449 | r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev, | |
450 | davinci_spi_dma_tx_callback, spi, | |
451 | davinci_spi_dma->eventq); | |
452 | if (r < 0) { | |
453 | edma_free_channel(davinci_spi_dma->dma_rx_channel); | |
454 | davinci_spi_dma->dma_rx_channel = -1; | |
455 | dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n"); | |
456 | return -EAGAIN; | |
457 | } | |
458 | davinci_spi_dma->dma_tx_channel = r; | |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
463 | /** | |
464 | * davinci_spi_setup - This functions will set default transfer method | |
465 | * @spi: spi device on which data transfer to be done | |
466 | * | |
467 | * This functions sets the default transfer method. | |
468 | */ | |
358934a6 SP |
469 | static int davinci_spi_setup(struct spi_device *spi) |
470 | { | |
471 | int retval; | |
472 | struct davinci_spi *davinci_spi; | |
473 | struct davinci_spi_dma *davinci_spi_dma; | |
358934a6 SP |
474 | |
475 | davinci_spi = spi_master_get_devdata(spi->master); | |
358934a6 SP |
476 | |
477 | /* if bits per word length is zero then set it default 8 */ | |
478 | if (!spi->bits_per_word) | |
479 | spi->bits_per_word = 8; | |
480 | ||
358934a6 SP |
481 | if (use_dma && davinci_spi->dma_channels) { |
482 | davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; | |
483 | ||
484 | if ((davinci_spi_dma->dma_rx_channel == -1) | |
485 | || (davinci_spi_dma->dma_tx_channel == -1)) { | |
486 | retval = davinci_spi_request_dma(spi); | |
487 | if (retval < 0) | |
488 | return retval; | |
489 | } | |
490 | } | |
491 | ||
358934a6 SP |
492 | retval = davinci_spi_setup_transfer(spi, NULL); |
493 | ||
494 | return retval; | |
495 | } | |
496 | ||
497 | static void davinci_spi_cleanup(struct spi_device *spi) | |
498 | { | |
499 | struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); | |
500 | struct davinci_spi_dma *davinci_spi_dma; | |
501 | ||
502 | davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; | |
503 | ||
504 | if (use_dma && davinci_spi->dma_channels) { | |
505 | davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; | |
506 | ||
507 | if ((davinci_spi_dma->dma_rx_channel != -1) | |
508 | && (davinci_spi_dma->dma_tx_channel != -1)) { | |
509 | edma_free_channel(davinci_spi_dma->dma_tx_channel); | |
510 | edma_free_channel(davinci_spi_dma->dma_rx_channel); | |
511 | } | |
512 | } | |
513 | } | |
514 | ||
515 | static int davinci_spi_bufs_prep(struct spi_device *spi, | |
516 | struct davinci_spi *davinci_spi) | |
517 | { | |
23853973 | 518 | struct davinci_spi_platform_data *pdata; |
358934a6 SP |
519 | int op_mode = 0; |
520 | ||
521 | /* | |
522 | * REVISIT unless devices disagree about SPI_LOOP or | |
523 | * SPI_READY (SPI_NO_CS only allows one device!), this | |
524 | * should not need to be done before each message... | |
525 | * optimize for both flags staying cleared. | |
526 | */ | |
527 | ||
528 | op_mode = SPIPC0_DIFUN_MASK | |
529 | | SPIPC0_DOFUN_MASK | |
530 | | SPIPC0_CLKFUN_MASK; | |
23853973 BN |
531 | if (!(spi->mode & SPI_NO_CS)) { |
532 | pdata = davinci_spi->pdata; | |
533 | if (!pdata->chip_sel || | |
534 | pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS) | |
535 | op_mode |= 1 << spi->chip_select; | |
536 | } | |
358934a6 SP |
537 | if (spi->mode & SPI_READY) |
538 | op_mode |= SPIPC0_SPIENA_MASK; | |
539 | ||
540 | iowrite32(op_mode, davinci_spi->base + SPIPC0); | |
541 | ||
542 | if (spi->mode & SPI_LOOP) | |
543 | set_io_bits(davinci_spi->base + SPIGCR1, | |
544 | SPIGCR1_LOOPBACK_MASK); | |
545 | else | |
546 | clear_io_bits(davinci_spi->base + SPIGCR1, | |
547 | SPIGCR1_LOOPBACK_MASK); | |
548 | ||
549 | return 0; | |
550 | } | |
551 | ||
552 | static int davinci_spi_check_error(struct davinci_spi *davinci_spi, | |
553 | int int_status) | |
554 | { | |
555 | struct device *sdev = davinci_spi->bitbang.master->dev.parent; | |
556 | ||
557 | if (int_status & SPIFLG_TIMEOUT_MASK) { | |
558 | dev_dbg(sdev, "SPI Time-out Error\n"); | |
559 | return -ETIMEDOUT; | |
560 | } | |
561 | if (int_status & SPIFLG_DESYNC_MASK) { | |
562 | dev_dbg(sdev, "SPI Desynchronization Error\n"); | |
563 | return -EIO; | |
564 | } | |
565 | if (int_status & SPIFLG_BITERR_MASK) { | |
566 | dev_dbg(sdev, "SPI Bit error\n"); | |
567 | return -EIO; | |
568 | } | |
569 | ||
570 | if (davinci_spi->version == SPI_VERSION_2) { | |
571 | if (int_status & SPIFLG_DLEN_ERR_MASK) { | |
572 | dev_dbg(sdev, "SPI Data Length Error\n"); | |
573 | return -EIO; | |
574 | } | |
575 | if (int_status & SPIFLG_PARERR_MASK) { | |
576 | dev_dbg(sdev, "SPI Parity Error\n"); | |
577 | return -EIO; | |
578 | } | |
579 | if (int_status & SPIFLG_OVRRUN_MASK) { | |
580 | dev_dbg(sdev, "SPI Data Overrun error\n"); | |
581 | return -EIO; | |
582 | } | |
358934a6 SP |
583 | if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { |
584 | dev_dbg(sdev, "SPI Buffer Init Active\n"); | |
585 | return -EBUSY; | |
586 | } | |
587 | } | |
588 | ||
589 | return 0; | |
590 | } | |
591 | ||
592 | /** | |
593 | * davinci_spi_bufs - functions which will handle transfer data | |
594 | * @spi: spi device on which data transfer to be done | |
595 | * @t: spi transfer in which transfer info is filled | |
596 | * | |
597 | * This function will put data to be transferred into data register | |
598 | * of SPI controller and then wait until the completion will be marked | |
599 | * by the IRQ Handler. | |
600 | */ | |
601 | static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t) | |
602 | { | |
603 | struct davinci_spi *davinci_spi; | |
cf90fe73 | 604 | int status, count, ret; |
7978b8c3 | 605 | u8 conv; |
358934a6 SP |
606 | u32 tx_data, data1_reg_val; |
607 | u32 buf_val, flg_val; | |
608 | struct davinci_spi_platform_data *pdata; | |
609 | ||
610 | davinci_spi = spi_master_get_devdata(spi->master); | |
611 | pdata = davinci_spi->pdata; | |
612 | ||
613 | davinci_spi->tx = t->tx_buf; | |
614 | davinci_spi->rx = t->rx_buf; | |
615 | ||
616 | /* convert len to words based on bits_per_word */ | |
cda987eb | 617 | conv = davinci_spi->bytes_per_word[spi->chip_select]; |
7978b8c3 BN |
618 | data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); |
619 | ||
358934a6 SP |
620 | ret = davinci_spi_bufs_prep(spi, davinci_spi); |
621 | if (ret) | |
622 | return ret; | |
623 | ||
624 | /* Enable SPI */ | |
625 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | |
626 | ||
f2bf4e84 | 627 | count = t->len / conv; |
358934a6 | 628 | |
cf90fe73 BN |
629 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); |
630 | ||
358934a6 SP |
631 | /* Determine the command to execute READ or WRITE */ |
632 | if (t->tx_buf) { | |
358934a6 SP |
633 | |
634 | while (1) { | |
635 | tx_data = davinci_spi->get_tx(davinci_spi); | |
636 | ||
637 | data1_reg_val &= ~(0xFFFF); | |
638 | data1_reg_val |= (0xFFFF & tx_data); | |
639 | ||
640 | buf_val = ioread32(davinci_spi->base + SPIBUF); | |
641 | if ((buf_val & SPIBUF_TXFULL_MASK) == 0) { | |
642 | iowrite32(data1_reg_val, | |
643 | davinci_spi->base + SPIDAT1); | |
644 | ||
645 | count--; | |
646 | } | |
647 | while (ioread32(davinci_spi->base + SPIBUF) | |
648 | & SPIBUF_RXEMPTY_MASK) | |
649 | cpu_relax(); | |
650 | ||
651 | /* getting the returned byte */ | |
652 | if (t->rx_buf) { | |
653 | buf_val = ioread32(davinci_spi->base + SPIBUF); | |
654 | davinci_spi->get_rx(buf_val, davinci_spi); | |
655 | } | |
656 | if (count <= 0) | |
657 | break; | |
658 | } | |
659 | } else { | |
cf90fe73 BN |
660 | while (1) { |
661 | /* keeps the serial clock going */ | |
662 | if ((ioread32(davinci_spi->base + SPIBUF) | |
663 | & SPIBUF_TXFULL_MASK) == 0) | |
664 | iowrite32(data1_reg_val, | |
665 | davinci_spi->base + SPIDAT1); | |
358934a6 SP |
666 | |
667 | while (ioread32(davinci_spi->base + SPIBUF) & | |
cf90fe73 | 668 | SPIBUF_RXEMPTY_MASK) |
358934a6 SP |
669 | cpu_relax(); |
670 | ||
cf90fe73 BN |
671 | flg_val = ioread32(davinci_spi->base + SPIFLG); |
672 | buf_val = ioread32(davinci_spi->base + SPIBUF); | |
358934a6 | 673 | |
cf90fe73 | 674 | davinci_spi->get_rx(buf_val, davinci_spi); |
358934a6 | 675 | |
cf90fe73 BN |
676 | count--; |
677 | if (count <= 0) | |
678 | break; | |
358934a6 SP |
679 | } |
680 | } | |
681 | ||
682 | /* | |
683 | * Check for bit error, desync error,parity error,timeout error and | |
684 | * receive overflow errors | |
685 | */ | |
cf90fe73 | 686 | status = ioread32(davinci_spi->base + SPIFLG); |
358934a6 | 687 | |
cf90fe73 | 688 | ret = davinci_spi_check_error(davinci_spi, status); |
358934a6 SP |
689 | if (ret != 0) |
690 | return ret; | |
691 | ||
358934a6 SP |
692 | return t->len; |
693 | } | |
694 | ||
358934a6 SP |
695 | static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t) |
696 | { | |
697 | struct davinci_spi *davinci_spi; | |
698 | int int_status = 0; | |
699 | int count, temp_count; | |
358934a6 SP |
700 | u32 data1_reg_val; |
701 | struct davinci_spi_dma *davinci_spi_dma; | |
b7ab24a0 | 702 | int data_type, ret; |
358934a6 | 703 | unsigned long tx_reg, rx_reg; |
358934a6 SP |
704 | struct device *sdev; |
705 | ||
706 | davinci_spi = spi_master_get_devdata(spi->master); | |
358934a6 SP |
707 | sdev = davinci_spi->bitbang.master->dev.parent; |
708 | ||
709 | davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; | |
710 | ||
711 | tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1; | |
712 | rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF; | |
713 | ||
714 | davinci_spi->tx = t->tx_buf; | |
715 | davinci_spi->rx = t->rx_buf; | |
716 | ||
717 | /* convert len to words based on bits_per_word */ | |
b7ab24a0 | 718 | data_type = davinci_spi->bytes_per_word[spi->chip_select]; |
358934a6 | 719 | |
7978b8c3 BN |
720 | data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); |
721 | ||
358934a6 SP |
722 | init_completion(&davinci_spi_dma->dma_rx_completion); |
723 | init_completion(&davinci_spi_dma->dma_tx_completion); | |
724 | ||
358934a6 SP |
725 | ret = davinci_spi_bufs_prep(spi, davinci_spi); |
726 | if (ret) | |
727 | return ret; | |
728 | ||
f2bf4e84 | 729 | count = t->len / data_type; /* the number of elements */ |
358934a6 SP |
730 | |
731 | /* disable all interrupts for dma transfers */ | |
732 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); | |
358934a6 SP |
733 | /* Enable SPI */ |
734 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | |
735 | ||
358934a6 SP |
736 | if (t->tx_buf) { |
737 | t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count, | |
738 | DMA_TO_DEVICE); | |
739 | if (dma_mapping_error(&spi->dev, t->tx_dma)) { | |
740 | dev_dbg(sdev, "Unable to DMA map a %d bytes" | |
741 | " TX buffer\n", count); | |
742 | return -ENOMEM; | |
743 | } | |
744 | temp_count = count; | |
745 | } else { | |
746 | /* We need TX clocking for RX transaction */ | |
747 | t->tx_dma = dma_map_single(&spi->dev, | |
748 | (void *)davinci_spi->tmp_buf, count + 1, | |
749 | DMA_TO_DEVICE); | |
750 | if (dma_mapping_error(&spi->dev, t->tx_dma)) { | |
751 | dev_dbg(sdev, "Unable to DMA map a %d bytes" | |
752 | " TX tmp buffer\n", count); | |
753 | return -ENOMEM; | |
754 | } | |
755 | temp_count = count + 1; | |
756 | } | |
757 | ||
758 | edma_set_transfer_params(davinci_spi_dma->dma_tx_channel, | |
759 | data_type, temp_count, 1, 0, ASYNC); | |
760 | edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT); | |
761 | edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT); | |
762 | edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0); | |
763 | edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0); | |
764 | ||
765 | if (t->rx_buf) { | |
766 | /* initiate transaction */ | |
767 | iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); | |
768 | ||
769 | t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count, | |
770 | DMA_FROM_DEVICE); | |
771 | if (dma_mapping_error(&spi->dev, t->rx_dma)) { | |
772 | dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", | |
773 | count); | |
774 | if (t->tx_buf != NULL) | |
775 | dma_unmap_single(NULL, t->tx_dma, | |
776 | count, DMA_TO_DEVICE); | |
777 | return -ENOMEM; | |
778 | } | |
779 | edma_set_transfer_params(davinci_spi_dma->dma_rx_channel, | |
780 | data_type, count, 1, 0, ASYNC); | |
781 | edma_set_src(davinci_spi_dma->dma_rx_channel, | |
782 | rx_reg, INCR, W8BIT); | |
783 | edma_set_dest(davinci_spi_dma->dma_rx_channel, | |
784 | t->rx_dma, INCR, W8BIT); | |
785 | edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0); | |
786 | edma_set_dest_index(davinci_spi_dma->dma_rx_channel, | |
787 | data_type, 0); | |
788 | } | |
789 | ||
790 | if ((t->tx_buf) || (t->rx_buf)) | |
791 | edma_start(davinci_spi_dma->dma_tx_channel); | |
792 | ||
793 | if (t->rx_buf) | |
794 | edma_start(davinci_spi_dma->dma_rx_channel); | |
795 | ||
796 | if ((t->rx_buf) || (t->tx_buf)) | |
797 | davinci_spi_set_dma_req(spi, 1); | |
798 | ||
799 | if (t->tx_buf) | |
800 | wait_for_completion_interruptible( | |
801 | &davinci_spi_dma->dma_tx_completion); | |
802 | ||
803 | if (t->rx_buf) | |
804 | wait_for_completion_interruptible( | |
805 | &davinci_spi_dma->dma_rx_completion); | |
806 | ||
807 | dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE); | |
808 | ||
809 | if (t->rx_buf) | |
810 | dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE); | |
811 | ||
812 | /* | |
813 | * Check for bit error, desync error,parity error,timeout error and | |
814 | * receive overflow errors | |
815 | */ | |
816 | int_status = ioread32(davinci_spi->base + SPIFLG); | |
817 | ||
818 | ret = davinci_spi_check_error(davinci_spi, int_status); | |
819 | if (ret != 0) | |
820 | return ret; | |
821 | ||
358934a6 SP |
822 | return t->len; |
823 | } | |
824 | ||
358934a6 SP |
825 | /** |
826 | * davinci_spi_probe - probe function for SPI Master Controller | |
827 | * @pdev: platform_device structure which contains plateform specific data | |
828 | */ | |
829 | static int davinci_spi_probe(struct platform_device *pdev) | |
830 | { | |
831 | struct spi_master *master; | |
832 | struct davinci_spi *davinci_spi; | |
833 | struct davinci_spi_platform_data *pdata; | |
834 | struct resource *r, *mem; | |
835 | resource_size_t dma_rx_chan = SPI_NO_RESOURCE; | |
836 | resource_size_t dma_tx_chan = SPI_NO_RESOURCE; | |
837 | resource_size_t dma_eventq = SPI_NO_RESOURCE; | |
838 | int i = 0, ret = 0; | |
839 | ||
840 | pdata = pdev->dev.platform_data; | |
841 | if (pdata == NULL) { | |
842 | ret = -ENODEV; | |
843 | goto err; | |
844 | } | |
845 | ||
846 | master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); | |
847 | if (master == NULL) { | |
848 | ret = -ENOMEM; | |
849 | goto err; | |
850 | } | |
851 | ||
852 | dev_set_drvdata(&pdev->dev, master); | |
853 | ||
854 | davinci_spi = spi_master_get_devdata(master); | |
855 | if (davinci_spi == NULL) { | |
856 | ret = -ENOENT; | |
857 | goto free_master; | |
858 | } | |
859 | ||
860 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
861 | if (r == NULL) { | |
862 | ret = -ENOENT; | |
863 | goto free_master; | |
864 | } | |
865 | ||
866 | davinci_spi->pbase = r->start; | |
867 | davinci_spi->region_size = resource_size(r); | |
868 | davinci_spi->pdata = pdata; | |
869 | ||
870 | mem = request_mem_region(r->start, davinci_spi->region_size, | |
871 | pdev->name); | |
872 | if (mem == NULL) { | |
873 | ret = -EBUSY; | |
874 | goto free_master; | |
875 | } | |
876 | ||
50356dd7 | 877 | davinci_spi->base = ioremap(r->start, davinci_spi->region_size); |
358934a6 SP |
878 | if (davinci_spi->base == NULL) { |
879 | ret = -ENOMEM; | |
880 | goto release_region; | |
881 | } | |
882 | ||
358934a6 SP |
883 | /* Allocate tmp_buf for tx_buf */ |
884 | davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL); | |
885 | if (davinci_spi->tmp_buf == NULL) { | |
886 | ret = -ENOMEM; | |
cf90fe73 | 887 | goto unmap_io; |
358934a6 SP |
888 | } |
889 | ||
890 | davinci_spi->bitbang.master = spi_master_get(master); | |
891 | if (davinci_spi->bitbang.master == NULL) { | |
892 | ret = -ENODEV; | |
893 | goto free_tmp_buf; | |
894 | } | |
895 | ||
896 | davinci_spi->clk = clk_get(&pdev->dev, NULL); | |
897 | if (IS_ERR(davinci_spi->clk)) { | |
898 | ret = -ENODEV; | |
899 | goto put_master; | |
900 | } | |
901 | clk_enable(davinci_spi->clk); | |
902 | ||
358934a6 SP |
903 | master->bus_num = pdev->id; |
904 | master->num_chipselect = pdata->num_chipselect; | |
905 | master->setup = davinci_spi_setup; | |
906 | master->cleanup = davinci_spi_cleanup; | |
907 | ||
908 | davinci_spi->bitbang.chipselect = davinci_spi_chipselect; | |
909 | davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer; | |
910 | ||
911 | davinci_spi->version = pdata->version; | |
912 | use_dma = pdata->use_dma; | |
913 | ||
914 | davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; | |
915 | if (davinci_spi->version == SPI_VERSION_2) | |
916 | davinci_spi->bitbang.flags |= SPI_READY; | |
917 | ||
918 | if (use_dma) { | |
778e261e BN |
919 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
920 | if (r) | |
921 | dma_rx_chan = r->start; | |
922 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
923 | if (r) | |
924 | dma_tx_chan = r->start; | |
925 | r = platform_get_resource(pdev, IORESOURCE_DMA, 2); | |
926 | if (r) | |
927 | dma_eventq = r->start; | |
358934a6 SP |
928 | } |
929 | ||
930 | if (!use_dma || | |
931 | dma_rx_chan == SPI_NO_RESOURCE || | |
932 | dma_tx_chan == SPI_NO_RESOURCE || | |
933 | dma_eventq == SPI_NO_RESOURCE) { | |
934 | davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio; | |
935 | use_dma = 0; | |
936 | } else { | |
937 | davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma; | |
938 | davinci_spi->dma_channels = kzalloc(master->num_chipselect | |
939 | * sizeof(struct davinci_spi_dma), GFP_KERNEL); | |
940 | if (davinci_spi->dma_channels == NULL) { | |
941 | ret = -ENOMEM; | |
942 | goto free_clk; | |
943 | } | |
944 | ||
945 | for (i = 0; i < master->num_chipselect; i++) { | |
946 | davinci_spi->dma_channels[i].dma_rx_channel = -1; | |
947 | davinci_spi->dma_channels[i].dma_rx_sync_dev = | |
948 | dma_rx_chan; | |
949 | davinci_spi->dma_channels[i].dma_tx_channel = -1; | |
950 | davinci_spi->dma_channels[i].dma_tx_sync_dev = | |
951 | dma_tx_chan; | |
952 | davinci_spi->dma_channels[i].eventq = dma_eventq; | |
953 | } | |
954 | dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n" | |
955 | "Using RX channel = %d , TX channel = %d and " | |
956 | "event queue = %d", dma_rx_chan, dma_tx_chan, | |
957 | dma_eventq); | |
958 | } | |
959 | ||
960 | davinci_spi->get_rx = davinci_spi_rx_buf_u8; | |
961 | davinci_spi->get_tx = davinci_spi_tx_buf_u8; | |
962 | ||
358934a6 SP |
963 | /* Reset In/OUT SPI module */ |
964 | iowrite32(0, davinci_spi->base + SPIGCR0); | |
965 | udelay(100); | |
966 | iowrite32(1, davinci_spi->base + SPIGCR0); | |
967 | ||
23853973 BN |
968 | /* initialize chip selects */ |
969 | if (pdata->chip_sel) { | |
970 | for (i = 0; i < pdata->num_chipselect; i++) { | |
971 | if (pdata->chip_sel[i] != SPI_INTERN_CS) | |
972 | gpio_direction_output(pdata->chip_sel[i], 1); | |
973 | } | |
974 | } | |
975 | ||
358934a6 SP |
976 | /* Clock internal */ |
977 | if (davinci_spi->pdata->clk_internal) | |
978 | set_io_bits(davinci_spi->base + SPIGCR1, | |
979 | SPIGCR1_CLKMOD_MASK); | |
980 | else | |
981 | clear_io_bits(davinci_spi->base + SPIGCR1, | |
982 | SPIGCR1_CLKMOD_MASK); | |
983 | ||
843a713b BN |
984 | iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF); |
985 | ||
358934a6 SP |
986 | /* master mode default */ |
987 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); | |
988 | ||
358934a6 SP |
989 | ret = spi_bitbang_start(&davinci_spi->bitbang); |
990 | if (ret) | |
991 | goto free_clk; | |
992 | ||
3b740b10 | 993 | dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base); |
358934a6 | 994 | |
358934a6 SP |
995 | return ret; |
996 | ||
997 | free_clk: | |
998 | clk_disable(davinci_spi->clk); | |
999 | clk_put(davinci_spi->clk); | |
1000 | put_master: | |
1001 | spi_master_put(master); | |
1002 | free_tmp_buf: | |
1003 | kfree(davinci_spi->tmp_buf); | |
358934a6 SP |
1004 | unmap_io: |
1005 | iounmap(davinci_spi->base); | |
1006 | release_region: | |
1007 | release_mem_region(davinci_spi->pbase, davinci_spi->region_size); | |
1008 | free_master: | |
1009 | kfree(master); | |
1010 | err: | |
1011 | return ret; | |
1012 | } | |
1013 | ||
1014 | /** | |
1015 | * davinci_spi_remove - remove function for SPI Master Controller | |
1016 | * @pdev: platform_device structure which contains plateform specific data | |
1017 | * | |
1018 | * This function will do the reverse action of davinci_spi_probe function | |
1019 | * It will free the IRQ and SPI controller's memory region. | |
1020 | * It will also call spi_bitbang_stop to destroy the work queue which was | |
1021 | * created by spi_bitbang_start. | |
1022 | */ | |
1023 | static int __exit davinci_spi_remove(struct platform_device *pdev) | |
1024 | { | |
1025 | struct davinci_spi *davinci_spi; | |
1026 | struct spi_master *master; | |
1027 | ||
1028 | master = dev_get_drvdata(&pdev->dev); | |
1029 | davinci_spi = spi_master_get_devdata(master); | |
1030 | ||
1031 | spi_bitbang_stop(&davinci_spi->bitbang); | |
1032 | ||
1033 | clk_disable(davinci_spi->clk); | |
1034 | clk_put(davinci_spi->clk); | |
1035 | spi_master_put(master); | |
1036 | kfree(davinci_spi->tmp_buf); | |
358934a6 SP |
1037 | iounmap(davinci_spi->base); |
1038 | release_mem_region(davinci_spi->pbase, davinci_spi->region_size); | |
1039 | ||
1040 | return 0; | |
1041 | } | |
1042 | ||
1043 | static struct platform_driver davinci_spi_driver = { | |
1044 | .driver.name = "spi_davinci", | |
1045 | .remove = __exit_p(davinci_spi_remove), | |
1046 | }; | |
1047 | ||
1048 | static int __init davinci_spi_init(void) | |
1049 | { | |
1050 | return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe); | |
1051 | } | |
1052 | module_init(davinci_spi_init); | |
1053 | ||
1054 | static void __exit davinci_spi_exit(void) | |
1055 | { | |
1056 | platform_driver_unregister(&davinci_spi_driver); | |
1057 | } | |
1058 | module_exit(davinci_spi_exit); | |
1059 | ||
1060 | MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); | |
1061 | MODULE_LICENSE("GPL"); |