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358934a6 SP |
1 | /* |
2 | * Copyright (C) 2009 Texas Instruments. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
19 | #include <linux/interrupt.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/gpio.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/dma-mapping.h> | |
28 | #include <linux/spi/spi.h> | |
29 | #include <linux/spi/spi_bitbang.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
358934a6 SP |
31 | |
32 | #include <mach/spi.h> | |
33 | #include <mach/edma.h> | |
34 | ||
35 | #define SPI_NO_RESOURCE ((resource_size_t)-1) | |
36 | ||
37 | #define SPI_MAX_CHIPSELECT 2 | |
38 | ||
39 | #define CS_DEFAULT 0xFF | |
40 | ||
358934a6 SP |
41 | #define SPIFMT_PHASE_MASK BIT(16) |
42 | #define SPIFMT_POLARITY_MASK BIT(17) | |
43 | #define SPIFMT_DISTIMER_MASK BIT(18) | |
44 | #define SPIFMT_SHIFTDIR_MASK BIT(20) | |
45 | #define SPIFMT_WAITENA_MASK BIT(21) | |
46 | #define SPIFMT_PARITYENA_MASK BIT(22) | |
47 | #define SPIFMT_ODD_PARITY_MASK BIT(23) | |
48 | #define SPIFMT_WDELAY_MASK 0x3f000000u | |
49 | #define SPIFMT_WDELAY_SHIFT 24 | |
7fe0092b | 50 | #define SPIFMT_PRESCALE_SHIFT 8 |
358934a6 | 51 | |
358934a6 SP |
52 | |
53 | /* SPIPC0 */ | |
54 | #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ | |
55 | #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ | |
56 | #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ | |
57 | #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ | |
358934a6 SP |
58 | |
59 | #define SPIINT_MASKALL 0x0101035F | |
e0d205e9 BN |
60 | #define SPIINT_MASKINT 0x0000015F |
61 | #define SPI_INTLVL_1 0x000001FF | |
62 | #define SPI_INTLVL_0 0x00000000 | |
358934a6 | 63 | |
cfbc5d1d BN |
64 | /* SPIDAT1 (upper 16 bit defines) */ |
65 | #define SPIDAT1_CSHOLD_MASK BIT(12) | |
66 | ||
67 | /* SPIGCR1 */ | |
358934a6 SP |
68 | #define SPIGCR1_CLKMOD_MASK BIT(1) |
69 | #define SPIGCR1_MASTER_MASK BIT(0) | |
70 | #define SPIGCR1_LOOPBACK_MASK BIT(16) | |
8e206f1c | 71 | #define SPIGCR1_SPIENA_MASK BIT(24) |
358934a6 SP |
72 | |
73 | /* SPIBUF */ | |
74 | #define SPIBUF_TXFULL_MASK BIT(29) | |
75 | #define SPIBUF_RXEMPTY_MASK BIT(31) | |
76 | ||
7abbf23c BN |
77 | /* SPIDELAY */ |
78 | #define SPIDELAY_C2TDELAY_SHIFT 24 | |
79 | #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) | |
80 | #define SPIDELAY_T2CDELAY_SHIFT 16 | |
81 | #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) | |
82 | #define SPIDELAY_T2EDELAY_SHIFT 8 | |
83 | #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) | |
84 | #define SPIDELAY_C2EDELAY_SHIFT 0 | |
85 | #define SPIDELAY_C2EDELAY_MASK 0xFF | |
86 | ||
358934a6 SP |
87 | /* Error Masks */ |
88 | #define SPIFLG_DLEN_ERR_MASK BIT(0) | |
89 | #define SPIFLG_TIMEOUT_MASK BIT(1) | |
90 | #define SPIFLG_PARERR_MASK BIT(2) | |
91 | #define SPIFLG_DESYNC_MASK BIT(3) | |
92 | #define SPIFLG_BITERR_MASK BIT(4) | |
93 | #define SPIFLG_OVRRUN_MASK BIT(6) | |
358934a6 | 94 | #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) |
839c996c BN |
95 | #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ |
96 | | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ | |
97 | | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ | |
98 | | SPIFLG_OVRRUN_MASK) | |
8e206f1c | 99 | |
358934a6 | 100 | #define SPIINT_DMA_REQ_EN BIT(16) |
358934a6 | 101 | |
358934a6 SP |
102 | /* SPI Controller registers */ |
103 | #define SPIGCR0 0x00 | |
104 | #define SPIGCR1 0x04 | |
105 | #define SPIINT 0x08 | |
106 | #define SPILVL 0x0c | |
107 | #define SPIFLG 0x10 | |
108 | #define SPIPC0 0x14 | |
358934a6 SP |
109 | #define SPIDAT1 0x3c |
110 | #define SPIBUF 0x40 | |
358934a6 SP |
111 | #define SPIDELAY 0x48 |
112 | #define SPIDEF 0x4c | |
113 | #define SPIFMT0 0x50 | |
358934a6 | 114 | |
358934a6 SP |
115 | /* We have 2 DMA channels per CS, one for RX and one for TX */ |
116 | struct davinci_spi_dma { | |
117 | int dma_tx_channel; | |
118 | int dma_rx_channel; | |
119 | int dma_tx_sync_dev; | |
120 | int dma_rx_sync_dev; | |
121 | enum dma_event_q eventq; | |
122 | ||
123 | struct completion dma_tx_completion; | |
124 | struct completion dma_rx_completion; | |
125 | }; | |
126 | ||
127 | /* SPI Controller driver's private data. */ | |
128 | struct davinci_spi { | |
129 | struct spi_bitbang bitbang; | |
130 | struct clk *clk; | |
131 | ||
132 | u8 version; | |
133 | resource_size_t pbase; | |
134 | void __iomem *base; | |
135 | size_t region_size; | |
e0d205e9 BN |
136 | u32 irq; |
137 | struct completion done; | |
358934a6 SP |
138 | |
139 | const void *tx; | |
140 | void *rx; | |
e0d205e9 BN |
141 | int rcount; |
142 | int wcount; | |
96fd881f | 143 | struct davinci_spi_dma dma_channels; |
778e261e | 144 | struct davinci_spi_platform_data *pdata; |
358934a6 SP |
145 | |
146 | void (*get_rx)(u32 rx_data, struct davinci_spi *); | |
147 | u32 (*get_tx)(struct davinci_spi *); | |
148 | ||
cda987eb | 149 | u8 bytes_per_word[SPI_MAX_CHIPSELECT]; |
358934a6 SP |
150 | }; |
151 | ||
53a31b07 BN |
152 | static struct davinci_spi_config davinci_spi_default_cfg; |
153 | ||
358934a6 SP |
154 | static unsigned use_dma; |
155 | ||
156 | static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi) | |
157 | { | |
53d454a1 BN |
158 | if (davinci_spi->rx) { |
159 | u8 *rx = davinci_spi->rx; | |
160 | *rx++ = (u8)data; | |
161 | davinci_spi->rx = rx; | |
162 | } | |
358934a6 SP |
163 | } |
164 | ||
165 | static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi) | |
166 | { | |
53d454a1 BN |
167 | if (davinci_spi->rx) { |
168 | u16 *rx = davinci_spi->rx; | |
169 | *rx++ = (u16)data; | |
170 | davinci_spi->rx = rx; | |
171 | } | |
358934a6 SP |
172 | } |
173 | ||
174 | static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi) | |
175 | { | |
53d454a1 BN |
176 | u32 data = 0; |
177 | if (davinci_spi->tx) { | |
178 | const u8 *tx = davinci_spi->tx; | |
179 | data = *tx++; | |
180 | davinci_spi->tx = tx; | |
181 | } | |
358934a6 SP |
182 | return data; |
183 | } | |
184 | ||
185 | static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi) | |
186 | { | |
53d454a1 BN |
187 | u32 data = 0; |
188 | if (davinci_spi->tx) { | |
189 | const u16 *tx = davinci_spi->tx; | |
190 | data = *tx++; | |
191 | davinci_spi->tx = tx; | |
192 | } | |
358934a6 SP |
193 | return data; |
194 | } | |
195 | ||
196 | static inline void set_io_bits(void __iomem *addr, u32 bits) | |
197 | { | |
198 | u32 v = ioread32(addr); | |
199 | ||
200 | v |= bits; | |
201 | iowrite32(v, addr); | |
202 | } | |
203 | ||
204 | static inline void clear_io_bits(void __iomem *addr, u32 bits) | |
205 | { | |
206 | u32 v = ioread32(addr); | |
207 | ||
208 | v &= ~bits; | |
209 | iowrite32(v, addr); | |
210 | } | |
211 | ||
358934a6 SP |
212 | static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable) |
213 | { | |
214 | struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); | |
215 | ||
216 | if (enable) | |
217 | set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); | |
218 | else | |
219 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); | |
220 | } | |
221 | ||
222 | /* | |
223 | * Interface to control the chip select signal | |
224 | */ | |
225 | static void davinci_spi_chipselect(struct spi_device *spi, int value) | |
226 | { | |
227 | struct davinci_spi *davinci_spi; | |
228 | struct davinci_spi_platform_data *pdata; | |
7978b8c3 | 229 | u8 chip_sel = spi->chip_select; |
cfbc5d1d | 230 | u16 spidat1_cfg = CS_DEFAULT; |
23853973 | 231 | bool gpio_chipsel = false; |
358934a6 SP |
232 | |
233 | davinci_spi = spi_master_get_devdata(spi->master); | |
234 | pdata = davinci_spi->pdata; | |
235 | ||
23853973 BN |
236 | if (pdata->chip_sel && chip_sel < pdata->num_chipselect && |
237 | pdata->chip_sel[chip_sel] != SPI_INTERN_CS) | |
238 | gpio_chipsel = true; | |
239 | ||
358934a6 SP |
240 | /* |
241 | * Board specific chip select logic decides the polarity and cs | |
242 | * line for the controller | |
243 | */ | |
23853973 BN |
244 | if (gpio_chipsel) { |
245 | if (value == BITBANG_CS_ACTIVE) | |
246 | gpio_set_value(pdata->chip_sel[chip_sel], 0); | |
247 | else | |
248 | gpio_set_value(pdata->chip_sel[chip_sel], 1); | |
249 | } else { | |
250 | if (value == BITBANG_CS_ACTIVE) { | |
251 | spidat1_cfg |= SPIDAT1_CSHOLD_MASK; | |
252 | spidat1_cfg &= ~(0x1 << chip_sel); | |
253 | } | |
7978b8c3 | 254 | |
23853973 BN |
255 | iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); |
256 | } | |
358934a6 SP |
257 | } |
258 | ||
7fe0092b BN |
259 | /** |
260 | * davinci_spi_get_prescale - Calculates the correct prescale value | |
261 | * @maxspeed_hz: the maximum rate the SPI clock can run at | |
262 | * | |
263 | * This function calculates the prescale value that generates a clock rate | |
264 | * less than or equal to the specified maximum. | |
265 | * | |
266 | * Returns: calculated prescale - 1 for easy programming into SPI registers | |
267 | * or negative error number if valid prescalar cannot be updated. | |
268 | */ | |
269 | static inline int davinci_spi_get_prescale(struct davinci_spi *davinci_spi, | |
270 | u32 max_speed_hz) | |
271 | { | |
272 | int ret; | |
273 | ||
274 | ret = DIV_ROUND_UP(clk_get_rate(davinci_spi->clk), max_speed_hz); | |
275 | ||
276 | if (ret < 3 || ret > 256) | |
277 | return -EINVAL; | |
278 | ||
279 | return ret - 1; | |
280 | } | |
281 | ||
358934a6 SP |
282 | /** |
283 | * davinci_spi_setup_transfer - This functions will determine transfer method | |
284 | * @spi: spi device on which data transfer to be done | |
285 | * @t: spi transfer in which transfer info is filled | |
286 | * | |
287 | * This function determines data transfer method (8/16/32 bit transfer). | |
288 | * It will also set the SPI Clock Control register according to | |
289 | * SPI slave device freq. | |
290 | */ | |
291 | static int davinci_spi_setup_transfer(struct spi_device *spi, | |
292 | struct spi_transfer *t) | |
293 | { | |
294 | ||
295 | struct davinci_spi *davinci_spi; | |
25f33512 | 296 | struct davinci_spi_config *spicfg; |
358934a6 | 297 | u8 bits_per_word = 0; |
25f33512 | 298 | u32 hz = 0, spifmt = 0, prescale = 0; |
358934a6 SP |
299 | |
300 | davinci_spi = spi_master_get_devdata(spi->master); | |
25f33512 BN |
301 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
302 | if (!spicfg) | |
303 | spicfg = &davinci_spi_default_cfg; | |
358934a6 SP |
304 | |
305 | if (t) { | |
306 | bits_per_word = t->bits_per_word; | |
307 | hz = t->speed_hz; | |
308 | } | |
309 | ||
310 | /* if bits_per_word is not set then set it default */ | |
311 | if (!bits_per_word) | |
312 | bits_per_word = spi->bits_per_word; | |
313 | ||
314 | /* | |
315 | * Assign function pointer to appropriate transfer method | |
316 | * 8bit, 16bit or 32bit transfer | |
317 | */ | |
318 | if (bits_per_word <= 8 && bits_per_word >= 2) { | |
319 | davinci_spi->get_rx = davinci_spi_rx_buf_u8; | |
320 | davinci_spi->get_tx = davinci_spi_tx_buf_u8; | |
cda987eb | 321 | davinci_spi->bytes_per_word[spi->chip_select] = 1; |
358934a6 SP |
322 | } else if (bits_per_word <= 16 && bits_per_word >= 2) { |
323 | davinci_spi->get_rx = davinci_spi_rx_buf_u16; | |
324 | davinci_spi->get_tx = davinci_spi_tx_buf_u16; | |
cda987eb | 325 | davinci_spi->bytes_per_word[spi->chip_select] = 2; |
358934a6 SP |
326 | } else |
327 | return -EINVAL; | |
328 | ||
329 | if (!hz) | |
330 | hz = spi->max_speed_hz; | |
331 | ||
25f33512 BN |
332 | /* Set up SPIFMTn register, unique to this chipselect. */ |
333 | ||
7fe0092b BN |
334 | prescale = davinci_spi_get_prescale(davinci_spi, hz); |
335 | if (prescale < 0) | |
336 | return prescale; | |
337 | ||
25f33512 BN |
338 | spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); |
339 | ||
340 | if (spi->mode & SPI_LSB_FIRST) | |
341 | spifmt |= SPIFMT_SHIFTDIR_MASK; | |
342 | ||
343 | if (spi->mode & SPI_CPOL) | |
344 | spifmt |= SPIFMT_POLARITY_MASK; | |
345 | ||
346 | if (!(spi->mode & SPI_CPHA)) | |
347 | spifmt |= SPIFMT_PHASE_MASK; | |
348 | ||
349 | /* | |
350 | * Version 1 hardware supports two basic SPI modes: | |
351 | * - Standard SPI mode uses 4 pins, with chipselect | |
352 | * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) | |
353 | * (distinct from SPI_3WIRE, with just one data wire; | |
354 | * or similar variants without MOSI or without MISO) | |
355 | * | |
356 | * Version 2 hardware supports an optional handshaking signal, | |
357 | * so it can support two more modes: | |
358 | * - 5 pin SPI variant is standard SPI plus SPI_READY | |
359 | * - 4 pin with enable is (SPI_READY | SPI_NO_CS) | |
360 | */ | |
361 | ||
362 | if (davinci_spi->version == SPI_VERSION_2) { | |
363 | ||
7abbf23c BN |
364 | u32 delay = 0; |
365 | ||
25f33512 BN |
366 | spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) |
367 | & SPIFMT_WDELAY_MASK); | |
358934a6 | 368 | |
25f33512 BN |
369 | if (spicfg->odd_parity) |
370 | spifmt |= SPIFMT_ODD_PARITY_MASK; | |
371 | ||
372 | if (spicfg->parity_enable) | |
373 | spifmt |= SPIFMT_PARITYENA_MASK; | |
374 | ||
7abbf23c | 375 | if (spicfg->timer_disable) { |
25f33512 | 376 | spifmt |= SPIFMT_DISTIMER_MASK; |
7abbf23c BN |
377 | } else { |
378 | delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) | |
379 | & SPIDELAY_C2TDELAY_MASK; | |
380 | delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) | |
381 | & SPIDELAY_T2CDELAY_MASK; | |
382 | } | |
25f33512 | 383 | |
7abbf23c | 384 | if (spi->mode & SPI_READY) { |
25f33512 | 385 | spifmt |= SPIFMT_WAITENA_MASK; |
7abbf23c BN |
386 | delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) |
387 | & SPIDELAY_T2EDELAY_MASK; | |
388 | delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) | |
389 | & SPIDELAY_C2EDELAY_MASK; | |
390 | } | |
391 | ||
392 | iowrite32(delay, davinci_spi->base + SPIDELAY); | |
25f33512 BN |
393 | } |
394 | ||
395 | iowrite32(spifmt, davinci_spi->base + SPIFMT0); | |
358934a6 SP |
396 | |
397 | return 0; | |
398 | } | |
399 | ||
400 | static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data) | |
401 | { | |
402 | struct spi_device *spi = (struct spi_device *)data; | |
403 | struct davinci_spi *davinci_spi; | |
404 | struct davinci_spi_dma *davinci_spi_dma; | |
358934a6 SP |
405 | |
406 | davinci_spi = spi_master_get_devdata(spi->master); | |
96fd881f | 407 | davinci_spi_dma = &davinci_spi->dma_channels; |
358934a6 SP |
408 | |
409 | if (ch_status == DMA_COMPLETE) | |
410 | edma_stop(davinci_spi_dma->dma_rx_channel); | |
411 | else | |
412 | edma_clean_channel(davinci_spi_dma->dma_rx_channel); | |
413 | ||
414 | complete(&davinci_spi_dma->dma_rx_completion); | |
415 | /* We must disable the DMA RX request */ | |
416 | davinci_spi_set_dma_req(spi, 0); | |
417 | } | |
418 | ||
419 | static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data) | |
420 | { | |
421 | struct spi_device *spi = (struct spi_device *)data; | |
422 | struct davinci_spi *davinci_spi; | |
423 | struct davinci_spi_dma *davinci_spi_dma; | |
358934a6 SP |
424 | |
425 | davinci_spi = spi_master_get_devdata(spi->master); | |
96fd881f | 426 | davinci_spi_dma = &davinci_spi->dma_channels; |
358934a6 SP |
427 | |
428 | if (ch_status == DMA_COMPLETE) | |
429 | edma_stop(davinci_spi_dma->dma_tx_channel); | |
430 | else | |
431 | edma_clean_channel(davinci_spi_dma->dma_tx_channel); | |
432 | ||
433 | complete(&davinci_spi_dma->dma_tx_completion); | |
434 | /* We must disable the DMA TX request */ | |
435 | davinci_spi_set_dma_req(spi, 0); | |
436 | } | |
437 | ||
438 | static int davinci_spi_request_dma(struct spi_device *spi) | |
439 | { | |
440 | struct davinci_spi *davinci_spi; | |
441 | struct davinci_spi_dma *davinci_spi_dma; | |
358934a6 SP |
442 | struct device *sdev; |
443 | int r; | |
444 | ||
445 | davinci_spi = spi_master_get_devdata(spi->master); | |
96fd881f | 446 | davinci_spi_dma = &davinci_spi->dma_channels; |
358934a6 SP |
447 | sdev = davinci_spi->bitbang.master->dev.parent; |
448 | ||
449 | r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev, | |
450 | davinci_spi_dma_rx_callback, spi, | |
451 | davinci_spi_dma->eventq); | |
452 | if (r < 0) { | |
453 | dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n"); | |
454 | return -EAGAIN; | |
455 | } | |
456 | davinci_spi_dma->dma_rx_channel = r; | |
457 | r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev, | |
458 | davinci_spi_dma_tx_callback, spi, | |
459 | davinci_spi_dma->eventq); | |
460 | if (r < 0) { | |
461 | edma_free_channel(davinci_spi_dma->dma_rx_channel); | |
462 | davinci_spi_dma->dma_rx_channel = -1; | |
463 | dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n"); | |
464 | return -EAGAIN; | |
465 | } | |
466 | davinci_spi_dma->dma_tx_channel = r; | |
467 | ||
468 | return 0; | |
469 | } | |
470 | ||
471 | /** | |
472 | * davinci_spi_setup - This functions will set default transfer method | |
473 | * @spi: spi device on which data transfer to be done | |
474 | * | |
475 | * This functions sets the default transfer method. | |
476 | */ | |
358934a6 SP |
477 | static int davinci_spi_setup(struct spi_device *spi) |
478 | { | |
b23a5d46 | 479 | int retval = 0; |
358934a6 SP |
480 | struct davinci_spi *davinci_spi; |
481 | struct davinci_spi_dma *davinci_spi_dma; | |
be88471b | 482 | struct davinci_spi_platform_data *pdata; |
358934a6 SP |
483 | |
484 | davinci_spi = spi_master_get_devdata(spi->master); | |
be88471b | 485 | pdata = davinci_spi->pdata; |
358934a6 SP |
486 | |
487 | /* if bits per word length is zero then set it default 8 */ | |
488 | if (!spi->bits_per_word) | |
489 | spi->bits_per_word = 8; | |
490 | ||
be88471b BN |
491 | if (!(spi->mode & SPI_NO_CS)) { |
492 | if ((pdata->chip_sel == NULL) || | |
493 | (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) | |
494 | set_io_bits(davinci_spi->base + SPIPC0, | |
495 | 1 << spi->chip_select); | |
496 | ||
497 | } | |
498 | ||
499 | if (spi->mode & SPI_READY) | |
500 | set_io_bits(davinci_spi->base + SPIPC0, SPIPC0_SPIENA_MASK); | |
501 | ||
502 | if (spi->mode & SPI_LOOP) | |
503 | set_io_bits(davinci_spi->base + SPIGCR1, | |
504 | SPIGCR1_LOOPBACK_MASK); | |
505 | else | |
506 | clear_io_bits(davinci_spi->base + SPIGCR1, | |
507 | SPIGCR1_LOOPBACK_MASK); | |
508 | ||
96fd881f BN |
509 | if (use_dma) { |
510 | davinci_spi_dma = &davinci_spi->dma_channels; | |
358934a6 | 511 | |
b23a5d46 BN |
512 | if ((davinci_spi_dma->dma_rx_channel == -1) || |
513 | (davinci_spi_dma->dma_tx_channel == -1)) | |
358934a6 | 514 | retval = davinci_spi_request_dma(spi); |
358934a6 SP |
515 | } |
516 | ||
358934a6 SP |
517 | return retval; |
518 | } | |
519 | ||
520 | static void davinci_spi_cleanup(struct spi_device *spi) | |
521 | { | |
96fd881f BN |
522 | if (use_dma) { |
523 | struct davinci_spi *davinci_spi = | |
524 | spi_master_get_devdata(spi->master); | |
525 | struct davinci_spi_dma *davinci_spi_dma = | |
526 | &davinci_spi->dma_channels; | |
358934a6 SP |
527 | |
528 | if ((davinci_spi_dma->dma_rx_channel != -1) | |
529 | && (davinci_spi_dma->dma_tx_channel != -1)) { | |
530 | edma_free_channel(davinci_spi_dma->dma_tx_channel); | |
531 | edma_free_channel(davinci_spi_dma->dma_rx_channel); | |
532 | } | |
533 | } | |
534 | } | |
535 | ||
358934a6 SP |
536 | static int davinci_spi_check_error(struct davinci_spi *davinci_spi, |
537 | int int_status) | |
538 | { | |
539 | struct device *sdev = davinci_spi->bitbang.master->dev.parent; | |
540 | ||
541 | if (int_status & SPIFLG_TIMEOUT_MASK) { | |
542 | dev_dbg(sdev, "SPI Time-out Error\n"); | |
543 | return -ETIMEDOUT; | |
544 | } | |
545 | if (int_status & SPIFLG_DESYNC_MASK) { | |
546 | dev_dbg(sdev, "SPI Desynchronization Error\n"); | |
547 | return -EIO; | |
548 | } | |
549 | if (int_status & SPIFLG_BITERR_MASK) { | |
550 | dev_dbg(sdev, "SPI Bit error\n"); | |
551 | return -EIO; | |
552 | } | |
553 | ||
554 | if (davinci_spi->version == SPI_VERSION_2) { | |
555 | if (int_status & SPIFLG_DLEN_ERR_MASK) { | |
556 | dev_dbg(sdev, "SPI Data Length Error\n"); | |
557 | return -EIO; | |
558 | } | |
559 | if (int_status & SPIFLG_PARERR_MASK) { | |
560 | dev_dbg(sdev, "SPI Parity Error\n"); | |
561 | return -EIO; | |
562 | } | |
563 | if (int_status & SPIFLG_OVRRUN_MASK) { | |
564 | dev_dbg(sdev, "SPI Data Overrun error\n"); | |
565 | return -EIO; | |
566 | } | |
358934a6 SP |
567 | if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { |
568 | dev_dbg(sdev, "SPI Buffer Init Active\n"); | |
569 | return -EBUSY; | |
570 | } | |
571 | } | |
572 | ||
573 | return 0; | |
574 | } | |
575 | ||
e0d205e9 BN |
576 | /** |
577 | * davinci_spi_process_events - check for and handle any SPI controller events | |
578 | * @davinci_spi: the controller data | |
579 | * | |
580 | * This function will check the SPIFLG register and handle any events that are | |
581 | * detected there | |
582 | */ | |
583 | static int davinci_spi_process_events(struct davinci_spi *davinci_spi) | |
584 | { | |
585 | u32 buf, status, errors = 0, data1_reg_val; | |
586 | ||
587 | buf = ioread32(davinci_spi->base + SPIBUF); | |
588 | ||
589 | if (davinci_spi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { | |
590 | davinci_spi->get_rx(buf & 0xFFFF, davinci_spi); | |
591 | davinci_spi->rcount--; | |
592 | } | |
593 | ||
594 | status = ioread32(davinci_spi->base + SPIFLG); | |
595 | ||
596 | if (unlikely(status & SPIFLG_ERROR_MASK)) { | |
597 | errors = status & SPIFLG_ERROR_MASK; | |
598 | goto out; | |
599 | } | |
600 | ||
601 | if (davinci_spi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { | |
602 | data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); | |
603 | davinci_spi->wcount--; | |
604 | data1_reg_val &= ~0xFFFF; | |
605 | data1_reg_val |= 0xFFFF & davinci_spi->get_tx(davinci_spi); | |
606 | iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); | |
607 | } | |
608 | ||
609 | out: | |
610 | return errors; | |
611 | } | |
612 | ||
358934a6 SP |
613 | /** |
614 | * davinci_spi_bufs - functions which will handle transfer data | |
615 | * @spi: spi device on which data transfer to be done | |
616 | * @t: spi transfer in which transfer info is filled | |
617 | * | |
618 | * This function will put data to be transferred into data register | |
619 | * of SPI controller and then wait until the completion will be marked | |
620 | * by the IRQ Handler. | |
621 | */ | |
622 | static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t) | |
623 | { | |
624 | struct davinci_spi *davinci_spi; | |
839c996c | 625 | int ret; |
358934a6 | 626 | u32 tx_data, data1_reg_val; |
839c996c | 627 | u32 errors = 0; |
e0d205e9 | 628 | struct davinci_spi_config *spicfg; |
358934a6 SP |
629 | struct davinci_spi_platform_data *pdata; |
630 | ||
631 | davinci_spi = spi_master_get_devdata(spi->master); | |
632 | pdata = davinci_spi->pdata; | |
e0d205e9 BN |
633 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
634 | if (!spicfg) | |
635 | spicfg = &davinci_spi_default_cfg; | |
358934a6 SP |
636 | |
637 | davinci_spi->tx = t->tx_buf; | |
638 | davinci_spi->rx = t->rx_buf; | |
e0d205e9 BN |
639 | davinci_spi->wcount = t->len / |
640 | davinci_spi->bytes_per_word[spi->chip_select]; | |
641 | davinci_spi->rcount = davinci_spi->wcount; | |
7978b8c3 | 642 | |
839c996c BN |
643 | data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); |
644 | ||
358934a6 SP |
645 | /* Enable SPI */ |
646 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | |
647 | ||
e0d205e9 BN |
648 | if (spicfg->io_type == SPI_IO_TYPE_INTR) { |
649 | set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); | |
650 | INIT_COMPLETION(davinci_spi->done); | |
651 | } | |
cf90fe73 | 652 | |
839c996c | 653 | /* start the transfer */ |
e0d205e9 | 654 | davinci_spi->wcount--; |
839c996c BN |
655 | tx_data = davinci_spi->get_tx(davinci_spi); |
656 | data1_reg_val &= 0xFFFF0000; | |
657 | data1_reg_val |= tx_data & 0xFFFF; | |
658 | iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); | |
358934a6 | 659 | |
e0d205e9 BN |
660 | /* Wait for the transfer to complete */ |
661 | if (spicfg->io_type == SPI_IO_TYPE_INTR) { | |
662 | wait_for_completion_interruptible(&(davinci_spi->done)); | |
663 | } else { | |
664 | while (davinci_spi->rcount > 0 || davinci_spi->wcount > 0) { | |
665 | errors = davinci_spi_process_events(davinci_spi); | |
666 | if (errors) | |
667 | break; | |
668 | cpu_relax(); | |
358934a6 SP |
669 | } |
670 | } | |
671 | ||
e0d205e9 BN |
672 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); |
673 | ||
358934a6 SP |
674 | /* |
675 | * Check for bit error, desync error,parity error,timeout error and | |
676 | * receive overflow errors | |
677 | */ | |
839c996c BN |
678 | if (errors) { |
679 | ret = davinci_spi_check_error(davinci_spi, errors); | |
680 | WARN(!ret, "%s: error reported but no error found!\n", | |
681 | dev_name(&spi->dev)); | |
358934a6 | 682 | return ret; |
839c996c | 683 | } |
358934a6 | 684 | |
358934a6 SP |
685 | return t->len; |
686 | } | |
687 | ||
e0d205e9 BN |
688 | /** |
689 | * davinci_spi_irq - Interrupt handler for SPI Master Controller | |
690 | * @irq: IRQ number for this SPI Master | |
691 | * @context_data: structure for SPI Master controller davinci_spi | |
692 | * | |
693 | * ISR will determine that interrupt arrives either for READ or WRITE command. | |
694 | * According to command it will do the appropriate action. It will check | |
695 | * transfer length and if it is not zero then dispatch transfer command again. | |
696 | * If transfer length is zero then it will indicate the COMPLETION so that | |
697 | * davinci_spi_bufs function can go ahead. | |
698 | */ | |
699 | static irqreturn_t davinci_spi_irq(s32 irq, void *context_data) | |
700 | { | |
701 | struct davinci_spi *davinci_spi = context_data; | |
702 | int status; | |
703 | ||
704 | status = davinci_spi_process_events(davinci_spi); | |
705 | if (unlikely(status != 0)) | |
706 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); | |
707 | ||
708 | if ((!davinci_spi->rcount && !davinci_spi->wcount) || status) | |
709 | complete(&davinci_spi->done); | |
710 | ||
711 | return IRQ_HANDLED; | |
712 | } | |
713 | ||
358934a6 SP |
714 | static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t) |
715 | { | |
716 | struct davinci_spi *davinci_spi; | |
717 | int int_status = 0; | |
d3f7141c | 718 | int count; |
358934a6 | 719 | struct davinci_spi_dma *davinci_spi_dma; |
b7ab24a0 | 720 | int data_type, ret; |
358934a6 | 721 | unsigned long tx_reg, rx_reg; |
c29e3c60 | 722 | struct davinci_spi_platform_data *pdata; |
358934a6 SP |
723 | struct device *sdev; |
724 | ||
725 | davinci_spi = spi_master_get_devdata(spi->master); | |
c29e3c60 | 726 | pdata = davinci_spi->pdata; |
358934a6 SP |
727 | sdev = davinci_spi->bitbang.master->dev.parent; |
728 | ||
96fd881f | 729 | davinci_spi_dma = &davinci_spi->dma_channels; |
358934a6 SP |
730 | |
731 | tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1; | |
732 | rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF; | |
733 | ||
734 | davinci_spi->tx = t->tx_buf; | |
735 | davinci_spi->rx = t->rx_buf; | |
736 | ||
737 | /* convert len to words based on bits_per_word */ | |
b7ab24a0 | 738 | data_type = davinci_spi->bytes_per_word[spi->chip_select]; |
358934a6 | 739 | |
358934a6 SP |
740 | init_completion(&davinci_spi_dma->dma_rx_completion); |
741 | init_completion(&davinci_spi_dma->dma_tx_completion); | |
742 | ||
f2bf4e84 | 743 | count = t->len / data_type; /* the number of elements */ |
358934a6 SP |
744 | |
745 | /* disable all interrupts for dma transfers */ | |
746 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); | |
358934a6 SP |
747 | /* Enable SPI */ |
748 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | |
749 | ||
d3f7141c BN |
750 | /* |
751 | * Transmit DMA setup | |
752 | * | |
753 | * If there is transmit data, map the transmit buffer, set it as the | |
754 | * source of data and set the source B index to data size. | |
755 | * If there is no transmit data, set the transmit register as the | |
756 | * source of data, and set the source B index to zero. | |
757 | * | |
758 | * The destination is always the transmit register itself. And the | |
759 | * destination never increments. | |
760 | */ | |
761 | ||
358934a6 SP |
762 | if (t->tx_buf) { |
763 | t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count, | |
764 | DMA_TO_DEVICE); | |
765 | if (dma_mapping_error(&spi->dev, t->tx_dma)) { | |
766 | dev_dbg(sdev, "Unable to DMA map a %d bytes" | |
767 | " TX buffer\n", count); | |
768 | return -ENOMEM; | |
769 | } | |
358934a6 SP |
770 | } |
771 | ||
772 | edma_set_transfer_params(davinci_spi_dma->dma_tx_channel, | |
d3f7141c | 773 | data_type, count, 1, 0, ASYNC); |
358934a6 | 774 | edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT); |
d3f7141c BN |
775 | edma_set_src(davinci_spi_dma->dma_tx_channel, |
776 | t->tx_buf ? t->tx_dma : tx_reg, INCR, W8BIT); | |
777 | edma_set_src_index(davinci_spi_dma->dma_tx_channel, | |
778 | t->tx_buf ? data_type : 0, 0); | |
358934a6 SP |
779 | edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0); |
780 | ||
781 | if (t->rx_buf) { | |
358934a6 SP |
782 | t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count, |
783 | DMA_FROM_DEVICE); | |
784 | if (dma_mapping_error(&spi->dev, t->rx_dma)) { | |
785 | dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", | |
786 | count); | |
787 | if (t->tx_buf != NULL) | |
788 | dma_unmap_single(NULL, t->tx_dma, | |
789 | count, DMA_TO_DEVICE); | |
790 | return -ENOMEM; | |
791 | } | |
792 | edma_set_transfer_params(davinci_spi_dma->dma_rx_channel, | |
793 | data_type, count, 1, 0, ASYNC); | |
794 | edma_set_src(davinci_spi_dma->dma_rx_channel, | |
795 | rx_reg, INCR, W8BIT); | |
796 | edma_set_dest(davinci_spi_dma->dma_rx_channel, | |
797 | t->rx_dma, INCR, W8BIT); | |
798 | edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0); | |
799 | edma_set_dest_index(davinci_spi_dma->dma_rx_channel, | |
800 | data_type, 0); | |
801 | } | |
802 | ||
c29e3c60 BN |
803 | if (pdata->cshold_bug) { |
804 | u16 spidat1 = ioread16(davinci_spi->base + SPIDAT1 + 2); | |
805 | iowrite16(spidat1, davinci_spi->base + SPIDAT1 + 2); | |
806 | } | |
358934a6 SP |
807 | |
808 | if (t->rx_buf) | |
809 | edma_start(davinci_spi_dma->dma_rx_channel); | |
810 | ||
c29e3c60 BN |
811 | edma_start(davinci_spi_dma->dma_tx_channel); |
812 | davinci_spi_set_dma_req(spi, 1); | |
358934a6 | 813 | |
c29e3c60 | 814 | wait_for_completion_interruptible(&davinci_spi_dma->dma_tx_completion); |
358934a6 SP |
815 | |
816 | if (t->rx_buf) | |
817 | wait_for_completion_interruptible( | |
818 | &davinci_spi_dma->dma_rx_completion); | |
819 | ||
d3f7141c BN |
820 | if (t->tx_buf) |
821 | dma_unmap_single(NULL, t->tx_dma, count, DMA_TO_DEVICE); | |
358934a6 SP |
822 | |
823 | if (t->rx_buf) | |
824 | dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE); | |
825 | ||
826 | /* | |
827 | * Check for bit error, desync error,parity error,timeout error and | |
828 | * receive overflow errors | |
829 | */ | |
830 | int_status = ioread32(davinci_spi->base + SPIFLG); | |
831 | ||
832 | ret = davinci_spi_check_error(davinci_spi, int_status); | |
833 | if (ret != 0) | |
834 | return ret; | |
835 | ||
358934a6 SP |
836 | return t->len; |
837 | } | |
838 | ||
358934a6 SP |
839 | /** |
840 | * davinci_spi_probe - probe function for SPI Master Controller | |
841 | * @pdev: platform_device structure which contains plateform specific data | |
842 | */ | |
843 | static int davinci_spi_probe(struct platform_device *pdev) | |
844 | { | |
845 | struct spi_master *master; | |
846 | struct davinci_spi *davinci_spi; | |
847 | struct davinci_spi_platform_data *pdata; | |
848 | struct resource *r, *mem; | |
849 | resource_size_t dma_rx_chan = SPI_NO_RESOURCE; | |
850 | resource_size_t dma_tx_chan = SPI_NO_RESOURCE; | |
851 | resource_size_t dma_eventq = SPI_NO_RESOURCE; | |
852 | int i = 0, ret = 0; | |
f34bd4cc | 853 | u32 spipc0; |
358934a6 SP |
854 | |
855 | pdata = pdev->dev.platform_data; | |
856 | if (pdata == NULL) { | |
857 | ret = -ENODEV; | |
858 | goto err; | |
859 | } | |
860 | ||
861 | master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); | |
862 | if (master == NULL) { | |
863 | ret = -ENOMEM; | |
864 | goto err; | |
865 | } | |
866 | ||
867 | dev_set_drvdata(&pdev->dev, master); | |
868 | ||
869 | davinci_spi = spi_master_get_devdata(master); | |
870 | if (davinci_spi == NULL) { | |
871 | ret = -ENOENT; | |
872 | goto free_master; | |
873 | } | |
874 | ||
875 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
876 | if (r == NULL) { | |
877 | ret = -ENOENT; | |
878 | goto free_master; | |
879 | } | |
880 | ||
881 | davinci_spi->pbase = r->start; | |
882 | davinci_spi->region_size = resource_size(r); | |
883 | davinci_spi->pdata = pdata; | |
884 | ||
885 | mem = request_mem_region(r->start, davinci_spi->region_size, | |
886 | pdev->name); | |
887 | if (mem == NULL) { | |
888 | ret = -EBUSY; | |
889 | goto free_master; | |
890 | } | |
891 | ||
50356dd7 | 892 | davinci_spi->base = ioremap(r->start, davinci_spi->region_size); |
358934a6 SP |
893 | if (davinci_spi->base == NULL) { |
894 | ret = -ENOMEM; | |
895 | goto release_region; | |
896 | } | |
897 | ||
e0d205e9 BN |
898 | davinci_spi->irq = platform_get_irq(pdev, 0); |
899 | if (davinci_spi->irq <= 0) { | |
900 | ret = -EINVAL; | |
901 | goto unmap_io; | |
902 | } | |
903 | ||
904 | ret = request_irq(davinci_spi->irq, davinci_spi_irq, 0, | |
905 | dev_name(&pdev->dev), davinci_spi); | |
906 | if (ret) | |
907 | goto unmap_io; | |
908 | ||
358934a6 SP |
909 | davinci_spi->bitbang.master = spi_master_get(master); |
910 | if (davinci_spi->bitbang.master == NULL) { | |
911 | ret = -ENODEV; | |
d3f7141c | 912 | goto irq_free; |
358934a6 SP |
913 | } |
914 | ||
915 | davinci_spi->clk = clk_get(&pdev->dev, NULL); | |
916 | if (IS_ERR(davinci_spi->clk)) { | |
917 | ret = -ENODEV; | |
918 | goto put_master; | |
919 | } | |
920 | clk_enable(davinci_spi->clk); | |
921 | ||
358934a6 SP |
922 | master->bus_num = pdev->id; |
923 | master->num_chipselect = pdata->num_chipselect; | |
924 | master->setup = davinci_spi_setup; | |
925 | master->cleanup = davinci_spi_cleanup; | |
926 | ||
927 | davinci_spi->bitbang.chipselect = davinci_spi_chipselect; | |
928 | davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer; | |
929 | ||
930 | davinci_spi->version = pdata->version; | |
931 | use_dma = pdata->use_dma; | |
932 | ||
933 | davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; | |
934 | if (davinci_spi->version == SPI_VERSION_2) | |
935 | davinci_spi->bitbang.flags |= SPI_READY; | |
936 | ||
937 | if (use_dma) { | |
778e261e BN |
938 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
939 | if (r) | |
940 | dma_rx_chan = r->start; | |
941 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
942 | if (r) | |
943 | dma_tx_chan = r->start; | |
944 | r = platform_get_resource(pdev, IORESOURCE_DMA, 2); | |
945 | if (r) | |
946 | dma_eventq = r->start; | |
358934a6 SP |
947 | } |
948 | ||
949 | if (!use_dma || | |
950 | dma_rx_chan == SPI_NO_RESOURCE || | |
951 | dma_tx_chan == SPI_NO_RESOURCE || | |
952 | dma_eventq == SPI_NO_RESOURCE) { | |
953 | davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio; | |
954 | use_dma = 0; | |
955 | } else { | |
956 | davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma; | |
358934a6 | 957 | |
96fd881f BN |
958 | davinci_spi->dma_channels.dma_rx_channel = -1; |
959 | davinci_spi->dma_channels.dma_rx_sync_dev = dma_rx_chan; | |
960 | davinci_spi->dma_channels.dma_tx_channel = -1; | |
961 | davinci_spi->dma_channels.dma_tx_sync_dev = dma_tx_chan; | |
962 | davinci_spi->dma_channels.eventq = dma_eventq; | |
963 | ||
358934a6 SP |
964 | dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n" |
965 | "Using RX channel = %d , TX channel = %d and " | |
966 | "event queue = %d", dma_rx_chan, dma_tx_chan, | |
967 | dma_eventq); | |
968 | } | |
969 | ||
970 | davinci_spi->get_rx = davinci_spi_rx_buf_u8; | |
971 | davinci_spi->get_tx = davinci_spi_tx_buf_u8; | |
972 | ||
e0d205e9 BN |
973 | init_completion(&davinci_spi->done); |
974 | ||
358934a6 SP |
975 | /* Reset In/OUT SPI module */ |
976 | iowrite32(0, davinci_spi->base + SPIGCR0); | |
977 | udelay(100); | |
978 | iowrite32(1, davinci_spi->base + SPIGCR0); | |
979 | ||
be88471b | 980 | /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ |
f34bd4cc BN |
981 | spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; |
982 | iowrite32(spipc0, davinci_spi->base + SPIPC0); | |
983 | ||
23853973 BN |
984 | /* initialize chip selects */ |
985 | if (pdata->chip_sel) { | |
986 | for (i = 0; i < pdata->num_chipselect; i++) { | |
987 | if (pdata->chip_sel[i] != SPI_INTERN_CS) | |
988 | gpio_direction_output(pdata->chip_sel[i], 1); | |
989 | } | |
990 | } | |
991 | ||
358934a6 SP |
992 | /* Clock internal */ |
993 | if (davinci_spi->pdata->clk_internal) | |
994 | set_io_bits(davinci_spi->base + SPIGCR1, | |
995 | SPIGCR1_CLKMOD_MASK); | |
996 | else | |
997 | clear_io_bits(davinci_spi->base + SPIGCR1, | |
998 | SPIGCR1_CLKMOD_MASK); | |
999 | ||
e0d205e9 BN |
1000 | if (pdata->intr_line) |
1001 | iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); | |
1002 | else | |
1003 | iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); | |
1004 | ||
843a713b BN |
1005 | iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF); |
1006 | ||
358934a6 SP |
1007 | /* master mode default */ |
1008 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); | |
1009 | ||
358934a6 SP |
1010 | ret = spi_bitbang_start(&davinci_spi->bitbang); |
1011 | if (ret) | |
1012 | goto free_clk; | |
1013 | ||
3b740b10 | 1014 | dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base); |
358934a6 | 1015 | |
358934a6 SP |
1016 | return ret; |
1017 | ||
1018 | free_clk: | |
1019 | clk_disable(davinci_spi->clk); | |
1020 | clk_put(davinci_spi->clk); | |
1021 | put_master: | |
1022 | spi_master_put(master); | |
e0d205e9 BN |
1023 | irq_free: |
1024 | free_irq(davinci_spi->irq, davinci_spi); | |
358934a6 SP |
1025 | unmap_io: |
1026 | iounmap(davinci_spi->base); | |
1027 | release_region: | |
1028 | release_mem_region(davinci_spi->pbase, davinci_spi->region_size); | |
1029 | free_master: | |
1030 | kfree(master); | |
1031 | err: | |
1032 | return ret; | |
1033 | } | |
1034 | ||
1035 | /** | |
1036 | * davinci_spi_remove - remove function for SPI Master Controller | |
1037 | * @pdev: platform_device structure which contains plateform specific data | |
1038 | * | |
1039 | * This function will do the reverse action of davinci_spi_probe function | |
1040 | * It will free the IRQ and SPI controller's memory region. | |
1041 | * It will also call spi_bitbang_stop to destroy the work queue which was | |
1042 | * created by spi_bitbang_start. | |
1043 | */ | |
1044 | static int __exit davinci_spi_remove(struct platform_device *pdev) | |
1045 | { | |
1046 | struct davinci_spi *davinci_spi; | |
1047 | struct spi_master *master; | |
1048 | ||
1049 | master = dev_get_drvdata(&pdev->dev); | |
1050 | davinci_spi = spi_master_get_devdata(master); | |
1051 | ||
1052 | spi_bitbang_stop(&davinci_spi->bitbang); | |
1053 | ||
1054 | clk_disable(davinci_spi->clk); | |
1055 | clk_put(davinci_spi->clk); | |
1056 | spi_master_put(master); | |
e0d205e9 | 1057 | free_irq(davinci_spi->irq, davinci_spi); |
358934a6 SP |
1058 | iounmap(davinci_spi->base); |
1059 | release_mem_region(davinci_spi->pbase, davinci_spi->region_size); | |
1060 | ||
1061 | return 0; | |
1062 | } | |
1063 | ||
1064 | static struct platform_driver davinci_spi_driver = { | |
1065 | .driver.name = "spi_davinci", | |
1066 | .remove = __exit_p(davinci_spi_remove), | |
1067 | }; | |
1068 | ||
1069 | static int __init davinci_spi_init(void) | |
1070 | { | |
1071 | return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe); | |
1072 | } | |
1073 | module_init(davinci_spi_init); | |
1074 | ||
1075 | static void __exit davinci_spi_exit(void) | |
1076 | { | |
1077 | platform_driver_unregister(&davinci_spi_driver); | |
1078 | } | |
1079 | module_exit(davinci_spi_exit); | |
1080 | ||
1081 | MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); | |
1082 | MODULE_LICENSE("GPL"); |