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358934a6 SP |
1 | /* |
2 | * Copyright (C) 2009 Texas Instruments. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
19 | #include <linux/interrupt.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/gpio.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/dma-mapping.h> | |
28 | #include <linux/spi/spi.h> | |
29 | #include <linux/spi/spi_bitbang.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
358934a6 SP |
31 | |
32 | #include <mach/spi.h> | |
33 | #include <mach/edma.h> | |
34 | ||
35 | #define SPI_NO_RESOURCE ((resource_size_t)-1) | |
36 | ||
37 | #define SPI_MAX_CHIPSELECT 2 | |
38 | ||
39 | #define CS_DEFAULT 0xFF | |
40 | ||
358934a6 SP |
41 | #define SPIFMT_PHASE_MASK BIT(16) |
42 | #define SPIFMT_POLARITY_MASK BIT(17) | |
43 | #define SPIFMT_DISTIMER_MASK BIT(18) | |
44 | #define SPIFMT_SHIFTDIR_MASK BIT(20) | |
45 | #define SPIFMT_WAITENA_MASK BIT(21) | |
46 | #define SPIFMT_PARITYENA_MASK BIT(22) | |
47 | #define SPIFMT_ODD_PARITY_MASK BIT(23) | |
48 | #define SPIFMT_WDELAY_MASK 0x3f000000u | |
49 | #define SPIFMT_WDELAY_SHIFT 24 | |
7fe0092b | 50 | #define SPIFMT_PRESCALE_SHIFT 8 |
358934a6 | 51 | |
358934a6 SP |
52 | /* SPIPC0 */ |
53 | #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ | |
54 | #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ | |
55 | #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ | |
56 | #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ | |
358934a6 SP |
57 | |
58 | #define SPIINT_MASKALL 0x0101035F | |
e0d205e9 BN |
59 | #define SPIINT_MASKINT 0x0000015F |
60 | #define SPI_INTLVL_1 0x000001FF | |
61 | #define SPI_INTLVL_0 0x00000000 | |
358934a6 | 62 | |
cfbc5d1d BN |
63 | /* SPIDAT1 (upper 16 bit defines) */ |
64 | #define SPIDAT1_CSHOLD_MASK BIT(12) | |
65 | ||
66 | /* SPIGCR1 */ | |
358934a6 SP |
67 | #define SPIGCR1_CLKMOD_MASK BIT(1) |
68 | #define SPIGCR1_MASTER_MASK BIT(0) | |
3f27b57c | 69 | #define SPIGCR1_POWERDOWN_MASK BIT(8) |
358934a6 | 70 | #define SPIGCR1_LOOPBACK_MASK BIT(16) |
8e206f1c | 71 | #define SPIGCR1_SPIENA_MASK BIT(24) |
358934a6 SP |
72 | |
73 | /* SPIBUF */ | |
74 | #define SPIBUF_TXFULL_MASK BIT(29) | |
75 | #define SPIBUF_RXEMPTY_MASK BIT(31) | |
76 | ||
7abbf23c BN |
77 | /* SPIDELAY */ |
78 | #define SPIDELAY_C2TDELAY_SHIFT 24 | |
79 | #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) | |
80 | #define SPIDELAY_T2CDELAY_SHIFT 16 | |
81 | #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) | |
82 | #define SPIDELAY_T2EDELAY_SHIFT 8 | |
83 | #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) | |
84 | #define SPIDELAY_C2EDELAY_SHIFT 0 | |
85 | #define SPIDELAY_C2EDELAY_MASK 0xFF | |
86 | ||
358934a6 SP |
87 | /* Error Masks */ |
88 | #define SPIFLG_DLEN_ERR_MASK BIT(0) | |
89 | #define SPIFLG_TIMEOUT_MASK BIT(1) | |
90 | #define SPIFLG_PARERR_MASK BIT(2) | |
91 | #define SPIFLG_DESYNC_MASK BIT(3) | |
92 | #define SPIFLG_BITERR_MASK BIT(4) | |
93 | #define SPIFLG_OVRRUN_MASK BIT(6) | |
358934a6 | 94 | #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) |
839c996c BN |
95 | #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ |
96 | | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ | |
97 | | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ | |
98 | | SPIFLG_OVRRUN_MASK) | |
8e206f1c | 99 | |
358934a6 | 100 | #define SPIINT_DMA_REQ_EN BIT(16) |
358934a6 | 101 | |
358934a6 SP |
102 | /* SPI Controller registers */ |
103 | #define SPIGCR0 0x00 | |
104 | #define SPIGCR1 0x04 | |
105 | #define SPIINT 0x08 | |
106 | #define SPILVL 0x0c | |
107 | #define SPIFLG 0x10 | |
108 | #define SPIPC0 0x14 | |
358934a6 SP |
109 | #define SPIDAT1 0x3c |
110 | #define SPIBUF 0x40 | |
358934a6 SP |
111 | #define SPIDELAY 0x48 |
112 | #define SPIDEF 0x4c | |
113 | #define SPIFMT0 0x50 | |
358934a6 | 114 | |
358934a6 SP |
115 | /* We have 2 DMA channels per CS, one for RX and one for TX */ |
116 | struct davinci_spi_dma { | |
117 | int dma_tx_channel; | |
118 | int dma_rx_channel; | |
523c37e7 | 119 | int dummy_param_slot; |
358934a6 | 120 | enum dma_event_q eventq; |
358934a6 SP |
121 | }; |
122 | ||
123 | /* SPI Controller driver's private data. */ | |
124 | struct davinci_spi { | |
125 | struct spi_bitbang bitbang; | |
126 | struct clk *clk; | |
127 | ||
128 | u8 version; | |
129 | resource_size_t pbase; | |
130 | void __iomem *base; | |
131 | size_t region_size; | |
e0d205e9 BN |
132 | u32 irq; |
133 | struct completion done; | |
358934a6 SP |
134 | |
135 | const void *tx; | |
136 | void *rx; | |
e91c659b BN |
137 | #define SPI_TMP_BUFSZ (SMP_CACHE_BYTES + 1) |
138 | u8 rx_tmp_buf[SPI_TMP_BUFSZ]; | |
e0d205e9 BN |
139 | int rcount; |
140 | int wcount; | |
96fd881f | 141 | struct davinci_spi_dma dma_channels; |
778e261e | 142 | struct davinci_spi_platform_data *pdata; |
358934a6 SP |
143 | |
144 | void (*get_rx)(u32 rx_data, struct davinci_spi *); | |
145 | u32 (*get_tx)(struct davinci_spi *); | |
146 | ||
cda987eb | 147 | u8 bytes_per_word[SPI_MAX_CHIPSELECT]; |
358934a6 SP |
148 | }; |
149 | ||
53a31b07 BN |
150 | static struct davinci_spi_config davinci_spi_default_cfg; |
151 | ||
358934a6 SP |
152 | static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi) |
153 | { | |
53d454a1 BN |
154 | if (davinci_spi->rx) { |
155 | u8 *rx = davinci_spi->rx; | |
156 | *rx++ = (u8)data; | |
157 | davinci_spi->rx = rx; | |
158 | } | |
358934a6 SP |
159 | } |
160 | ||
161 | static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi) | |
162 | { | |
53d454a1 BN |
163 | if (davinci_spi->rx) { |
164 | u16 *rx = davinci_spi->rx; | |
165 | *rx++ = (u16)data; | |
166 | davinci_spi->rx = rx; | |
167 | } | |
358934a6 SP |
168 | } |
169 | ||
170 | static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi) | |
171 | { | |
53d454a1 BN |
172 | u32 data = 0; |
173 | if (davinci_spi->tx) { | |
174 | const u8 *tx = davinci_spi->tx; | |
175 | data = *tx++; | |
176 | davinci_spi->tx = tx; | |
177 | } | |
358934a6 SP |
178 | return data; |
179 | } | |
180 | ||
181 | static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi) | |
182 | { | |
53d454a1 BN |
183 | u32 data = 0; |
184 | if (davinci_spi->tx) { | |
185 | const u16 *tx = davinci_spi->tx; | |
186 | data = *tx++; | |
187 | davinci_spi->tx = tx; | |
188 | } | |
358934a6 SP |
189 | return data; |
190 | } | |
191 | ||
192 | static inline void set_io_bits(void __iomem *addr, u32 bits) | |
193 | { | |
194 | u32 v = ioread32(addr); | |
195 | ||
196 | v |= bits; | |
197 | iowrite32(v, addr); | |
198 | } | |
199 | ||
200 | static inline void clear_io_bits(void __iomem *addr, u32 bits) | |
201 | { | |
202 | u32 v = ioread32(addr); | |
203 | ||
204 | v &= ~bits; | |
205 | iowrite32(v, addr); | |
206 | } | |
207 | ||
358934a6 SP |
208 | /* |
209 | * Interface to control the chip select signal | |
210 | */ | |
211 | static void davinci_spi_chipselect(struct spi_device *spi, int value) | |
212 | { | |
213 | struct davinci_spi *davinci_spi; | |
214 | struct davinci_spi_platform_data *pdata; | |
7978b8c3 | 215 | u8 chip_sel = spi->chip_select; |
cfbc5d1d | 216 | u16 spidat1_cfg = CS_DEFAULT; |
23853973 | 217 | bool gpio_chipsel = false; |
358934a6 SP |
218 | |
219 | davinci_spi = spi_master_get_devdata(spi->master); | |
220 | pdata = davinci_spi->pdata; | |
221 | ||
23853973 BN |
222 | if (pdata->chip_sel && chip_sel < pdata->num_chipselect && |
223 | pdata->chip_sel[chip_sel] != SPI_INTERN_CS) | |
224 | gpio_chipsel = true; | |
225 | ||
358934a6 SP |
226 | /* |
227 | * Board specific chip select logic decides the polarity and cs | |
228 | * line for the controller | |
229 | */ | |
23853973 BN |
230 | if (gpio_chipsel) { |
231 | if (value == BITBANG_CS_ACTIVE) | |
232 | gpio_set_value(pdata->chip_sel[chip_sel], 0); | |
233 | else | |
234 | gpio_set_value(pdata->chip_sel[chip_sel], 1); | |
235 | } else { | |
236 | if (value == BITBANG_CS_ACTIVE) { | |
237 | spidat1_cfg |= SPIDAT1_CSHOLD_MASK; | |
238 | spidat1_cfg &= ~(0x1 << chip_sel); | |
239 | } | |
7978b8c3 | 240 | |
23853973 BN |
241 | iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); |
242 | } | |
358934a6 SP |
243 | } |
244 | ||
7fe0092b BN |
245 | /** |
246 | * davinci_spi_get_prescale - Calculates the correct prescale value | |
247 | * @maxspeed_hz: the maximum rate the SPI clock can run at | |
248 | * | |
249 | * This function calculates the prescale value that generates a clock rate | |
250 | * less than or equal to the specified maximum. | |
251 | * | |
252 | * Returns: calculated prescale - 1 for easy programming into SPI registers | |
253 | * or negative error number if valid prescalar cannot be updated. | |
254 | */ | |
255 | static inline int davinci_spi_get_prescale(struct davinci_spi *davinci_spi, | |
256 | u32 max_speed_hz) | |
257 | { | |
258 | int ret; | |
259 | ||
260 | ret = DIV_ROUND_UP(clk_get_rate(davinci_spi->clk), max_speed_hz); | |
261 | ||
262 | if (ret < 3 || ret > 256) | |
263 | return -EINVAL; | |
264 | ||
265 | return ret - 1; | |
266 | } | |
267 | ||
358934a6 SP |
268 | /** |
269 | * davinci_spi_setup_transfer - This functions will determine transfer method | |
270 | * @spi: spi device on which data transfer to be done | |
271 | * @t: spi transfer in which transfer info is filled | |
272 | * | |
273 | * This function determines data transfer method (8/16/32 bit transfer). | |
274 | * It will also set the SPI Clock Control register according to | |
275 | * SPI slave device freq. | |
276 | */ | |
277 | static int davinci_spi_setup_transfer(struct spi_device *spi, | |
278 | struct spi_transfer *t) | |
279 | { | |
280 | ||
281 | struct davinci_spi *davinci_spi; | |
25f33512 | 282 | struct davinci_spi_config *spicfg; |
358934a6 | 283 | u8 bits_per_word = 0; |
25f33512 | 284 | u32 hz = 0, spifmt = 0, prescale = 0; |
358934a6 SP |
285 | |
286 | davinci_spi = spi_master_get_devdata(spi->master); | |
25f33512 BN |
287 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
288 | if (!spicfg) | |
289 | spicfg = &davinci_spi_default_cfg; | |
358934a6 SP |
290 | |
291 | if (t) { | |
292 | bits_per_word = t->bits_per_word; | |
293 | hz = t->speed_hz; | |
294 | } | |
295 | ||
296 | /* if bits_per_word is not set then set it default */ | |
297 | if (!bits_per_word) | |
298 | bits_per_word = spi->bits_per_word; | |
299 | ||
300 | /* | |
301 | * Assign function pointer to appropriate transfer method | |
302 | * 8bit, 16bit or 32bit transfer | |
303 | */ | |
304 | if (bits_per_word <= 8 && bits_per_word >= 2) { | |
305 | davinci_spi->get_rx = davinci_spi_rx_buf_u8; | |
306 | davinci_spi->get_tx = davinci_spi_tx_buf_u8; | |
cda987eb | 307 | davinci_spi->bytes_per_word[spi->chip_select] = 1; |
358934a6 SP |
308 | } else if (bits_per_word <= 16 && bits_per_word >= 2) { |
309 | davinci_spi->get_rx = davinci_spi_rx_buf_u16; | |
310 | davinci_spi->get_tx = davinci_spi_tx_buf_u16; | |
cda987eb | 311 | davinci_spi->bytes_per_word[spi->chip_select] = 2; |
358934a6 SP |
312 | } else |
313 | return -EINVAL; | |
314 | ||
315 | if (!hz) | |
316 | hz = spi->max_speed_hz; | |
317 | ||
25f33512 BN |
318 | /* Set up SPIFMTn register, unique to this chipselect. */ |
319 | ||
7fe0092b BN |
320 | prescale = davinci_spi_get_prescale(davinci_spi, hz); |
321 | if (prescale < 0) | |
322 | return prescale; | |
323 | ||
25f33512 BN |
324 | spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); |
325 | ||
326 | if (spi->mode & SPI_LSB_FIRST) | |
327 | spifmt |= SPIFMT_SHIFTDIR_MASK; | |
328 | ||
329 | if (spi->mode & SPI_CPOL) | |
330 | spifmt |= SPIFMT_POLARITY_MASK; | |
331 | ||
332 | if (!(spi->mode & SPI_CPHA)) | |
333 | spifmt |= SPIFMT_PHASE_MASK; | |
334 | ||
335 | /* | |
336 | * Version 1 hardware supports two basic SPI modes: | |
337 | * - Standard SPI mode uses 4 pins, with chipselect | |
338 | * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) | |
339 | * (distinct from SPI_3WIRE, with just one data wire; | |
340 | * or similar variants without MOSI or without MISO) | |
341 | * | |
342 | * Version 2 hardware supports an optional handshaking signal, | |
343 | * so it can support two more modes: | |
344 | * - 5 pin SPI variant is standard SPI plus SPI_READY | |
345 | * - 4 pin with enable is (SPI_READY | SPI_NO_CS) | |
346 | */ | |
347 | ||
348 | if (davinci_spi->version == SPI_VERSION_2) { | |
349 | ||
7abbf23c BN |
350 | u32 delay = 0; |
351 | ||
25f33512 BN |
352 | spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) |
353 | & SPIFMT_WDELAY_MASK); | |
358934a6 | 354 | |
25f33512 BN |
355 | if (spicfg->odd_parity) |
356 | spifmt |= SPIFMT_ODD_PARITY_MASK; | |
357 | ||
358 | if (spicfg->parity_enable) | |
359 | spifmt |= SPIFMT_PARITYENA_MASK; | |
360 | ||
7abbf23c | 361 | if (spicfg->timer_disable) { |
25f33512 | 362 | spifmt |= SPIFMT_DISTIMER_MASK; |
7abbf23c BN |
363 | } else { |
364 | delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) | |
365 | & SPIDELAY_C2TDELAY_MASK; | |
366 | delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) | |
367 | & SPIDELAY_T2CDELAY_MASK; | |
368 | } | |
25f33512 | 369 | |
7abbf23c | 370 | if (spi->mode & SPI_READY) { |
25f33512 | 371 | spifmt |= SPIFMT_WAITENA_MASK; |
7abbf23c BN |
372 | delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) |
373 | & SPIDELAY_T2EDELAY_MASK; | |
374 | delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) | |
375 | & SPIDELAY_C2EDELAY_MASK; | |
376 | } | |
377 | ||
378 | iowrite32(delay, davinci_spi->base + SPIDELAY); | |
25f33512 BN |
379 | } |
380 | ||
381 | iowrite32(spifmt, davinci_spi->base + SPIFMT0); | |
358934a6 SP |
382 | |
383 | return 0; | |
384 | } | |
385 | ||
358934a6 SP |
386 | /** |
387 | * davinci_spi_setup - This functions will set default transfer method | |
388 | * @spi: spi device on which data transfer to be done | |
389 | * | |
390 | * This functions sets the default transfer method. | |
391 | */ | |
358934a6 SP |
392 | static int davinci_spi_setup(struct spi_device *spi) |
393 | { | |
b23a5d46 | 394 | int retval = 0; |
358934a6 | 395 | struct davinci_spi *davinci_spi; |
be88471b | 396 | struct davinci_spi_platform_data *pdata; |
358934a6 SP |
397 | |
398 | davinci_spi = spi_master_get_devdata(spi->master); | |
be88471b | 399 | pdata = davinci_spi->pdata; |
358934a6 SP |
400 | |
401 | /* if bits per word length is zero then set it default 8 */ | |
402 | if (!spi->bits_per_word) | |
403 | spi->bits_per_word = 8; | |
404 | ||
be88471b BN |
405 | if (!(spi->mode & SPI_NO_CS)) { |
406 | if ((pdata->chip_sel == NULL) || | |
407 | (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) | |
408 | set_io_bits(davinci_spi->base + SPIPC0, | |
409 | 1 << spi->chip_select); | |
410 | ||
411 | } | |
412 | ||
413 | if (spi->mode & SPI_READY) | |
414 | set_io_bits(davinci_spi->base + SPIPC0, SPIPC0_SPIENA_MASK); | |
415 | ||
416 | if (spi->mode & SPI_LOOP) | |
417 | set_io_bits(davinci_spi->base + SPIGCR1, | |
418 | SPIGCR1_LOOPBACK_MASK); | |
419 | else | |
420 | clear_io_bits(davinci_spi->base + SPIGCR1, | |
421 | SPIGCR1_LOOPBACK_MASK); | |
422 | ||
358934a6 SP |
423 | return retval; |
424 | } | |
425 | ||
358934a6 SP |
426 | static int davinci_spi_check_error(struct davinci_spi *davinci_spi, |
427 | int int_status) | |
428 | { | |
429 | struct device *sdev = davinci_spi->bitbang.master->dev.parent; | |
430 | ||
431 | if (int_status & SPIFLG_TIMEOUT_MASK) { | |
432 | dev_dbg(sdev, "SPI Time-out Error\n"); | |
433 | return -ETIMEDOUT; | |
434 | } | |
435 | if (int_status & SPIFLG_DESYNC_MASK) { | |
436 | dev_dbg(sdev, "SPI Desynchronization Error\n"); | |
437 | return -EIO; | |
438 | } | |
439 | if (int_status & SPIFLG_BITERR_MASK) { | |
440 | dev_dbg(sdev, "SPI Bit error\n"); | |
441 | return -EIO; | |
442 | } | |
443 | ||
444 | if (davinci_spi->version == SPI_VERSION_2) { | |
445 | if (int_status & SPIFLG_DLEN_ERR_MASK) { | |
446 | dev_dbg(sdev, "SPI Data Length Error\n"); | |
447 | return -EIO; | |
448 | } | |
449 | if (int_status & SPIFLG_PARERR_MASK) { | |
450 | dev_dbg(sdev, "SPI Parity Error\n"); | |
451 | return -EIO; | |
452 | } | |
453 | if (int_status & SPIFLG_OVRRUN_MASK) { | |
454 | dev_dbg(sdev, "SPI Data Overrun error\n"); | |
455 | return -EIO; | |
456 | } | |
358934a6 SP |
457 | if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { |
458 | dev_dbg(sdev, "SPI Buffer Init Active\n"); | |
459 | return -EBUSY; | |
460 | } | |
461 | } | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
e0d205e9 BN |
466 | /** |
467 | * davinci_spi_process_events - check for and handle any SPI controller events | |
468 | * @davinci_spi: the controller data | |
469 | * | |
470 | * This function will check the SPIFLG register and handle any events that are | |
471 | * detected there | |
472 | */ | |
473 | static int davinci_spi_process_events(struct davinci_spi *davinci_spi) | |
474 | { | |
475 | u32 buf, status, errors = 0, data1_reg_val; | |
476 | ||
477 | buf = ioread32(davinci_spi->base + SPIBUF); | |
478 | ||
479 | if (davinci_spi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { | |
480 | davinci_spi->get_rx(buf & 0xFFFF, davinci_spi); | |
481 | davinci_spi->rcount--; | |
482 | } | |
483 | ||
484 | status = ioread32(davinci_spi->base + SPIFLG); | |
485 | ||
486 | if (unlikely(status & SPIFLG_ERROR_MASK)) { | |
487 | errors = status & SPIFLG_ERROR_MASK; | |
488 | goto out; | |
489 | } | |
490 | ||
491 | if (davinci_spi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { | |
492 | data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); | |
493 | davinci_spi->wcount--; | |
494 | data1_reg_val &= ~0xFFFF; | |
495 | data1_reg_val |= 0xFFFF & davinci_spi->get_tx(davinci_spi); | |
496 | iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); | |
497 | } | |
498 | ||
499 | out: | |
500 | return errors; | |
501 | } | |
502 | ||
87467bd9 BN |
503 | static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data) |
504 | { | |
505 | struct davinci_spi *davinci_spi = data; | |
506 | struct davinci_spi_dma *davinci_spi_dma = &davinci_spi->dma_channels; | |
507 | ||
508 | edma_stop(lch); | |
509 | ||
510 | if (status == DMA_COMPLETE) { | |
511 | if (lch == davinci_spi_dma->dma_rx_channel) | |
512 | davinci_spi->rcount = 0; | |
513 | if (lch == davinci_spi_dma->dma_tx_channel) | |
514 | davinci_spi->wcount = 0; | |
515 | } | |
516 | ||
517 | if ((!davinci_spi->wcount && !davinci_spi->rcount) || | |
518 | (status != DMA_COMPLETE)) | |
519 | complete(&davinci_spi->done); | |
520 | } | |
521 | ||
358934a6 SP |
522 | /** |
523 | * davinci_spi_bufs - functions which will handle transfer data | |
524 | * @spi: spi device on which data transfer to be done | |
525 | * @t: spi transfer in which transfer info is filled | |
526 | * | |
527 | * This function will put data to be transferred into data register | |
528 | * of SPI controller and then wait until the completion will be marked | |
529 | * by the IRQ Handler. | |
530 | */ | |
87467bd9 | 531 | static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) |
358934a6 SP |
532 | { |
533 | struct davinci_spi *davinci_spi; | |
87467bd9 | 534 | int data_type, ret; |
358934a6 | 535 | u32 tx_data, data1_reg_val; |
839c996c | 536 | u32 errors = 0; |
e0d205e9 | 537 | struct davinci_spi_config *spicfg; |
358934a6 | 538 | struct davinci_spi_platform_data *pdata; |
87467bd9 BN |
539 | unsigned uninitialized_var(rx_buf_count); |
540 | struct device *sdev; | |
358934a6 SP |
541 | |
542 | davinci_spi = spi_master_get_devdata(spi->master); | |
543 | pdata = davinci_spi->pdata; | |
e0d205e9 BN |
544 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
545 | if (!spicfg) | |
546 | spicfg = &davinci_spi_default_cfg; | |
87467bd9 BN |
547 | sdev = davinci_spi->bitbang.master->dev.parent; |
548 | ||
549 | /* convert len to words based on bits_per_word */ | |
550 | data_type = davinci_spi->bytes_per_word[spi->chip_select]; | |
358934a6 SP |
551 | |
552 | davinci_spi->tx = t->tx_buf; | |
553 | davinci_spi->rx = t->rx_buf; | |
87467bd9 | 554 | davinci_spi->wcount = t->len / data_type; |
e0d205e9 | 555 | davinci_spi->rcount = davinci_spi->wcount; |
7978b8c3 | 556 | |
839c996c BN |
557 | data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); |
558 | ||
3f27b57c | 559 | clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); |
358934a6 SP |
560 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); |
561 | ||
87467bd9 BN |
562 | INIT_COMPLETION(davinci_spi->done); |
563 | ||
564 | if (spicfg->io_type == SPI_IO_TYPE_INTR) | |
e0d205e9 | 565 | set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); |
cf90fe73 | 566 | |
87467bd9 BN |
567 | if (spicfg->io_type != SPI_IO_TYPE_DMA) { |
568 | /* start the transfer */ | |
569 | davinci_spi->wcount--; | |
570 | tx_data = davinci_spi->get_tx(davinci_spi); | |
571 | data1_reg_val &= 0xFFFF0000; | |
572 | data1_reg_val |= tx_data & 0xFFFF; | |
573 | iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); | |
574 | } else { | |
575 | struct davinci_spi_dma *davinci_spi_dma; | |
576 | unsigned long tx_reg, rx_reg; | |
577 | struct edmacc_param param; | |
578 | void *rx_buf; | |
579 | ||
580 | davinci_spi_dma = &davinci_spi->dma_channels; | |
581 | ||
582 | tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1; | |
583 | rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF; | |
584 | ||
585 | /* | |
586 | * Transmit DMA setup | |
587 | * | |
588 | * If there is transmit data, map the transmit buffer, set it | |
589 | * as the source of data and set the source B index to data | |
590 | * size. If there is no transmit data, set the transmit register | |
591 | * as the source of data, and set the source B index to zero. | |
592 | * | |
593 | * The destination is always the transmit register itself. And | |
594 | * the destination never increments. | |
595 | */ | |
596 | ||
597 | if (t->tx_buf) { | |
598 | t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, | |
599 | davinci_spi->wcount, DMA_TO_DEVICE); | |
600 | if (dma_mapping_error(&spi->dev, t->tx_dma)) { | |
601 | dev_dbg(sdev, "Unable to DMA map %d bytes" | |
602 | "TX buffer\n", | |
603 | davinci_spi->wcount); | |
604 | return -ENOMEM; | |
605 | } | |
606 | } | |
607 | ||
608 | param.opt = TCINTEN | EDMA_TCC(davinci_spi_dma->dma_tx_channel); | |
609 | param.src = t->tx_buf ? t->tx_dma : tx_reg; | |
610 | param.a_b_cnt = davinci_spi->wcount << 16 | data_type; | |
611 | param.dst = tx_reg; | |
612 | param.src_dst_bidx = t->tx_buf ? data_type : 0; | |
613 | param.link_bcntrld = 0xffff; | |
614 | param.src_dst_cidx = 0; | |
615 | param.ccnt = 1; | |
616 | edma_write_slot(davinci_spi_dma->dma_tx_channel, ¶m); | |
617 | edma_link(davinci_spi_dma->dma_tx_channel, | |
618 | davinci_spi_dma->dummy_param_slot); | |
619 | ||
620 | /* | |
621 | * Receive DMA setup | |
622 | * | |
623 | * If there is receive buffer, use it to receive data. If there | |
624 | * is none provided, use a temporary receive buffer. Set the | |
625 | * destination B index to 0 so effectively only one byte is used | |
626 | * in the temporary buffer (address does not increment). | |
627 | * | |
628 | * The source of receive data is the receive data register. The | |
629 | * source address never increments. | |
630 | */ | |
631 | ||
632 | if (t->rx_buf) { | |
633 | rx_buf = t->rx_buf; | |
634 | rx_buf_count = davinci_spi->rcount; | |
635 | } else { | |
636 | rx_buf = davinci_spi->rx_tmp_buf; | |
637 | rx_buf_count = sizeof(davinci_spi->rx_tmp_buf); | |
638 | } | |
639 | ||
640 | t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count, | |
641 | DMA_FROM_DEVICE); | |
642 | if (dma_mapping_error(&spi->dev, t->rx_dma)) { | |
643 | dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", | |
644 | rx_buf_count); | |
645 | if (t->tx_buf) | |
646 | dma_unmap_single(NULL, t->tx_dma, | |
647 | davinci_spi->wcount, | |
648 | DMA_TO_DEVICE); | |
649 | return -ENOMEM; | |
650 | } | |
651 | ||
652 | param.opt = TCINTEN | EDMA_TCC(davinci_spi_dma->dma_rx_channel); | |
653 | param.src = rx_reg; | |
654 | param.a_b_cnt = davinci_spi->rcount << 16 | data_type; | |
655 | param.dst = t->rx_dma; | |
656 | param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16; | |
657 | param.link_bcntrld = 0xffff; | |
658 | param.src_dst_cidx = 0; | |
659 | param.ccnt = 1; | |
660 | edma_write_slot(davinci_spi_dma->dma_rx_channel, ¶m); | |
661 | ||
662 | if (pdata->cshold_bug) | |
663 | iowrite16(data1_reg_val >> 16, | |
664 | davinci_spi->base + SPIDAT1 + 2); | |
665 | ||
666 | edma_start(davinci_spi_dma->dma_rx_channel); | |
667 | edma_start(davinci_spi_dma->dma_tx_channel); | |
668 | set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); | |
669 | } | |
358934a6 | 670 | |
e0d205e9 | 671 | /* Wait for the transfer to complete */ |
87467bd9 | 672 | if (spicfg->io_type != SPI_IO_TYPE_POLL) { |
e0d205e9 BN |
673 | wait_for_completion_interruptible(&(davinci_spi->done)); |
674 | } else { | |
675 | while (davinci_spi->rcount > 0 || davinci_spi->wcount > 0) { | |
676 | errors = davinci_spi_process_events(davinci_spi); | |
677 | if (errors) | |
678 | break; | |
679 | cpu_relax(); | |
358934a6 SP |
680 | } |
681 | } | |
682 | ||
e0d205e9 | 683 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); |
87467bd9 BN |
684 | if (spicfg->io_type == SPI_IO_TYPE_DMA) { |
685 | ||
686 | if (t->tx_buf) | |
687 | dma_unmap_single(NULL, t->tx_dma, davinci_spi->wcount, | |
688 | DMA_TO_DEVICE); | |
689 | ||
690 | dma_unmap_single(NULL, t->rx_dma, rx_buf_count, | |
691 | DMA_FROM_DEVICE); | |
692 | ||
693 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); | |
694 | } | |
e0d205e9 | 695 | |
3f27b57c BN |
696 | clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); |
697 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); | |
698 | ||
358934a6 SP |
699 | /* |
700 | * Check for bit error, desync error,parity error,timeout error and | |
701 | * receive overflow errors | |
702 | */ | |
839c996c BN |
703 | if (errors) { |
704 | ret = davinci_spi_check_error(davinci_spi, errors); | |
705 | WARN(!ret, "%s: error reported but no error found!\n", | |
706 | dev_name(&spi->dev)); | |
358934a6 | 707 | return ret; |
839c996c | 708 | } |
358934a6 | 709 | |
87467bd9 BN |
710 | if (davinci_spi->rcount != 0 || davinci_spi->wcount != 0) { |
711 | dev_err(sdev, "SPI data transfer error\n"); | |
712 | return -EIO; | |
713 | } | |
714 | ||
358934a6 SP |
715 | return t->len; |
716 | } | |
717 | ||
e0d205e9 BN |
718 | /** |
719 | * davinci_spi_irq - Interrupt handler for SPI Master Controller | |
720 | * @irq: IRQ number for this SPI Master | |
721 | * @context_data: structure for SPI Master controller davinci_spi | |
722 | * | |
723 | * ISR will determine that interrupt arrives either for READ or WRITE command. | |
724 | * According to command it will do the appropriate action. It will check | |
725 | * transfer length and if it is not zero then dispatch transfer command again. | |
726 | * If transfer length is zero then it will indicate the COMPLETION so that | |
727 | * davinci_spi_bufs function can go ahead. | |
728 | */ | |
729 | static irqreturn_t davinci_spi_irq(s32 irq, void *context_data) | |
730 | { | |
731 | struct davinci_spi *davinci_spi = context_data; | |
732 | int status; | |
733 | ||
734 | status = davinci_spi_process_events(davinci_spi); | |
735 | if (unlikely(status != 0)) | |
736 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); | |
737 | ||
738 | if ((!davinci_spi->rcount && !davinci_spi->wcount) || status) | |
739 | complete(&davinci_spi->done); | |
740 | ||
741 | return IRQ_HANDLED; | |
742 | } | |
743 | ||
9b189fd7 | 744 | static int davinci_spi_request_dma(struct davinci_spi *davinci_spi) |
903ca25b SN |
745 | { |
746 | int r; | |
9b189fd7 | 747 | struct davinci_spi_dma *davinci_spi_dma = &davinci_spi->dma_channels; |
903ca25b SN |
748 | |
749 | r = edma_alloc_channel(davinci_spi_dma->dma_rx_channel, | |
6dbd29b2 | 750 | davinci_spi_dma_callback, davinci_spi, |
903ca25b SN |
751 | davinci_spi_dma->eventq); |
752 | if (r < 0) { | |
753 | pr_err("Unable to request DMA channel for SPI RX\n"); | |
523c37e7 BN |
754 | r = -EAGAIN; |
755 | goto rx_dma_failed; | |
903ca25b SN |
756 | } |
757 | ||
758 | r = edma_alloc_channel(davinci_spi_dma->dma_tx_channel, | |
6dbd29b2 | 759 | davinci_spi_dma_callback, davinci_spi, |
903ca25b SN |
760 | davinci_spi_dma->eventq); |
761 | if (r < 0) { | |
903ca25b | 762 | pr_err("Unable to request DMA channel for SPI TX\n"); |
523c37e7 BN |
763 | r = -EAGAIN; |
764 | goto tx_dma_failed; | |
903ca25b SN |
765 | } |
766 | ||
523c37e7 BN |
767 | r = edma_alloc_slot(EDMA_CTLR(davinci_spi_dma->dma_tx_channel), |
768 | EDMA_SLOT_ANY); | |
769 | if (r < 0) { | |
770 | pr_err("Unable to request SPI TX DMA param slot\n"); | |
771 | r = -EAGAIN; | |
772 | goto param_failed; | |
773 | } | |
774 | davinci_spi_dma->dummy_param_slot = r; | |
775 | edma_link(davinci_spi_dma->dummy_param_slot, | |
776 | davinci_spi_dma->dummy_param_slot); | |
777 | ||
903ca25b | 778 | return 0; |
523c37e7 BN |
779 | param_failed: |
780 | edma_free_channel(davinci_spi_dma->dma_tx_channel); | |
781 | tx_dma_failed: | |
782 | edma_free_channel(davinci_spi_dma->dma_rx_channel); | |
783 | rx_dma_failed: | |
784 | return r; | |
903ca25b SN |
785 | } |
786 | ||
358934a6 SP |
787 | /** |
788 | * davinci_spi_probe - probe function for SPI Master Controller | |
789 | * @pdev: platform_device structure which contains plateform specific data | |
790 | */ | |
791 | static int davinci_spi_probe(struct platform_device *pdev) | |
792 | { | |
793 | struct spi_master *master; | |
794 | struct davinci_spi *davinci_spi; | |
795 | struct davinci_spi_platform_data *pdata; | |
796 | struct resource *r, *mem; | |
797 | resource_size_t dma_rx_chan = SPI_NO_RESOURCE; | |
798 | resource_size_t dma_tx_chan = SPI_NO_RESOURCE; | |
799 | resource_size_t dma_eventq = SPI_NO_RESOURCE; | |
800 | int i = 0, ret = 0; | |
f34bd4cc | 801 | u32 spipc0; |
358934a6 SP |
802 | |
803 | pdata = pdev->dev.platform_data; | |
804 | if (pdata == NULL) { | |
805 | ret = -ENODEV; | |
806 | goto err; | |
807 | } | |
808 | ||
809 | master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); | |
810 | if (master == NULL) { | |
811 | ret = -ENOMEM; | |
812 | goto err; | |
813 | } | |
814 | ||
815 | dev_set_drvdata(&pdev->dev, master); | |
816 | ||
817 | davinci_spi = spi_master_get_devdata(master); | |
818 | if (davinci_spi == NULL) { | |
819 | ret = -ENOENT; | |
820 | goto free_master; | |
821 | } | |
822 | ||
823 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
824 | if (r == NULL) { | |
825 | ret = -ENOENT; | |
826 | goto free_master; | |
827 | } | |
828 | ||
829 | davinci_spi->pbase = r->start; | |
830 | davinci_spi->region_size = resource_size(r); | |
831 | davinci_spi->pdata = pdata; | |
832 | ||
833 | mem = request_mem_region(r->start, davinci_spi->region_size, | |
834 | pdev->name); | |
835 | if (mem == NULL) { | |
836 | ret = -EBUSY; | |
837 | goto free_master; | |
838 | } | |
839 | ||
50356dd7 | 840 | davinci_spi->base = ioremap(r->start, davinci_spi->region_size); |
358934a6 SP |
841 | if (davinci_spi->base == NULL) { |
842 | ret = -ENOMEM; | |
843 | goto release_region; | |
844 | } | |
845 | ||
e0d205e9 BN |
846 | davinci_spi->irq = platform_get_irq(pdev, 0); |
847 | if (davinci_spi->irq <= 0) { | |
848 | ret = -EINVAL; | |
849 | goto unmap_io; | |
850 | } | |
851 | ||
852 | ret = request_irq(davinci_spi->irq, davinci_spi_irq, 0, | |
853 | dev_name(&pdev->dev), davinci_spi); | |
854 | if (ret) | |
855 | goto unmap_io; | |
856 | ||
358934a6 SP |
857 | davinci_spi->bitbang.master = spi_master_get(master); |
858 | if (davinci_spi->bitbang.master == NULL) { | |
859 | ret = -ENODEV; | |
d3f7141c | 860 | goto irq_free; |
358934a6 SP |
861 | } |
862 | ||
863 | davinci_spi->clk = clk_get(&pdev->dev, NULL); | |
864 | if (IS_ERR(davinci_spi->clk)) { | |
865 | ret = -ENODEV; | |
866 | goto put_master; | |
867 | } | |
868 | clk_enable(davinci_spi->clk); | |
869 | ||
358934a6 SP |
870 | master->bus_num = pdev->id; |
871 | master->num_chipselect = pdata->num_chipselect; | |
872 | master->setup = davinci_spi_setup; | |
358934a6 SP |
873 | |
874 | davinci_spi->bitbang.chipselect = davinci_spi_chipselect; | |
875 | davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer; | |
876 | ||
877 | davinci_spi->version = pdata->version; | |
358934a6 SP |
878 | |
879 | davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; | |
880 | if (davinci_spi->version == SPI_VERSION_2) | |
881 | davinci_spi->bitbang.flags |= SPI_READY; | |
882 | ||
903ca25b SN |
883 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
884 | if (r) | |
885 | dma_rx_chan = r->start; | |
886 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
887 | if (r) | |
888 | dma_tx_chan = r->start; | |
889 | r = platform_get_resource(pdev, IORESOURCE_DMA, 2); | |
890 | if (r) | |
891 | dma_eventq = r->start; | |
892 | ||
87467bd9 | 893 | davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs; |
903ca25b SN |
894 | if (dma_rx_chan != SPI_NO_RESOURCE && |
895 | dma_tx_chan != SPI_NO_RESOURCE && | |
896 | dma_eventq != SPI_NO_RESOURCE) { | |
897 | davinci_spi->dma_channels.dma_rx_channel = dma_rx_chan; | |
898 | davinci_spi->dma_channels.dma_tx_channel = dma_tx_chan; | |
96fd881f BN |
899 | davinci_spi->dma_channels.eventq = dma_eventq; |
900 | ||
9b189fd7 | 901 | ret = davinci_spi_request_dma(davinci_spi); |
903ca25b SN |
902 | if (ret) |
903 | goto free_clk; | |
904 | ||
87467bd9 BN |
905 | dev_info(&pdev->dev, "DMA: supported\n"); |
906 | dev_info(&pdev->dev, "DMA: RX channel: %d, TX channel: %d, " | |
907 | "event queue: %d\n", dma_rx_chan, dma_tx_chan, | |
358934a6 SP |
908 | dma_eventq); |
909 | } | |
910 | ||
911 | davinci_spi->get_rx = davinci_spi_rx_buf_u8; | |
912 | davinci_spi->get_tx = davinci_spi_tx_buf_u8; | |
913 | ||
e0d205e9 BN |
914 | init_completion(&davinci_spi->done); |
915 | ||
358934a6 SP |
916 | /* Reset In/OUT SPI module */ |
917 | iowrite32(0, davinci_spi->base + SPIGCR0); | |
918 | udelay(100); | |
919 | iowrite32(1, davinci_spi->base + SPIGCR0); | |
920 | ||
be88471b | 921 | /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ |
f34bd4cc BN |
922 | spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; |
923 | iowrite32(spipc0, davinci_spi->base + SPIPC0); | |
924 | ||
23853973 BN |
925 | /* initialize chip selects */ |
926 | if (pdata->chip_sel) { | |
927 | for (i = 0; i < pdata->num_chipselect; i++) { | |
928 | if (pdata->chip_sel[i] != SPI_INTERN_CS) | |
929 | gpio_direction_output(pdata->chip_sel[i], 1); | |
930 | } | |
931 | } | |
932 | ||
e0d205e9 BN |
933 | if (pdata->intr_line) |
934 | iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); | |
935 | else | |
936 | iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); | |
937 | ||
843a713b BN |
938 | iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF); |
939 | ||
358934a6 | 940 | /* master mode default */ |
3409e408 | 941 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); |
358934a6 | 942 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); |
3f27b57c | 943 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); |
358934a6 | 944 | |
358934a6 SP |
945 | ret = spi_bitbang_start(&davinci_spi->bitbang); |
946 | if (ret) | |
903ca25b | 947 | goto free_dma; |
358934a6 | 948 | |
3b740b10 | 949 | dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base); |
358934a6 | 950 | |
358934a6 SP |
951 | return ret; |
952 | ||
903ca25b SN |
953 | free_dma: |
954 | edma_free_channel(davinci_spi->dma_channels.dma_tx_channel); | |
955 | edma_free_channel(davinci_spi->dma_channels.dma_rx_channel); | |
523c37e7 | 956 | edma_free_slot(davinci_spi->dma_channels.dummy_param_slot); |
358934a6 SP |
957 | free_clk: |
958 | clk_disable(davinci_spi->clk); | |
959 | clk_put(davinci_spi->clk); | |
960 | put_master: | |
961 | spi_master_put(master); | |
e0d205e9 BN |
962 | irq_free: |
963 | free_irq(davinci_spi->irq, davinci_spi); | |
358934a6 SP |
964 | unmap_io: |
965 | iounmap(davinci_spi->base); | |
966 | release_region: | |
967 | release_mem_region(davinci_spi->pbase, davinci_spi->region_size); | |
968 | free_master: | |
969 | kfree(master); | |
970 | err: | |
971 | return ret; | |
972 | } | |
973 | ||
974 | /** | |
975 | * davinci_spi_remove - remove function for SPI Master Controller | |
976 | * @pdev: platform_device structure which contains plateform specific data | |
977 | * | |
978 | * This function will do the reverse action of davinci_spi_probe function | |
979 | * It will free the IRQ and SPI controller's memory region. | |
980 | * It will also call spi_bitbang_stop to destroy the work queue which was | |
981 | * created by spi_bitbang_start. | |
982 | */ | |
983 | static int __exit davinci_spi_remove(struct platform_device *pdev) | |
984 | { | |
985 | struct davinci_spi *davinci_spi; | |
986 | struct spi_master *master; | |
987 | ||
988 | master = dev_get_drvdata(&pdev->dev); | |
989 | davinci_spi = spi_master_get_devdata(master); | |
990 | ||
991 | spi_bitbang_stop(&davinci_spi->bitbang); | |
992 | ||
993 | clk_disable(davinci_spi->clk); | |
994 | clk_put(davinci_spi->clk); | |
995 | spi_master_put(master); | |
e0d205e9 | 996 | free_irq(davinci_spi->irq, davinci_spi); |
358934a6 SP |
997 | iounmap(davinci_spi->base); |
998 | release_mem_region(davinci_spi->pbase, davinci_spi->region_size); | |
999 | ||
1000 | return 0; | |
1001 | } | |
1002 | ||
1003 | static struct platform_driver davinci_spi_driver = { | |
d8c174cd BN |
1004 | .driver = { |
1005 | .name = "spi_davinci", | |
1006 | .owner = THIS_MODULE, | |
1007 | }, | |
358934a6 SP |
1008 | .remove = __exit_p(davinci_spi_remove), |
1009 | }; | |
1010 | ||
1011 | static int __init davinci_spi_init(void) | |
1012 | { | |
1013 | return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe); | |
1014 | } | |
1015 | module_init(davinci_spi_init); | |
1016 | ||
1017 | static void __exit davinci_spi_exit(void) | |
1018 | { | |
1019 | platform_driver_unregister(&davinci_spi_driver); | |
1020 | } | |
1021 | module_exit(davinci_spi_exit); | |
1022 | ||
1023 | MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); | |
1024 | MODULE_LICENSE("GPL"); |