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e24c7452 FT |
1 | /* |
2 | * dw_spi.c - Designware SPI core controller driver (refer pxa2xx_spi.c) | |
3 | * | |
4 | * Copyright (c) 2009, Intel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program; if not, write to the Free Software Foundation, Inc., | |
17 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | */ | |
19 | ||
20 | #include <linux/dma-mapping.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/highmem.h> | |
23 | #include <linux/delay.h> | |
24 | ||
25 | #include <linux/spi/dw_spi.h> | |
26 | #include <linux/spi/spi.h> | |
27 | ||
28 | #ifdef CONFIG_DEBUG_FS | |
29 | #include <linux/debugfs.h> | |
30 | #endif | |
31 | ||
32 | #define START_STATE ((void *)0) | |
33 | #define RUNNING_STATE ((void *)1) | |
34 | #define DONE_STATE ((void *)2) | |
35 | #define ERROR_STATE ((void *)-1) | |
36 | ||
37 | #define QUEUE_RUNNING 0 | |
38 | #define QUEUE_STOPPED 1 | |
39 | ||
40 | #define MRST_SPI_DEASSERT 0 | |
41 | #define MRST_SPI_ASSERT 1 | |
42 | ||
43 | /* Slave spi_dev related */ | |
44 | struct chip_data { | |
45 | u16 cr0; | |
46 | u8 cs; /* chip select pin */ | |
47 | u8 n_bytes; /* current is a 1/2/4 byte op */ | |
48 | u8 tmode; /* TR/TO/RO/EEPROM */ | |
49 | u8 type; /* SPI/SSP/MicroWire */ | |
50 | ||
51 | u8 poll_mode; /* 1 means use poll mode */ | |
52 | ||
53 | u32 dma_width; | |
54 | u32 rx_threshold; | |
55 | u32 tx_threshold; | |
56 | u8 enable_dma; | |
57 | u8 bits_per_word; | |
58 | u16 clk_div; /* baud rate divider */ | |
59 | u32 speed_hz; /* baud rate */ | |
60 | int (*write)(struct dw_spi *dws); | |
61 | int (*read)(struct dw_spi *dws); | |
62 | void (*cs_control)(u32 command); | |
63 | }; | |
64 | ||
65 | #ifdef CONFIG_DEBUG_FS | |
66 | static int spi_show_regs_open(struct inode *inode, struct file *file) | |
67 | { | |
68 | file->private_data = inode->i_private; | |
69 | return 0; | |
70 | } | |
71 | ||
72 | #define SPI_REGS_BUFSIZE 1024 | |
73 | static ssize_t spi_show_regs(struct file *file, char __user *user_buf, | |
74 | size_t count, loff_t *ppos) | |
75 | { | |
76 | struct dw_spi *dws; | |
77 | char *buf; | |
78 | u32 len = 0; | |
79 | ssize_t ret; | |
80 | ||
81 | dws = file->private_data; | |
82 | ||
83 | buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL); | |
84 | if (!buf) | |
85 | return 0; | |
86 | ||
87 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
88 | "MRST SPI0 registers:\n"); | |
89 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
90 | "=================================\n"); | |
91 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
92 | "CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0)); | |
93 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
94 | "CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1)); | |
95 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
96 | "SSIENR: \t0x%08x\n", dw_readl(dws, ssienr)); | |
97 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
98 | "SER: \t\t0x%08x\n", dw_readl(dws, ser)); | |
99 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
100 | "BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr)); | |
101 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
102 | "TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr)); | |
103 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
104 | "RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr)); | |
105 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
106 | "TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr)); | |
107 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
108 | "RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr)); | |
109 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
110 | "SR: \t\t0x%08x\n", dw_readl(dws, sr)); | |
111 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
112 | "IMR: \t\t0x%08x\n", dw_readl(dws, imr)); | |
113 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
114 | "ISR: \t\t0x%08x\n", dw_readl(dws, isr)); | |
115 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
116 | "DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr)); | |
117 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
118 | "DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr)); | |
119 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
120 | "DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr)); | |
121 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
122 | "=================================\n"); | |
123 | ||
124 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); | |
125 | kfree(buf); | |
126 | return ret; | |
127 | } | |
128 | ||
129 | static const struct file_operations mrst_spi_regs_ops = { | |
130 | .owner = THIS_MODULE, | |
131 | .open = spi_show_regs_open, | |
132 | .read = spi_show_regs, | |
133 | }; | |
134 | ||
135 | static int mrst_spi_debugfs_init(struct dw_spi *dws) | |
136 | { | |
137 | dws->debugfs = debugfs_create_dir("mrst_spi", NULL); | |
138 | if (!dws->debugfs) | |
139 | return -ENOMEM; | |
140 | ||
141 | debugfs_create_file("registers", S_IFREG | S_IRUGO, | |
142 | dws->debugfs, (void *)dws, &mrst_spi_regs_ops); | |
143 | return 0; | |
144 | } | |
145 | ||
146 | static void mrst_spi_debugfs_remove(struct dw_spi *dws) | |
147 | { | |
148 | if (dws->debugfs) | |
149 | debugfs_remove_recursive(dws->debugfs); | |
150 | } | |
151 | ||
152 | #else | |
153 | static inline int mrst_spi_debugfs_init(struct dw_spi *dws) | |
154 | { | |
20a588fc | 155 | return 0; |
e24c7452 FT |
156 | } |
157 | ||
158 | static inline void mrst_spi_debugfs_remove(struct dw_spi *dws) | |
159 | { | |
160 | } | |
161 | #endif /* CONFIG_DEBUG_FS */ | |
162 | ||
163 | static void wait_till_not_busy(struct dw_spi *dws) | |
164 | { | |
b490e370 | 165 | unsigned long end = jiffies + 1 + usecs_to_jiffies(1000); |
e24c7452 FT |
166 | |
167 | while (time_before(jiffies, end)) { | |
168 | if (!(dw_readw(dws, sr) & SR_BUSY)) | |
169 | return; | |
170 | } | |
171 | dev_err(&dws->master->dev, | |
426c0093 | 172 | "DW SPI: Status keeps busy for 1000us after a read/write!\n"); |
e24c7452 FT |
173 | } |
174 | ||
175 | static void flush(struct dw_spi *dws) | |
176 | { | |
177 | while (dw_readw(dws, sr) & SR_RF_NOT_EMPT) | |
178 | dw_readw(dws, dr); | |
179 | ||
180 | wait_till_not_busy(dws); | |
181 | } | |
182 | ||
183 | static void null_cs_control(u32 command) | |
184 | { | |
185 | } | |
186 | ||
187 | static int null_writer(struct dw_spi *dws) | |
188 | { | |
189 | u8 n_bytes = dws->n_bytes; | |
190 | ||
191 | if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL) | |
192 | || (dws->tx == dws->tx_end)) | |
193 | return 0; | |
194 | dw_writew(dws, dr, 0); | |
195 | dws->tx += n_bytes; | |
196 | ||
197 | wait_till_not_busy(dws); | |
198 | return 1; | |
199 | } | |
200 | ||
201 | static int null_reader(struct dw_spi *dws) | |
202 | { | |
203 | u8 n_bytes = dws->n_bytes; | |
204 | ||
205 | while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT) | |
206 | && (dws->rx < dws->rx_end)) { | |
207 | dw_readw(dws, dr); | |
208 | dws->rx += n_bytes; | |
209 | } | |
210 | wait_till_not_busy(dws); | |
211 | return dws->rx == dws->rx_end; | |
212 | } | |
213 | ||
214 | static int u8_writer(struct dw_spi *dws) | |
215 | { | |
216 | if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL) | |
217 | || (dws->tx == dws->tx_end)) | |
218 | return 0; | |
219 | ||
220 | dw_writew(dws, dr, *(u8 *)(dws->tx)); | |
221 | ++dws->tx; | |
222 | ||
223 | wait_till_not_busy(dws); | |
224 | return 1; | |
225 | } | |
226 | ||
227 | static int u8_reader(struct dw_spi *dws) | |
228 | { | |
229 | while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT) | |
230 | && (dws->rx < dws->rx_end)) { | |
231 | *(u8 *)(dws->rx) = dw_readw(dws, dr); | |
232 | ++dws->rx; | |
233 | } | |
234 | ||
235 | wait_till_not_busy(dws); | |
236 | return dws->rx == dws->rx_end; | |
237 | } | |
238 | ||
239 | static int u16_writer(struct dw_spi *dws) | |
240 | { | |
241 | if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL) | |
242 | || (dws->tx == dws->tx_end)) | |
243 | return 0; | |
244 | ||
245 | dw_writew(dws, dr, *(u16 *)(dws->tx)); | |
246 | dws->tx += 2; | |
247 | ||
248 | wait_till_not_busy(dws); | |
249 | return 1; | |
250 | } | |
251 | ||
252 | static int u16_reader(struct dw_spi *dws) | |
253 | { | |
254 | u16 temp; | |
255 | ||
256 | while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT) | |
257 | && (dws->rx < dws->rx_end)) { | |
258 | temp = dw_readw(dws, dr); | |
259 | *(u16 *)(dws->rx) = temp; | |
260 | dws->rx += 2; | |
261 | } | |
262 | ||
263 | wait_till_not_busy(dws); | |
264 | return dws->rx == dws->rx_end; | |
265 | } | |
266 | ||
267 | static void *next_transfer(struct dw_spi *dws) | |
268 | { | |
269 | struct spi_message *msg = dws->cur_msg; | |
270 | struct spi_transfer *trans = dws->cur_transfer; | |
271 | ||
272 | /* Move to next transfer */ | |
273 | if (trans->transfer_list.next != &msg->transfers) { | |
274 | dws->cur_transfer = | |
275 | list_entry(trans->transfer_list.next, | |
276 | struct spi_transfer, | |
277 | transfer_list); | |
278 | return RUNNING_STATE; | |
279 | } else | |
280 | return DONE_STATE; | |
281 | } | |
282 | ||
283 | /* | |
284 | * Note: first step is the protocol driver prepares | |
285 | * a dma-capable memory, and this func just need translate | |
286 | * the virt addr to physical | |
287 | */ | |
288 | static int map_dma_buffers(struct dw_spi *dws) | |
289 | { | |
290 | if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited | |
291 | || !dws->cur_chip->enable_dma) | |
292 | return 0; | |
293 | ||
294 | if (dws->cur_transfer->tx_dma) | |
295 | dws->tx_dma = dws->cur_transfer->tx_dma; | |
296 | ||
297 | if (dws->cur_transfer->rx_dma) | |
298 | dws->rx_dma = dws->cur_transfer->rx_dma; | |
299 | ||
300 | return 1; | |
301 | } | |
302 | ||
303 | /* Caller already set message->status; dma and pio irqs are blocked */ | |
304 | static void giveback(struct dw_spi *dws) | |
305 | { | |
306 | struct spi_transfer *last_transfer; | |
307 | unsigned long flags; | |
308 | struct spi_message *msg; | |
309 | ||
310 | spin_lock_irqsave(&dws->lock, flags); | |
311 | msg = dws->cur_msg; | |
312 | dws->cur_msg = NULL; | |
313 | dws->cur_transfer = NULL; | |
314 | dws->prev_chip = dws->cur_chip; | |
315 | dws->cur_chip = NULL; | |
316 | dws->dma_mapped = 0; | |
317 | queue_work(dws->workqueue, &dws->pump_messages); | |
318 | spin_unlock_irqrestore(&dws->lock, flags); | |
319 | ||
320 | last_transfer = list_entry(msg->transfers.prev, | |
321 | struct spi_transfer, | |
322 | transfer_list); | |
323 | ||
324 | if (!last_transfer->cs_change) | |
325 | dws->cs_control(MRST_SPI_DEASSERT); | |
326 | ||
327 | msg->state = NULL; | |
328 | if (msg->complete) | |
329 | msg->complete(msg->context); | |
330 | } | |
331 | ||
332 | static void int_error_stop(struct dw_spi *dws, const char *msg) | |
333 | { | |
334 | /* Stop and reset hw */ | |
335 | flush(dws); | |
336 | spi_enable_chip(dws, 0); | |
337 | ||
338 | dev_err(&dws->master->dev, "%s\n", msg); | |
339 | dws->cur_msg->state = ERROR_STATE; | |
340 | tasklet_schedule(&dws->pump_transfers); | |
341 | } | |
342 | ||
343 | static void transfer_complete(struct dw_spi *dws) | |
344 | { | |
345 | /* Update total byte transfered return count actual bytes read */ | |
346 | dws->cur_msg->actual_length += dws->len; | |
347 | ||
348 | /* Move to next transfer */ | |
349 | dws->cur_msg->state = next_transfer(dws); | |
350 | ||
351 | /* Handle end of message */ | |
352 | if (dws->cur_msg->state == DONE_STATE) { | |
353 | dws->cur_msg->status = 0; | |
354 | giveback(dws); | |
355 | } else | |
356 | tasklet_schedule(&dws->pump_transfers); | |
357 | } | |
358 | ||
359 | static irqreturn_t interrupt_transfer(struct dw_spi *dws) | |
360 | { | |
361 | u16 irq_status, irq_mask = 0x3f; | |
552e4509 FT |
362 | u32 int_level = dws->fifo_len / 2; |
363 | u32 left; | |
e24c7452 FT |
364 | |
365 | irq_status = dw_readw(dws, isr) & irq_mask; | |
366 | /* Error handling */ | |
367 | if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) { | |
368 | dw_readw(dws, txoicr); | |
369 | dw_readw(dws, rxoicr); | |
370 | dw_readw(dws, rxuicr); | |
371 | int_error_stop(dws, "interrupt_transfer: fifo overrun"); | |
372 | return IRQ_HANDLED; | |
373 | } | |
374 | ||
552e4509 FT |
375 | if (irq_status & SPI_INT_TXEI) { |
376 | spi_mask_intr(dws, SPI_INT_TXEI); | |
377 | ||
378 | left = (dws->tx_end - dws->tx) / dws->n_bytes; | |
379 | left = (left > int_level) ? int_level : left; | |
380 | ||
381 | while (left--) | |
e24c7452 | 382 | dws->write(dws); |
552e4509 | 383 | dws->read(dws); |
e24c7452 | 384 | |
552e4509 FT |
385 | /* Re-enable the IRQ if there is still data left to tx */ |
386 | if (dws->tx_end > dws->tx) | |
387 | spi_umask_intr(dws, SPI_INT_TXEI); | |
388 | else | |
e24c7452 | 389 | transfer_complete(dws); |
e24c7452 FT |
390 | } |
391 | ||
e24c7452 FT |
392 | return IRQ_HANDLED; |
393 | } | |
394 | ||
395 | static irqreturn_t dw_spi_irq(int irq, void *dev_id) | |
396 | { | |
397 | struct dw_spi *dws = dev_id; | |
398 | ||
399 | if (!dws->cur_msg) { | |
400 | spi_mask_intr(dws, SPI_INT_TXEI); | |
401 | /* Never fail */ | |
402 | return IRQ_HANDLED; | |
403 | } | |
404 | ||
405 | return dws->transfer_handler(dws); | |
406 | } | |
407 | ||
408 | /* Must be called inside pump_transfers() */ | |
409 | static void poll_transfer(struct dw_spi *dws) | |
410 | { | |
f4aec798 GS |
411 | while (dws->write(dws)) |
412 | dws->read(dws); | |
e24c7452 | 413 | |
e24c7452 FT |
414 | transfer_complete(dws); |
415 | } | |
416 | ||
417 | static void dma_transfer(struct dw_spi *dws, int cs_change) | |
418 | { | |
419 | } | |
420 | ||
421 | static void pump_transfers(unsigned long data) | |
422 | { | |
423 | struct dw_spi *dws = (struct dw_spi *)data; | |
424 | struct spi_message *message = NULL; | |
425 | struct spi_transfer *transfer = NULL; | |
426 | struct spi_transfer *previous = NULL; | |
427 | struct spi_device *spi = NULL; | |
428 | struct chip_data *chip = NULL; | |
429 | u8 bits = 0; | |
430 | u8 imask = 0; | |
431 | u8 cs_change = 0; | |
552e4509 | 432 | u16 txint_level = 0; |
e24c7452 FT |
433 | u16 clk_div = 0; |
434 | u32 speed = 0; | |
435 | u32 cr0 = 0; | |
436 | ||
437 | /* Get current state information */ | |
438 | message = dws->cur_msg; | |
439 | transfer = dws->cur_transfer; | |
440 | chip = dws->cur_chip; | |
441 | spi = message->spi; | |
442 | ||
552e4509 FT |
443 | if (unlikely(!chip->clk_div)) |
444 | chip->clk_div = dws->max_freq / chip->speed_hz; | |
445 | ||
e24c7452 FT |
446 | if (message->state == ERROR_STATE) { |
447 | message->status = -EIO; | |
448 | goto early_exit; | |
449 | } | |
450 | ||
451 | /* Handle end of message */ | |
452 | if (message->state == DONE_STATE) { | |
453 | message->status = 0; | |
454 | goto early_exit; | |
455 | } | |
456 | ||
457 | /* Delay if requested at end of transfer*/ | |
458 | if (message->state == RUNNING_STATE) { | |
459 | previous = list_entry(transfer->transfer_list.prev, | |
460 | struct spi_transfer, | |
461 | transfer_list); | |
462 | if (previous->delay_usecs) | |
463 | udelay(previous->delay_usecs); | |
464 | } | |
465 | ||
466 | dws->n_bytes = chip->n_bytes; | |
467 | dws->dma_width = chip->dma_width; | |
468 | dws->cs_control = chip->cs_control; | |
469 | ||
470 | dws->rx_dma = transfer->rx_dma; | |
471 | dws->tx_dma = transfer->tx_dma; | |
472 | dws->tx = (void *)transfer->tx_buf; | |
473 | dws->tx_end = dws->tx + transfer->len; | |
474 | dws->rx = transfer->rx_buf; | |
475 | dws->rx_end = dws->rx + transfer->len; | |
476 | dws->write = dws->tx ? chip->write : null_writer; | |
477 | dws->read = dws->rx ? chip->read : null_reader; | |
478 | dws->cs_change = transfer->cs_change; | |
479 | dws->len = dws->cur_transfer->len; | |
480 | if (chip != dws->prev_chip) | |
481 | cs_change = 1; | |
482 | ||
483 | cr0 = chip->cr0; | |
484 | ||
485 | /* Handle per transfer options for bpw and speed */ | |
486 | if (transfer->speed_hz) { | |
487 | speed = chip->speed_hz; | |
488 | ||
489 | if (transfer->speed_hz != speed) { | |
490 | speed = transfer->speed_hz; | |
491 | if (speed > dws->max_freq) { | |
492 | printk(KERN_ERR "MRST SPI0: unsupported" | |
493 | "freq: %dHz\n", speed); | |
494 | message->status = -EIO; | |
495 | goto early_exit; | |
496 | } | |
497 | ||
498 | /* clk_div doesn't support odd number */ | |
499 | clk_div = dws->max_freq / speed; | |
552e4509 | 500 | clk_div = (clk_div + 1) & 0xfffe; |
e24c7452 FT |
501 | |
502 | chip->speed_hz = speed; | |
503 | chip->clk_div = clk_div; | |
504 | } | |
505 | } | |
506 | if (transfer->bits_per_word) { | |
507 | bits = transfer->bits_per_word; | |
508 | ||
509 | switch (bits) { | |
510 | case 8: | |
511 | dws->n_bytes = 1; | |
512 | dws->dma_width = 1; | |
513 | dws->read = (dws->read != null_reader) ? | |
514 | u8_reader : null_reader; | |
515 | dws->write = (dws->write != null_writer) ? | |
516 | u8_writer : null_writer; | |
517 | break; | |
518 | case 16: | |
519 | dws->n_bytes = 2; | |
520 | dws->dma_width = 2; | |
521 | dws->read = (dws->read != null_reader) ? | |
522 | u16_reader : null_reader; | |
523 | dws->write = (dws->write != null_writer) ? | |
524 | u16_writer : null_writer; | |
525 | break; | |
526 | default: | |
527 | printk(KERN_ERR "MRST SPI0: unsupported bits:" | |
528 | "%db\n", bits); | |
529 | message->status = -EIO; | |
530 | goto early_exit; | |
531 | } | |
532 | ||
533 | cr0 = (bits - 1) | |
534 | | (chip->type << SPI_FRF_OFFSET) | |
535 | | (spi->mode << SPI_MODE_OFFSET) | |
536 | | (chip->tmode << SPI_TMOD_OFFSET); | |
537 | } | |
538 | message->state = RUNNING_STATE; | |
539 | ||
540 | /* Check if current transfer is a DMA transaction */ | |
541 | dws->dma_mapped = map_dma_buffers(dws); | |
542 | ||
552e4509 FT |
543 | /* |
544 | * Interrupt mode | |
545 | * we only need set the TXEI IRQ, as TX/RX always happen syncronizely | |
546 | */ | |
e24c7452 | 547 | if (!dws->dma_mapped && !chip->poll_mode) { |
552e4509 FT |
548 | int templen = dws->len / dws->n_bytes; |
549 | txint_level = dws->fifo_len / 2; | |
550 | txint_level = (templen > txint_level) ? txint_level : templen; | |
551 | ||
552 | imask |= SPI_INT_TXEI; | |
e24c7452 FT |
553 | dws->transfer_handler = interrupt_transfer; |
554 | } | |
555 | ||
556 | /* | |
557 | * Reprogram registers only if | |
558 | * 1. chip select changes | |
559 | * 2. clk_div is changed | |
560 | * 3. control value changes | |
561 | */ | |
552e4509 | 562 | if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div || imask) { |
e24c7452 FT |
563 | spi_enable_chip(dws, 0); |
564 | ||
565 | if (dw_readw(dws, ctrl0) != cr0) | |
566 | dw_writew(dws, ctrl0, cr0); | |
567 | ||
552e4509 FT |
568 | spi_set_clk(dws, clk_div ? clk_div : chip->clk_div); |
569 | spi_chip_sel(dws, spi->chip_select); | |
570 | ||
e24c7452 FT |
571 | /* Set the interrupt mask, for poll mode just diable all int */ |
572 | spi_mask_intr(dws, 0xff); | |
552e4509 | 573 | if (imask) |
e24c7452 | 574 | spi_umask_intr(dws, imask); |
552e4509 FT |
575 | if (txint_level) |
576 | dw_writew(dws, txfltr, txint_level); | |
e24c7452 | 577 | |
e24c7452 | 578 | spi_enable_chip(dws, 1); |
e24c7452 FT |
579 | if (cs_change) |
580 | dws->prev_chip = chip; | |
581 | } | |
582 | ||
583 | if (dws->dma_mapped) | |
584 | dma_transfer(dws, cs_change); | |
585 | ||
586 | if (chip->poll_mode) | |
587 | poll_transfer(dws); | |
588 | ||
589 | return; | |
590 | ||
591 | early_exit: | |
592 | giveback(dws); | |
593 | return; | |
594 | } | |
595 | ||
596 | static void pump_messages(struct work_struct *work) | |
597 | { | |
598 | struct dw_spi *dws = | |
599 | container_of(work, struct dw_spi, pump_messages); | |
600 | unsigned long flags; | |
601 | ||
602 | /* Lock queue and check for queue work */ | |
603 | spin_lock_irqsave(&dws->lock, flags); | |
604 | if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) { | |
605 | dws->busy = 0; | |
606 | spin_unlock_irqrestore(&dws->lock, flags); | |
607 | return; | |
608 | } | |
609 | ||
610 | /* Make sure we are not already running a message */ | |
611 | if (dws->cur_msg) { | |
612 | spin_unlock_irqrestore(&dws->lock, flags); | |
613 | return; | |
614 | } | |
615 | ||
616 | /* Extract head of queue */ | |
617 | dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue); | |
618 | list_del_init(&dws->cur_msg->queue); | |
619 | ||
620 | /* Initial message state*/ | |
621 | dws->cur_msg->state = START_STATE; | |
622 | dws->cur_transfer = list_entry(dws->cur_msg->transfers.next, | |
623 | struct spi_transfer, | |
624 | transfer_list); | |
625 | dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi); | |
626 | ||
627 | /* Mark as busy and launch transfers */ | |
628 | tasklet_schedule(&dws->pump_transfers); | |
629 | ||
630 | dws->busy = 1; | |
631 | spin_unlock_irqrestore(&dws->lock, flags); | |
632 | } | |
633 | ||
634 | /* spi_device use this to queue in their spi_msg */ | |
635 | static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg) | |
636 | { | |
637 | struct dw_spi *dws = spi_master_get_devdata(spi->master); | |
638 | unsigned long flags; | |
639 | ||
640 | spin_lock_irqsave(&dws->lock, flags); | |
641 | ||
642 | if (dws->run == QUEUE_STOPPED) { | |
643 | spin_unlock_irqrestore(&dws->lock, flags); | |
644 | return -ESHUTDOWN; | |
645 | } | |
646 | ||
647 | msg->actual_length = 0; | |
648 | msg->status = -EINPROGRESS; | |
649 | msg->state = START_STATE; | |
650 | ||
651 | list_add_tail(&msg->queue, &dws->queue); | |
652 | ||
653 | if (dws->run == QUEUE_RUNNING && !dws->busy) { | |
654 | ||
655 | if (dws->cur_transfer || dws->cur_msg) | |
656 | queue_work(dws->workqueue, | |
657 | &dws->pump_messages); | |
658 | else { | |
659 | /* If no other data transaction in air, just go */ | |
660 | spin_unlock_irqrestore(&dws->lock, flags); | |
661 | pump_messages(&dws->pump_messages); | |
662 | return 0; | |
663 | } | |
664 | } | |
665 | ||
666 | spin_unlock_irqrestore(&dws->lock, flags); | |
667 | return 0; | |
668 | } | |
669 | ||
670 | /* This may be called twice for each spi dev */ | |
671 | static int dw_spi_setup(struct spi_device *spi) | |
672 | { | |
673 | struct dw_spi_chip *chip_info = NULL; | |
674 | struct chip_data *chip; | |
675 | ||
676 | if (spi->bits_per_word != 8 && spi->bits_per_word != 16) | |
677 | return -EINVAL; | |
678 | ||
679 | /* Only alloc on first setup */ | |
680 | chip = spi_get_ctldata(spi); | |
681 | if (!chip) { | |
682 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); | |
683 | if (!chip) | |
684 | return -ENOMEM; | |
685 | ||
686 | chip->cs_control = null_cs_control; | |
687 | chip->enable_dma = 0; | |
688 | } | |
689 | ||
690 | /* | |
691 | * Protocol drivers may change the chip settings, so... | |
692 | * if chip_info exists, use it | |
693 | */ | |
694 | chip_info = spi->controller_data; | |
695 | ||
696 | /* chip_info doesn't always exist */ | |
697 | if (chip_info) { | |
698 | if (chip_info->cs_control) | |
699 | chip->cs_control = chip_info->cs_control; | |
700 | ||
701 | chip->poll_mode = chip_info->poll_mode; | |
702 | chip->type = chip_info->type; | |
703 | ||
704 | chip->rx_threshold = 0; | |
705 | chip->tx_threshold = 0; | |
706 | ||
707 | chip->enable_dma = chip_info->enable_dma; | |
708 | } | |
709 | ||
710 | if (spi->bits_per_word <= 8) { | |
711 | chip->n_bytes = 1; | |
712 | chip->dma_width = 1; | |
713 | chip->read = u8_reader; | |
714 | chip->write = u8_writer; | |
715 | } else if (spi->bits_per_word <= 16) { | |
716 | chip->n_bytes = 2; | |
717 | chip->dma_width = 2; | |
718 | chip->read = u16_reader; | |
719 | chip->write = u16_writer; | |
720 | } else { | |
721 | /* Never take >16b case for MRST SPIC */ | |
722 | dev_err(&spi->dev, "invalid wordsize\n"); | |
723 | return -EINVAL; | |
724 | } | |
725 | chip->bits_per_word = spi->bits_per_word; | |
726 | ||
552e4509 FT |
727 | if (!spi->max_speed_hz) { |
728 | dev_err(&spi->dev, "No max speed HZ parameter\n"); | |
729 | return -EINVAL; | |
730 | } | |
e24c7452 | 731 | chip->speed_hz = spi->max_speed_hz; |
e24c7452 FT |
732 | |
733 | chip->tmode = 0; /* Tx & Rx */ | |
734 | /* Default SPI mode is SCPOL = 0, SCPH = 0 */ | |
735 | chip->cr0 = (chip->bits_per_word - 1) | |
736 | | (chip->type << SPI_FRF_OFFSET) | |
737 | | (spi->mode << SPI_MODE_OFFSET) | |
738 | | (chip->tmode << SPI_TMOD_OFFSET); | |
739 | ||
740 | spi_set_ctldata(spi, chip); | |
741 | return 0; | |
742 | } | |
743 | ||
744 | static void dw_spi_cleanup(struct spi_device *spi) | |
745 | { | |
746 | struct chip_data *chip = spi_get_ctldata(spi); | |
747 | kfree(chip); | |
748 | } | |
749 | ||
99147b5c | 750 | static int __devinit init_queue(struct dw_spi *dws) |
e24c7452 FT |
751 | { |
752 | INIT_LIST_HEAD(&dws->queue); | |
753 | spin_lock_init(&dws->lock); | |
754 | ||
755 | dws->run = QUEUE_STOPPED; | |
756 | dws->busy = 0; | |
757 | ||
758 | tasklet_init(&dws->pump_transfers, | |
759 | pump_transfers, (unsigned long)dws); | |
760 | ||
761 | INIT_WORK(&dws->pump_messages, pump_messages); | |
762 | dws->workqueue = create_singlethread_workqueue( | |
763 | dev_name(dws->master->dev.parent)); | |
764 | if (dws->workqueue == NULL) | |
765 | return -EBUSY; | |
766 | ||
767 | return 0; | |
768 | } | |
769 | ||
770 | static int start_queue(struct dw_spi *dws) | |
771 | { | |
772 | unsigned long flags; | |
773 | ||
774 | spin_lock_irqsave(&dws->lock, flags); | |
775 | ||
776 | if (dws->run == QUEUE_RUNNING || dws->busy) { | |
777 | spin_unlock_irqrestore(&dws->lock, flags); | |
778 | return -EBUSY; | |
779 | } | |
780 | ||
781 | dws->run = QUEUE_RUNNING; | |
782 | dws->cur_msg = NULL; | |
783 | dws->cur_transfer = NULL; | |
784 | dws->cur_chip = NULL; | |
785 | dws->prev_chip = NULL; | |
786 | spin_unlock_irqrestore(&dws->lock, flags); | |
787 | ||
788 | queue_work(dws->workqueue, &dws->pump_messages); | |
789 | ||
790 | return 0; | |
791 | } | |
792 | ||
793 | static int stop_queue(struct dw_spi *dws) | |
794 | { | |
795 | unsigned long flags; | |
796 | unsigned limit = 50; | |
797 | int status = 0; | |
798 | ||
799 | spin_lock_irqsave(&dws->lock, flags); | |
800 | dws->run = QUEUE_STOPPED; | |
801 | while (!list_empty(&dws->queue) && dws->busy && limit--) { | |
802 | spin_unlock_irqrestore(&dws->lock, flags); | |
803 | msleep(10); | |
804 | spin_lock_irqsave(&dws->lock, flags); | |
805 | } | |
806 | ||
807 | if (!list_empty(&dws->queue) || dws->busy) | |
808 | status = -EBUSY; | |
809 | spin_unlock_irqrestore(&dws->lock, flags); | |
810 | ||
811 | return status; | |
812 | } | |
813 | ||
814 | static int destroy_queue(struct dw_spi *dws) | |
815 | { | |
816 | int status; | |
817 | ||
818 | status = stop_queue(dws); | |
819 | if (status != 0) | |
820 | return status; | |
821 | destroy_workqueue(dws->workqueue); | |
822 | return 0; | |
823 | } | |
824 | ||
825 | /* Restart the controller, disable all interrupts, clean rx fifo */ | |
826 | static void spi_hw_init(struct dw_spi *dws) | |
827 | { | |
828 | spi_enable_chip(dws, 0); | |
829 | spi_mask_intr(dws, 0xff); | |
830 | spi_enable_chip(dws, 1); | |
831 | flush(dws); | |
c587b6fa FT |
832 | |
833 | /* | |
834 | * Try to detect the FIFO depth if not set by interface driver, | |
835 | * the depth could be from 2 to 256 from HW spec | |
836 | */ | |
837 | if (!dws->fifo_len) { | |
838 | u32 fifo; | |
839 | for (fifo = 2; fifo <= 257; fifo++) { | |
840 | dw_writew(dws, txfltr, fifo); | |
841 | if (fifo != dw_readw(dws, txfltr)) | |
842 | break; | |
843 | } | |
844 | ||
845 | dws->fifo_len = (fifo == 257) ? 0 : fifo; | |
846 | dw_writew(dws, txfltr, 0); | |
847 | } | |
e24c7452 FT |
848 | } |
849 | ||
850 | int __devinit dw_spi_add_host(struct dw_spi *dws) | |
851 | { | |
852 | struct spi_master *master; | |
853 | int ret; | |
854 | ||
855 | BUG_ON(dws == NULL); | |
856 | ||
857 | master = spi_alloc_master(dws->parent_dev, 0); | |
858 | if (!master) { | |
859 | ret = -ENOMEM; | |
860 | goto exit; | |
861 | } | |
862 | ||
863 | dws->master = master; | |
864 | dws->type = SSI_MOTO_SPI; | |
865 | dws->prev_chip = NULL; | |
866 | dws->dma_inited = 0; | |
867 | dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60); | |
868 | ||
869 | ret = request_irq(dws->irq, dw_spi_irq, 0, | |
870 | "dw_spi", dws); | |
871 | if (ret < 0) { | |
872 | dev_err(&master->dev, "can not get IRQ\n"); | |
873 | goto err_free_master; | |
874 | } | |
875 | ||
876 | master->mode_bits = SPI_CPOL | SPI_CPHA; | |
877 | master->bus_num = dws->bus_num; | |
878 | master->num_chipselect = dws->num_cs; | |
879 | master->cleanup = dw_spi_cleanup; | |
880 | master->setup = dw_spi_setup; | |
881 | master->transfer = dw_spi_transfer; | |
882 | ||
883 | dws->dma_inited = 0; | |
884 | ||
885 | /* Basic HW init */ | |
886 | spi_hw_init(dws); | |
887 | ||
888 | /* Initial and start queue */ | |
889 | ret = init_queue(dws); | |
890 | if (ret) { | |
891 | dev_err(&master->dev, "problem initializing queue\n"); | |
892 | goto err_diable_hw; | |
893 | } | |
894 | ret = start_queue(dws); | |
895 | if (ret) { | |
896 | dev_err(&master->dev, "problem starting queue\n"); | |
897 | goto err_diable_hw; | |
898 | } | |
899 | ||
900 | spi_master_set_devdata(master, dws); | |
901 | ret = spi_register_master(master); | |
902 | if (ret) { | |
903 | dev_err(&master->dev, "problem registering spi master\n"); | |
904 | goto err_queue_alloc; | |
905 | } | |
906 | ||
907 | mrst_spi_debugfs_init(dws); | |
908 | return 0; | |
909 | ||
910 | err_queue_alloc: | |
911 | destroy_queue(dws); | |
912 | err_diable_hw: | |
913 | spi_enable_chip(dws, 0); | |
914 | free_irq(dws->irq, dws); | |
915 | err_free_master: | |
916 | spi_master_put(master); | |
917 | exit: | |
918 | return ret; | |
919 | } | |
920 | EXPORT_SYMBOL(dw_spi_add_host); | |
921 | ||
922 | void __devexit dw_spi_remove_host(struct dw_spi *dws) | |
923 | { | |
924 | int status = 0; | |
925 | ||
926 | if (!dws) | |
927 | return; | |
928 | mrst_spi_debugfs_remove(dws); | |
929 | ||
930 | /* Remove the queue */ | |
931 | status = destroy_queue(dws); | |
932 | if (status != 0) | |
933 | dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not " | |
934 | "complete, message memory not freed\n"); | |
935 | ||
936 | spi_enable_chip(dws, 0); | |
937 | /* Disable clk */ | |
938 | spi_set_clk(dws, 0); | |
939 | free_irq(dws->irq, dws); | |
940 | ||
941 | /* Disconnect from the SPI framework */ | |
942 | spi_unregister_master(dws->master); | |
943 | } | |
944 | ||
945 | int dw_spi_suspend_host(struct dw_spi *dws) | |
946 | { | |
947 | int ret = 0; | |
948 | ||
949 | ret = stop_queue(dws); | |
950 | if (ret) | |
951 | return ret; | |
952 | spi_enable_chip(dws, 0); | |
953 | spi_set_clk(dws, 0); | |
954 | return ret; | |
955 | } | |
956 | EXPORT_SYMBOL(dw_spi_suspend_host); | |
957 | ||
958 | int dw_spi_resume_host(struct dw_spi *dws) | |
959 | { | |
960 | int ret; | |
961 | ||
962 | spi_hw_init(dws); | |
963 | ret = start_queue(dws); | |
964 | if (ret) | |
965 | dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret); | |
966 | return ret; | |
967 | } | |
968 | EXPORT_SYMBOL(dw_spi_resume_host); | |
969 | ||
970 | MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>"); | |
971 | MODULE_DESCRIPTION("Driver for DesignWare SPI controller core"); | |
972 | MODULE_LICENSE("GPL v2"); |