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00b8fd23 DC |
1 | /* |
2 | * MPC52xx SPC in SPI mode driver. | |
3 | * | |
4 | * Maintainer: Dragos Carp | |
5 | * | |
6 | * Copyright (C) 2006 TOPTICA Photonics AG. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/interrupt.h> | |
18 | ||
19 | #if defined(CONFIG_PPC_MERGE) | |
20 | #include <asm/of_platform.h> | |
21 | #else | |
22 | #include <linux/platform_device.h> | |
23 | #endif | |
24 | ||
25 | #include <linux/workqueue.h> | |
26 | #include <linux/completion.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/spi/spi.h> | |
30 | #include <linux/fsl_devices.h> | |
31 | ||
32 | #include <asm/mpc52xx.h> | |
33 | #include <asm/mpc52xx_psc.h> | |
34 | ||
35 | #define MCLK 20000000 /* PSC port MClk in hz */ | |
36 | ||
37 | struct mpc52xx_psc_spi { | |
38 | /* fsl_spi_platform data */ | |
39 | void (*activate_cs)(u8, u8); | |
40 | void (*deactivate_cs)(u8, u8); | |
41 | u32 sysclk; | |
42 | ||
43 | /* driver internal data */ | |
44 | struct mpc52xx_psc __iomem *psc; | |
45 | unsigned int irq; | |
46 | u8 bits_per_word; | |
47 | u8 busy; | |
48 | ||
49 | struct workqueue_struct *workqueue; | |
50 | struct work_struct work; | |
51 | ||
52 | struct list_head queue; | |
53 | spinlock_t lock; | |
54 | ||
55 | struct completion done; | |
56 | }; | |
57 | ||
58 | /* controller state */ | |
59 | struct mpc52xx_psc_spi_cs { | |
60 | int bits_per_word; | |
61 | int speed_hz; | |
62 | }; | |
63 | ||
64 | /* set clock freq, clock ramp, bits per work | |
65 | * if t is NULL then reset the values to the default values | |
66 | */ | |
67 | static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi, | |
68 | struct spi_transfer *t) | |
69 | { | |
70 | struct mpc52xx_psc_spi_cs *cs = spi->controller_state; | |
71 | ||
72 | cs->speed_hz = (t && t->speed_hz) | |
73 | ? t->speed_hz : spi->max_speed_hz; | |
74 | cs->bits_per_word = (t && t->bits_per_word) | |
75 | ? t->bits_per_word : spi->bits_per_word; | |
76 | cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8; | |
77 | return 0; | |
78 | } | |
79 | ||
80 | static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi) | |
81 | { | |
82 | struct mpc52xx_psc_spi_cs *cs = spi->controller_state; | |
83 | struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); | |
84 | struct mpc52xx_psc __iomem *psc = mps->psc; | |
85 | u32 sicr; | |
86 | u16 ccr; | |
87 | ||
88 | sicr = in_be32(&psc->sicr); | |
89 | ||
90 | /* Set clock phase and polarity */ | |
91 | if (spi->mode & SPI_CPHA) | |
92 | sicr |= 0x00001000; | |
93 | else | |
94 | sicr &= ~0x00001000; | |
95 | if (spi->mode & SPI_CPOL) | |
96 | sicr |= 0x00002000; | |
97 | else | |
98 | sicr &= ~0x00002000; | |
99 | ||
100 | if (spi->mode & SPI_LSB_FIRST) | |
101 | sicr |= 0x10000000; | |
102 | else | |
103 | sicr &= ~0x10000000; | |
104 | out_be32(&psc->sicr, sicr); | |
105 | ||
106 | /* Set clock frequency and bits per word | |
107 | * Because psc->ccr is defined as 16bit register instead of 32bit | |
108 | * just set the lower byte of BitClkDiv | |
109 | */ | |
110 | ccr = in_be16(&psc->ccr); | |
111 | ccr &= 0xFF00; | |
112 | if (cs->speed_hz) | |
113 | ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; | |
114 | else /* by default SPI Clk 1MHz */ | |
115 | ccr |= (MCLK / 1000000 - 1) & 0xFF; | |
116 | out_be16(&psc->ccr, ccr); | |
117 | mps->bits_per_word = cs->bits_per_word; | |
118 | ||
119 | if (mps->activate_cs) | |
120 | mps->activate_cs(spi->chip_select, | |
121 | (spi->mode & SPI_CS_HIGH) ? 1 : 0); | |
122 | } | |
123 | ||
124 | static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi) | |
125 | { | |
126 | struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); | |
127 | ||
128 | if (mps->deactivate_cs) | |
129 | mps->deactivate_cs(spi->chip_select, | |
130 | (spi->mode & SPI_CS_HIGH) ? 1 : 0); | |
131 | } | |
132 | ||
133 | #define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1) | |
134 | /* wake up when 80% fifo full */ | |
135 | #define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100) | |
136 | ||
137 | static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi, | |
138 | struct spi_transfer *t) | |
139 | { | |
140 | struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); | |
141 | struct mpc52xx_psc __iomem *psc = mps->psc; | |
142 | unsigned rb = 0; /* number of bytes receieved */ | |
143 | unsigned sb = 0; /* number of bytes sent */ | |
144 | unsigned char *rx_buf = (unsigned char *)t->rx_buf; | |
145 | unsigned char *tx_buf = (unsigned char *)t->tx_buf; | |
146 | unsigned rfalarm; | |
147 | unsigned send_at_once = MPC52xx_PSC_BUFSIZE; | |
148 | unsigned recv_at_once; | |
149 | unsigned bpw = mps->bits_per_word / 8; | |
150 | ||
151 | if (!t->tx_buf && !t->rx_buf && t->len) | |
152 | return -EINVAL; | |
153 | ||
154 | /* enable transmiter/receiver */ | |
155 | out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE); | |
156 | while (rb < t->len) { | |
157 | if (t->len - rb > MPC52xx_PSC_BUFSIZE) { | |
158 | rfalarm = MPC52xx_PSC_RFALARM; | |
159 | } else { | |
160 | send_at_once = t->len - sb; | |
161 | rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb); | |
162 | } | |
163 | ||
164 | dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once); | |
165 | if (tx_buf) { | |
166 | for (; send_at_once; sb++, send_at_once--) { | |
167 | /* set EOF flag */ | |
168 | if (mps->bits_per_word | |
169 | && (sb + 1) % bpw == 0) | |
170 | out_8(&psc->ircr2, 0x01); | |
171 | out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]); | |
172 | } | |
173 | } else { | |
174 | for (; send_at_once; sb++, send_at_once--) { | |
175 | /* set EOF flag */ | |
176 | if (mps->bits_per_word | |
177 | && ((sb + 1) % bpw) == 0) | |
178 | out_8(&psc->ircr2, 0x01); | |
179 | out_8(&psc->mpc52xx_psc_buffer_8, 0); | |
180 | } | |
181 | } | |
182 | ||
183 | ||
184 | /* enable interupts and wait for wake up | |
185 | * if just one byte is expected the Rx FIFO genererates no | |
186 | * FFULL interrupt, so activate the RxRDY interrupt | |
187 | */ | |
188 | out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); | |
189 | if (t->len - rb == 1) { | |
190 | out_8(&psc->mode, 0); | |
191 | } else { | |
192 | out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL); | |
193 | out_be16(&psc->rfalarm, rfalarm); | |
194 | } | |
195 | out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY); | |
196 | wait_for_completion(&mps->done); | |
197 | recv_at_once = in_be16(&psc->rfnum); | |
198 | dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once); | |
199 | ||
200 | send_at_once = recv_at_once; | |
201 | if (rx_buf) { | |
202 | for (; recv_at_once; rb++, recv_at_once--) | |
203 | rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8); | |
204 | } else { | |
205 | for (; recv_at_once; rb++, recv_at_once--) | |
206 | in_8(&psc->mpc52xx_psc_buffer_8); | |
207 | } | |
208 | } | |
209 | /* disable transmiter/receiver */ | |
210 | out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); | |
211 | ||
212 | return 0; | |
213 | } | |
214 | ||
215 | static void mpc52xx_psc_spi_work(struct work_struct *work) | |
216 | { | |
217 | struct mpc52xx_psc_spi *mps = | |
218 | container_of(work, struct mpc52xx_psc_spi, work); | |
219 | ||
220 | spin_lock_irq(&mps->lock); | |
221 | mps->busy = 1; | |
222 | while (!list_empty(&mps->queue)) { | |
223 | struct spi_message *m; | |
224 | struct spi_device *spi; | |
225 | struct spi_transfer *t = NULL; | |
226 | unsigned cs_change; | |
227 | int status; | |
228 | ||
229 | m = container_of(mps->queue.next, struct spi_message, queue); | |
230 | list_del_init(&m->queue); | |
231 | spin_unlock_irq(&mps->lock); | |
232 | ||
233 | spi = m->spi; | |
234 | cs_change = 1; | |
235 | status = 0; | |
236 | list_for_each_entry (t, &m->transfers, transfer_list) { | |
237 | if (t->bits_per_word || t->speed_hz) { | |
238 | status = mpc52xx_psc_spi_transfer_setup(spi, t); | |
239 | if (status < 0) | |
240 | break; | |
241 | } | |
242 | ||
243 | if (cs_change) | |
244 | mpc52xx_psc_spi_activate_cs(spi); | |
245 | cs_change = t->cs_change; | |
246 | ||
247 | status = mpc52xx_psc_spi_transfer_rxtx(spi, t); | |
248 | if (status) | |
249 | break; | |
250 | m->actual_length += t->len; | |
251 | ||
252 | if (t->delay_usecs) | |
253 | udelay(t->delay_usecs); | |
254 | ||
255 | if (cs_change) | |
256 | mpc52xx_psc_spi_deactivate_cs(spi); | |
257 | } | |
258 | ||
259 | m->status = status; | |
260 | m->complete(m->context); | |
261 | ||
262 | if (status || !cs_change) | |
263 | mpc52xx_psc_spi_deactivate_cs(spi); | |
264 | ||
265 | mpc52xx_psc_spi_transfer_setup(spi, NULL); | |
266 | ||
267 | spin_lock_irq(&mps->lock); | |
268 | } | |
269 | mps->busy = 0; | |
270 | spin_unlock_irq(&mps->lock); | |
271 | } | |
272 | ||
dccd573b DB |
273 | /* the spi->mode bits understood by this driver: */ |
274 | #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST) | |
275 | ||
00b8fd23 DC |
276 | static int mpc52xx_psc_spi_setup(struct spi_device *spi) |
277 | { | |
278 | struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); | |
279 | struct mpc52xx_psc_spi_cs *cs = spi->controller_state; | |
280 | unsigned long flags; | |
281 | ||
282 | if (spi->bits_per_word%8) | |
283 | return -EINVAL; | |
284 | ||
dccd573b DB |
285 | if (spi->mode & ~MODEBITS) { |
286 | dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", | |
287 | spi->mode & ~MODEBITS); | |
288 | return -EINVAL; | |
289 | } | |
290 | ||
00b8fd23 DC |
291 | if (!cs) { |
292 | cs = kzalloc(sizeof *cs, GFP_KERNEL); | |
293 | if (!cs) | |
294 | return -ENOMEM; | |
295 | spi->controller_state = cs; | |
296 | } | |
297 | ||
298 | cs->bits_per_word = spi->bits_per_word; | |
299 | cs->speed_hz = spi->max_speed_hz; | |
300 | ||
301 | spin_lock_irqsave(&mps->lock, flags); | |
302 | if (!mps->busy) | |
303 | mpc52xx_psc_spi_deactivate_cs(spi); | |
304 | spin_unlock_irqrestore(&mps->lock, flags); | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
309 | static int mpc52xx_psc_spi_transfer(struct spi_device *spi, | |
310 | struct spi_message *m) | |
311 | { | |
312 | struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); | |
313 | unsigned long flags; | |
314 | ||
315 | m->actual_length = 0; | |
316 | m->status = -EINPROGRESS; | |
317 | ||
318 | spin_lock_irqsave(&mps->lock, flags); | |
319 | list_add_tail(&m->queue, &mps->queue); | |
320 | queue_work(mps->workqueue, &mps->work); | |
321 | spin_unlock_irqrestore(&mps->lock, flags); | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
326 | static void mpc52xx_psc_spi_cleanup(struct spi_device *spi) | |
327 | { | |
328 | kfree(spi->controller_state); | |
329 | } | |
330 | ||
331 | static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps) | |
332 | { | |
333 | struct mpc52xx_cdm __iomem *cdm; | |
334 | struct mpc52xx_gpio __iomem *gpio; | |
335 | struct mpc52xx_psc __iomem *psc = mps->psc; | |
336 | u32 ul; | |
337 | u32 mclken_div; | |
338 | int ret = 0; | |
339 | ||
340 | #if defined(CONFIG_PPC_MERGE) | |
8888735f DP |
341 | cdm = mpc52xx_find_and_map("mpc5200-cdm"); |
342 | gpio = mpc52xx_find_and_map("mpc5200-gpio"); | |
00b8fd23 DC |
343 | #else |
344 | cdm = ioremap(MPC52xx_PA(MPC52xx_CDM_OFFSET), MPC52xx_CDM_SIZE); | |
345 | gpio = ioremap(MPC52xx_PA(MPC52xx_GPIO_OFFSET), MPC52xx_GPIO_SIZE); | |
346 | #endif | |
347 | if (!cdm || !gpio) { | |
348 | printk(KERN_ERR "Error mapping CDM/GPIO\n"); | |
349 | ret = -EFAULT; | |
350 | goto unmap_regs; | |
351 | } | |
352 | ||
353 | /* default sysclk is 512MHz */ | |
354 | mclken_div = 0x8000 | | |
355 | (((mps->sysclk ? mps->sysclk : 512000000) / MCLK) & 0x1FF); | |
356 | ||
357 | switch (psc_id) { | |
358 | case 1: | |
359 | ul = in_be32(&gpio->port_config); | |
360 | ul &= 0xFFFFFFF8; | |
361 | ul |= 0x00000006; | |
362 | out_be32(&gpio->port_config, ul); | |
363 | out_be16(&cdm->mclken_div_psc1, mclken_div); | |
364 | ul = in_be32(&cdm->clk_enables); | |
365 | ul |= 0x00000020; | |
366 | out_be32(&cdm->clk_enables, ul); | |
367 | break; | |
368 | case 2: | |
369 | ul = in_be32(&gpio->port_config); | |
370 | ul &= 0xFFFFFF8F; | |
371 | ul |= 0x00000060; | |
372 | out_be32(&gpio->port_config, ul); | |
373 | out_be16(&cdm->mclken_div_psc2, mclken_div); | |
374 | ul = in_be32(&cdm->clk_enables); | |
375 | ul |= 0x00000040; | |
376 | out_be32(&cdm->clk_enables, ul); | |
377 | break; | |
378 | case 3: | |
379 | ul = in_be32(&gpio->port_config); | |
380 | ul &= 0xFFFFF0FF; | |
381 | ul |= 0x00000600; | |
382 | out_be32(&gpio->port_config, ul); | |
383 | out_be16(&cdm->mclken_div_psc3, mclken_div); | |
384 | ul = in_be32(&cdm->clk_enables); | |
385 | ul |= 0x00000080; | |
386 | out_be32(&cdm->clk_enables, ul); | |
387 | break; | |
388 | case 6: | |
389 | ul = in_be32(&gpio->port_config); | |
390 | ul &= 0xFF8FFFFF; | |
391 | ul |= 0x00700000; | |
392 | out_be32(&gpio->port_config, ul); | |
393 | out_be16(&cdm->mclken_div_psc6, mclken_div); | |
394 | ul = in_be32(&cdm->clk_enables); | |
395 | ul |= 0x00000010; | |
396 | out_be32(&cdm->clk_enables, ul); | |
397 | break; | |
398 | default: | |
399 | ret = -EINVAL; | |
400 | goto unmap_regs; | |
401 | } | |
402 | ||
403 | /* Reset the PSC into a known state */ | |
404 | out_8(&psc->command, MPC52xx_PSC_RST_RX); | |
405 | out_8(&psc->command, MPC52xx_PSC_RST_TX); | |
406 | out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); | |
407 | ||
408 | /* Disable interrupts, interrupts are based on alarm level */ | |
409 | out_be16(&psc->mpc52xx_psc_imr, 0); | |
410 | out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); | |
411 | out_8(&psc->rfcntl, 0); | |
412 | out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL); | |
413 | ||
414 | /* Configure 8bit codec mode as a SPI master and use EOF flags */ | |
415 | /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */ | |
416 | out_be32(&psc->sicr, 0x0180C800); | |
417 | out_be16(&psc->ccr, 0x070F); /* by default SPI Clk 1MHz */ | |
418 | ||
419 | /* Set 2ms DTL delay */ | |
420 | out_8(&psc->ctur, 0x00); | |
421 | out_8(&psc->ctlr, 0x84); | |
422 | ||
423 | mps->bits_per_word = 8; | |
424 | ||
425 | unmap_regs: | |
426 | if (cdm) | |
427 | iounmap(cdm); | |
428 | if (gpio) | |
429 | iounmap(gpio); | |
430 | ||
431 | return ret; | |
432 | } | |
433 | ||
434 | static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id) | |
435 | { | |
436 | struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id; | |
437 | struct mpc52xx_psc __iomem *psc = mps->psc; | |
438 | ||
439 | /* disable interrupt and wake up the work queue */ | |
440 | if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) { | |
441 | out_be16(&psc->mpc52xx_psc_imr, 0); | |
442 | complete(&mps->done); | |
443 | return IRQ_HANDLED; | |
444 | } | |
445 | return IRQ_NONE; | |
446 | } | |
447 | ||
448 | /* bus_num is used only for the case dev->platform_data == NULL */ | |
449 | static int __init mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr, | |
450 | u32 size, unsigned int irq, s16 bus_num) | |
451 | { | |
452 | struct fsl_spi_platform_data *pdata = dev->platform_data; | |
453 | struct mpc52xx_psc_spi *mps; | |
454 | struct spi_master *master; | |
455 | int ret; | |
456 | ||
00b8fd23 DC |
457 | master = spi_alloc_master(dev, sizeof *mps); |
458 | if (master == NULL) | |
459 | return -ENOMEM; | |
460 | ||
461 | dev_set_drvdata(dev, master); | |
462 | mps = spi_master_get_devdata(master); | |
463 | ||
464 | mps->irq = irq; | |
465 | if (pdata == NULL) { | |
466 | dev_warn(dev, "probe called without platform data, no " | |
467 | "(de)activate_cs function will be called\n"); | |
468 | mps->activate_cs = NULL; | |
469 | mps->deactivate_cs = NULL; | |
470 | mps->sysclk = 0; | |
471 | master->bus_num = bus_num; | |
472 | master->num_chipselect = 255; | |
473 | } else { | |
474 | mps->activate_cs = pdata->activate_cs; | |
475 | mps->deactivate_cs = pdata->deactivate_cs; | |
476 | mps->sysclk = pdata->sysclk; | |
477 | master->bus_num = pdata->bus_num; | |
478 | master->num_chipselect = pdata->max_chipselect; | |
479 | } | |
480 | master->setup = mpc52xx_psc_spi_setup; | |
481 | master->transfer = mpc52xx_psc_spi_transfer; | |
482 | master->cleanup = mpc52xx_psc_spi_cleanup; | |
483 | ||
484 | mps->psc = ioremap(regaddr, size); | |
485 | if (!mps->psc) { | |
486 | dev_err(dev, "could not ioremap I/O port range\n"); | |
487 | ret = -EFAULT; | |
488 | goto free_master; | |
489 | } | |
490 | ||
491 | ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi", | |
492 | mps); | |
493 | if (ret) | |
494 | goto free_master; | |
495 | ||
496 | ret = mpc52xx_psc_spi_port_config(master->bus_num, mps); | |
497 | if (ret < 0) | |
498 | goto free_irq; | |
499 | ||
500 | spin_lock_init(&mps->lock); | |
501 | init_completion(&mps->done); | |
502 | INIT_WORK(&mps->work, mpc52xx_psc_spi_work); | |
503 | INIT_LIST_HEAD(&mps->queue); | |
504 | ||
505 | mps->workqueue = create_singlethread_workqueue( | |
49dce689 | 506 | master->dev.parent->bus_id); |
00b8fd23 DC |
507 | if (mps->workqueue == NULL) { |
508 | ret = -EBUSY; | |
509 | goto free_irq; | |
510 | } | |
511 | ||
512 | ret = spi_register_master(master); | |
513 | if (ret < 0) | |
514 | goto unreg_master; | |
515 | ||
516 | return ret; | |
517 | ||
518 | unreg_master: | |
519 | destroy_workqueue(mps->workqueue); | |
520 | free_irq: | |
521 | free_irq(mps->irq, mps); | |
522 | free_master: | |
523 | if (mps->psc) | |
524 | iounmap(mps->psc); | |
525 | spi_master_put(master); | |
526 | ||
527 | return ret; | |
528 | } | |
529 | ||
530 | static int __exit mpc52xx_psc_spi_do_remove(struct device *dev) | |
531 | { | |
532 | struct spi_master *master = dev_get_drvdata(dev); | |
533 | struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master); | |
534 | ||
535 | flush_workqueue(mps->workqueue); | |
536 | destroy_workqueue(mps->workqueue); | |
537 | spi_unregister_master(master); | |
538 | free_irq(mps->irq, mps); | |
539 | if (mps->psc) | |
540 | iounmap(mps->psc); | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
545 | #if !defined(CONFIG_PPC_MERGE) | |
546 | static int __init mpc52xx_psc_spi_probe(struct platform_device *dev) | |
547 | { | |
548 | switch(dev->id) { | |
549 | case 1: | |
550 | case 2: | |
551 | case 3: | |
552 | case 6: | |
553 | return mpc52xx_psc_spi_do_probe(&dev->dev, | |
554 | MPC52xx_PA(MPC52xx_PSCx_OFFSET(dev->id)), | |
555 | MPC52xx_PSC_SIZE, platform_get_irq(dev, 0), dev->id); | |
556 | default: | |
557 | return -EINVAL; | |
558 | } | |
559 | } | |
560 | ||
561 | static int __exit mpc52xx_psc_spi_remove(struct platform_device *dev) | |
562 | { | |
563 | return mpc52xx_psc_spi_do_remove(&dev->dev); | |
564 | } | |
565 | ||
566 | static struct platform_driver mpc52xx_psc_spi_platform_driver = { | |
567 | .remove = __exit_p(mpc52xx_psc_spi_remove), | |
568 | .driver = { | |
569 | .name = "mpc52xx-psc-spi", | |
570 | .owner = THIS_MODULE, | |
571 | }, | |
572 | }; | |
573 | ||
574 | static int __init mpc52xx_psc_spi_init(void) | |
575 | { | |
576 | return platform_driver_probe(&mpc52xx_psc_spi_platform_driver, | |
577 | mpc52xx_psc_spi_probe); | |
578 | } | |
579 | module_init(mpc52xx_psc_spi_init); | |
580 | ||
581 | static void __exit mpc52xx_psc_spi_exit(void) | |
582 | { | |
583 | platform_driver_unregister(&mpc52xx_psc_spi_platform_driver); | |
584 | } | |
585 | module_exit(mpc52xx_psc_spi_exit); | |
586 | ||
587 | #else /* defined(CONFIG_PPC_MERGE) */ | |
588 | ||
589 | static int __init mpc52xx_psc_spi_of_probe(struct of_device *op, | |
590 | const struct of_device_id *match) | |
591 | { | |
592 | const u32 *regaddr_p; | |
593 | u64 regaddr64, size64; | |
594 | s16 id = -1; | |
595 | ||
596 | regaddr_p = of_get_address(op->node, 0, &size64, NULL); | |
597 | if (!regaddr_p) { | |
598 | printk(KERN_ERR "Invalid PSC address\n"); | |
599 | return -EINVAL; | |
600 | } | |
601 | regaddr64 = of_translate_address(op->node, regaddr_p); | |
602 | ||
8888735f | 603 | /* get PSC id (1..6, used by port_config) */ |
00b8fd23 | 604 | if (op->dev.platform_data == NULL) { |
8888735f | 605 | const u32 *psc_nump; |
00b8fd23 | 606 | |
8888735f DP |
607 | psc_nump = of_get_property(op->node, "cell-index", NULL); |
608 | if (!psc_nump || *psc_nump > 5) { | |
609 | printk(KERN_ERR "mpc52xx_psc_spi: Device node %s has invalid " | |
610 | "cell-index property\n", op->node->full_name); | |
611 | return -EINVAL; | |
00b8fd23 | 612 | } |
8888735f | 613 | id = *psc_nump + 1; |
00b8fd23 DC |
614 | } |
615 | ||
616 | return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64, | |
617 | irq_of_parse_and_map(op->node, 0), id); | |
618 | } | |
619 | ||
620 | static int __exit mpc52xx_psc_spi_of_remove(struct of_device *op) | |
621 | { | |
622 | return mpc52xx_psc_spi_do_remove(&op->dev); | |
623 | } | |
624 | ||
625 | static struct of_device_id mpc52xx_psc_spi_of_match[] = { | |
8888735f | 626 | { .type = "spi", .compatible = "mpc5200-psc-spi", }, |
00b8fd23 DC |
627 | {}, |
628 | }; | |
629 | ||
630 | MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match); | |
631 | ||
632 | static struct of_platform_driver mpc52xx_psc_spi_of_driver = { | |
633 | .owner = THIS_MODULE, | |
634 | .name = "mpc52xx-psc-spi", | |
635 | .match_table = mpc52xx_psc_spi_of_match, | |
636 | .probe = mpc52xx_psc_spi_of_probe, | |
637 | .remove = __exit_p(mpc52xx_psc_spi_of_remove), | |
638 | .driver = { | |
639 | .name = "mpc52xx-psc-spi", | |
640 | .owner = THIS_MODULE, | |
641 | }, | |
642 | }; | |
643 | ||
644 | static int __init mpc52xx_psc_spi_init(void) | |
645 | { | |
646 | return of_register_platform_driver(&mpc52xx_psc_spi_of_driver); | |
647 | } | |
648 | module_init(mpc52xx_psc_spi_init); | |
649 | ||
650 | static void __exit mpc52xx_psc_spi_exit(void) | |
651 | { | |
652 | of_unregister_platform_driver(&mpc52xx_psc_spi_of_driver); | |
653 | } | |
654 | module_exit(mpc52xx_psc_spi_exit); | |
655 | ||
656 | #endif /* defined(CONFIG_PPC_MERGE) */ | |
657 | ||
658 | MODULE_AUTHOR("Dragos Carp"); | |
659 | MODULE_DESCRIPTION("MPC52xx PSC SPI Driver"); | |
660 | MODULE_LICENSE("GPL"); |