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ccdc7bf9 SO |
1 | /* |
2 | * OMAP2 McSPI controller driver | |
3 | * | |
4 | * Copyright (C) 2005, 2006 Nokia Corporation | |
5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and | |
1a5d8190 | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
ccdc7bf9 SO |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/device.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/dma-mapping.h> | |
31 | #include <linux/platform_device.h> | |
32 | #include <linux/err.h> | |
33 | #include <linux/clk.h> | |
34 | #include <linux/io.h> | |
5a0e3ad6 | 35 | #include <linux/slab.h> |
ccdc7bf9 SO |
36 | |
37 | #include <linux/spi/spi.h> | |
38 | ||
ce491cf8 TL |
39 | #include <plat/dma.h> |
40 | #include <plat/clock.h> | |
4743a0f8 | 41 | #include <plat/mcspi.h> |
ccdc7bf9 SO |
42 | |
43 | #define OMAP2_MCSPI_MAX_FREQ 48000000 | |
44 | ||
a41ae1ad H |
45 | /* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */ |
46 | #define OMAP2_MCSPI_MAX_CTRL 4 | |
47 | ||
ccdc7bf9 SO |
48 | #define OMAP2_MCSPI_REVISION 0x00 |
49 | #define OMAP2_MCSPI_SYSCONFIG 0x10 | |
50 | #define OMAP2_MCSPI_SYSSTATUS 0x14 | |
51 | #define OMAP2_MCSPI_IRQSTATUS 0x18 | |
52 | #define OMAP2_MCSPI_IRQENABLE 0x1c | |
53 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 | |
54 | #define OMAP2_MCSPI_SYST 0x24 | |
55 | #define OMAP2_MCSPI_MODULCTRL 0x28 | |
56 | ||
57 | /* per-channel banks, 0x14 bytes each, first is: */ | |
58 | #define OMAP2_MCSPI_CHCONF0 0x2c | |
59 | #define OMAP2_MCSPI_CHSTAT0 0x30 | |
60 | #define OMAP2_MCSPI_CHCTRL0 0x34 | |
61 | #define OMAP2_MCSPI_TX0 0x38 | |
62 | #define OMAP2_MCSPI_RX0 0x3c | |
63 | ||
64 | /* per-register bitmasks: */ | |
65 | ||
7a8fa725 JH |
66 | #define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4) |
67 | #define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2) | |
68 | #define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0) | |
69 | #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1) | |
ccdc7bf9 | 70 | |
7a8fa725 | 71 | #define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0) |
ccdc7bf9 | 72 | |
7a8fa725 JH |
73 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
74 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) | |
75 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) | |
ccdc7bf9 | 76 | |
7a8fa725 JH |
77 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
78 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) | |
ccdc7bf9 | 79 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
7a8fa725 | 80 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
ccdc7bf9 | 81 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
7a8fa725 JH |
82 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
83 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) | |
ccdc7bf9 | 84 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
7a8fa725 JH |
85 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
86 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) | |
87 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) | |
88 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) | |
89 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) | |
90 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) | |
91 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) | |
ccdc7bf9 | 92 | |
7a8fa725 JH |
93 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
94 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) | |
95 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) | |
ccdc7bf9 | 96 | |
7a8fa725 | 97 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
ccdc7bf9 | 98 | |
7a8fa725 | 99 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
ccdc7bf9 SO |
100 | |
101 | /* We have 2 DMA channels per CS, one for RX and one for TX */ | |
102 | struct omap2_mcspi_dma { | |
103 | int dma_tx_channel; | |
104 | int dma_rx_channel; | |
105 | ||
106 | int dma_tx_sync_dev; | |
107 | int dma_rx_sync_dev; | |
108 | ||
109 | struct completion dma_tx_completion; | |
110 | struct completion dma_rx_completion; | |
111 | }; | |
112 | ||
113 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and | |
114 | * cache operations; better heuristics consider wordsize and bitrate. | |
115 | */ | |
8b66c134 | 116 | #define DMA_MIN_BYTES 160 |
ccdc7bf9 SO |
117 | |
118 | ||
119 | struct omap2_mcspi { | |
120 | struct work_struct work; | |
121 | /* lock protects queue and registers */ | |
122 | spinlock_t lock; | |
123 | struct list_head msg_queue; | |
124 | struct spi_master *master; | |
125 | struct clk *ick; | |
126 | struct clk *fck; | |
127 | /* Virtual base address of the controller */ | |
128 | void __iomem *base; | |
e5480b73 | 129 | unsigned long phys; |
ccdc7bf9 SO |
130 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
131 | struct omap2_mcspi_dma *dma_channels; | |
132 | }; | |
133 | ||
134 | struct omap2_mcspi_cs { | |
135 | void __iomem *base; | |
e5480b73 | 136 | unsigned long phys; |
ccdc7bf9 | 137 | int word_len; |
89c05372 | 138 | struct list_head node; |
a41ae1ad H |
139 | /* Context save and restore shadow register */ |
140 | u32 chconf0; | |
141 | }; | |
142 | ||
143 | /* used for context save and restore, structure members to be updated whenever | |
144 | * corresponding registers are modified. | |
145 | */ | |
146 | struct omap2_mcspi_regs { | |
147 | u32 sysconfig; | |
148 | u32 modulctrl; | |
149 | u32 wakeupenable; | |
89c05372 | 150 | struct list_head cs; |
ccdc7bf9 SO |
151 | }; |
152 | ||
a41ae1ad H |
153 | static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL]; |
154 | ||
ccdc7bf9 SO |
155 | static struct workqueue_struct *omap2_mcspi_wq; |
156 | ||
157 | #define MOD_REG_BIT(val, mask, set) do { \ | |
158 | if (set) \ | |
159 | val |= mask; \ | |
160 | else \ | |
161 | val &= ~mask; \ | |
162 | } while (0) | |
163 | ||
164 | static inline void mcspi_write_reg(struct spi_master *master, | |
165 | int idx, u32 val) | |
166 | { | |
167 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
168 | ||
169 | __raw_writel(val, mcspi->base + idx); | |
170 | } | |
171 | ||
172 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) | |
173 | { | |
174 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
175 | ||
176 | return __raw_readl(mcspi->base + idx); | |
177 | } | |
178 | ||
179 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, | |
180 | int idx, u32 val) | |
181 | { | |
182 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
183 | ||
184 | __raw_writel(val, cs->base + idx); | |
185 | } | |
186 | ||
187 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) | |
188 | { | |
189 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
190 | ||
191 | return __raw_readl(cs->base + idx); | |
192 | } | |
193 | ||
a41ae1ad H |
194 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
195 | { | |
196 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
197 | ||
198 | return cs->chconf0; | |
199 | } | |
200 | ||
201 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) | |
202 | { | |
203 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
204 | ||
205 | cs->chconf0 = val; | |
206 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); | |
a330ce20 | 207 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
a41ae1ad H |
208 | } |
209 | ||
ccdc7bf9 SO |
210 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
211 | int is_read, int enable) | |
212 | { | |
213 | u32 l, rw; | |
214 | ||
a41ae1ad | 215 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
216 | |
217 | if (is_read) /* 1 is read, 0 write */ | |
218 | rw = OMAP2_MCSPI_CHCONF_DMAR; | |
219 | else | |
220 | rw = OMAP2_MCSPI_CHCONF_DMAW; | |
221 | ||
222 | MOD_REG_BIT(l, rw, enable); | |
a41ae1ad | 223 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
224 | } |
225 | ||
226 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) | |
227 | { | |
228 | u32 l; | |
229 | ||
230 | l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; | |
231 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); | |
4743a0f8 RT |
232 | /* Flash post-writes */ |
233 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); | |
ccdc7bf9 SO |
234 | } |
235 | ||
236 | static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) | |
237 | { | |
238 | u32 l; | |
239 | ||
a41ae1ad | 240 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 | 241 | MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active); |
a41ae1ad | 242 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
243 | } |
244 | ||
245 | static void omap2_mcspi_set_master_mode(struct spi_master *master) | |
246 | { | |
247 | u32 l; | |
248 | ||
249 | /* setup when switching from (reset default) slave mode | |
250 | * to single-channel master mode | |
251 | */ | |
252 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); | |
253 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0); | |
254 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0); | |
255 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1); | |
256 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); | |
a41ae1ad H |
257 | |
258 | omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l; | |
259 | } | |
260 | ||
261 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) | |
262 | { | |
263 | struct spi_master *spi_cntrl; | |
89c05372 | 264 | struct omap2_mcspi_cs *cs; |
a41ae1ad H |
265 | spi_cntrl = mcspi->master; |
266 | ||
267 | /* McSPI: context restore */ | |
268 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, | |
269 | omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl); | |
270 | ||
271 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG, | |
272 | omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig); | |
273 | ||
274 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, | |
275 | omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable); | |
89c05372 TK |
276 | |
277 | list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs, | |
278 | node) | |
279 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); | |
a41ae1ad H |
280 | } |
281 | static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi) | |
282 | { | |
283 | clk_disable(mcspi->ick); | |
284 | clk_disable(mcspi->fck); | |
285 | } | |
286 | ||
287 | static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi) | |
288 | { | |
289 | if (clk_enable(mcspi->ick)) | |
290 | return -ENODEV; | |
291 | if (clk_enable(mcspi->fck)) | |
292 | return -ENODEV; | |
293 | ||
294 | omap2_mcspi_restore_ctx(mcspi); | |
295 | ||
296 | return 0; | |
ccdc7bf9 SO |
297 | } |
298 | ||
2764c500 IK |
299 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
300 | { | |
301 | unsigned long timeout; | |
302 | ||
303 | timeout = jiffies + msecs_to_jiffies(1000); | |
304 | while (!(__raw_readl(reg) & bit)) { | |
305 | if (time_after(jiffies, timeout)) | |
306 | return -1; | |
307 | cpu_relax(); | |
308 | } | |
309 | return 0; | |
310 | } | |
311 | ||
ccdc7bf9 SO |
312 | static unsigned |
313 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) | |
314 | { | |
315 | struct omap2_mcspi *mcspi; | |
316 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
317 | struct omap2_mcspi_dma *mcspi_dma; | |
318 | unsigned int count, c; | |
319 | unsigned long base, tx_reg, rx_reg; | |
320 | int word_len, data_type, element_count; | |
4743a0f8 RT |
321 | int elements; |
322 | u32 l; | |
ccdc7bf9 SO |
323 | u8 * rx; |
324 | const u8 * tx; | |
2764c500 | 325 | void __iomem *chstat_reg; |
ccdc7bf9 SO |
326 | |
327 | mcspi = spi_master_get_devdata(spi->master); | |
328 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
4743a0f8 | 329 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 | 330 | |
2764c500 IK |
331 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
332 | ||
ccdc7bf9 SO |
333 | count = xfer->len; |
334 | c = count; | |
335 | word_len = cs->word_len; | |
336 | ||
e5480b73 | 337 | base = cs->phys; |
ccdc7bf9 SO |
338 | tx_reg = base + OMAP2_MCSPI_TX0; |
339 | rx_reg = base + OMAP2_MCSPI_RX0; | |
340 | rx = xfer->rx_buf; | |
341 | tx = xfer->tx_buf; | |
342 | ||
343 | if (word_len <= 8) { | |
344 | data_type = OMAP_DMA_DATA_TYPE_S8; | |
345 | element_count = count; | |
346 | } else if (word_len <= 16) { | |
347 | data_type = OMAP_DMA_DATA_TYPE_S16; | |
348 | element_count = count >> 1; | |
349 | } else /* word_len <= 32 */ { | |
350 | data_type = OMAP_DMA_DATA_TYPE_S32; | |
351 | element_count = count >> 2; | |
352 | } | |
353 | ||
354 | if (tx != NULL) { | |
355 | omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel, | |
356 | data_type, element_count, 1, | |
357 | OMAP_DMA_SYNC_ELEMENT, | |
358 | mcspi_dma->dma_tx_sync_dev, 0); | |
359 | ||
360 | omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0, | |
361 | OMAP_DMA_AMODE_CONSTANT, | |
362 | tx_reg, 0, 0); | |
363 | ||
364 | omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0, | |
365 | OMAP_DMA_AMODE_POST_INC, | |
366 | xfer->tx_dma, 0, 0); | |
367 | } | |
368 | ||
369 | if (rx != NULL) { | |
4743a0f8 RT |
370 | elements = element_count - 1; |
371 | if (l & OMAP2_MCSPI_CHCONF_TURBO) | |
372 | elements--; | |
373 | ||
ccdc7bf9 | 374 | omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel, |
4743a0f8 | 375 | data_type, elements, 1, |
ccdc7bf9 SO |
376 | OMAP_DMA_SYNC_ELEMENT, |
377 | mcspi_dma->dma_rx_sync_dev, 1); | |
378 | ||
379 | omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0, | |
380 | OMAP_DMA_AMODE_CONSTANT, | |
381 | rx_reg, 0, 0); | |
382 | ||
383 | omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0, | |
384 | OMAP_DMA_AMODE_POST_INC, | |
385 | xfer->rx_dma, 0, 0); | |
386 | } | |
387 | ||
388 | if (tx != NULL) { | |
389 | omap_start_dma(mcspi_dma->dma_tx_channel); | |
390 | omap2_mcspi_set_dma_req(spi, 0, 1); | |
391 | } | |
392 | ||
393 | if (rx != NULL) { | |
394 | omap_start_dma(mcspi_dma->dma_rx_channel); | |
395 | omap2_mcspi_set_dma_req(spi, 1, 1); | |
396 | } | |
397 | ||
398 | if (tx != NULL) { | |
399 | wait_for_completion(&mcspi_dma->dma_tx_completion); | |
07fe0351 | 400 | dma_unmap_single(&spi->dev, xfer->tx_dma, count, DMA_TO_DEVICE); |
2764c500 IK |
401 | |
402 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
403 | if (rx == NULL) { | |
404 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
405 | OMAP2_MCSPI_CHSTAT_TXS) < 0) | |
406 | dev_err(&spi->dev, "TXS timed out\n"); | |
407 | else if (mcspi_wait_for_reg_bit(chstat_reg, | |
408 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
409 | dev_err(&spi->dev, "EOT timed out\n"); | |
410 | } | |
ccdc7bf9 SO |
411 | } |
412 | ||
413 | if (rx != NULL) { | |
414 | wait_for_completion(&mcspi_dma->dma_rx_completion); | |
07fe0351 | 415 | dma_unmap_single(&spi->dev, xfer->rx_dma, count, DMA_FROM_DEVICE); |
57c5c28d | 416 | omap2_mcspi_set_enable(spi, 0); |
4743a0f8 RT |
417 | |
418 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { | |
419 | ||
420 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) | |
421 | & OMAP2_MCSPI_CHSTAT_RXS)) { | |
422 | u32 w; | |
423 | ||
424 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
425 | if (word_len <= 8) | |
426 | ((u8 *)xfer->rx_buf)[elements++] = w; | |
427 | else if (word_len <= 16) | |
428 | ((u16 *)xfer->rx_buf)[elements++] = w; | |
429 | else /* word_len <= 32 */ | |
430 | ((u32 *)xfer->rx_buf)[elements++] = w; | |
431 | } else { | |
432 | dev_err(&spi->dev, | |
433 | "DMA RX penultimate word empty"); | |
434 | count -= (word_len <= 8) ? 2 : | |
435 | (word_len <= 16) ? 4 : | |
436 | /* word_len <= 32 */ 8; | |
437 | omap2_mcspi_set_enable(spi, 1); | |
438 | return count; | |
439 | } | |
440 | } | |
441 | ||
57c5c28d EN |
442 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
443 | & OMAP2_MCSPI_CHSTAT_RXS)) { | |
444 | u32 w; | |
445 | ||
446 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
447 | if (word_len <= 8) | |
4743a0f8 | 448 | ((u8 *)xfer->rx_buf)[elements] = w; |
57c5c28d | 449 | else if (word_len <= 16) |
4743a0f8 | 450 | ((u16 *)xfer->rx_buf)[elements] = w; |
57c5c28d | 451 | else /* word_len <= 32 */ |
4743a0f8 | 452 | ((u32 *)xfer->rx_buf)[elements] = w; |
57c5c28d EN |
453 | } else { |
454 | dev_err(&spi->dev, "DMA RX last word empty"); | |
455 | count -= (word_len <= 8) ? 1 : | |
456 | (word_len <= 16) ? 2 : | |
457 | /* word_len <= 32 */ 4; | |
458 | } | |
459 | omap2_mcspi_set_enable(spi, 1); | |
ccdc7bf9 SO |
460 | } |
461 | return count; | |
462 | } | |
463 | ||
ccdc7bf9 SO |
464 | static unsigned |
465 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |
466 | { | |
467 | struct omap2_mcspi *mcspi; | |
468 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
469 | unsigned int count, c; | |
470 | u32 l; | |
471 | void __iomem *base = cs->base; | |
472 | void __iomem *tx_reg; | |
473 | void __iomem *rx_reg; | |
474 | void __iomem *chstat_reg; | |
475 | int word_len; | |
476 | ||
477 | mcspi = spi_master_get_devdata(spi->master); | |
478 | count = xfer->len; | |
479 | c = count; | |
480 | word_len = cs->word_len; | |
481 | ||
a41ae1ad | 482 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
483 | |
484 | /* We store the pre-calculated register addresses on stack to speed | |
485 | * up the transfer loop. */ | |
486 | tx_reg = base + OMAP2_MCSPI_TX0; | |
487 | rx_reg = base + OMAP2_MCSPI_RX0; | |
488 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; | |
489 | ||
490 | if (word_len <= 8) { | |
491 | u8 *rx; | |
492 | const u8 *tx; | |
493 | ||
494 | rx = xfer->rx_buf; | |
495 | tx = xfer->tx_buf; | |
496 | ||
497 | do { | |
feed9bab | 498 | c -= 1; |
ccdc7bf9 SO |
499 | if (tx != NULL) { |
500 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
501 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
502 | dev_err(&spi->dev, "TXS timed out\n"); | |
503 | goto out; | |
504 | } | |
079a176d | 505 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
ccdc7bf9 | 506 | word_len, *tx); |
ccdc7bf9 SO |
507 | __raw_writel(*tx++, tx_reg); |
508 | } | |
509 | if (rx != NULL) { | |
510 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
511 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
512 | dev_err(&spi->dev, "RXS timed out\n"); | |
513 | goto out; | |
514 | } | |
4743a0f8 RT |
515 | |
516 | if (c == 1 && tx == NULL && | |
517 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
518 | omap2_mcspi_set_enable(spi, 0); | |
519 | *rx++ = __raw_readl(rx_reg); | |
079a176d | 520 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
4743a0f8 | 521 | word_len, *(rx - 1)); |
4743a0f8 RT |
522 | if (mcspi_wait_for_reg_bit(chstat_reg, |
523 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
524 | dev_err(&spi->dev, | |
525 | "RXS timed out\n"); | |
526 | goto out; | |
527 | } | |
528 | c = 0; | |
529 | } else if (c == 0 && tx == NULL) { | |
530 | omap2_mcspi_set_enable(spi, 0); | |
531 | } | |
532 | ||
ccdc7bf9 | 533 | *rx++ = __raw_readl(rx_reg); |
079a176d | 534 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
ccdc7bf9 | 535 | word_len, *(rx - 1)); |
ccdc7bf9 | 536 | } |
ccdc7bf9 SO |
537 | } while (c); |
538 | } else if (word_len <= 16) { | |
539 | u16 *rx; | |
540 | const u16 *tx; | |
541 | ||
542 | rx = xfer->rx_buf; | |
543 | tx = xfer->tx_buf; | |
544 | do { | |
feed9bab | 545 | c -= 2; |
ccdc7bf9 SO |
546 | if (tx != NULL) { |
547 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
548 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
549 | dev_err(&spi->dev, "TXS timed out\n"); | |
550 | goto out; | |
551 | } | |
079a176d | 552 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
ccdc7bf9 | 553 | word_len, *tx); |
ccdc7bf9 SO |
554 | __raw_writel(*tx++, tx_reg); |
555 | } | |
556 | if (rx != NULL) { | |
557 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
558 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
559 | dev_err(&spi->dev, "RXS timed out\n"); | |
560 | goto out; | |
561 | } | |
4743a0f8 RT |
562 | |
563 | if (c == 2 && tx == NULL && | |
564 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
565 | omap2_mcspi_set_enable(spi, 0); | |
566 | *rx++ = __raw_readl(rx_reg); | |
079a176d | 567 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
4743a0f8 | 568 | word_len, *(rx - 1)); |
4743a0f8 RT |
569 | if (mcspi_wait_for_reg_bit(chstat_reg, |
570 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
571 | dev_err(&spi->dev, | |
572 | "RXS timed out\n"); | |
573 | goto out; | |
574 | } | |
575 | c = 0; | |
576 | } else if (c == 0 && tx == NULL) { | |
577 | omap2_mcspi_set_enable(spi, 0); | |
578 | } | |
579 | ||
ccdc7bf9 | 580 | *rx++ = __raw_readl(rx_reg); |
079a176d | 581 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
ccdc7bf9 | 582 | word_len, *(rx - 1)); |
ccdc7bf9 | 583 | } |
ccdc7bf9 SO |
584 | } while (c); |
585 | } else if (word_len <= 32) { | |
586 | u32 *rx; | |
587 | const u32 *tx; | |
588 | ||
589 | rx = xfer->rx_buf; | |
590 | tx = xfer->tx_buf; | |
591 | do { | |
feed9bab | 592 | c -= 4; |
ccdc7bf9 SO |
593 | if (tx != NULL) { |
594 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
595 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
596 | dev_err(&spi->dev, "TXS timed out\n"); | |
597 | goto out; | |
598 | } | |
079a176d | 599 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
ccdc7bf9 | 600 | word_len, *tx); |
ccdc7bf9 SO |
601 | __raw_writel(*tx++, tx_reg); |
602 | } | |
603 | if (rx != NULL) { | |
604 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
605 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
606 | dev_err(&spi->dev, "RXS timed out\n"); | |
607 | goto out; | |
608 | } | |
4743a0f8 RT |
609 | |
610 | if (c == 4 && tx == NULL && | |
611 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
612 | omap2_mcspi_set_enable(spi, 0); | |
613 | *rx++ = __raw_readl(rx_reg); | |
079a176d | 614 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
4743a0f8 | 615 | word_len, *(rx - 1)); |
4743a0f8 RT |
616 | if (mcspi_wait_for_reg_bit(chstat_reg, |
617 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
618 | dev_err(&spi->dev, | |
619 | "RXS timed out\n"); | |
620 | goto out; | |
621 | } | |
622 | c = 0; | |
623 | } else if (c == 0 && tx == NULL) { | |
624 | omap2_mcspi_set_enable(spi, 0); | |
625 | } | |
626 | ||
ccdc7bf9 | 627 | *rx++ = __raw_readl(rx_reg); |
079a176d | 628 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
ccdc7bf9 | 629 | word_len, *(rx - 1)); |
ccdc7bf9 | 630 | } |
ccdc7bf9 SO |
631 | } while (c); |
632 | } | |
633 | ||
634 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
635 | if (xfer->rx_buf == NULL) { | |
636 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
637 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
638 | dev_err(&spi->dev, "TXS timed out\n"); | |
639 | } else if (mcspi_wait_for_reg_bit(chstat_reg, | |
640 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
641 | dev_err(&spi->dev, "EOT timed out\n"); | |
e1993ed6 JW |
642 | |
643 | /* disable chan to purge rx datas received in TX_ONLY transfer, | |
644 | * otherwise these rx datas will affect the direct following | |
645 | * RX_ONLY transfer. | |
646 | */ | |
647 | omap2_mcspi_set_enable(spi, 0); | |
ccdc7bf9 SO |
648 | } |
649 | out: | |
4743a0f8 | 650 | omap2_mcspi_set_enable(spi, 1); |
ccdc7bf9 SO |
651 | return count - c; |
652 | } | |
653 | ||
654 | /* called only when no transfer is active to this device */ | |
655 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, | |
656 | struct spi_transfer *t) | |
657 | { | |
658 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
659 | struct omap2_mcspi *mcspi; | |
a41ae1ad | 660 | struct spi_master *spi_cntrl; |
ccdc7bf9 SO |
661 | u32 l = 0, div = 0; |
662 | u8 word_len = spi->bits_per_word; | |
9bd4517d | 663 | u32 speed_hz = spi->max_speed_hz; |
ccdc7bf9 SO |
664 | |
665 | mcspi = spi_master_get_devdata(spi->master); | |
a41ae1ad | 666 | spi_cntrl = mcspi->master; |
ccdc7bf9 SO |
667 | |
668 | if (t != NULL && t->bits_per_word) | |
669 | word_len = t->bits_per_word; | |
670 | ||
671 | cs->word_len = word_len; | |
672 | ||
9bd4517d SE |
673 | if (t && t->speed_hz) |
674 | speed_hz = t->speed_hz; | |
675 | ||
676 | if (speed_hz) { | |
ccdc7bf9 | 677 | while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div)) |
9bd4517d | 678 | > speed_hz) |
ccdc7bf9 SO |
679 | div++; |
680 | } else | |
681 | div = 15; | |
682 | ||
a41ae1ad | 683 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
684 | |
685 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS | |
686 | * REVISIT: this controller could support SPI_3WIRE mode. | |
687 | */ | |
688 | l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1); | |
689 | l |= OMAP2_MCSPI_CHCONF_DPE0; | |
690 | ||
691 | /* wordlength */ | |
692 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; | |
693 | l |= (word_len - 1) << 7; | |
694 | ||
695 | /* set chipselect polarity; manage with FORCE */ | |
696 | if (!(spi->mode & SPI_CS_HIGH)) | |
697 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ | |
698 | else | |
699 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; | |
700 | ||
701 | /* set clock divisor */ | |
702 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; | |
703 | l |= div << 2; | |
704 | ||
705 | /* set SPI mode 0..3 */ | |
706 | if (spi->mode & SPI_CPOL) | |
707 | l |= OMAP2_MCSPI_CHCONF_POL; | |
708 | else | |
709 | l &= ~OMAP2_MCSPI_CHCONF_POL; | |
710 | if (spi->mode & SPI_CPHA) | |
711 | l |= OMAP2_MCSPI_CHCONF_PHA; | |
712 | else | |
713 | l &= ~OMAP2_MCSPI_CHCONF_PHA; | |
714 | ||
a41ae1ad | 715 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
716 | |
717 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", | |
718 | OMAP2_MCSPI_MAX_FREQ / (1 << div), | |
719 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", | |
720 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); | |
721 | ||
722 | return 0; | |
723 | } | |
724 | ||
725 | static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data) | |
726 | { | |
727 | struct spi_device *spi = data; | |
728 | struct omap2_mcspi *mcspi; | |
729 | struct omap2_mcspi_dma *mcspi_dma; | |
730 | ||
731 | mcspi = spi_master_get_devdata(spi->master); | |
732 | mcspi_dma = &(mcspi->dma_channels[spi->chip_select]); | |
733 | ||
734 | complete(&mcspi_dma->dma_rx_completion); | |
735 | ||
736 | /* We must disable the DMA RX request */ | |
737 | omap2_mcspi_set_dma_req(spi, 1, 0); | |
738 | } | |
739 | ||
740 | static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data) | |
741 | { | |
742 | struct spi_device *spi = data; | |
743 | struct omap2_mcspi *mcspi; | |
744 | struct omap2_mcspi_dma *mcspi_dma; | |
745 | ||
746 | mcspi = spi_master_get_devdata(spi->master); | |
747 | mcspi_dma = &(mcspi->dma_channels[spi->chip_select]); | |
748 | ||
749 | complete(&mcspi_dma->dma_tx_completion); | |
750 | ||
751 | /* We must disable the DMA TX request */ | |
752 | omap2_mcspi_set_dma_req(spi, 0, 0); | |
753 | } | |
754 | ||
755 | static int omap2_mcspi_request_dma(struct spi_device *spi) | |
756 | { | |
757 | struct spi_master *master = spi->master; | |
758 | struct omap2_mcspi *mcspi; | |
759 | struct omap2_mcspi_dma *mcspi_dma; | |
760 | ||
761 | mcspi = spi_master_get_devdata(master); | |
762 | mcspi_dma = mcspi->dma_channels + spi->chip_select; | |
763 | ||
764 | if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX", | |
765 | omap2_mcspi_dma_rx_callback, spi, | |
766 | &mcspi_dma->dma_rx_channel)) { | |
767 | dev_err(&spi->dev, "no RX DMA channel for McSPI\n"); | |
768 | return -EAGAIN; | |
769 | } | |
770 | ||
771 | if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX", | |
772 | omap2_mcspi_dma_tx_callback, spi, | |
773 | &mcspi_dma->dma_tx_channel)) { | |
774 | omap_free_dma(mcspi_dma->dma_rx_channel); | |
775 | mcspi_dma->dma_rx_channel = -1; | |
776 | dev_err(&spi->dev, "no TX DMA channel for McSPI\n"); | |
777 | return -EAGAIN; | |
778 | } | |
779 | ||
780 | init_completion(&mcspi_dma->dma_rx_completion); | |
781 | init_completion(&mcspi_dma->dma_tx_completion); | |
782 | ||
783 | return 0; | |
784 | } | |
785 | ||
ccdc7bf9 SO |
786 | static int omap2_mcspi_setup(struct spi_device *spi) |
787 | { | |
788 | int ret; | |
789 | struct omap2_mcspi *mcspi; | |
790 | struct omap2_mcspi_dma *mcspi_dma; | |
791 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
792 | ||
7d077197 | 793 | if (spi->bits_per_word < 4 || spi->bits_per_word > 32) { |
ccdc7bf9 SO |
794 | dev_dbg(&spi->dev, "setup: unsupported %d bit words\n", |
795 | spi->bits_per_word); | |
796 | return -EINVAL; | |
797 | } | |
798 | ||
799 | mcspi = spi_master_get_devdata(spi->master); | |
800 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
801 | ||
802 | if (!cs) { | |
803 | cs = kzalloc(sizeof *cs, GFP_KERNEL); | |
804 | if (!cs) | |
805 | return -ENOMEM; | |
806 | cs->base = mcspi->base + spi->chip_select * 0x14; | |
e5480b73 | 807 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
a41ae1ad | 808 | cs->chconf0 = 0; |
ccdc7bf9 | 809 | spi->controller_state = cs; |
89c05372 TK |
810 | /* Link this to context save list */ |
811 | list_add_tail(&cs->node, | |
812 | &omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs); | |
ccdc7bf9 SO |
813 | } |
814 | ||
815 | if (mcspi_dma->dma_rx_channel == -1 | |
816 | || mcspi_dma->dma_tx_channel == -1) { | |
817 | ret = omap2_mcspi_request_dma(spi); | |
818 | if (ret < 0) | |
819 | return ret; | |
820 | } | |
821 | ||
a41ae1ad H |
822 | if (omap2_mcspi_enable_clocks(mcspi)) |
823 | return -ENODEV; | |
824 | ||
86eeb6fe | 825 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
a41ae1ad | 826 | omap2_mcspi_disable_clocks(mcspi); |
ccdc7bf9 SO |
827 | |
828 | return ret; | |
829 | } | |
830 | ||
831 | static void omap2_mcspi_cleanup(struct spi_device *spi) | |
832 | { | |
833 | struct omap2_mcspi *mcspi; | |
834 | struct omap2_mcspi_dma *mcspi_dma; | |
89c05372 | 835 | struct omap2_mcspi_cs *cs; |
ccdc7bf9 SO |
836 | |
837 | mcspi = spi_master_get_devdata(spi->master); | |
ccdc7bf9 | 838 | |
5e774943 SE |
839 | if (spi->controller_state) { |
840 | /* Unlink controller state from context save list */ | |
841 | cs = spi->controller_state; | |
842 | list_del(&cs->node); | |
89c05372 | 843 | |
5e774943 SE |
844 | kfree(spi->controller_state); |
845 | } | |
ccdc7bf9 | 846 | |
99f1a43f SE |
847 | if (spi->chip_select < spi->master->num_chipselect) { |
848 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
849 | ||
850 | if (mcspi_dma->dma_rx_channel != -1) { | |
851 | omap_free_dma(mcspi_dma->dma_rx_channel); | |
852 | mcspi_dma->dma_rx_channel = -1; | |
853 | } | |
854 | if (mcspi_dma->dma_tx_channel != -1) { | |
855 | omap_free_dma(mcspi_dma->dma_tx_channel); | |
856 | mcspi_dma->dma_tx_channel = -1; | |
857 | } | |
ccdc7bf9 SO |
858 | } |
859 | } | |
860 | ||
861 | static void omap2_mcspi_work(struct work_struct *work) | |
862 | { | |
863 | struct omap2_mcspi *mcspi; | |
864 | ||
865 | mcspi = container_of(work, struct omap2_mcspi, work); | |
866 | spin_lock_irq(&mcspi->lock); | |
867 | ||
a41ae1ad H |
868 | if (omap2_mcspi_enable_clocks(mcspi)) |
869 | goto out; | |
ccdc7bf9 SO |
870 | |
871 | /* We only enable one channel at a time -- the one whose message is | |
872 | * at the head of the queue -- although this controller would gladly | |
873 | * arbitrate among multiple channels. This corresponds to "single | |
874 | * channel" master mode. As a side effect, we need to manage the | |
875 | * chipselect with the FORCE bit ... CS != channel enable. | |
876 | */ | |
877 | while (!list_empty(&mcspi->msg_queue)) { | |
878 | struct spi_message *m; | |
879 | struct spi_device *spi; | |
880 | struct spi_transfer *t = NULL; | |
881 | int cs_active = 0; | |
ccdc7bf9 | 882 | struct omap2_mcspi_cs *cs; |
4743a0f8 | 883 | struct omap2_mcspi_device_config *cd; |
ccdc7bf9 SO |
884 | int par_override = 0; |
885 | int status = 0; | |
886 | u32 chconf; | |
887 | ||
888 | m = container_of(mcspi->msg_queue.next, struct spi_message, | |
889 | queue); | |
890 | ||
891 | list_del_init(&m->queue); | |
892 | spin_unlock_irq(&mcspi->lock); | |
893 | ||
894 | spi = m->spi; | |
ccdc7bf9 | 895 | cs = spi->controller_state; |
4743a0f8 | 896 | cd = spi->controller_data; |
ccdc7bf9 SO |
897 | |
898 | omap2_mcspi_set_enable(spi, 1); | |
899 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
900 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { | |
901 | status = -EINVAL; | |
902 | break; | |
903 | } | |
904 | if (par_override || t->speed_hz || t->bits_per_word) { | |
905 | par_override = 1; | |
906 | status = omap2_mcspi_setup_transfer(spi, t); | |
907 | if (status < 0) | |
908 | break; | |
909 | if (!t->speed_hz && !t->bits_per_word) | |
910 | par_override = 0; | |
911 | } | |
912 | ||
913 | if (!cs_active) { | |
914 | omap2_mcspi_force_cs(spi, 1); | |
915 | cs_active = 1; | |
916 | } | |
917 | ||
a41ae1ad | 918 | chconf = mcspi_cached_chconf0(spi); |
ccdc7bf9 | 919 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; |
4743a0f8 RT |
920 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; |
921 | ||
ccdc7bf9 SO |
922 | if (t->tx_buf == NULL) |
923 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; | |
924 | else if (t->rx_buf == NULL) | |
925 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; | |
4743a0f8 RT |
926 | |
927 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { | |
928 | /* Turbo mode is for more than one word */ | |
929 | if (t->len > ((cs->word_len + 7) >> 3)) | |
930 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; | |
931 | } | |
932 | ||
a41ae1ad | 933 | mcspi_write_chconf0(spi, chconf); |
ccdc7bf9 SO |
934 | |
935 | if (t->len) { | |
936 | unsigned count; | |
937 | ||
938 | /* RX_ONLY mode needs dummy data in TX reg */ | |
939 | if (t->tx_buf == NULL) | |
940 | __raw_writel(0, cs->base | |
941 | + OMAP2_MCSPI_TX0); | |
942 | ||
943 | if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES) | |
944 | count = omap2_mcspi_txrx_dma(spi, t); | |
945 | else | |
946 | count = omap2_mcspi_txrx_pio(spi, t); | |
947 | m->actual_length += count; | |
948 | ||
949 | if (count != t->len) { | |
950 | status = -EIO; | |
951 | break; | |
952 | } | |
953 | } | |
954 | ||
955 | if (t->delay_usecs) | |
956 | udelay(t->delay_usecs); | |
957 | ||
958 | /* ignore the "leave it on after last xfer" hint */ | |
959 | if (t->cs_change) { | |
960 | omap2_mcspi_force_cs(spi, 0); | |
961 | cs_active = 0; | |
962 | } | |
963 | } | |
964 | ||
965 | /* Restore defaults if they were overriden */ | |
966 | if (par_override) { | |
967 | par_override = 0; | |
968 | status = omap2_mcspi_setup_transfer(spi, NULL); | |
969 | } | |
970 | ||
971 | if (cs_active) | |
972 | omap2_mcspi_force_cs(spi, 0); | |
973 | ||
974 | omap2_mcspi_set_enable(spi, 0); | |
975 | ||
976 | m->status = status; | |
977 | m->complete(m->context); | |
978 | ||
979 | spin_lock_irq(&mcspi->lock); | |
980 | } | |
981 | ||
a41ae1ad | 982 | omap2_mcspi_disable_clocks(mcspi); |
ccdc7bf9 | 983 | |
a41ae1ad | 984 | out: |
ccdc7bf9 SO |
985 | spin_unlock_irq(&mcspi->lock); |
986 | } | |
987 | ||
988 | static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m) | |
989 | { | |
990 | struct omap2_mcspi *mcspi; | |
991 | unsigned long flags; | |
992 | struct spi_transfer *t; | |
993 | ||
994 | m->actual_length = 0; | |
995 | m->status = 0; | |
996 | ||
997 | /* reject invalid messages and transfers */ | |
998 | if (list_empty(&m->transfers) || !m->complete) | |
999 | return -EINVAL; | |
1000 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
1001 | const void *tx_buf = t->tx_buf; | |
1002 | void *rx_buf = t->rx_buf; | |
1003 | unsigned len = t->len; | |
1004 | ||
1005 | if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ | |
1006 | || (len && !(rx_buf || tx_buf)) | |
1007 | || (t->bits_per_word && | |
1008 | ( t->bits_per_word < 4 | |
1009 | || t->bits_per_word > 32))) { | |
1010 | dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", | |
1011 | t->speed_hz, | |
1012 | len, | |
1013 | tx_buf ? "tx" : "", | |
1014 | rx_buf ? "rx" : "", | |
1015 | t->bits_per_word); | |
1016 | return -EINVAL; | |
1017 | } | |
1018 | if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) { | |
1019 | dev_dbg(&spi->dev, "%d Hz max exceeds %d\n", | |
1020 | t->speed_hz, | |
1021 | OMAP2_MCSPI_MAX_FREQ/(1<<16)); | |
1022 | return -EINVAL; | |
1023 | } | |
1024 | ||
1025 | if (m->is_dma_mapped || len < DMA_MIN_BYTES) | |
1026 | continue; | |
1027 | ||
ccdc7bf9 SO |
1028 | if (tx_buf != NULL) { |
1029 | t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf, | |
1030 | len, DMA_TO_DEVICE); | |
8d8bb39b | 1031 | if (dma_mapping_error(&spi->dev, t->tx_dma)) { |
ccdc7bf9 SO |
1032 | dev_dbg(&spi->dev, "dma %cX %d bytes error\n", |
1033 | 'T', len); | |
1034 | return -EINVAL; | |
1035 | } | |
1036 | } | |
1037 | if (rx_buf != NULL) { | |
1038 | t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len, | |
1039 | DMA_FROM_DEVICE); | |
8d8bb39b | 1040 | if (dma_mapping_error(&spi->dev, t->rx_dma)) { |
ccdc7bf9 SO |
1041 | dev_dbg(&spi->dev, "dma %cX %d bytes error\n", |
1042 | 'R', len); | |
1043 | if (tx_buf != NULL) | |
07fe0351 | 1044 | dma_unmap_single(&spi->dev, t->tx_dma, |
ccdc7bf9 SO |
1045 | len, DMA_TO_DEVICE); |
1046 | return -EINVAL; | |
1047 | } | |
1048 | } | |
1049 | } | |
1050 | ||
1051 | mcspi = spi_master_get_devdata(spi->master); | |
1052 | ||
1053 | spin_lock_irqsave(&mcspi->lock, flags); | |
1054 | list_add_tail(&m->queue, &mcspi->msg_queue); | |
1055 | queue_work(omap2_mcspi_wq, &mcspi->work); | |
1056 | spin_unlock_irqrestore(&mcspi->lock, flags); | |
1057 | ||
1058 | return 0; | |
1059 | } | |
1060 | ||
1061 | static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi) | |
1062 | { | |
1063 | struct spi_master *master = mcspi->master; | |
1064 | u32 tmp; | |
1065 | ||
a41ae1ad H |
1066 | if (omap2_mcspi_enable_clocks(mcspi)) |
1067 | return -1; | |
ccdc7bf9 SO |
1068 | |
1069 | mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, | |
1070 | OMAP2_MCSPI_SYSCONFIG_SOFTRESET); | |
1071 | do { | |
1072 | tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS); | |
1073 | } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE)); | |
1074 | ||
a41ae1ad H |
1075 | tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE | |
1076 | OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP | | |
1077 | OMAP2_MCSPI_SYSCONFIG_SMARTIDLE; | |
1078 | mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp); | |
1079 | omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp; | |
ddb22195 | 1080 | |
a41ae1ad H |
1081 | tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
1082 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp); | |
1083 | omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp; | |
ccdc7bf9 SO |
1084 | |
1085 | omap2_mcspi_set_master_mode(master); | |
a41ae1ad | 1086 | omap2_mcspi_disable_clocks(mcspi); |
ccdc7bf9 SO |
1087 | return 0; |
1088 | } | |
1089 | ||
ccc7baed | 1090 | |
ccdc7bf9 SO |
1091 | static int __init omap2_mcspi_probe(struct platform_device *pdev) |
1092 | { | |
1093 | struct spi_master *master; | |
1a5d8190 | 1094 | struct omap2_mcspi_platform_config *pdata = pdev->dev.platform_data; |
ccdc7bf9 SO |
1095 | struct omap2_mcspi *mcspi; |
1096 | struct resource *r; | |
1097 | int status = 0, i; | |
ccdc7bf9 SO |
1098 | |
1099 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); | |
1100 | if (master == NULL) { | |
1101 | dev_dbg(&pdev->dev, "master allocation failed\n"); | |
1102 | return -ENOMEM; | |
1103 | } | |
1104 | ||
e7db06b5 DB |
1105 | /* the spi->mode bits understood by this driver: */ |
1106 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
1107 | ||
ccdc7bf9 SO |
1108 | if (pdev->id != -1) |
1109 | master->bus_num = pdev->id; | |
1110 | ||
1111 | master->setup = omap2_mcspi_setup; | |
1112 | master->transfer = omap2_mcspi_transfer; | |
1113 | master->cleanup = omap2_mcspi_cleanup; | |
1a5d8190 | 1114 | master->num_chipselect = pdata->num_cs; |
ccdc7bf9 SO |
1115 | |
1116 | dev_set_drvdata(&pdev->dev, master); | |
1117 | ||
1118 | mcspi = spi_master_get_devdata(master); | |
1119 | mcspi->master = master; | |
1120 | ||
1121 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1122 | if (r == NULL) { | |
1123 | status = -ENODEV; | |
1124 | goto err1; | |
1125 | } | |
1126 | if (!request_mem_region(r->start, (r->end - r->start) + 1, | |
6c7377ab | 1127 | dev_name(&pdev->dev))) { |
ccdc7bf9 SO |
1128 | status = -EBUSY; |
1129 | goto err1; | |
1130 | } | |
1131 | ||
1a5d8190 C |
1132 | r->start += pdata->regs_offset; |
1133 | r->end += pdata->regs_offset; | |
e5480b73 | 1134 | mcspi->phys = r->start; |
55c381e4 RK |
1135 | mcspi->base = ioremap(r->start, r->end - r->start + 1); |
1136 | if (!mcspi->base) { | |
1137 | dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); | |
1138 | status = -ENOMEM; | |
1139 | goto err1aa; | |
1140 | } | |
ccdc7bf9 SO |
1141 | |
1142 | INIT_WORK(&mcspi->work, omap2_mcspi_work); | |
1143 | ||
1144 | spin_lock_init(&mcspi->lock); | |
1145 | INIT_LIST_HEAD(&mcspi->msg_queue); | |
89c05372 | 1146 | INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs); |
ccdc7bf9 | 1147 | |
1b5715ec | 1148 | mcspi->ick = clk_get(&pdev->dev, "ick"); |
ccdc7bf9 SO |
1149 | if (IS_ERR(mcspi->ick)) { |
1150 | dev_dbg(&pdev->dev, "can't get mcspi_ick\n"); | |
1151 | status = PTR_ERR(mcspi->ick); | |
1152 | goto err1a; | |
1153 | } | |
1b5715ec | 1154 | mcspi->fck = clk_get(&pdev->dev, "fck"); |
ccdc7bf9 SO |
1155 | if (IS_ERR(mcspi->fck)) { |
1156 | dev_dbg(&pdev->dev, "can't get mcspi_fck\n"); | |
1157 | status = PTR_ERR(mcspi->fck); | |
1158 | goto err2; | |
1159 | } | |
1160 | ||
1161 | mcspi->dma_channels = kcalloc(master->num_chipselect, | |
1162 | sizeof(struct omap2_mcspi_dma), | |
1163 | GFP_KERNEL); | |
1164 | ||
1165 | if (mcspi->dma_channels == NULL) | |
1166 | goto err3; | |
1167 | ||
1a5d8190 C |
1168 | for (i = 0; i < master->num_chipselect; i++) { |
1169 | char dma_ch_name[14]; | |
1170 | struct resource *dma_res; | |
1171 | ||
1172 | sprintf(dma_ch_name, "rx%d", i); | |
1173 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, | |
1174 | dma_ch_name); | |
1175 | if (!dma_res) { | |
1176 | dev_dbg(&pdev->dev, "cannot get DMA RX channel\n"); | |
1177 | status = -ENODEV; | |
1178 | break; | |
1179 | } | |
1180 | ||
ccdc7bf9 | 1181 | mcspi->dma_channels[i].dma_rx_channel = -1; |
1a5d8190 C |
1182 | mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; |
1183 | sprintf(dma_ch_name, "tx%d", i); | |
1184 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, | |
1185 | dma_ch_name); | |
1186 | if (!dma_res) { | |
1187 | dev_dbg(&pdev->dev, "cannot get DMA TX channel\n"); | |
1188 | status = -ENODEV; | |
1189 | break; | |
1190 | } | |
1191 | ||
ccdc7bf9 | 1192 | mcspi->dma_channels[i].dma_tx_channel = -1; |
1a5d8190 | 1193 | mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start; |
ccdc7bf9 SO |
1194 | } |
1195 | ||
1196 | if (omap2_mcspi_reset(mcspi) < 0) | |
1197 | goto err4; | |
1198 | ||
1199 | status = spi_register_master(master); | |
1200 | if (status < 0) | |
1201 | goto err4; | |
1202 | ||
1203 | return status; | |
1204 | ||
1205 | err4: | |
1206 | kfree(mcspi->dma_channels); | |
1207 | err3: | |
1208 | clk_put(mcspi->fck); | |
1209 | err2: | |
1210 | clk_put(mcspi->ick); | |
1211 | err1a: | |
55c381e4 RK |
1212 | iounmap(mcspi->base); |
1213 | err1aa: | |
ccdc7bf9 SO |
1214 | release_mem_region(r->start, (r->end - r->start) + 1); |
1215 | err1: | |
1216 | spi_master_put(master); | |
1217 | return status; | |
1218 | } | |
1219 | ||
1220 | static int __exit omap2_mcspi_remove(struct platform_device *pdev) | |
1221 | { | |
1222 | struct spi_master *master; | |
1223 | struct omap2_mcspi *mcspi; | |
1224 | struct omap2_mcspi_dma *dma_channels; | |
1225 | struct resource *r; | |
55c381e4 | 1226 | void __iomem *base; |
ccdc7bf9 SO |
1227 | |
1228 | master = dev_get_drvdata(&pdev->dev); | |
1229 | mcspi = spi_master_get_devdata(master); | |
1230 | dma_channels = mcspi->dma_channels; | |
1231 | ||
1232 | clk_put(mcspi->fck); | |
1233 | clk_put(mcspi->ick); | |
1234 | ||
1235 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1236 | release_mem_region(r->start, (r->end - r->start) + 1); | |
1237 | ||
55c381e4 | 1238 | base = mcspi->base; |
ccdc7bf9 | 1239 | spi_unregister_master(master); |
55c381e4 | 1240 | iounmap(base); |
ccdc7bf9 SO |
1241 | kfree(dma_channels); |
1242 | ||
1243 | return 0; | |
1244 | } | |
1245 | ||
7e38c3c4 KS |
1246 | /* work with hotplug and coldplug */ |
1247 | MODULE_ALIAS("platform:omap2_mcspi"); | |
1248 | ||
42ce7fd6 GC |
1249 | #ifdef CONFIG_SUSPEND |
1250 | /* | |
1251 | * When SPI wake up from off-mode, CS is in activate state. If it was in | |
1252 | * unactive state when driver was suspend, then force it to unactive state at | |
1253 | * wake up. | |
1254 | */ | |
1255 | static int omap2_mcspi_resume(struct device *dev) | |
1256 | { | |
1257 | struct spi_master *master = dev_get_drvdata(dev); | |
1258 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1259 | struct omap2_mcspi_cs *cs; | |
1260 | ||
1261 | omap2_mcspi_enable_clocks(mcspi); | |
1262 | list_for_each_entry(cs, &omap2_mcspi_ctx[master->bus_num - 1].cs, | |
1263 | node) { | |
1264 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { | |
1265 | ||
1266 | /* | |
1267 | * We need to toggle CS state for OMAP take this | |
1268 | * change in account. | |
1269 | */ | |
1270 | MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 1); | |
1271 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); | |
1272 | MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 0); | |
1273 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); | |
1274 | } | |
1275 | } | |
1276 | omap2_mcspi_disable_clocks(mcspi); | |
1277 | return 0; | |
1278 | } | |
1279 | #else | |
1280 | #define omap2_mcspi_resume NULL | |
1281 | #endif | |
1282 | ||
1283 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { | |
1284 | .resume = omap2_mcspi_resume, | |
1285 | }; | |
1286 | ||
ccdc7bf9 SO |
1287 | static struct platform_driver omap2_mcspi_driver = { |
1288 | .driver = { | |
1289 | .name = "omap2_mcspi", | |
1290 | .owner = THIS_MODULE, | |
42ce7fd6 | 1291 | .pm = &omap2_mcspi_pm_ops |
ccdc7bf9 SO |
1292 | }, |
1293 | .remove = __exit_p(omap2_mcspi_remove), | |
1294 | }; | |
1295 | ||
1296 | ||
1297 | static int __init omap2_mcspi_init(void) | |
1298 | { | |
1299 | omap2_mcspi_wq = create_singlethread_workqueue( | |
1300 | omap2_mcspi_driver.driver.name); | |
1301 | if (omap2_mcspi_wq == NULL) | |
1302 | return -1; | |
1303 | return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe); | |
1304 | } | |
1305 | subsys_initcall(omap2_mcspi_init); | |
1306 | ||
1307 | static void __exit omap2_mcspi_exit(void) | |
1308 | { | |
1309 | platform_driver_unregister(&omap2_mcspi_driver); | |
1310 | ||
1311 | destroy_workqueue(omap2_mcspi_wq); | |
1312 | } | |
1313 | module_exit(omap2_mcspi_exit); | |
1314 | ||
1315 | MODULE_LICENSE("GPL"); |