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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/device.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/spi/spi.h> | |
28 | #include <linux/workqueue.h> | |
e0c9905e | 29 | #include <linux/delay.h> |
2f1a74e5 | 30 | #include <linux/clk.h> |
e0c9905e SS |
31 | |
32 | #include <asm/io.h> | |
33 | #include <asm/irq.h> | |
34 | #include <asm/hardware.h> | |
35 | #include <asm/delay.h> | |
36 | #include <asm/dma.h> | |
37 | ||
38 | #include <asm/arch/hardware.h> | |
39 | #include <asm/arch/pxa-regs.h> | |
0aea1fd5 | 40 | #include <asm/arch/regs-ssp.h> |
2f1a74e5 | 41 | #include <asm/arch/ssp.h> |
e0c9905e SS |
42 | #include <asm/arch/pxa2xx_spi.h> |
43 | ||
44 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 45 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 46 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 47 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e SS |
48 | |
49 | #define MAX_BUSES 3 | |
50 | ||
51 | #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR) | |
52 | #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK) | |
53 | #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0) | |
54 | ||
b97c74bd NF |
55 | /* |
56 | * for testing SSCR1 changes that require SSP restart, basically | |
57 | * everything except the service and interrupt enables, the pxa270 developer | |
58 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
59 | * list, but the PXA255 dev man says all bits without really meaning the | |
60 | * service and interrupt enables | |
61 | */ | |
62 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 63 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
64 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
65 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
66 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
67 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 68 | |
e0c9905e | 69 | #define DEFINE_SSP_REG(reg, off) \ |
cf43369d DB |
70 | static inline u32 read_##reg(void const __iomem *p) \ |
71 | { return __raw_readl(p + (off)); } \ | |
72 | \ | |
73 | static inline void write_##reg(u32 v, void __iomem *p) \ | |
74 | { __raw_writel(v, p + (off)); } | |
e0c9905e SS |
75 | |
76 | DEFINE_SSP_REG(SSCR0, 0x00) | |
77 | DEFINE_SSP_REG(SSCR1, 0x04) | |
78 | DEFINE_SSP_REG(SSSR, 0x08) | |
79 | DEFINE_SSP_REG(SSITR, 0x0c) | |
80 | DEFINE_SSP_REG(SSDR, 0x10) | |
81 | DEFINE_SSP_REG(SSTO, 0x28) | |
82 | DEFINE_SSP_REG(SSPSP, 0x2c) | |
83 | ||
84 | #define START_STATE ((void*)0) | |
85 | #define RUNNING_STATE ((void*)1) | |
86 | #define DONE_STATE ((void*)2) | |
87 | #define ERROR_STATE ((void*)-1) | |
88 | ||
89 | #define QUEUE_RUNNING 0 | |
90 | #define QUEUE_STOPPED 1 | |
91 | ||
92 | struct driver_data { | |
93 | /* Driver model hookup */ | |
94 | struct platform_device *pdev; | |
95 | ||
2f1a74e5 | 96 | /* SSP Info */ |
97 | struct ssp_device *ssp; | |
98 | ||
e0c9905e SS |
99 | /* SPI framework hookup */ |
100 | enum pxa_ssp_type ssp_type; | |
101 | struct spi_master *master; | |
102 | ||
103 | /* PXA hookup */ | |
104 | struct pxa2xx_spi_master *master_info; | |
105 | ||
106 | /* DMA setup stuff */ | |
107 | int rx_channel; | |
108 | int tx_channel; | |
109 | u32 *null_dma_buf; | |
110 | ||
111 | /* SSP register addresses */ | |
cf43369d | 112 | void __iomem *ioaddr; |
e0c9905e SS |
113 | u32 ssdr_physical; |
114 | ||
115 | /* SSP masks*/ | |
116 | u32 dma_cr1; | |
117 | u32 int_cr1; | |
118 | u32 clear_sr; | |
119 | u32 mask_sr; | |
120 | ||
121 | /* Driver message queue */ | |
122 | struct workqueue_struct *workqueue; | |
123 | struct work_struct pump_messages; | |
124 | spinlock_t lock; | |
125 | struct list_head queue; | |
126 | int busy; | |
127 | int run; | |
128 | ||
129 | /* Message Transfer pump */ | |
130 | struct tasklet_struct pump_transfers; | |
131 | ||
132 | /* Current message transfer state info */ | |
133 | struct spi_message* cur_msg; | |
134 | struct spi_transfer* cur_transfer; | |
135 | struct chip_data *cur_chip; | |
136 | size_t len; | |
137 | void *tx; | |
138 | void *tx_end; | |
139 | void *rx; | |
140 | void *rx_end; | |
141 | int dma_mapped; | |
142 | dma_addr_t rx_dma; | |
143 | dma_addr_t tx_dma; | |
144 | size_t rx_map_len; | |
145 | size_t tx_map_len; | |
9708c121 SS |
146 | u8 n_bytes; |
147 | u32 dma_width; | |
e0c9905e | 148 | int cs_change; |
8d94cc50 SS |
149 | int (*write)(struct driver_data *drv_data); |
150 | int (*read)(struct driver_data *drv_data); | |
e0c9905e SS |
151 | irqreturn_t (*transfer_handler)(struct driver_data *drv_data); |
152 | void (*cs_control)(u32 command); | |
153 | }; | |
154 | ||
155 | struct chip_data { | |
156 | u32 cr0; | |
157 | u32 cr1; | |
e0c9905e SS |
158 | u32 psp; |
159 | u32 timeout; | |
160 | u8 n_bytes; | |
161 | u32 dma_width; | |
162 | u32 dma_burst_size; | |
163 | u32 threshold; | |
164 | u32 dma_threshold; | |
165 | u8 enable_dma; | |
9708c121 SS |
166 | u8 bits_per_word; |
167 | u32 speed_hz; | |
8d94cc50 SS |
168 | int (*write)(struct driver_data *drv_data); |
169 | int (*read)(struct driver_data *drv_data); | |
e0c9905e SS |
170 | void (*cs_control)(u32 command); |
171 | }; | |
172 | ||
6d5aefb8 | 173 | static void pump_messages(struct work_struct *work); |
e0c9905e SS |
174 | |
175 | static int flush(struct driver_data *drv_data) | |
176 | { | |
177 | unsigned long limit = loops_per_jiffy << 1; | |
178 | ||
cf43369d | 179 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
180 | |
181 | do { | |
182 | while (read_SSSR(reg) & SSSR_RNE) { | |
183 | read_SSDR(reg); | |
184 | } | |
185 | } while ((read_SSSR(reg) & SSSR_BSY) && limit--); | |
186 | write_SSSR(SSSR_ROR, reg); | |
187 | ||
188 | return limit; | |
189 | } | |
190 | ||
e0c9905e SS |
191 | static void null_cs_control(u32 command) |
192 | { | |
193 | } | |
194 | ||
8d94cc50 | 195 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 196 | { |
cf43369d | 197 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 198 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 199 | |
8d94cc50 SS |
200 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
201 | || (drv_data->tx == drv_data->tx_end)) | |
202 | return 0; | |
203 | ||
204 | write_SSDR(0, reg); | |
205 | drv_data->tx += n_bytes; | |
206 | ||
207 | return 1; | |
e0c9905e SS |
208 | } |
209 | ||
8d94cc50 | 210 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 211 | { |
cf43369d | 212 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 213 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e SS |
214 | |
215 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 216 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
217 | read_SSDR(reg); |
218 | drv_data->rx += n_bytes; | |
219 | } | |
8d94cc50 SS |
220 | |
221 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
222 | } |
223 | ||
8d94cc50 | 224 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 225 | { |
cf43369d | 226 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 227 | |
8d94cc50 SS |
228 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
229 | || (drv_data->tx == drv_data->tx_end)) | |
230 | return 0; | |
231 | ||
232 | write_SSDR(*(u8 *)(drv_data->tx), reg); | |
233 | ++drv_data->tx; | |
234 | ||
235 | return 1; | |
e0c9905e SS |
236 | } |
237 | ||
8d94cc50 | 238 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 239 | { |
cf43369d | 240 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
241 | |
242 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 243 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
244 | *(u8 *)(drv_data->rx) = read_SSDR(reg); |
245 | ++drv_data->rx; | |
246 | } | |
8d94cc50 SS |
247 | |
248 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
249 | } |
250 | ||
8d94cc50 | 251 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 252 | { |
cf43369d | 253 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 254 | |
8d94cc50 SS |
255 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
256 | || (drv_data->tx == drv_data->tx_end)) | |
257 | return 0; | |
258 | ||
259 | write_SSDR(*(u16 *)(drv_data->tx), reg); | |
260 | drv_data->tx += 2; | |
261 | ||
262 | return 1; | |
e0c9905e SS |
263 | } |
264 | ||
8d94cc50 | 265 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 266 | { |
cf43369d | 267 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
268 | |
269 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 270 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
271 | *(u16 *)(drv_data->rx) = read_SSDR(reg); |
272 | drv_data->rx += 2; | |
273 | } | |
8d94cc50 SS |
274 | |
275 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 276 | } |
8d94cc50 SS |
277 | |
278 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 279 | { |
cf43369d | 280 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 281 | |
8d94cc50 SS |
282 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
283 | || (drv_data->tx == drv_data->tx_end)) | |
284 | return 0; | |
285 | ||
286 | write_SSDR(*(u32 *)(drv_data->tx), reg); | |
287 | drv_data->tx += 4; | |
288 | ||
289 | return 1; | |
e0c9905e SS |
290 | } |
291 | ||
8d94cc50 | 292 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 293 | { |
cf43369d | 294 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
295 | |
296 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 297 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
298 | *(u32 *)(drv_data->rx) = read_SSDR(reg); |
299 | drv_data->rx += 4; | |
300 | } | |
8d94cc50 SS |
301 | |
302 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
303 | } |
304 | ||
305 | static void *next_transfer(struct driver_data *drv_data) | |
306 | { | |
307 | struct spi_message *msg = drv_data->cur_msg; | |
308 | struct spi_transfer *trans = drv_data->cur_transfer; | |
309 | ||
310 | /* Move to next transfer */ | |
311 | if (trans->transfer_list.next != &msg->transfers) { | |
312 | drv_data->cur_transfer = | |
313 | list_entry(trans->transfer_list.next, | |
314 | struct spi_transfer, | |
315 | transfer_list); | |
316 | return RUNNING_STATE; | |
317 | } else | |
318 | return DONE_STATE; | |
319 | } | |
320 | ||
321 | static int map_dma_buffers(struct driver_data *drv_data) | |
322 | { | |
323 | struct spi_message *msg = drv_data->cur_msg; | |
324 | struct device *dev = &msg->spi->dev; | |
325 | ||
326 | if (!drv_data->cur_chip->enable_dma) | |
327 | return 0; | |
328 | ||
329 | if (msg->is_dma_mapped) | |
330 | return drv_data->rx_dma && drv_data->tx_dma; | |
331 | ||
332 | if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx)) | |
333 | return 0; | |
334 | ||
335 | /* Modify setup if rx buffer is null */ | |
336 | if (drv_data->rx == NULL) { | |
337 | *drv_data->null_dma_buf = 0; | |
338 | drv_data->rx = drv_data->null_dma_buf; | |
339 | drv_data->rx_map_len = 4; | |
340 | } else | |
341 | drv_data->rx_map_len = drv_data->len; | |
342 | ||
343 | ||
344 | /* Modify setup if tx buffer is null */ | |
345 | if (drv_data->tx == NULL) { | |
346 | *drv_data->null_dma_buf = 0; | |
347 | drv_data->tx = drv_data->null_dma_buf; | |
348 | drv_data->tx_map_len = 4; | |
349 | } else | |
350 | drv_data->tx_map_len = drv_data->len; | |
351 | ||
352 | /* Stream map the rx buffer */ | |
353 | drv_data->rx_dma = dma_map_single(dev, drv_data->rx, | |
354 | drv_data->rx_map_len, | |
355 | DMA_FROM_DEVICE); | |
356 | if (dma_mapping_error(drv_data->rx_dma)) | |
357 | return 0; | |
358 | ||
359 | /* Stream map the tx buffer */ | |
360 | drv_data->tx_dma = dma_map_single(dev, drv_data->tx, | |
361 | drv_data->tx_map_len, | |
362 | DMA_TO_DEVICE); | |
363 | ||
364 | if (dma_mapping_error(drv_data->tx_dma)) { | |
365 | dma_unmap_single(dev, drv_data->rx_dma, | |
366 | drv_data->rx_map_len, DMA_FROM_DEVICE); | |
367 | return 0; | |
368 | } | |
369 | ||
370 | return 1; | |
371 | } | |
372 | ||
373 | static void unmap_dma_buffers(struct driver_data *drv_data) | |
374 | { | |
375 | struct device *dev; | |
376 | ||
377 | if (!drv_data->dma_mapped) | |
378 | return; | |
379 | ||
380 | if (!drv_data->cur_msg->is_dma_mapped) { | |
381 | dev = &drv_data->cur_msg->spi->dev; | |
382 | dma_unmap_single(dev, drv_data->rx_dma, | |
383 | drv_data->rx_map_len, DMA_FROM_DEVICE); | |
384 | dma_unmap_single(dev, drv_data->tx_dma, | |
385 | drv_data->tx_map_len, DMA_TO_DEVICE); | |
386 | } | |
387 | ||
388 | drv_data->dma_mapped = 0; | |
389 | } | |
390 | ||
391 | /* caller already set message->status; dma and pio irqs are blocked */ | |
5daa3ba0 | 392 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
393 | { |
394 | struct spi_transfer* last_transfer; | |
5daa3ba0 SS |
395 | unsigned long flags; |
396 | struct spi_message *msg; | |
e0c9905e | 397 | |
5daa3ba0 SS |
398 | spin_lock_irqsave(&drv_data->lock, flags); |
399 | msg = drv_data->cur_msg; | |
400 | drv_data->cur_msg = NULL; | |
401 | drv_data->cur_transfer = NULL; | |
402 | drv_data->cur_chip = NULL; | |
403 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
404 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
405 | ||
406 | last_transfer = list_entry(msg->transfers.prev, | |
e0c9905e SS |
407 | struct spi_transfer, |
408 | transfer_list); | |
409 | ||
410 | if (!last_transfer->cs_change) | |
411 | drv_data->cs_control(PXA2XX_CS_DEASSERT); | |
412 | ||
5daa3ba0 SS |
413 | msg->state = NULL; |
414 | if (msg->complete) | |
415 | msg->complete(msg->context); | |
e0c9905e SS |
416 | } |
417 | ||
cf43369d | 418 | static int wait_ssp_rx_stall(void const __iomem *ioaddr) |
e0c9905e SS |
419 | { |
420 | unsigned long limit = loops_per_jiffy << 1; | |
421 | ||
422 | while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--) | |
423 | cpu_relax(); | |
424 | ||
425 | return limit; | |
426 | } | |
427 | ||
428 | static int wait_dma_channel_stop(int channel) | |
429 | { | |
430 | unsigned long limit = loops_per_jiffy << 1; | |
431 | ||
432 | while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--) | |
433 | cpu_relax(); | |
434 | ||
435 | return limit; | |
436 | } | |
437 | ||
cf43369d | 438 | static void dma_error_stop(struct driver_data *drv_data, const char *msg) |
e0c9905e | 439 | { |
cf43369d | 440 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 441 | |
8d94cc50 SS |
442 | /* Stop and reset */ |
443 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
444 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
445 | write_SSSR(drv_data->clear_sr, reg); | |
446 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); | |
447 | if (drv_data->ssp_type != PXA25x_SSP) | |
448 | write_SSTO(0, reg); | |
449 | flush(drv_data); | |
450 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
e0c9905e | 451 | |
8d94cc50 | 452 | unmap_dma_buffers(drv_data); |
e0c9905e | 453 | |
8d94cc50 | 454 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 455 | |
8d94cc50 SS |
456 | drv_data->cur_msg->state = ERROR_STATE; |
457 | tasklet_schedule(&drv_data->pump_transfers); | |
458 | } | |
459 | ||
460 | static void dma_transfer_complete(struct driver_data *drv_data) | |
461 | { | |
cf43369d | 462 | void __iomem *reg = drv_data->ioaddr; |
8d94cc50 SS |
463 | struct spi_message *msg = drv_data->cur_msg; |
464 | ||
465 | /* Clear and disable interrupts on SSP and DMA channels*/ | |
466 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); | |
467 | write_SSSR(drv_data->clear_sr, reg); | |
468 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
469 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
470 | ||
471 | if (wait_dma_channel_stop(drv_data->rx_channel) == 0) | |
472 | dev_err(&drv_data->pdev->dev, | |
473 | "dma_handler: dma rx channel stop failed\n"); | |
474 | ||
475 | if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) | |
476 | dev_err(&drv_data->pdev->dev, | |
477 | "dma_transfer: ssp rx stall failed\n"); | |
478 | ||
479 | unmap_dma_buffers(drv_data); | |
480 | ||
481 | /* update the buffer pointer for the amount completed in dma */ | |
482 | drv_data->rx += drv_data->len - | |
483 | (DCMD(drv_data->rx_channel) & DCMD_LENGTH); | |
484 | ||
485 | /* read trailing data from fifo, it does not matter how many | |
486 | * bytes are in the fifo just read until buffer is full | |
487 | * or fifo is empty, which ever occurs first */ | |
488 | drv_data->read(drv_data); | |
489 | ||
490 | /* return count of what was actually read */ | |
491 | msg->actual_length += drv_data->len - | |
492 | (drv_data->rx_end - drv_data->rx); | |
493 | ||
494 | /* Release chip select if requested, transfer delays are | |
495 | * handled in pump_transfers */ | |
496 | if (drv_data->cs_change) | |
497 | drv_data->cs_control(PXA2XX_CS_DEASSERT); | |
498 | ||
499 | /* Move to next transfer */ | |
500 | msg->state = next_transfer(drv_data); | |
501 | ||
502 | /* Schedule transfer tasklet */ | |
503 | tasklet_schedule(&drv_data->pump_transfers); | |
504 | } | |
505 | ||
506 | static void dma_handler(int channel, void *data) | |
507 | { | |
508 | struct driver_data *drv_data = data; | |
509 | u32 irq_status = DCSR(channel) & DMA_INT_MASK; | |
510 | ||
511 | if (irq_status & DCSR_BUSERR) { | |
e0c9905e SS |
512 | |
513 | if (channel == drv_data->tx_channel) | |
8d94cc50 SS |
514 | dma_error_stop(drv_data, |
515 | "dma_handler: " | |
516 | "bad bus address on tx channel"); | |
e0c9905e | 517 | else |
8d94cc50 SS |
518 | dma_error_stop(drv_data, |
519 | "dma_handler: " | |
520 | "bad bus address on rx channel"); | |
521 | return; | |
e0c9905e SS |
522 | } |
523 | ||
524 | /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */ | |
8d94cc50 SS |
525 | if ((channel == drv_data->tx_channel) |
526 | && (irq_status & DCSR_ENDINTR) | |
527 | && (drv_data->ssp_type == PXA25x_SSP)) { | |
e0c9905e SS |
528 | |
529 | /* Wait for rx to stall */ | |
530 | if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) | |
531 | dev_err(&drv_data->pdev->dev, | |
532 | "dma_handler: ssp rx stall failed\n"); | |
533 | ||
8d94cc50 SS |
534 | /* finish this transfer, start the next */ |
535 | dma_transfer_complete(drv_data); | |
e0c9905e SS |
536 | } |
537 | } | |
538 | ||
539 | static irqreturn_t dma_transfer(struct driver_data *drv_data) | |
540 | { | |
541 | u32 irq_status; | |
cf43369d | 542 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
543 | |
544 | irq_status = read_SSSR(reg) & drv_data->mask_sr; | |
545 | if (irq_status & SSSR_ROR) { | |
8d94cc50 | 546 | dma_error_stop(drv_data, "dma_transfer: fifo overrun"); |
e0c9905e SS |
547 | return IRQ_HANDLED; |
548 | } | |
549 | ||
550 | /* Check for false positive timeout */ | |
8d94cc50 SS |
551 | if ((irq_status & SSSR_TINT) |
552 | && (DCSR(drv_data->tx_channel) & DCSR_RUN)) { | |
e0c9905e SS |
553 | write_SSSR(SSSR_TINT, reg); |
554 | return IRQ_HANDLED; | |
555 | } | |
556 | ||
557 | if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) { | |
558 | ||
8d94cc50 SS |
559 | /* Clear and disable timeout interrupt, do the rest in |
560 | * dma_transfer_complete */ | |
e0c9905e SS |
561 | if (drv_data->ssp_type != PXA25x_SSP) |
562 | write_SSTO(0, reg); | |
e0c9905e | 563 | |
8d94cc50 SS |
564 | /* finish this transfer, start the next */ |
565 | dma_transfer_complete(drv_data); | |
e0c9905e SS |
566 | |
567 | return IRQ_HANDLED; | |
568 | } | |
569 | ||
570 | /* Opps problem detected */ | |
571 | return IRQ_NONE; | |
572 | } | |
573 | ||
8d94cc50 | 574 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 575 | { |
cf43369d | 576 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 577 | |
8d94cc50 SS |
578 | /* Stop and reset SSP */ |
579 | write_SSSR(drv_data->clear_sr, reg); | |
580 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
581 | if (drv_data->ssp_type != PXA25x_SSP) | |
582 | write_SSTO(0, reg); | |
583 | flush(drv_data); | |
584 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
e0c9905e | 585 | |
8d94cc50 | 586 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 587 | |
8d94cc50 SS |
588 | drv_data->cur_msg->state = ERROR_STATE; |
589 | tasklet_schedule(&drv_data->pump_transfers); | |
590 | } | |
5daa3ba0 | 591 | |
8d94cc50 SS |
592 | static void int_transfer_complete(struct driver_data *drv_data) |
593 | { | |
cf43369d | 594 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 595 | |
8d94cc50 SS |
596 | /* Stop SSP */ |
597 | write_SSSR(drv_data->clear_sr, reg); | |
598 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
599 | if (drv_data->ssp_type != PXA25x_SSP) | |
600 | write_SSTO(0, reg); | |
e0c9905e | 601 | |
8d94cc50 SS |
602 | /* Update total byte transfered return count actual bytes read */ |
603 | drv_data->cur_msg->actual_length += drv_data->len - | |
604 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 605 | |
8d94cc50 SS |
606 | /* Release chip select if requested, transfer delays are |
607 | * handled in pump_transfers */ | |
608 | if (drv_data->cs_change) | |
609 | drv_data->cs_control(PXA2XX_CS_DEASSERT); | |
e0c9905e | 610 | |
8d94cc50 SS |
611 | /* Move to next transfer */ |
612 | drv_data->cur_msg->state = next_transfer(drv_data); | |
e0c9905e | 613 | |
8d94cc50 SS |
614 | /* Schedule transfer tasklet */ |
615 | tasklet_schedule(&drv_data->pump_transfers); | |
616 | } | |
e0c9905e | 617 | |
8d94cc50 SS |
618 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
619 | { | |
cf43369d | 620 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 621 | |
8d94cc50 SS |
622 | u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? |
623 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 624 | |
8d94cc50 | 625 | u32 irq_status = read_SSSR(reg) & irq_mask; |
e0c9905e | 626 | |
8d94cc50 SS |
627 | if (irq_status & SSSR_ROR) { |
628 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
629 | return IRQ_HANDLED; | |
630 | } | |
e0c9905e | 631 | |
8d94cc50 SS |
632 | if (irq_status & SSSR_TINT) { |
633 | write_SSSR(SSSR_TINT, reg); | |
634 | if (drv_data->read(drv_data)) { | |
635 | int_transfer_complete(drv_data); | |
636 | return IRQ_HANDLED; | |
637 | } | |
638 | } | |
e0c9905e | 639 | |
8d94cc50 SS |
640 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
641 | do { | |
642 | if (drv_data->read(drv_data)) { | |
643 | int_transfer_complete(drv_data); | |
644 | return IRQ_HANDLED; | |
645 | } | |
646 | } while (drv_data->write(drv_data)); | |
e0c9905e | 647 | |
8d94cc50 SS |
648 | if (drv_data->read(drv_data)) { |
649 | int_transfer_complete(drv_data); | |
650 | return IRQ_HANDLED; | |
651 | } | |
e0c9905e | 652 | |
8d94cc50 SS |
653 | if (drv_data->tx == drv_data->tx_end) { |
654 | write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg); | |
655 | /* PXA25x_SSP has no timeout, read trailing bytes */ | |
656 | if (drv_data->ssp_type == PXA25x_SSP) { | |
657 | if (!wait_ssp_rx_stall(reg)) | |
658 | { | |
659 | int_error_stop(drv_data, "interrupt_transfer: " | |
660 | "rx stall failed"); | |
661 | return IRQ_HANDLED; | |
662 | } | |
663 | if (!drv_data->read(drv_data)) | |
664 | { | |
665 | int_error_stop(drv_data, | |
666 | "interrupt_transfer: " | |
667 | "trailing byte read failed"); | |
668 | return IRQ_HANDLED; | |
669 | } | |
670 | int_transfer_complete(drv_data); | |
e0c9905e | 671 | } |
e0c9905e SS |
672 | } |
673 | ||
5daa3ba0 SS |
674 | /* We did something */ |
675 | return IRQ_HANDLED; | |
e0c9905e SS |
676 | } |
677 | ||
7d12e780 | 678 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 679 | { |
c7bec5ab | 680 | struct driver_data *drv_data = dev_id; |
cf43369d | 681 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
682 | |
683 | if (!drv_data->cur_msg) { | |
5daa3ba0 SS |
684 | |
685 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
686 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
687 | if (drv_data->ssp_type != PXA25x_SSP) | |
688 | write_SSTO(0, reg); | |
689 | write_SSSR(drv_data->clear_sr, reg); | |
690 | ||
e0c9905e | 691 | dev_err(&drv_data->pdev->dev, "bad message state " |
8d94cc50 | 692 | "in interrupt handler\n"); |
5daa3ba0 | 693 | |
e0c9905e SS |
694 | /* Never fail */ |
695 | return IRQ_HANDLED; | |
696 | } | |
697 | ||
698 | return drv_data->transfer_handler(drv_data); | |
699 | } | |
700 | ||
cf43369d DB |
701 | static int set_dma_burst_and_threshold(struct chip_data *chip, |
702 | struct spi_device *spi, | |
8d94cc50 SS |
703 | u8 bits_per_word, u32 *burst_code, |
704 | u32 *threshold) | |
705 | { | |
706 | struct pxa2xx_spi_chip *chip_info = | |
707 | (struct pxa2xx_spi_chip *)spi->controller_data; | |
708 | int bytes_per_word; | |
709 | int burst_bytes; | |
710 | int thresh_words; | |
711 | int req_burst_size; | |
712 | int retval = 0; | |
713 | ||
714 | /* Set the threshold (in registers) to equal the same amount of data | |
715 | * as represented by burst size (in bytes). The computation below | |
716 | * is (burst_size rounded up to nearest 8 byte, word or long word) | |
717 | * divided by (bytes/register); the tx threshold is the inverse of | |
718 | * the rx, so that there will always be enough data in the rx fifo | |
719 | * to satisfy a burst, and there will always be enough space in the | |
720 | * tx fifo to accept a burst (a tx burst will overwrite the fifo if | |
721 | * there is not enough space), there must always remain enough empty | |
722 | * space in the rx fifo for any data loaded to the tx fifo. | |
723 | * Whenever burst_size (in bytes) equals bits/word, the fifo threshold | |
724 | * will be 8, or half the fifo; | |
725 | * The threshold can only be set to 2, 4 or 8, but not 16, because | |
726 | * to burst 16 to the tx fifo, the fifo would have to be empty; | |
727 | * however, the minimum fifo trigger level is 1, and the tx will | |
728 | * request service when the fifo is at this level, with only 15 spaces. | |
729 | */ | |
730 | ||
731 | /* find bytes/word */ | |
732 | if (bits_per_word <= 8) | |
733 | bytes_per_word = 1; | |
734 | else if (bits_per_word <= 16) | |
735 | bytes_per_word = 2; | |
736 | else | |
737 | bytes_per_word = 4; | |
738 | ||
739 | /* use struct pxa2xx_spi_chip->dma_burst_size if available */ | |
740 | if (chip_info) | |
741 | req_burst_size = chip_info->dma_burst_size; | |
742 | else { | |
743 | switch (chip->dma_burst_size) { | |
744 | default: | |
745 | /* if the default burst size is not set, | |
746 | * do it now */ | |
747 | chip->dma_burst_size = DCMD_BURST8; | |
748 | case DCMD_BURST8: | |
749 | req_burst_size = 8; | |
750 | break; | |
751 | case DCMD_BURST16: | |
752 | req_burst_size = 16; | |
753 | break; | |
754 | case DCMD_BURST32: | |
755 | req_burst_size = 32; | |
756 | break; | |
757 | } | |
758 | } | |
759 | if (req_burst_size <= 8) { | |
760 | *burst_code = DCMD_BURST8; | |
761 | burst_bytes = 8; | |
762 | } else if (req_burst_size <= 16) { | |
763 | if (bytes_per_word == 1) { | |
764 | /* don't burst more than 1/2 the fifo */ | |
765 | *burst_code = DCMD_BURST8; | |
766 | burst_bytes = 8; | |
767 | retval = 1; | |
768 | } else { | |
769 | *burst_code = DCMD_BURST16; | |
770 | burst_bytes = 16; | |
771 | } | |
772 | } else { | |
773 | if (bytes_per_word == 1) { | |
774 | /* don't burst more than 1/2 the fifo */ | |
775 | *burst_code = DCMD_BURST8; | |
776 | burst_bytes = 8; | |
777 | retval = 1; | |
778 | } else if (bytes_per_word == 2) { | |
779 | /* don't burst more than 1/2 the fifo */ | |
780 | *burst_code = DCMD_BURST16; | |
781 | burst_bytes = 16; | |
782 | retval = 1; | |
783 | } else { | |
784 | *burst_code = DCMD_BURST32; | |
785 | burst_bytes = 32; | |
786 | } | |
787 | } | |
788 | ||
789 | thresh_words = burst_bytes / bytes_per_word; | |
790 | ||
791 | /* thresh_words will be between 2 and 8 */ | |
792 | *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT) | |
793 | | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT); | |
794 | ||
795 | return retval; | |
796 | } | |
797 | ||
2f1a74e5 | 798 | static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate) |
799 | { | |
800 | unsigned long ssp_clk = clk_get_rate(ssp->clk); | |
801 | ||
802 | if (ssp->type == PXA25x_SSP) | |
803 | return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; | |
804 | else | |
805 | return ((ssp_clk / rate - 1) & 0xfff) << 8; | |
806 | } | |
807 | ||
e0c9905e SS |
808 | static void pump_transfers(unsigned long data) |
809 | { | |
810 | struct driver_data *drv_data = (struct driver_data *)data; | |
811 | struct spi_message *message = NULL; | |
812 | struct spi_transfer *transfer = NULL; | |
813 | struct spi_transfer *previous = NULL; | |
814 | struct chip_data *chip = NULL; | |
2f1a74e5 | 815 | struct ssp_device *ssp = drv_data->ssp; |
cf43369d | 816 | void __iomem *reg = drv_data->ioaddr; |
9708c121 SS |
817 | u32 clk_div = 0; |
818 | u8 bits = 0; | |
819 | u32 speed = 0; | |
820 | u32 cr0; | |
8d94cc50 SS |
821 | u32 cr1; |
822 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
823 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
e0c9905e SS |
824 | |
825 | /* Get current state information */ | |
826 | message = drv_data->cur_msg; | |
827 | transfer = drv_data->cur_transfer; | |
828 | chip = drv_data->cur_chip; | |
829 | ||
830 | /* Handle for abort */ | |
831 | if (message->state == ERROR_STATE) { | |
832 | message->status = -EIO; | |
5daa3ba0 | 833 | giveback(drv_data); |
e0c9905e SS |
834 | return; |
835 | } | |
836 | ||
837 | /* Handle end of message */ | |
838 | if (message->state == DONE_STATE) { | |
839 | message->status = 0; | |
5daa3ba0 | 840 | giveback(drv_data); |
e0c9905e SS |
841 | return; |
842 | } | |
843 | ||
844 | /* Delay if requested at end of transfer*/ | |
845 | if (message->state == RUNNING_STATE) { | |
846 | previous = list_entry(transfer->transfer_list.prev, | |
847 | struct spi_transfer, | |
848 | transfer_list); | |
849 | if (previous->delay_usecs) | |
850 | udelay(previous->delay_usecs); | |
851 | } | |
852 | ||
8d94cc50 SS |
853 | /* Check transfer length */ |
854 | if (transfer->len > 8191) | |
855 | { | |
856 | dev_warn(&drv_data->pdev->dev, "pump_transfers: transfer " | |
857 | "length greater than 8191\n"); | |
858 | message->status = -EINVAL; | |
859 | giveback(drv_data); | |
860 | return; | |
861 | } | |
862 | ||
e0c9905e SS |
863 | /* Setup the transfer state based on the type of transfer */ |
864 | if (flush(drv_data) == 0) { | |
865 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); | |
866 | message->status = -EIO; | |
5daa3ba0 | 867 | giveback(drv_data); |
e0c9905e SS |
868 | return; |
869 | } | |
9708c121 SS |
870 | drv_data->n_bytes = chip->n_bytes; |
871 | drv_data->dma_width = chip->dma_width; | |
e0c9905e SS |
872 | drv_data->cs_control = chip->cs_control; |
873 | drv_data->tx = (void *)transfer->tx_buf; | |
874 | drv_data->tx_end = drv_data->tx + transfer->len; | |
875 | drv_data->rx = transfer->rx_buf; | |
876 | drv_data->rx_end = drv_data->rx + transfer->len; | |
877 | drv_data->rx_dma = transfer->rx_dma; | |
878 | drv_data->tx_dma = transfer->tx_dma; | |
8d94cc50 | 879 | drv_data->len = transfer->len & DCMD_LENGTH; |
e0c9905e SS |
880 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
881 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
882 | drv_data->cs_change = transfer->cs_change; | |
9708c121 SS |
883 | |
884 | /* Change speed and bit per word on a per transfer */ | |
8d94cc50 | 885 | cr0 = chip->cr0; |
9708c121 SS |
886 | if (transfer->speed_hz || transfer->bits_per_word) { |
887 | ||
9708c121 SS |
888 | bits = chip->bits_per_word; |
889 | speed = chip->speed_hz; | |
890 | ||
891 | if (transfer->speed_hz) | |
892 | speed = transfer->speed_hz; | |
893 | ||
894 | if (transfer->bits_per_word) | |
895 | bits = transfer->bits_per_word; | |
896 | ||
2f1a74e5 | 897 | clk_div = ssp_get_clk_div(ssp, speed); |
9708c121 SS |
898 | |
899 | if (bits <= 8) { | |
900 | drv_data->n_bytes = 1; | |
901 | drv_data->dma_width = DCMD_WIDTH1; | |
902 | drv_data->read = drv_data->read != null_reader ? | |
903 | u8_reader : null_reader; | |
904 | drv_data->write = drv_data->write != null_writer ? | |
905 | u8_writer : null_writer; | |
906 | } else if (bits <= 16) { | |
907 | drv_data->n_bytes = 2; | |
908 | drv_data->dma_width = DCMD_WIDTH2; | |
909 | drv_data->read = drv_data->read != null_reader ? | |
910 | u16_reader : null_reader; | |
911 | drv_data->write = drv_data->write != null_writer ? | |
912 | u16_writer : null_writer; | |
913 | } else if (bits <= 32) { | |
914 | drv_data->n_bytes = 4; | |
915 | drv_data->dma_width = DCMD_WIDTH4; | |
916 | drv_data->read = drv_data->read != null_reader ? | |
917 | u32_reader : null_reader; | |
918 | drv_data->write = drv_data->write != null_writer ? | |
919 | u32_writer : null_writer; | |
920 | } | |
8d94cc50 SS |
921 | /* if bits/word is changed in dma mode, then must check the |
922 | * thresholds and burst also */ | |
923 | if (chip->enable_dma) { | |
924 | if (set_dma_burst_and_threshold(chip, message->spi, | |
925 | bits, &dma_burst, | |
926 | &dma_thresh)) | |
927 | if (printk_ratelimit()) | |
928 | dev_warn(&message->spi->dev, | |
929 | "pump_transfer: " | |
930 | "DMA burst size reduced to " | |
931 | "match bits_per_word\n"); | |
932 | } | |
9708c121 SS |
933 | |
934 | cr0 = clk_div | |
935 | | SSCR0_Motorola | |
5daa3ba0 | 936 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) |
9708c121 SS |
937 | | SSCR0_SSE |
938 | | (bits > 16 ? SSCR0_EDSS : 0); | |
9708c121 SS |
939 | } |
940 | ||
e0c9905e SS |
941 | message->state = RUNNING_STATE; |
942 | ||
943 | /* Try to map dma buffer and do a dma transfer if successful */ | |
944 | if ((drv_data->dma_mapped = map_dma_buffers(drv_data))) { | |
945 | ||
946 | /* Ensure we have the correct interrupt handler */ | |
947 | drv_data->transfer_handler = dma_transfer; | |
948 | ||
949 | /* Setup rx DMA Channel */ | |
950 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
951 | DSADR(drv_data->rx_channel) = drv_data->ssdr_physical; | |
952 | DTADR(drv_data->rx_channel) = drv_data->rx_dma; | |
953 | if (drv_data->rx == drv_data->null_dma_buf) | |
954 | /* No target address increment */ | |
955 | DCMD(drv_data->rx_channel) = DCMD_FLOWSRC | |
9708c121 | 956 | | drv_data->dma_width |
8d94cc50 | 957 | | dma_burst |
e0c9905e SS |
958 | | drv_data->len; |
959 | else | |
960 | DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR | |
961 | | DCMD_FLOWSRC | |
9708c121 | 962 | | drv_data->dma_width |
8d94cc50 | 963 | | dma_burst |
e0c9905e SS |
964 | | drv_data->len; |
965 | ||
966 | /* Setup tx DMA Channel */ | |
967 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
968 | DSADR(drv_data->tx_channel) = drv_data->tx_dma; | |
969 | DTADR(drv_data->tx_channel) = drv_data->ssdr_physical; | |
970 | if (drv_data->tx == drv_data->null_dma_buf) | |
971 | /* No source address increment */ | |
972 | DCMD(drv_data->tx_channel) = DCMD_FLOWTRG | |
9708c121 | 973 | | drv_data->dma_width |
8d94cc50 | 974 | | dma_burst |
e0c9905e SS |
975 | | drv_data->len; |
976 | else | |
977 | DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR | |
978 | | DCMD_FLOWTRG | |
9708c121 | 979 | | drv_data->dma_width |
8d94cc50 | 980 | | dma_burst |
e0c9905e SS |
981 | | drv_data->len; |
982 | ||
983 | /* Enable dma end irqs on SSP to detect end of transfer */ | |
984 | if (drv_data->ssp_type == PXA25x_SSP) | |
985 | DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN; | |
986 | ||
8d94cc50 SS |
987 | /* Clear status and start DMA engine */ |
988 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
e0c9905e SS |
989 | write_SSSR(drv_data->clear_sr, reg); |
990 | DCSR(drv_data->rx_channel) |= DCSR_RUN; | |
991 | DCSR(drv_data->tx_channel) |= DCSR_RUN; | |
e0c9905e SS |
992 | } else { |
993 | /* Ensure we have the correct interrupt handler */ | |
994 | drv_data->transfer_handler = interrupt_transfer; | |
995 | ||
8d94cc50 SS |
996 | /* Clear status */ |
997 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
e0c9905e | 998 | write_SSSR(drv_data->clear_sr, reg); |
8d94cc50 SS |
999 | } |
1000 | ||
1001 | /* see if we need to reload the config registers */ | |
1002 | if ((read_SSCR0(reg) != cr0) | |
1003 | || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != | |
1004 | (cr1 & SSCR1_CHANGE_MASK)) { | |
1005 | ||
b97c74bd | 1006 | /* stop the SSP, and update the other bits */ |
8d94cc50 | 1007 | write_SSCR0(cr0 & ~SSCR0_SSE, reg); |
e0c9905e SS |
1008 | if (drv_data->ssp_type != PXA25x_SSP) |
1009 | write_SSTO(chip->timeout, reg); | |
b97c74bd NF |
1010 | /* first set CR1 without interrupt and service enables */ |
1011 | write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); | |
1012 | /* restart the SSP */ | |
8d94cc50 | 1013 | write_SSCR0(cr0, reg); |
b97c74bd | 1014 | |
8d94cc50 SS |
1015 | } else { |
1016 | if (drv_data->ssp_type != PXA25x_SSP) | |
1017 | write_SSTO(chip->timeout, reg); | |
e0c9905e | 1018 | } |
b97c74bd NF |
1019 | |
1020 | /* FIXME, need to handle cs polarity, | |
1021 | * this driver uses struct pxa2xx_spi_chip.cs_control to | |
1022 | * specify a CS handling function, and it ignores most | |
1023 | * struct spi_device.mode[s], including SPI_CS_HIGH */ | |
1024 | drv_data->cs_control(PXA2XX_CS_ASSERT); | |
1025 | ||
1026 | /* after chip select, release the data by enabling service | |
1027 | * requests and interrupts, without changing any mode bits */ | |
1028 | write_SSCR1(cr1, reg); | |
e0c9905e SS |
1029 | } |
1030 | ||
6d5aefb8 | 1031 | static void pump_messages(struct work_struct *work) |
e0c9905e | 1032 | { |
6d5aefb8 DH |
1033 | struct driver_data *drv_data = |
1034 | container_of(work, struct driver_data, pump_messages); | |
e0c9905e SS |
1035 | unsigned long flags; |
1036 | ||
1037 | /* Lock queue and check for queue work */ | |
1038 | spin_lock_irqsave(&drv_data->lock, flags); | |
1039 | if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) { | |
1040 | drv_data->busy = 0; | |
1041 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1042 | return; | |
1043 | } | |
1044 | ||
1045 | /* Make sure we are not already running a message */ | |
1046 | if (drv_data->cur_msg) { | |
1047 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1048 | return; | |
1049 | } | |
1050 | ||
1051 | /* Extract head of queue */ | |
1052 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
1053 | struct spi_message, queue); | |
1054 | list_del_init(&drv_data->cur_msg->queue); | |
e0c9905e SS |
1055 | |
1056 | /* Initial message state*/ | |
1057 | drv_data->cur_msg->state = START_STATE; | |
1058 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
1059 | struct spi_transfer, | |
1060 | transfer_list); | |
1061 | ||
8d94cc50 SS |
1062 | /* prepare to setup the SSP, in pump_transfers, using the per |
1063 | * chip configuration */ | |
e0c9905e | 1064 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
1065 | |
1066 | /* Mark as busy and launch transfers */ | |
1067 | tasklet_schedule(&drv_data->pump_transfers); | |
5daa3ba0 SS |
1068 | |
1069 | drv_data->busy = 1; | |
1070 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
e0c9905e SS |
1071 | } |
1072 | ||
1073 | static int transfer(struct spi_device *spi, struct spi_message *msg) | |
1074 | { | |
1075 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
1076 | unsigned long flags; | |
1077 | ||
1078 | spin_lock_irqsave(&drv_data->lock, flags); | |
1079 | ||
1080 | if (drv_data->run == QUEUE_STOPPED) { | |
1081 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1082 | return -ESHUTDOWN; | |
1083 | } | |
1084 | ||
1085 | msg->actual_length = 0; | |
1086 | msg->status = -EINPROGRESS; | |
1087 | msg->state = START_STATE; | |
1088 | ||
1089 | list_add_tail(&msg->queue, &drv_data->queue); | |
1090 | ||
1091 | if (drv_data->run == QUEUE_RUNNING && !drv_data->busy) | |
1092 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1093 | ||
1094 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1095 | ||
1096 | return 0; | |
1097 | } | |
1098 | ||
dccd573b DB |
1099 | /* the spi->mode bits understood by this driver: */ |
1100 | #define MODEBITS (SPI_CPOL | SPI_CPHA) | |
1101 | ||
e0c9905e SS |
1102 | static int setup(struct spi_device *spi) |
1103 | { | |
1104 | struct pxa2xx_spi_chip *chip_info = NULL; | |
1105 | struct chip_data *chip; | |
1106 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
2f1a74e5 | 1107 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1108 | unsigned int clk_div; |
1109 | ||
1110 | if (!spi->bits_per_word) | |
1111 | spi->bits_per_word = 8; | |
1112 | ||
1113 | if (drv_data->ssp_type != PXA25x_SSP | |
8d94cc50 SS |
1114 | && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) { |
1115 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
1116 | "b/w not 4-32 for type non-PXA25x_SSP\n", | |
1117 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 1118 | return -EINVAL; |
8d94cc50 SS |
1119 | } |
1120 | else if (drv_data->ssp_type == PXA25x_SSP | |
1121 | && (spi->bits_per_word < 4 | |
1122 | || spi->bits_per_word > 16)) { | |
1123 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
1124 | "b/w not 4-16 for type PXA25x_SSP\n", | |
1125 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 1126 | return -EINVAL; |
8d94cc50 | 1127 | } |
e0c9905e | 1128 | |
dccd573b DB |
1129 | if (spi->mode & ~MODEBITS) { |
1130 | dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", | |
1131 | spi->mode & ~MODEBITS); | |
1132 | return -EINVAL; | |
1133 | } | |
1134 | ||
8d94cc50 | 1135 | /* Only alloc on first setup */ |
e0c9905e | 1136 | chip = spi_get_ctldata(spi); |
8d94cc50 | 1137 | if (!chip) { |
e0c9905e | 1138 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
8d94cc50 SS |
1139 | if (!chip) { |
1140 | dev_err(&spi->dev, | |
1141 | "failed setup: can't allocate chip data\n"); | |
e0c9905e | 1142 | return -ENOMEM; |
8d94cc50 | 1143 | } |
e0c9905e SS |
1144 | |
1145 | chip->cs_control = null_cs_control; | |
1146 | chip->enable_dma = 0; | |
8d94cc50 | 1147 | chip->timeout = 1000; |
e0c9905e SS |
1148 | chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1); |
1149 | chip->dma_burst_size = drv_data->master_info->enable_dma ? | |
1150 | DCMD_BURST8 : 0; | |
e0c9905e SS |
1151 | } |
1152 | ||
8d94cc50 SS |
1153 | /* protocol drivers may change the chip settings, so... |
1154 | * if chip_info exists, use it */ | |
1155 | chip_info = spi->controller_data; | |
1156 | ||
e0c9905e | 1157 | /* chip_info isn't always needed */ |
8d94cc50 | 1158 | chip->cr1 = 0; |
e0c9905e SS |
1159 | if (chip_info) { |
1160 | if (chip_info->cs_control) | |
1161 | chip->cs_control = chip_info->cs_control; | |
1162 | ||
8d94cc50 | 1163 | chip->timeout = chip_info->timeout; |
e0c9905e | 1164 | |
8d94cc50 SS |
1165 | chip->threshold = (SSCR1_RxTresh(chip_info->rx_threshold) & |
1166 | SSCR1_RFT) | | |
1167 | (SSCR1_TxTresh(chip_info->tx_threshold) & | |
1168 | SSCR1_TFT); | |
e0c9905e SS |
1169 | |
1170 | chip->enable_dma = chip_info->dma_burst_size != 0 | |
1171 | && drv_data->master_info->enable_dma; | |
1172 | chip->dma_threshold = 0; | |
1173 | ||
e0c9905e SS |
1174 | if (chip_info->enable_loopback) |
1175 | chip->cr1 = SSCR1_LBM; | |
1176 | } | |
1177 | ||
8d94cc50 SS |
1178 | /* set dma burst and threshold outside of chip_info path so that if |
1179 | * chip_info goes away after setting chip->enable_dma, the | |
1180 | * burst and threshold can still respond to changes in bits_per_word */ | |
1181 | if (chip->enable_dma) { | |
1182 | /* set up legal burst and threshold for dma */ | |
1183 | if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word, | |
1184 | &chip->dma_burst_size, | |
1185 | &chip->dma_threshold)) { | |
1186 | dev_warn(&spi->dev, "in setup: DMA burst size reduced " | |
1187 | "to match bits_per_word\n"); | |
1188 | } | |
1189 | } | |
1190 | ||
2f1a74e5 | 1191 | clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz); |
9708c121 | 1192 | chip->speed_hz = spi->max_speed_hz; |
e0c9905e SS |
1193 | |
1194 | chip->cr0 = clk_div | |
1195 | | SSCR0_Motorola | |
5daa3ba0 SS |
1196 | | SSCR0_DataSize(spi->bits_per_word > 16 ? |
1197 | spi->bits_per_word - 16 : spi->bits_per_word) | |
e0c9905e SS |
1198 | | SSCR0_SSE |
1199 | | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); | |
7f6ee1ad JC |
1200 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
1201 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
1202 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e SS |
1203 | |
1204 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ | |
1205 | if (drv_data->ssp_type != PXA25x_SSP) | |
2f1a74e5 | 1206 | dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n", |
e0c9905e | 1207 | spi->bits_per_word, |
2f1a74e5 | 1208 | clk_get_rate(ssp->clk) |
e0c9905e SS |
1209 | / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), |
1210 | spi->mode & 0x3); | |
1211 | else | |
2f1a74e5 | 1212 | dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n", |
e0c9905e | 1213 | spi->bits_per_word, |
2f1a74e5 | 1214 | clk_get_rate(ssp->clk) |
e0c9905e SS |
1215 | / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), |
1216 | spi->mode & 0x3); | |
1217 | ||
1218 | if (spi->bits_per_word <= 8) { | |
1219 | chip->n_bytes = 1; | |
1220 | chip->dma_width = DCMD_WIDTH1; | |
1221 | chip->read = u8_reader; | |
1222 | chip->write = u8_writer; | |
1223 | } else if (spi->bits_per_word <= 16) { | |
1224 | chip->n_bytes = 2; | |
1225 | chip->dma_width = DCMD_WIDTH2; | |
1226 | chip->read = u16_reader; | |
1227 | chip->write = u16_writer; | |
1228 | } else if (spi->bits_per_word <= 32) { | |
1229 | chip->cr0 |= SSCR0_EDSS; | |
1230 | chip->n_bytes = 4; | |
1231 | chip->dma_width = DCMD_WIDTH4; | |
1232 | chip->read = u32_reader; | |
1233 | chip->write = u32_writer; | |
1234 | } else { | |
1235 | dev_err(&spi->dev, "invalid wordsize\n"); | |
e0c9905e SS |
1236 | return -ENODEV; |
1237 | } | |
9708c121 | 1238 | chip->bits_per_word = spi->bits_per_word; |
e0c9905e SS |
1239 | |
1240 | spi_set_ctldata(spi, chip); | |
1241 | ||
1242 | return 0; | |
1243 | } | |
1244 | ||
0ffa0285 | 1245 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1246 | { |
0ffa0285 | 1247 | struct chip_data *chip = spi_get_ctldata(spi); |
e0c9905e SS |
1248 | |
1249 | kfree(chip); | |
1250 | } | |
1251 | ||
d1e44d9c | 1252 | static int __init init_queue(struct driver_data *drv_data) |
e0c9905e SS |
1253 | { |
1254 | INIT_LIST_HEAD(&drv_data->queue); | |
1255 | spin_lock_init(&drv_data->lock); | |
1256 | ||
1257 | drv_data->run = QUEUE_STOPPED; | |
1258 | drv_data->busy = 0; | |
1259 | ||
1260 | tasklet_init(&drv_data->pump_transfers, | |
1261 | pump_transfers, (unsigned long)drv_data); | |
1262 | ||
6d5aefb8 | 1263 | INIT_WORK(&drv_data->pump_messages, pump_messages); |
e0c9905e | 1264 | drv_data->workqueue = create_singlethread_workqueue( |
49dce689 | 1265 | drv_data->master->dev.parent->bus_id); |
e0c9905e SS |
1266 | if (drv_data->workqueue == NULL) |
1267 | return -EBUSY; | |
1268 | ||
1269 | return 0; | |
1270 | } | |
1271 | ||
1272 | static int start_queue(struct driver_data *drv_data) | |
1273 | { | |
1274 | unsigned long flags; | |
1275 | ||
1276 | spin_lock_irqsave(&drv_data->lock, flags); | |
1277 | ||
1278 | if (drv_data->run == QUEUE_RUNNING || drv_data->busy) { | |
1279 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1280 | return -EBUSY; | |
1281 | } | |
1282 | ||
1283 | drv_data->run = QUEUE_RUNNING; | |
1284 | drv_data->cur_msg = NULL; | |
1285 | drv_data->cur_transfer = NULL; | |
1286 | drv_data->cur_chip = NULL; | |
1287 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1288 | ||
1289 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1290 | ||
1291 | return 0; | |
1292 | } | |
1293 | ||
1294 | static int stop_queue(struct driver_data *drv_data) | |
1295 | { | |
1296 | unsigned long flags; | |
1297 | unsigned limit = 500; | |
1298 | int status = 0; | |
1299 | ||
1300 | spin_lock_irqsave(&drv_data->lock, flags); | |
1301 | ||
1302 | /* This is a bit lame, but is optimized for the common execution path. | |
1303 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1304 | * execution path (pump_messages) would be required to call wake_up or | |
1305 | * friends on every SPI message. Do this instead */ | |
1306 | drv_data->run = QUEUE_STOPPED; | |
1307 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { | |
1308 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1309 | msleep(10); | |
1310 | spin_lock_irqsave(&drv_data->lock, flags); | |
1311 | } | |
1312 | ||
1313 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1314 | status = -EBUSY; | |
1315 | ||
1316 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1317 | ||
1318 | return status; | |
1319 | } | |
1320 | ||
1321 | static int destroy_queue(struct driver_data *drv_data) | |
1322 | { | |
1323 | int status; | |
1324 | ||
1325 | status = stop_queue(drv_data); | |
8d94cc50 SS |
1326 | /* we are unloading the module or failing to load (only two calls |
1327 | * to this routine), and neither call can handle a return value. | |
1328 | * However, destroy_workqueue calls flush_workqueue, and that will | |
1329 | * block until all work is done. If the reason that stop_queue | |
1330 | * timed out is that the work will never finish, then it does no | |
1331 | * good to call destroy_workqueue, so return anyway. */ | |
e0c9905e SS |
1332 | if (status != 0) |
1333 | return status; | |
1334 | ||
1335 | destroy_workqueue(drv_data->workqueue); | |
1336 | ||
1337 | return 0; | |
1338 | } | |
1339 | ||
d1e44d9c | 1340 | static int __init pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1341 | { |
1342 | struct device *dev = &pdev->dev; | |
1343 | struct pxa2xx_spi_master *platform_info; | |
1344 | struct spi_master *master; | |
cf43369d | 1345 | struct driver_data *drv_data = NULL; |
2f1a74e5 | 1346 | struct ssp_device *ssp; |
e0c9905e SS |
1347 | int status = 0; |
1348 | ||
1349 | platform_info = dev->platform_data; | |
1350 | ||
2f1a74e5 | 1351 | ssp = ssp_request(pdev->id, pdev->name); |
1352 | if (ssp == NULL) { | |
1353 | dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id); | |
e0c9905e SS |
1354 | return -ENODEV; |
1355 | } | |
1356 | ||
1357 | /* Allocate master with space for drv_data and null dma buffer */ | |
1358 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1359 | if (!master) { | |
1360 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
2f1a74e5 | 1361 | ssp_free(ssp); |
e0c9905e SS |
1362 | return -ENOMEM; |
1363 | } | |
1364 | drv_data = spi_master_get_devdata(master); | |
1365 | drv_data->master = master; | |
1366 | drv_data->master_info = platform_info; | |
1367 | drv_data->pdev = pdev; | |
2f1a74e5 | 1368 | drv_data->ssp = ssp; |
e0c9905e SS |
1369 | |
1370 | master->bus_num = pdev->id; | |
1371 | master->num_chipselect = platform_info->num_chipselect; | |
1372 | master->cleanup = cleanup; | |
1373 | master->setup = setup; | |
1374 | master->transfer = transfer; | |
1375 | ||
2f1a74e5 | 1376 | drv_data->ssp_type = ssp->type; |
e0c9905e SS |
1377 | drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data + |
1378 | sizeof(struct driver_data)), 8); | |
1379 | ||
2f1a74e5 | 1380 | drv_data->ioaddr = ssp->mmio_base; |
1381 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
1382 | if (ssp->type == PXA25x_SSP) { | |
e0c9905e SS |
1383 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1384 | drv_data->dma_cr1 = 0; | |
1385 | drv_data->clear_sr = SSSR_ROR; | |
1386 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1387 | } else { | |
1388 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; | |
1389 | drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE; | |
1390 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; | |
1391 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1392 | } | |
1393 | ||
2f1a74e5 | 1394 | status = request_irq(ssp->irq, ssp_int, 0, dev->bus_id, drv_data); |
e0c9905e SS |
1395 | if (status < 0) { |
1396 | dev_err(&pdev->dev, "can not get IRQ\n"); | |
1397 | goto out_error_master_alloc; | |
1398 | } | |
1399 | ||
1400 | /* Setup DMA if requested */ | |
1401 | drv_data->tx_channel = -1; | |
1402 | drv_data->rx_channel = -1; | |
1403 | if (platform_info->enable_dma) { | |
1404 | ||
1405 | /* Get two DMA channels (rx and tx) */ | |
1406 | drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx", | |
1407 | DMA_PRIO_HIGH, | |
1408 | dma_handler, | |
1409 | drv_data); | |
1410 | if (drv_data->rx_channel < 0) { | |
1411 | dev_err(dev, "problem (%d) requesting rx channel\n", | |
1412 | drv_data->rx_channel); | |
1413 | status = -ENODEV; | |
1414 | goto out_error_irq_alloc; | |
1415 | } | |
1416 | drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx", | |
1417 | DMA_PRIO_MEDIUM, | |
1418 | dma_handler, | |
1419 | drv_data); | |
1420 | if (drv_data->tx_channel < 0) { | |
1421 | dev_err(dev, "problem (%d) requesting tx channel\n", | |
1422 | drv_data->tx_channel); | |
1423 | status = -ENODEV; | |
1424 | goto out_error_dma_alloc; | |
1425 | } | |
1426 | ||
2f1a74e5 | 1427 | DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel; |
1428 | DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel; | |
e0c9905e SS |
1429 | } |
1430 | ||
1431 | /* Enable SOC clock */ | |
2f1a74e5 | 1432 | clk_enable(ssp->clk); |
e0c9905e SS |
1433 | |
1434 | /* Load default SSP configuration */ | |
1435 | write_SSCR0(0, drv_data->ioaddr); | |
1436 | write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr); | |
1437 | write_SSCR0(SSCR0_SerClkDiv(2) | |
1438 | | SSCR0_Motorola | |
1439 | | SSCR0_DataSize(8), | |
1440 | drv_data->ioaddr); | |
1441 | if (drv_data->ssp_type != PXA25x_SSP) | |
1442 | write_SSTO(0, drv_data->ioaddr); | |
1443 | write_SSPSP(0, drv_data->ioaddr); | |
1444 | ||
1445 | /* Initial and start queue */ | |
1446 | status = init_queue(drv_data); | |
1447 | if (status != 0) { | |
1448 | dev_err(&pdev->dev, "problem initializing queue\n"); | |
1449 | goto out_error_clock_enabled; | |
1450 | } | |
1451 | status = start_queue(drv_data); | |
1452 | if (status != 0) { | |
1453 | dev_err(&pdev->dev, "problem starting queue\n"); | |
1454 | goto out_error_clock_enabled; | |
1455 | } | |
1456 | ||
1457 | /* Register with the SPI framework */ | |
1458 | platform_set_drvdata(pdev, drv_data); | |
1459 | status = spi_register_master(master); | |
1460 | if (status != 0) { | |
1461 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
1462 | goto out_error_queue_alloc; | |
1463 | } | |
1464 | ||
1465 | return status; | |
1466 | ||
1467 | out_error_queue_alloc: | |
1468 | destroy_queue(drv_data); | |
1469 | ||
1470 | out_error_clock_enabled: | |
2f1a74e5 | 1471 | clk_disable(ssp->clk); |
e0c9905e SS |
1472 | |
1473 | out_error_dma_alloc: | |
1474 | if (drv_data->tx_channel != -1) | |
1475 | pxa_free_dma(drv_data->tx_channel); | |
1476 | if (drv_data->rx_channel != -1) | |
1477 | pxa_free_dma(drv_data->rx_channel); | |
1478 | ||
1479 | out_error_irq_alloc: | |
2f1a74e5 | 1480 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1481 | |
1482 | out_error_master_alloc: | |
1483 | spi_master_put(master); | |
2f1a74e5 | 1484 | ssp_free(ssp); |
e0c9905e SS |
1485 | return status; |
1486 | } | |
1487 | ||
1488 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1489 | { | |
1490 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
2f1a74e5 | 1491 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1492 | int status = 0; |
1493 | ||
1494 | if (!drv_data) | |
1495 | return 0; | |
1496 | ||
1497 | /* Remove the queue */ | |
1498 | status = destroy_queue(drv_data); | |
1499 | if (status != 0) | |
8d94cc50 SS |
1500 | /* the kernel does not check the return status of this |
1501 | * this routine (mod->exit, within the kernel). Therefore | |
1502 | * nothing is gained by returning from here, the module is | |
1503 | * going away regardless, and we should not leave any more | |
1504 | * resources allocated than necessary. We cannot free the | |
1505 | * message memory in drv_data->queue, but we can release the | |
1506 | * resources below. I think the kernel should honor -EBUSY | |
1507 | * returns but... */ | |
1508 | dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not " | |
1509 | "complete, message memory not freed\n"); | |
e0c9905e SS |
1510 | |
1511 | /* Disable the SSP at the peripheral and SOC level */ | |
1512 | write_SSCR0(0, drv_data->ioaddr); | |
2f1a74e5 | 1513 | clk_disable(ssp->clk); |
e0c9905e SS |
1514 | |
1515 | /* Release DMA */ | |
1516 | if (drv_data->master_info->enable_dma) { | |
2f1a74e5 | 1517 | DRCMR(ssp->drcmr_rx) = 0; |
1518 | DRCMR(ssp->drcmr_tx) = 0; | |
e0c9905e SS |
1519 | pxa_free_dma(drv_data->tx_channel); |
1520 | pxa_free_dma(drv_data->rx_channel); | |
1521 | } | |
1522 | ||
1523 | /* Release IRQ */ | |
2f1a74e5 | 1524 | free_irq(ssp->irq, drv_data); |
1525 | ||
1526 | /* Release SSP */ | |
1527 | ssp_free(ssp); | |
e0c9905e SS |
1528 | |
1529 | /* Disconnect from the SPI framework */ | |
1530 | spi_unregister_master(drv_data->master); | |
1531 | ||
1532 | /* Prevent double remove */ | |
1533 | platform_set_drvdata(pdev, NULL); | |
1534 | ||
1535 | return 0; | |
1536 | } | |
1537 | ||
1538 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1539 | { | |
1540 | int status = 0; | |
1541 | ||
1542 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1543 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1544 | } | |
1545 | ||
1546 | #ifdef CONFIG_PM | |
e0c9905e SS |
1547 | |
1548 | static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state) | |
1549 | { | |
1550 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
2f1a74e5 | 1551 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1552 | int status = 0; |
1553 | ||
e0c9905e SS |
1554 | status = stop_queue(drv_data); |
1555 | if (status != 0) | |
1556 | return status; | |
1557 | write_SSCR0(0, drv_data->ioaddr); | |
2f1a74e5 | 1558 | clk_disable(ssp->clk); |
e0c9905e SS |
1559 | |
1560 | return 0; | |
1561 | } | |
1562 | ||
1563 | static int pxa2xx_spi_resume(struct platform_device *pdev) | |
1564 | { | |
1565 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
2f1a74e5 | 1566 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1567 | int status = 0; |
1568 | ||
1569 | /* Enable the SSP clock */ | |
2f1a74e5 | 1570 | clk_disable(ssp->clk); |
e0c9905e SS |
1571 | |
1572 | /* Start the queue running */ | |
1573 | status = start_queue(drv_data); | |
1574 | if (status != 0) { | |
1575 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1576 | return status; | |
1577 | } | |
1578 | ||
1579 | return 0; | |
1580 | } | |
1581 | #else | |
1582 | #define pxa2xx_spi_suspend NULL | |
1583 | #define pxa2xx_spi_resume NULL | |
1584 | #endif /* CONFIG_PM */ | |
1585 | ||
1586 | static struct platform_driver driver = { | |
1587 | .driver = { | |
1588 | .name = "pxa2xx-spi", | |
e0c9905e SS |
1589 | .owner = THIS_MODULE, |
1590 | }, | |
d1e44d9c | 1591 | .remove = pxa2xx_spi_remove, |
e0c9905e SS |
1592 | .shutdown = pxa2xx_spi_shutdown, |
1593 | .suspend = pxa2xx_spi_suspend, | |
1594 | .resume = pxa2xx_spi_resume, | |
1595 | }; | |
1596 | ||
1597 | static int __init pxa2xx_spi_init(void) | |
1598 | { | |
d1e44d9c | 1599 | return platform_driver_probe(&driver, pxa2xx_spi_probe); |
e0c9905e SS |
1600 | } |
1601 | module_init(pxa2xx_spi_init); | |
1602 | ||
1603 | static void __exit pxa2xx_spi_exit(void) | |
1604 | { | |
1605 | platform_driver_unregister(&driver); | |
1606 | } | |
1607 | module_exit(pxa2xx_spi_exit); |