]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/spi/spi-adi-v3.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
spi: convert spi-bfin-v3.c to a multiplatform driver
[mirror_ubuntu-bionic-kernel.git] / drivers / spi / spi-adi-v3.c
CommitLineData
fa4bd4f1
SJ		 1/*
2 * Analog Devices SPI3 controller driver
3 *
766e3721 4 * Copyright (c) 2014 Analog Devices Inc.
fa4bd4f1
SJ		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/errno.h>
20#include <linux/gpio.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/ioport.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/slab.h>
28#include <linux/spi/spi.h>
766e3721 29#include <linux/spi/adi_spi3.h>
fa4bd4f1
SJ		 30#include <linux/types.h>
31
fa4bd4f1
SJ		 32#include <asm/dma.h>
33#include <asm/portmux.h>
34
766e3721 35enum adi_spi_state {
fa4bd4f1
SJ		 36 START_STATE,
37 RUNNING_STATE,
38 DONE_STATE,
39 ERROR_STATE
40};
41
766e3721 42struct adi_spi_master;
fa4bd4f1 43
766e3721
SJ		 44struct adi_spi_transfer_ops {
45 void (*write) (struct adi_spi_master *);
46 void (*read) (struct adi_spi_master *);
47 void (*duplex) (struct adi_spi_master *);
fa4bd4f1
SJ		 48};
49
50/* runtime info for spi master */
766e3721 51struct adi_spi_master {
fa4bd4f1
SJ		 52 /* SPI framework hookup */
53 struct spi_master *master;
54
55 /* Regs base of SPI controller */
766e3721 56 struct adi_spi_regs __iomem *regs;
fa4bd4f1
SJ		 57
58 /* Pin request list */
59 u16 *pin_req;
60
61 /* Message Transfer pump */
62 struct tasklet_struct pump_transfers;
63
64 /* Current message transfer state info */
65 struct spi_message *cur_msg;
66 struct spi_transfer *cur_transfer;
766e3721 67 struct adi_spi_device *cur_chip;
fa4bd4f1
SJ		 68 unsigned transfer_len;
69
70 /* transfer buffer */
71 void *tx;
72 void *tx_end;
73 void *rx;
74 void *rx_end;
75
76 /* dma info */
77 unsigned int tx_dma;
78 unsigned int rx_dma;
79 dma_addr_t tx_dma_addr;
80 dma_addr_t rx_dma_addr;
81 unsigned long dummy_buffer; /* used in unidirectional transfer */
82 unsigned long tx_dma_size;
83 unsigned long rx_dma_size;
84 int tx_num;
85 int rx_num;
86
87 /* store register value for suspend/resume */
88 u32 control;
89 u32 ssel;
90
91 unsigned long sclk;
766e3721 92 enum adi_spi_state state;
fa4bd4f1 93
766e3721 94 const struct adi_spi_transfer_ops *ops;
fa4bd4f1
SJ		 95};
96
766e3721 97struct adi_spi_device {
fa4bd4f1
SJ		 98 u32 control;
99 u32 clock;
100 u32 ssel;
101
102 u8 cs;
103 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
104 u32 cs_gpio;
105 u32 tx_dummy_val; /* tx value for rx only transfer */
106 bool enable_dma;
766e3721 107 const struct adi_spi_transfer_ops *ops;
fa4bd4f1
SJ		 108};
109
766e3721 110static void adi_spi_enable(struct adi_spi_master *drv_data)
fa4bd4f1 111{
766e3721
SJ		 112 u32 ctl;
113
114 ctl = ioread32(&drv_data->regs->control);
115 ctl |= SPI_CTL_EN;
116 iowrite32(ctl, &drv_data->regs->control);
fa4bd4f1
SJ		 117}
118
766e3721 119static void adi_spi_disable(struct adi_spi_master *drv_data)
fa4bd4f1 120{
766e3721
SJ		 121 u32 ctl;
122
123 ctl = ioread32(&drv_data->regs->control);
124 ctl &= ~SPI_CTL_EN;
125 iowrite32(ctl, &drv_data->regs->control);
fa4bd4f1
SJ		 126}
127
128/* Caculate the SPI_CLOCK register value based on input HZ */
129static u32 hz_to_spi_clock(u32 sclk, u32 speed_hz)
130{
131 u32 spi_clock = sclk / speed_hz;
132
133 if (spi_clock)
134 spi_clock--;
135 return spi_clock;
136}
137
766e3721 138static int adi_spi_flush(struct adi_spi_master *drv_data)
fa4bd4f1
SJ		 139{
140 unsigned long limit = loops_per_jiffy << 1;
141
142 /* wait for stop and clear stat */
766e3721 143 while (!(ioread32(&drv_data->regs->status) & SPI_STAT_SPIF) && --limit)
fa4bd4f1
SJ		 144 cpu_relax();
145
766e3721 146 iowrite32(0xFFFFFFFF, &drv_data->regs->status);
fa4bd4f1
SJ		 147
148 return limit;
149}
150
151/* Chip select operation functions for cs_change flag */
766e3721 152static void adi_spi_cs_active(struct adi_spi_master *drv_data, struct adi_spi_device *chip)
fa4bd4f1 153{
766e3721
SJ		 154 if (likely(chip->cs < MAX_CTRL_CS)) {
155 u32 reg;
156 reg = ioread32(&drv_data->regs->ssel);
157 reg &= ~chip->ssel;
158 iowrite32(reg, &drv_data->regs->ssel);
159 } else {
fa4bd4f1 160 gpio_set_value(chip->cs_gpio, 0);
766e3721 161 }
fa4bd4f1
SJ		 162}
163
766e3721
SJ		 164static void adi_spi_cs_deactive(struct adi_spi_master *drv_data,
165 struct adi_spi_device *chip)
fa4bd4f1 166{
766e3721
SJ		 167 if (likely(chip->cs < MAX_CTRL_CS)) {
168 u32 reg;
169 reg = ioread32(&drv_data->regs->ssel);
170 reg |= chip->ssel;
171 iowrite32(reg, &drv_data->regs->ssel);
172 } else {
fa4bd4f1 173 gpio_set_value(chip->cs_gpio, 1);
766e3721 174 }
fa4bd4f1
SJ		 175
176 /* Move delay here for consistency */
177 if (chip->cs_chg_udelay)
178 udelay(chip->cs_chg_udelay);
179}
180
181/* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
766e3721
SJ		 182static inline void adi_spi_cs_enable(struct adi_spi_master *drv_data,
183 struct adi_spi_device *chip)
fa4bd4f1 184{
766e3721
SJ		 185 if (chip->cs < MAX_CTRL_CS) {
186 u32 reg;
187 reg = ioread32(&drv_data->regs->ssel);
188 reg |= chip->ssel >> 8;
189 iowrite32(reg, &drv_data->regs->ssel);
190 }
fa4bd4f1
SJ		 191}
192
766e3721
SJ		 193static inline void adi_spi_cs_disable(struct adi_spi_master *drv_data,
194 struct adi_spi_device *chip)
fa4bd4f1 195{
766e3721
SJ		 196 if (chip->cs < MAX_CTRL_CS) {
197 u32 reg;
198 reg = ioread32(&drv_data->regs->ssel);
199 reg &= ~(chip->ssel >> 8);
200 iowrite32(reg, &drv_data->regs->ssel);
201 }
fa4bd4f1
SJ		 202}
203
204/* stop controller and re-config current chip*/
766e3721 205static void adi_spi_restore_state(struct adi_spi_master *drv_data)
fa4bd4f1 206{
766e3721 207 struct adi_spi_device *chip = drv_data->cur_chip;
fa4bd4f1
SJ		 208
209 /* Clear status and disable clock */
766e3721
SJ		 210 iowrite32(0xFFFFFFFF, &drv_data->regs->status);
211 iowrite32(0x0, &drv_data->regs->rx_control);
212 iowrite32(0x0, &drv_data->regs->tx_control);
213 adi_spi_disable(drv_data);
fa4bd4f1
SJ		 214
215 /* Load the registers */
766e3721
SJ		 216 iowrite32(chip->control, &drv_data->regs->control);
217 iowrite32(chip->clock, &drv_data->regs->clock);
fa4bd4f1 218
766e3721 219 adi_spi_enable(drv_data);
fa4bd4f1
SJ		 220 drv_data->tx_num = drv_data->rx_num = 0;
221 /* we always choose tx transfer initiate */
766e3721
SJ		 222 iowrite32(SPI_RXCTL_REN, &drv_data->regs->rx_control);
223 iowrite32(SPI_TXCTL_TEN | SPI_TXCTL_TTI, &drv_data->regs->tx_control);
224 adi_spi_cs_active(drv_data, chip);
fa4bd4f1
SJ		 225}
226
227/* discard invalid rx data and empty rfifo */
766e3721 228static inline void dummy_read(struct adi_spi_master *drv_data)
fa4bd4f1 229{
766e3721
SJ		 230 while (!(ioread32(&drv_data->regs->status) & SPI_STAT_RFE))
231 ioread32(&drv_data->regs->rfifo);
fa4bd4f1
SJ		 232}
233
766e3721 234static void adi_spi_u8_write(struct adi_spi_master *drv_data)
fa4bd4f1
SJ		 235{
236 dummy_read(drv_data);
237 while (drv_data->tx < drv_data->tx_end) {
766e3721
SJ		 238 iowrite32(*(u8 *)(drv_data->tx++), &drv_data->regs->tfifo);
239 while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
fa4bd4f1 240 cpu_relax();
766e3721 241 ioread32(&drv_data->regs->rfifo);
fa4bd4f1
SJ		 242 }
243}
244
766e3721 245static void adi_spi_u8_read(struct adi_spi_master *drv_data)
fa4bd4f1
SJ		 246{
247 u32 tx_val = drv_data->cur_chip->tx_dummy_val;
248
249 dummy_read(drv_data);
250 while (drv_data->rx < drv_data->rx_end) {
766e3721
SJ		 251 iowrite32(tx_val, &drv_data->regs->tfifo);
252 while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
fa4bd4f1 253 cpu_relax();
766e3721 254 *(u8 *)(drv_data->rx++) = ioread32(&drv_data->regs->rfifo);
fa4bd4f1
SJ		 255 }
256}
257
766e3721 258static void adi_spi_u8_duplex(struct adi_spi_master *drv_data)
fa4bd4f1
SJ		 259{
260 dummy_read(drv_data);
261 while (drv_data->rx < drv_data->rx_end) {
766e3721
SJ		 262 iowrite32(*(u8 *)(drv_data->tx++), &drv_data->regs->tfifo);
263 while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
fa4bd4f1 264 cpu_relax();
766e3721 265 *(u8 *)(drv_data->rx++) = ioread32(&drv_data->regs->rfifo);
fa4bd4f1
SJ		 266 }
267}
268
766e3721
SJ		 269static const struct adi_spi_transfer_ops adi_spi_transfer_ops_u8 = {
270 .write = adi_spi_u8_write,
271 .read = adi_spi_u8_read,
272 .duplex = adi_spi_u8_duplex,
fa4bd4f1
SJ		 273};
274
766e3721 275static void adi_spi_u16_write(struct adi_spi_master *drv_data)
fa4bd4f1
SJ		 276{
277 dummy_read(drv_data);
278 while (drv_data->tx < drv_data->tx_end) {
766e3721 279 iowrite32(*(u16 *)drv_data->tx, &drv_data->regs->tfifo);
fa4bd4f1 280 drv_data->tx += 2;
766e3721 281 while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
fa4bd4f1 282 cpu_relax();
766e3721 283 ioread32(&drv_data->regs->rfifo);
fa4bd4f1
SJ		 284 }
285}
286
766e3721 287static void adi_spi_u16_read(struct adi_spi_master *drv_data)
fa4bd4f1
SJ		 288{
289 u32 tx_val = drv_data->cur_chip->tx_dummy_val;
290
291 dummy_read(drv_data);
292 while (drv_data->rx < drv_data->rx_end) {
766e3721
SJ		 293 iowrite32(tx_val, &drv_data->regs->tfifo);
294 while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
fa4bd4f1 295 cpu_relax();
766e3721 296 *(u16 *)drv_data->rx = ioread32(&drv_data->regs->rfifo);
fa4bd4f1
SJ		 297 drv_data->rx += 2;
298 }
299}
300
766e3721 301static void adi_spi_u16_duplex(struct adi_spi_master *drv_data)
fa4bd4f1
SJ		 302{
303 dummy_read(drv_data);
304 while (drv_data->rx < drv_data->rx_end) {
766e3721 305 iowrite32(*(u16 *)drv_data->tx, &drv_data->regs->tfifo);
fa4bd4f1 306 drv_data->tx += 2;
766e3721 307 while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
fa4bd4f1 308 cpu_relax();
766e3721 309 *(u16 *)drv_data->rx = ioread32(&drv_data->regs->rfifo);
fa4bd4f1
SJ		 310 drv_data->rx += 2;
311 }
312}
313
766e3721
SJ		 314static const struct adi_spi_transfer_ops adi_spi_transfer_ops_u16 = {
315 .write = adi_spi_u16_write,
316 .read = adi_spi_u16_read,
317 .duplex = adi_spi_u16_duplex,
fa4bd4f1
SJ		 318};
319
766e3721 320static void adi_spi_u32_write(struct adi_spi_master *drv_data)
fa4bd4f1
SJ		 321{
322 dummy_read(drv_data);
323 while (drv_data->tx < drv_data->tx_end) {
766e3721 324 iowrite32(*(u32 *)drv_data->tx, &drv_data->regs->tfifo);
fa4bd4f1 325 drv_data->tx += 4;
766e3721 326 while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
fa4bd4f1 327 cpu_relax();
766e3721 328 ioread32(&drv_data->regs->rfifo);
fa4bd4f1
SJ		 329 }
330}
331
766e3721 332static void adi_spi_u32_read(struct adi_spi_master *drv_data)
fa4bd4f1
SJ		 333{
334 u32 tx_val = drv_data->cur_chip->tx_dummy_val;
335
336 dummy_read(drv_data);
337 while (drv_data->rx < drv_data->rx_end) {
766e3721
SJ		 338 iowrite32(tx_val, &drv_data->regs->tfifo);
339 while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
fa4bd4f1 340 cpu_relax();
766e3721 341 *(u32 *)drv_data->rx = ioread32(&drv_data->regs->rfifo);
fa4bd4f1
SJ		 342 drv_data->rx += 4;
343 }
344}
345
766e3721 346static void adi_spi_u32_duplex(struct adi_spi_master *drv_data)
fa4bd4f1
SJ		 347{
348 dummy_read(drv_data);
349 while (drv_data->rx < drv_data->rx_end) {
766e3721 350 iowrite32(*(u32 *)drv_data->tx, &drv_data->regs->tfifo);
fa4bd4f1 351 drv_data->tx += 4;
766e3721 352 while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
fa4bd4f1 353 cpu_relax();
766e3721 354 *(u32 *)drv_data->rx = ioread32(&drv_data->regs->rfifo);
fa4bd4f1
SJ		 355 drv_data->rx += 4;
356 }
357}
358
766e3721
SJ		 359static const struct adi_spi_transfer_ops adi_spi_transfer_ops_u32 = {
360 .write = adi_spi_u32_write,
361 .read = adi_spi_u32_read,
362 .duplex = adi_spi_u32_duplex,
fa4bd4f1
SJ		 363};
364
365
366/* test if there is more transfer to be done */
766e3721 367static void adi_spi_next_transfer(struct adi_spi_master *drv)
fa4bd4f1
SJ		 368{
369 struct spi_message *msg = drv->cur_msg;
370 struct spi_transfer *t = drv->cur_transfer;
371
372 /* Move to next transfer */
373 if (t->transfer_list.next != &msg->transfers) {
374 drv->cur_transfer = list_entry(t->transfer_list.next,
375 struct spi_transfer, transfer_list);
376 drv->state = RUNNING_STATE;
377 } else {
378 drv->state = DONE_STATE;
379 drv->cur_transfer = NULL;
380 }
381}
382
766e3721 383static void adi_spi_giveback(struct adi_spi_master *drv_data)
fa4bd4f1 384{
766e3721 385 struct adi_spi_device *chip = drv_data->cur_chip;
fa4bd4f1 386
766e3721 387 adi_spi_cs_deactive(drv_data, chip);
fa4bd4f1
SJ		 388 spi_finalize_current_message(drv_data->master);
389}
390
766e3721 391static int adi_spi_setup_transfer(struct adi_spi_master *drv)
fa4bd4f1
SJ		 392{
393 struct spi_transfer *t = drv->cur_transfer;
394 u32 cr, cr_width;
395
396 if (t->tx_buf) {
397 drv->tx = (void *)t->tx_buf;
398 drv->tx_end = drv->tx + t->len;
399 } else {
400 drv->tx = NULL;
401 }
402
403 if (t->rx_buf) {
404 drv->rx = t->rx_buf;
405 drv->rx_end = drv->rx + t->len;
406 } else {
407 drv->rx = NULL;
408 }
409
410 drv->transfer_len = t->len;
411
412 /* bits per word setup */
413 switch (t->bits_per_word) {
414 case 8:
415 cr_width = SPI_CTL_SIZE08;
766e3721 416 drv->ops = &adi_spi_transfer_ops_u8;
fa4bd4f1
SJ		 417 break;
418 case 16:
419 cr_width = SPI_CTL_SIZE16;
766e3721 420 drv->ops = &adi_spi_transfer_ops_u16;
fa4bd4f1
SJ		 421 break;
422 case 32:
423 cr_width = SPI_CTL_SIZE32;
766e3721 424 drv->ops = &adi_spi_transfer_ops_u32;
fa4bd4f1
SJ		 425 break;
426 default:
427 return -EINVAL;
428 }
766e3721 429 cr = ioread32(&drv->regs->control) & ~SPI_CTL_SIZE;
fa4bd4f1 430 cr |= cr_width;
766e3721 431 iowrite32(cr, &drv->regs->control);
fa4bd4f1
SJ		 432
433 /* speed setup */
766e3721 434 iowrite32(hz_to_spi_clock(drv->sclk, t->speed_hz), &drv->regs->clock);
fa4bd4f1
SJ		 435 return 0;
436}
437
766e3721 438static int adi_spi_dma_xfer(struct adi_spi_master *drv_data)
fa4bd4f1
SJ		 439{
440 struct spi_transfer *t = drv_data->cur_transfer;
441 struct spi_message *msg = drv_data->cur_msg;
766e3721 442 struct adi_spi_device *chip = drv_data->cur_chip;
fa4bd4f1
SJ		 443 u32 dma_config;
444 unsigned long word_count, word_size;
445 void *tx_buf, *rx_buf;
446
447 switch (t->bits_per_word) {
448 case 8:
449 dma_config = WDSIZE_8 | PSIZE_8;
450 word_count = drv_data->transfer_len;
451 word_size = 1;
452 break;
453 case 16:
454 dma_config = WDSIZE_16 | PSIZE_16;
455 word_count = drv_data->transfer_len / 2;
456 word_size = 2;
457 break;
458 default:
459 dma_config = WDSIZE_32 | PSIZE_32;
460 word_count = drv_data->transfer_len / 4;
461 word_size = 4;
462 break;
463 }
464
465 if (!drv_data->rx) {
466 tx_buf = drv_data->tx;
467 rx_buf = &drv_data->dummy_buffer;
468 drv_data->tx_dma_size = drv_data->transfer_len;
469 drv_data->rx_dma_size = sizeof(drv_data->dummy_buffer);
470 set_dma_x_modify(drv_data->tx_dma, word_size);
471 set_dma_x_modify(drv_data->rx_dma, 0);
472 } else if (!drv_data->tx) {
473 drv_data->dummy_buffer = chip->tx_dummy_val;
474 tx_buf = &drv_data->dummy_buffer;
475 rx_buf = drv_data->rx;
476 drv_data->tx_dma_size = sizeof(drv_data->dummy_buffer);
477 drv_data->rx_dma_size = drv_data->transfer_len;
478 set_dma_x_modify(drv_data->tx_dma, 0);
479 set_dma_x_modify(drv_data->rx_dma, word_size);
480 } else {
481 tx_buf = drv_data->tx;
482 rx_buf = drv_data->rx;
483 drv_data->tx_dma_size = drv_data->rx_dma_size
484 = drv_data->transfer_len;
485 set_dma_x_modify(drv_data->tx_dma, word_size);
486 set_dma_x_modify(drv_data->rx_dma, word_size);
487 }
488
489 drv_data->tx_dma_addr = dma_map_single(&msg->spi->dev,
490 (void *)tx_buf,
491 drv_data->tx_dma_size,
492 DMA_TO_DEVICE);
493 if (dma_mapping_error(&msg->spi->dev,
494 drv_data->tx_dma_addr))
495 return -ENOMEM;
496
497 drv_data->rx_dma_addr = dma_map_single(&msg->spi->dev,
498 (void *)rx_buf,
499 drv_data->rx_dma_size,
500 DMA_FROM_DEVICE);
501 if (dma_mapping_error(&msg->spi->dev,
502 drv_data->rx_dma_addr)) {
503 dma_unmap_single(&msg->spi->dev,
504 drv_data->tx_dma_addr,
505 drv_data->tx_dma_size,
506 DMA_TO_DEVICE);
507 return -ENOMEM;
508 }
509
510 dummy_read(drv_data);
511 set_dma_x_count(drv_data->tx_dma, word_count);
512 set_dma_x_count(drv_data->rx_dma, word_count);
513 set_dma_start_addr(drv_data->tx_dma, drv_data->tx_dma_addr);
514 set_dma_start_addr(drv_data->rx_dma, drv_data->rx_dma_addr);
515 dma_config |= DMAFLOW_STOP | RESTART | DI_EN;
516 set_dma_config(drv_data->tx_dma, dma_config);
517 set_dma_config(drv_data->rx_dma, dma_config | WNR);
518 enable_dma(drv_data->tx_dma);
519 enable_dma(drv_data->rx_dma);
fa4bd4f1 520
766e3721
SJ		 521 iowrite32(SPI_RXCTL_REN | SPI_RXCTL_RDR_NE,
522 &drv_data->regs->rx_control);
523 iowrite32(SPI_TXCTL_TEN | SPI_TXCTL_TTI | SPI_TXCTL_TDR_NF,
524 &drv_data->regs->tx_control);
fa4bd4f1
SJ		 525
526 return 0;
527}
528
766e3721 529static int adi_spi_pio_xfer(struct adi_spi_master *drv_data)
fa4bd4f1
SJ		 530{
531 struct spi_message *msg = drv_data->cur_msg;
532
533 if (!drv_data->rx) {
534 /* write only half duplex */
535 drv_data->ops->write(drv_data);
536 if (drv_data->tx != drv_data->tx_end)
537 return -EIO;
538 } else if (!drv_data->tx) {
539 /* read only half duplex */
540 drv_data->ops->read(drv_data);
541 if (drv_data->rx != drv_data->rx_end)
542 return -EIO;
543 } else {
544 /* full duplex mode */
545 drv_data->ops->duplex(drv_data);
546 if (drv_data->tx != drv_data->tx_end)
547 return -EIO;
548 }
549
766e3721 550 if (!adi_spi_flush(drv_data))
fa4bd4f1
SJ		 551 return -EIO;
552 msg->actual_length += drv_data->transfer_len;
553 tasklet_schedule(&drv_data->pump_transfers);
554 return 0;
555}
556
766e3721 557static void adi_spi_pump_transfers(unsigned long data)
fa4bd4f1 558{
766e3721 559 struct adi_spi_master *drv_data = (struct adi_spi_master *)data;
fa4bd4f1
SJ		 560 struct spi_message *msg = NULL;
561 struct spi_transfer *t = NULL;
766e3721 562 struct adi_spi_device *chip = NULL;
fa4bd4f1
SJ		 563 int ret;
564
565 /* Get current state information */
566 msg = drv_data->cur_msg;
567 t = drv_data->cur_transfer;
568 chip = drv_data->cur_chip;
569
570 /* Handle for abort */
571 if (drv_data->state == ERROR_STATE) {
572 msg->status = -EIO;
766e3721 573 adi_spi_giveback(drv_data);
fa4bd4f1
SJ		 574 return;
575 }
576
577 if (drv_data->state == RUNNING_STATE) {
578 if (t->delay_usecs)
579 udelay(t->delay_usecs);
580 if (t->cs_change)
766e3721
SJ		 581 adi_spi_cs_deactive(drv_data, chip);
582 adi_spi_next_transfer(drv_data);
fa4bd4f1
SJ		 583 t = drv_data->cur_transfer;
584 }
585 /* Handle end of message */
586 if (drv_data->state == DONE_STATE) {
587 msg->status = 0;
766e3721 588 adi_spi_giveback(drv_data);
fa4bd4f1
SJ		 589 return;
590 }
591
592 if ((t->len == 0) || (t->tx_buf == NULL && t->rx_buf == NULL)) {
593 /* Schedule next transfer tasklet */
594 tasklet_schedule(&drv_data->pump_transfers);
595 return;
596 }
597
766e3721 598 ret = adi_spi_setup_transfer(drv_data);
fa4bd4f1
SJ		 599 if (ret) {
600 msg->status = ret;
766e3721 601 adi_spi_giveback(drv_data);
fa4bd4f1
SJ		 602 }
603
766e3721
SJ		 604 iowrite32(0xFFFFFFFF, &drv_data->regs->status);
605 adi_spi_cs_active(drv_data, chip);
fa4bd4f1
SJ		 606 drv_data->state = RUNNING_STATE;
607
608 if (chip->enable_dma)
766e3721 609 ret = adi_spi_dma_xfer(drv_data);
fa4bd4f1 610 else
766e3721 611 ret = adi_spi_pio_xfer(drv_data);
fa4bd4f1
SJ		 612 if (ret) {
613 msg->status = ret;
766e3721 614 adi_spi_giveback(drv_data);
fa4bd4f1
SJ		 615 }
616}
617
766e3721 618static int adi_spi_transfer_one_message(struct spi_master *master,
fa4bd4f1
SJ		 619 struct spi_message *m)
620{
766e3721 621 struct adi_spi_master *drv_data = spi_master_get_devdata(master);
fa4bd4f1
SJ		 622
623 drv_data->cur_msg = m;
624 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
766e3721 625 adi_spi_restore_state(drv_data);
fa4bd4f1
SJ		 626
627 drv_data->state = START_STATE;
628 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
629 struct spi_transfer, transfer_list);
630
631 tasklet_schedule(&drv_data->pump_transfers);
632 return 0;
633}
634
635#define MAX_SPI_SSEL 7
636
637static const u16 ssel[][MAX_SPI_SSEL] = {
638 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
639 P_SPI0_SSEL4, P_SPI0_SSEL5,
640 P_SPI0_SSEL6, P_SPI0_SSEL7},
641
642 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
643 P_SPI1_SSEL4, P_SPI1_SSEL5,
644 P_SPI1_SSEL6, P_SPI1_SSEL7},
645
646 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
647 P_SPI2_SSEL4, P_SPI2_SSEL5,
648 P_SPI2_SSEL6, P_SPI2_SSEL7},
649};
650
766e3721 651static int adi_spi_setup(struct spi_device *spi)
fa4bd4f1 652{
766e3721
SJ		 653 struct adi_spi_master *drv_data = spi_master_get_devdata(spi->master);
654 struct adi_spi_device *chip = spi_get_ctldata(spi);
655 u32 ctl_reg = SPI_CTL_ODM | SPI_CTL_PSSE;
fa4bd4f1
SJ		 656 int ret = -EINVAL;
657
658 if (!chip) {
766e3721 659 struct adi_spi3_chip *chip_info = spi->controller_data;
fa4bd4f1
SJ		 660
661 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
662 if (!chip) {
663 dev_err(&spi->dev, "can not allocate chip data\n");
664 return -ENOMEM;
665 }
666 if (chip_info) {
766e3721 667 if (chip_info->control & ~ctl_reg) {
fa4bd4f1
SJ		 668 dev_err(&spi->dev,
669 "do not set bits that the SPI framework manages\n");
670 goto error;
671 }
672 chip->control = chip_info->control;
673 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
674 chip->tx_dummy_val = chip_info->tx_dummy_val;
675 chip->enable_dma = chip_info->enable_dma;
676 }
677 chip->cs = spi->chip_select;
766e3721 678
fa4bd4f1
SJ		 679 if (chip->cs < MAX_CTRL_CS) {
680 chip->ssel = (1 << chip->cs) << 8;
681 ret = peripheral_request(ssel[spi->master->bus_num]
682 [chip->cs-1], dev_name(&spi->dev));
683 if (ret) {
684 dev_err(&spi->dev, "peripheral_request() error\n");
685 goto error;
686 }
687 } else {
688 chip->cs_gpio = chip->cs - MAX_CTRL_CS;
689 ret = gpio_request_one(chip->cs_gpio, GPIOF_OUT_INIT_HIGH,
690 dev_name(&spi->dev));
691 if (ret) {
692 dev_err(&spi->dev, "gpio_request_one() error\n");
693 goto error;
694 }
695 }
696 spi_set_ctldata(spi, chip);
697 }
698
699 /* force a default base state */
766e3721 700 chip->control &= ctl_reg;
fa4bd4f1
SJ		 701
702 if (spi->mode & SPI_CPOL)
703 chip->control |= SPI_CTL_CPOL;
704 if (spi->mode & SPI_CPHA)
705 chip->control |= SPI_CTL_CPHA;
706 if (spi->mode & SPI_LSB_FIRST)
707 chip->control |= SPI_CTL_LSBF;
708 chip->control |= SPI_CTL_MSTR;
709 /* we choose software to controll cs */
710 chip->control &= ~SPI_CTL_ASSEL;
711
712 chip->clock = hz_to_spi_clock(drv_data->sclk, spi->max_speed_hz);
713
766e3721
SJ		 714 adi_spi_cs_enable(drv_data, chip);
715 adi_spi_cs_deactive(drv_data, chip);
fa4bd4f1
SJ		 716
717 return 0;
718error:
719 if (chip) {
720 kfree(chip);
721 spi_set_ctldata(spi, NULL);
722 }
723
724 return ret;
725}
726
766e3721 727static void adi_spi_cleanup(struct spi_device *spi)
fa4bd4f1 728{
766e3721
SJ		 729 struct adi_spi_device *chip = spi_get_ctldata(spi);
730 struct adi_spi_master *drv_data = spi_master_get_devdata(spi->master);
fa4bd4f1
SJ		 731
732 if (!chip)
733 return;
734
735 if (chip->cs < MAX_CTRL_CS) {
736 peripheral_free(ssel[spi->master->bus_num]
737 [chip->cs-1]);
766e3721 738 adi_spi_cs_disable(drv_data, chip);
fa4bd4f1
SJ		 739 } else {
740 gpio_free(chip->cs_gpio);
741 }
742
743 kfree(chip);
744 spi_set_ctldata(spi, NULL);
745}
746
766e3721 747static irqreturn_t adi_spi_tx_dma_isr(int irq, void *dev_id)
fa4bd4f1 748{
766e3721 749 struct adi_spi_master *drv_data = dev_id;
fa4bd4f1 750 u32 dma_stat = get_dma_curr_irqstat(drv_data->tx_dma);
766e3721 751 u32 tx_ctl;
fa4bd4f1
SJ		 752
753 clear_dma_irqstat(drv_data->tx_dma);
754 if (dma_stat & DMA_DONE) {
755 drv_data->tx_num++;
756 } else {
757 dev_err(&drv_data->master->dev,
758 "spi tx dma error: %d\n", dma_stat);
759 if (drv_data->tx)
760 drv_data->state = ERROR_STATE;
761 }
766e3721
SJ		 762 tx_ctl = ioread32(&drv_data->regs->tx_control);
763 tx_ctl &= ~SPI_TXCTL_TDR_NF;
764 iowrite32(tx_ctl, &drv_data->regs->tx_control);
fa4bd4f1
SJ		 765 return IRQ_HANDLED;
766}
767
766e3721 768static irqreturn_t adi_spi_rx_dma_isr(int irq, void *dev_id)
fa4bd4f1 769{
766e3721 770 struct adi_spi_master *drv_data = dev_id;
fa4bd4f1
SJ		 771 struct spi_message *msg = drv_data->cur_msg;
772 u32 dma_stat = get_dma_curr_irqstat(drv_data->rx_dma);
773
774 clear_dma_irqstat(drv_data->rx_dma);
775 if (dma_stat & DMA_DONE) {
776 drv_data->rx_num++;
777 /* we may fail on tx dma */
778 if (drv_data->state != ERROR_STATE)
779 msg->actual_length += drv_data->transfer_len;
780 } else {
781 drv_data->state = ERROR_STATE;
782 dev_err(&drv_data->master->dev,
783 "spi rx dma error: %d\n", dma_stat);
784 }
766e3721
SJ		 785 iowrite32(0, &drv_data->regs->tx_control);
786 iowrite32(0, &drv_data->regs->rx_control);
fa4bd4f1
SJ		 787 if (drv_data->rx_num != drv_data->tx_num)
788 dev_dbg(&drv_data->master->dev,
789 "dma interrupt missing: tx=%d,rx=%d\n",
790 drv_data->tx_num, drv_data->rx_num);
791 tasklet_schedule(&drv_data->pump_transfers);
792 return IRQ_HANDLED;
793}
794
766e3721 795static int adi_spi_probe(struct platform_device *pdev)
fa4bd4f1
SJ		 796{
797 struct device *dev = &pdev->dev;
766e3721 798 struct adi_spi3_master *info = dev_get_platdata(dev);
fa4bd4f1 799 struct spi_master *master;
766e3721 800 struct adi_spi_master *drv_data;
fa4bd4f1
SJ		 801 struct resource *mem, *res;
802 unsigned int tx_dma, rx_dma;
803 unsigned long sclk;
804 int ret;
805
806 if (!info) {
807 dev_err(dev, "platform data missing!\n");
808 return -ENODEV;
809 }
810
811 sclk = get_sclk1();
812 if (!sclk) {
813 dev_err(dev, "can not get sclk1\n");
814 return -ENXIO;
815 }
816
fa4bd4f1
SJ		 817 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
818 if (!res) {
819 dev_err(dev, "can not get tx dma resource\n");
820 return -ENXIO;
821 }
822 tx_dma = res->start;
823
824 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
825 if (!res) {
826 dev_err(dev, "can not get rx dma resource\n");
827 return -ENXIO;
828 }
829 rx_dma = res->start;
830
831 /* allocate master with space for drv_data */
832 master = spi_alloc_master(dev, sizeof(*drv_data));
833 if (!master) {
834 dev_err(dev, "can not alloc spi_master\n");
835 return -ENOMEM;
836 }
837 platform_set_drvdata(pdev, master);
838
839 /* the mode bits supported by this driver */
840 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
841
842 master->bus_num = pdev->id;
843 master->num_chipselect = info->num_chipselect;
766e3721
SJ		 844 master->cleanup = adi_spi_cleanup;
845 master->setup = adi_spi_setup;
846 master->transfer_one_message = adi_spi_transfer_one_message;
aa188f90
AL		 847 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
848 SPI_BPW_MASK(8);
fa4bd4f1
SJ		 849
850 drv_data = spi_master_get_devdata(master);
851 drv_data->master = master;
852 drv_data->tx_dma = tx_dma;
853 drv_data->rx_dma = rx_dma;
854 drv_data->pin_req = info->pin_req;
855 drv_data->sclk = sclk;
856
de0fa83c 857 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
fa4bd4f1
SJ		 858 drv_data->regs = devm_ioremap_resource(dev, mem);
859 if (IS_ERR(drv_data->regs)) {
860 ret = PTR_ERR(drv_data->regs);
861 goto err_put_master;
862 }
863
864 /* request tx and rx dma */
865 ret = request_dma(tx_dma, "SPI_TX_DMA");
866 if (ret) {
867 dev_err(dev, "can not request SPI TX DMA channel\n");
868 goto err_put_master;
869 }
766e3721 870 set_dma_callback(tx_dma, adi_spi_tx_dma_isr, drv_data);
fa4bd4f1
SJ		 871
872 ret = request_dma(rx_dma, "SPI_RX_DMA");
873 if (ret) {
874 dev_err(dev, "can not request SPI RX DMA channel\n");
875 goto err_free_tx_dma;
876 }
766e3721 877 set_dma_callback(drv_data->rx_dma, adi_spi_rx_dma_isr, drv_data);
fa4bd4f1
SJ		 878
879 /* request CLK, MOSI and MISO */
766e3721 880 ret = peripheral_request_list(drv_data->pin_req, "adi-spi3");
fa4bd4f1
SJ		 881 if (ret < 0) {
882 dev_err(dev, "can not request spi pins\n");
883 goto err_free_rx_dma;
884 }
885
766e3721
SJ		 886 iowrite32(SPI_CTL_MSTR | SPI_CTL_CPHA, &drv_data->regs->control);
887 iowrite32(0x0000FE00, &drv_data->regs->ssel);
888 iowrite32(0x0, &drv_data->regs->delay);
fa4bd4f1
SJ		 889
890 tasklet_init(&drv_data->pump_transfers,
766e3721 891 adi_spi_pump_transfers, (unsigned long)drv_data);
fa4bd4f1 892 /* register with the SPI framework */
6221df6d 893 ret = devm_spi_register_master(dev, master);
fa4bd4f1
SJ		 894 if (ret) {
895 dev_err(dev, "can not register spi master\n");
896 goto err_free_peripheral;
897 }
898
899 return ret;
900
901err_free_peripheral:
902 peripheral_free_list(drv_data->pin_req);
903err_free_rx_dma:
904 free_dma(rx_dma);
905err_free_tx_dma:
906 free_dma(tx_dma);
907err_put_master:
fa4bd4f1
SJ		 908 spi_master_put(master);
909
910 return ret;
911}
912
766e3721 913static int adi_spi_remove(struct platform_device *pdev)
fa4bd4f1
SJ		 914{
915 struct spi_master *master = platform_get_drvdata(pdev);
766e3721 916 struct adi_spi_master *drv_data = spi_master_get_devdata(master);
fa4bd4f1 917
766e3721 918 adi_spi_disable(drv_data);
fa4bd4f1
SJ		 919 peripheral_free_list(drv_data->pin_req);
920 free_dma(drv_data->rx_dma);
921 free_dma(drv_data->tx_dma);
fa4bd4f1
SJ		 922 return 0;
923}
924
925#ifdef CONFIG_PM
766e3721 926static int adi_spi_suspend(struct device *dev)
fa4bd4f1
SJ		 927{
928 struct spi_master *master = dev_get_drvdata(dev);
766e3721 929 struct adi_spi_master *drv_data = spi_master_get_devdata(master);
fa4bd4f1
SJ		 930
931 spi_master_suspend(master);
932
766e3721
SJ		 933 drv_data->control = ioread32(&drv_data->regs->control);
934 drv_data->ssel = ioread32(&drv_data->regs->ssel);
fa4bd4f1 935
766e3721
SJ		 936 iowrite32(SPI_CTL_MSTR | SPI_CTL_CPHA, &drv_data->regs->control);
937 iowrite32(0x0000FE00, &drv_data->regs->ssel);
fa4bd4f1
SJ		 938 dma_disable_irq(drv_data->rx_dma);
939 dma_disable_irq(drv_data->tx_dma);
940
941 return 0;
942}
943
766e3721 944static int adi_spi_resume(struct device *dev)
fa4bd4f1
SJ		 945{
946 struct spi_master *master = dev_get_drvdata(dev);
766e3721 947 struct adi_spi_master *drv_data = spi_master_get_devdata(master);
fa4bd4f1
SJ		 948 int ret = 0;
949
950 /* bootrom may modify spi and dma status when resume in spi boot mode */
951 disable_dma(drv_data->rx_dma);
952
953 dma_enable_irq(drv_data->rx_dma);
954 dma_enable_irq(drv_data->tx_dma);
766e3721
SJ		 955 iowrite32(drv_data->control, &drv_data->regs->control);
956 iowrite32(drv_data->ssel, &drv_data->regs->ssel);
fa4bd4f1
SJ		 957
958 ret = spi_master_resume(master);
959 if (ret) {
960 free_dma(drv_data->rx_dma);
961 free_dma(drv_data->tx_dma);
962 }
963
964 return ret;
965}
966#endif
766e3721
SJ		 967static const struct dev_pm_ops adi_spi_pm_ops = {
968 SET_SYSTEM_SLEEP_PM_OPS(adi_spi_suspend, adi_spi_resume)
fa4bd4f1
SJ		 969};
970
766e3721
SJ		 971MODULE_ALIAS("platform:adi-spi3");
972static struct platform_driver adi_spi_driver = {
fa4bd4f1 973 .driver = {
766e3721 974 .name = "adi-spi3",
fa4bd4f1 975 .owner = THIS_MODULE,
766e3721 976 .pm = &adi_spi_pm_ops,
fa4bd4f1 977 },
766e3721 978 .remove = adi_spi_remove,
fa4bd4f1
SJ		 979};
980
766e3721 981module_platform_driver_probe(adi_spi_driver, adi_spi_probe);
fa4bd4f1
SJ		 982
983MODULE_DESCRIPTION("Analog Devices SPI3 controller driver");
984MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
985MODULE_LICENSE("GPL v2");
ubuntu-bionic-kernel mirror