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spi: armada-3700: Remove unnecessary condition
[mirror_ubuntu-focal-kernel.git] / drivers / spi / spi-armada-3700.c
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5762ab71
RP		 1/*
2 * Marvell Armada-3700 SPI controller driver
3 *
4 * Copyright (C) 2016 Marvell Ltd.
5 *
6 * Author: Wilson Ding <dingwei@marvell.com>
7 * Author: Romain Perier <romain.perier@free-electrons.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/clk.h>
15#include <linux/completion.h>
16#include <linux/delay.h>
17#include <linux/err.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_irq.h>
24#include <linux/of_device.h>
25#include <linux/pinctrl/consumer.h>
26#include <linux/spi/spi.h>
27
28#define DRIVER_NAME "armada_3700_spi"
29
30#define A3700_SPI_TIMEOUT 10
31
32/* SPI Register Offest */
33#define A3700_SPI_IF_CTRL_REG 0x00
34#define A3700_SPI_IF_CFG_REG 0x04
35#define A3700_SPI_DATA_OUT_REG 0x08
36#define A3700_SPI_DATA_IN_REG 0x0C
37#define A3700_SPI_IF_INST_REG 0x10
38#define A3700_SPI_IF_ADDR_REG 0x14
39#define A3700_SPI_IF_RMODE_REG 0x18
40#define A3700_SPI_IF_HDR_CNT_REG 0x1C
41#define A3700_SPI_IF_DIN_CNT_REG 0x20
42#define A3700_SPI_IF_TIME_REG 0x24
43#define A3700_SPI_INT_STAT_REG 0x28
44#define A3700_SPI_INT_MASK_REG 0x2C
45
46/* A3700_SPI_IF_CTRL_REG */
47#define A3700_SPI_EN BIT(16)
48#define A3700_SPI_ADDR_NOT_CONFIG BIT(12)
49#define A3700_SPI_WFIFO_OVERFLOW BIT(11)
50#define A3700_SPI_WFIFO_UNDERFLOW BIT(10)
51#define A3700_SPI_RFIFO_OVERFLOW BIT(9)
52#define A3700_SPI_RFIFO_UNDERFLOW BIT(8)
53#define A3700_SPI_WFIFO_FULL BIT(7)
54#define A3700_SPI_WFIFO_EMPTY BIT(6)
55#define A3700_SPI_RFIFO_FULL BIT(5)
56#define A3700_SPI_RFIFO_EMPTY BIT(4)
57#define A3700_SPI_WFIFO_RDY BIT(3)
58#define A3700_SPI_RFIFO_RDY BIT(2)
59#define A3700_SPI_XFER_RDY BIT(1)
60#define A3700_SPI_XFER_DONE BIT(0)
61
62/* A3700_SPI_IF_CFG_REG */
63#define A3700_SPI_WFIFO_THRS BIT(28)
64#define A3700_SPI_RFIFO_THRS BIT(24)
65#define A3700_SPI_AUTO_CS BIT(20)
66#define A3700_SPI_DMA_RD_EN BIT(18)
67#define A3700_SPI_FIFO_MODE BIT(17)
68#define A3700_SPI_SRST BIT(16)
69#define A3700_SPI_XFER_START BIT(15)
70#define A3700_SPI_XFER_STOP BIT(14)
71#define A3700_SPI_INST_PIN BIT(13)
72#define A3700_SPI_ADDR_PIN BIT(12)
73#define A3700_SPI_DATA_PIN1 BIT(11)
74#define A3700_SPI_DATA_PIN0 BIT(10)
75#define A3700_SPI_FIFO_FLUSH BIT(9)
76#define A3700_SPI_RW_EN BIT(8)
77#define A3700_SPI_CLK_POL BIT(7)
78#define A3700_SPI_CLK_PHA BIT(6)
79#define A3700_SPI_BYTE_LEN BIT(5)
80#define A3700_SPI_CLK_PRESCALE BIT(0)
81#define A3700_SPI_CLK_PRESCALE_MASK (0x1f)
82
83#define A3700_SPI_WFIFO_THRS_BIT 28
84#define A3700_SPI_RFIFO_THRS_BIT 24
85#define A3700_SPI_FIFO_THRS_MASK 0x7
86
87#define A3700_SPI_DATA_PIN_MASK 0x3
88
89/* A3700_SPI_IF_HDR_CNT_REG */
90#define A3700_SPI_DUMMY_CNT_BIT 12
91#define A3700_SPI_DUMMY_CNT_MASK 0x7
92#define A3700_SPI_RMODE_CNT_BIT 8
93#define A3700_SPI_RMODE_CNT_MASK 0x3
94#define A3700_SPI_ADDR_CNT_BIT 4
95#define A3700_SPI_ADDR_CNT_MASK 0x7
96#define A3700_SPI_INSTR_CNT_BIT 0
97#define A3700_SPI_INSTR_CNT_MASK 0x3
98
99/* A3700_SPI_IF_TIME_REG */
100#define A3700_SPI_CLK_CAPT_EDGE BIT(7)
101
102/* Flags and macros for struct a3700_spi */
103#define A3700_INSTR_CNT 1
104#define A3700_ADDR_CNT 3
105#define A3700_DUMMY_CNT 1
106
107struct a3700_spi {
108 struct spi_master *master;
109 void __iomem *base;
110 struct clk *clk;
111 unsigned int irq;
112 unsigned int flags;
113 bool xmit_data;
114 const u8 *tx_buf;
115 u8 *rx_buf;
116 size_t buf_len;
117 u8 byte_len;
118 u32 wait_mask;
119 struct completion done;
120 u32 addr_cnt;
121 u32 instr_cnt;
122 size_t hdr_cnt;
123};
124
125static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset)
126{
127 return readl(a3700_spi->base + offset);
128}
129
130static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data)
131{
132 writel(data, a3700_spi->base + offset);
133}
134
135static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi)
136{
137 u32 val;
138
139 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
140 val &= ~A3700_SPI_AUTO_CS;
141 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
142}
143
144static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs)
145{
146 u32 val;
147
148 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
149 val |= (A3700_SPI_EN << cs);
150 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
151}
152
153static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi,
154 unsigned int cs)
155{
156 u32 val;
157
158 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
159 val &= ~(A3700_SPI_EN << cs);
160 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
161}
162
163static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi,
164 unsigned int pin_mode)
165{
166 u32 val;
167
168 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
169 val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN);
170 val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1);
171
172 switch (pin_mode) {
173 case 1:
174 break;
175 case 2:
176 val |= A3700_SPI_DATA_PIN0;
177 break;
178 case 4:
179 val |= A3700_SPI_DATA_PIN1;
180 break;
181 default:
182 dev_err(&a3700_spi->master->dev, "wrong pin mode %u", pin_mode);
183 return -EINVAL;
184 }
185
186 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
187
188 return 0;
189}
190
191static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi)
192{
193 u32 val;
194
195 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
196 val |= A3700_SPI_FIFO_MODE;
197 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
198}
199
200static void a3700_spi_mode_set(struct a3700_spi *a3700_spi,
201 unsigned int mode_bits)
202{
203 u32 val;
204
205 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
206
207 if (mode_bits & SPI_CPOL)
208 val |= A3700_SPI_CLK_POL;
209 else
210 val &= ~A3700_SPI_CLK_POL;
211
212 if (mode_bits & SPI_CPHA)
213 val |= A3700_SPI_CLK_PHA;
214 else
215 val &= ~A3700_SPI_CLK_PHA;
216
217 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
218}
219
220static void a3700_spi_clock_set(struct a3700_spi *a3700_spi,
221 unsigned int speed_hz, u16 mode)
222{
223 u32 val;
224 u32 prescale;
225
226 prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz);
227
228 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
229 val = val & ~A3700_SPI_CLK_PRESCALE_MASK;
230
231 val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK);
232 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
233
234 if (prescale <= 2) {
235 val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG);
236 val |= A3700_SPI_CLK_CAPT_EDGE;
237 spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val);
238 }
239
240 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
241 val &= ~(A3700_SPI_CLK_POL | A3700_SPI_CLK_PHA);
242
243 if (mode & SPI_CPOL)
244 val |= A3700_SPI_CLK_POL;
245
246 if (mode & SPI_CPHA)
247 val |= A3700_SPI_CLK_PHA;
248
249 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
250}
251
252static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len)
253{
254 u32 val;
255
256 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
257 if (len == 4)
258 val |= A3700_SPI_BYTE_LEN;
259 else
260 val &= ~A3700_SPI_BYTE_LEN;
261 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
262
263 a3700_spi->byte_len = len;
264}
265
266static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi)
267{
268 int timeout = A3700_SPI_TIMEOUT;
269 u32 val;
270
271 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
272 val |= A3700_SPI_FIFO_FLUSH;
273 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
274
275 while (--timeout) {
276 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
277 if (!(val & A3700_SPI_FIFO_FLUSH))
278 return 0;
279 udelay(1);
280 }
281
282 return -ETIMEDOUT;
283}
284
285static int a3700_spi_init(struct a3700_spi *a3700_spi)
286{
287 struct spi_master *master = a3700_spi->master;
288 u32 val;
289 int i, ret = 0;
290
291 /* Reset SPI unit */
292 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
293 val |= A3700_SPI_SRST;
294 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
295
296 udelay(A3700_SPI_TIMEOUT);
297
298 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
299 val &= ~A3700_SPI_SRST;
300 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
301
302 /* Disable AUTO_CS and deactivate all chip-selects */
303 a3700_spi_auto_cs_unset(a3700_spi);
304 for (i = 0; i < master->num_chipselect; i++)
305 a3700_spi_deactivate_cs(a3700_spi, i);
306
307 /* Enable FIFO mode */
308 a3700_spi_fifo_mode_set(a3700_spi);
309
310 /* Set SPI mode */
311 a3700_spi_mode_set(a3700_spi, master->mode_bits);
312
313 /* Reset counters */
314 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
315 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0);
316
317 /* Mask the interrupts and clear cause bits */
318 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
319 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U);
320
321 return ret;
322}
323
324static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id)
325{
326 struct spi_master *master = dev_id;
327 struct a3700_spi *a3700_spi;
328 u32 cause;
329
330 a3700_spi = spi_master_get_devdata(master);
331
332 /* Get interrupt causes */
333 cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG);
334
335 if (!cause || !(a3700_spi->wait_mask & cause))
336 return IRQ_NONE;
337
338 /* mask and acknowledge the SPI interrupts */
339 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
340 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause);
341
342 /* Wake up the transfer */
0cc059ab 343 complete(&a3700_spi->done);
5762ab71
RP		 344
345 return IRQ_HANDLED;
346}
347
348static bool a3700_spi_wait_completion(struct spi_device *spi)
349{
350 struct a3700_spi *a3700_spi;
351 unsigned int timeout;
352 unsigned int ctrl_reg;
353 unsigned long timeout_jiffies;
354
355 a3700_spi = spi_master_get_devdata(spi->master);
356
357 /* SPI interrupt is edge-triggered, which means an interrupt will
358 * be generated only when detecting a specific status bit changed
359 * from '0' to '1'. So when we start waiting for a interrupt, we
360 * need to check status bit in control reg first, if it is already 1,
361 * then we do not need to wait for interrupt
362 */
363 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
364 if (a3700_spi->wait_mask & ctrl_reg)
365 return true;
366
367 reinit_completion(&a3700_spi->done);
368
369 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG,
370 a3700_spi->wait_mask);
371
372 timeout_jiffies = msecs_to_jiffies(A3700_SPI_TIMEOUT);
373 timeout = wait_for_completion_timeout(&a3700_spi->done,
374 timeout_jiffies);
375
376 a3700_spi->wait_mask = 0;
377
378 if (timeout)
379 return true;
380
381 /* there might be the case that right after we checked the
382 * status bits in this routine and before start to wait for
383 * interrupt by wait_for_completion_timeout, the interrupt
384 * happens, to avoid missing it we need to double check
385 * status bits in control reg, if it is already 1, then
386 * consider that we have the interrupt successfully and
387 * return true.
388 */
389 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
390 if (a3700_spi->wait_mask & ctrl_reg)
391 return true;
392
393 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
394
395 return true;
396}
397
398static bool a3700_spi_transfer_wait(struct spi_device *spi,
399 unsigned int bit_mask)
400{
401 struct a3700_spi *a3700_spi;
402
403 a3700_spi = spi_master_get_devdata(spi->master);
404 a3700_spi->wait_mask = bit_mask;
405
406 return a3700_spi_wait_completion(spi);
407}
408
409static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi,
410 unsigned int bytes)
411{
412 u32 val;
413
414 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
415 val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT);
416 val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT;
417 val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT);
418 val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT;
419 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
420}
421
422static void a3700_spi_transfer_setup(struct spi_device *spi,
423 struct spi_transfer *xfer)
424{
425 struct a3700_spi *a3700_spi;
426 unsigned int byte_len;
427
428 a3700_spi = spi_master_get_devdata(spi->master);
429
430 a3700_spi_clock_set(a3700_spi, xfer->speed_hz, spi->mode);
431
432 byte_len = xfer->bits_per_word >> 3;
433
434 a3700_spi_fifo_thres_set(a3700_spi, byte_len);
435}
436
437static void a3700_spi_set_cs(struct spi_device *spi, bool enable)
438{
439 struct a3700_spi *a3700_spi = spi_master_get_devdata(spi->master);
440
441 if (!enable)
442 a3700_spi_activate_cs(a3700_spi, spi->chip_select);
443 else
444 a3700_spi_deactivate_cs(a3700_spi, spi->chip_select);
445}
446
447static void a3700_spi_header_set(struct a3700_spi *a3700_spi)
448{
449 u32 instr_cnt = 0, addr_cnt = 0, dummy_cnt = 0;
450 u32 val = 0;
451
452 /* Clear the header registers */
453 spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0);
454 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0);
455 spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0);
456
457 /* Set header counters */
458 if (a3700_spi->tx_buf) {
459 if (a3700_spi->buf_len <= a3700_spi->instr_cnt) {
460 instr_cnt = a3700_spi->buf_len;
461 } else if (a3700_spi->buf_len <= (a3700_spi->instr_cnt +
462 a3700_spi->addr_cnt)) {
463 instr_cnt = a3700_spi->instr_cnt;
464 addr_cnt = a3700_spi->buf_len - instr_cnt;
465 } else if (a3700_spi->buf_len <= a3700_spi->hdr_cnt) {
466 instr_cnt = a3700_spi->instr_cnt;
467 addr_cnt = a3700_spi->addr_cnt;
468 /* Need to handle the normal write case with 1 byte
469 * data
470 */
471 if (!a3700_spi->tx_buf[instr_cnt + addr_cnt])
472 dummy_cnt = a3700_spi->buf_len - instr_cnt -
473 addr_cnt;
474 }
475 val |= ((instr_cnt & A3700_SPI_INSTR_CNT_MASK)
476 << A3700_SPI_INSTR_CNT_BIT);
477 val |= ((addr_cnt & A3700_SPI_ADDR_CNT_MASK)
478 << A3700_SPI_ADDR_CNT_BIT);
479 val |= ((dummy_cnt & A3700_SPI_DUMMY_CNT_MASK)
480 << A3700_SPI_DUMMY_CNT_BIT);
481 }
482 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val);
483
484 /* Update the buffer length to be transferred */
485 a3700_spi->buf_len -= (instr_cnt + addr_cnt + dummy_cnt);
486
487 /* Set Instruction */
488 val = 0;
489 while (instr_cnt--) {
490 val = (val << 8) | a3700_spi->tx_buf[0];
491 a3700_spi->tx_buf++;
492 }
493 spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, val);
494
495 /* Set Address */
496 val = 0;
497 while (addr_cnt--) {
498 val = (val << 8) | a3700_spi->tx_buf[0];
499 a3700_spi->tx_buf++;
500 }
501 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val);
502}
503
504static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi)
505{
506 u32 val;
507
508 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
509 return (val & A3700_SPI_WFIFO_FULL);
510}
511
512static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi)
513{
514 u32 val;
515 int i = 0;
516
517 while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) {
518 val = 0;
519 if (a3700_spi->buf_len >= 4) {
520 val = cpu_to_le32(*(u32 *)a3700_spi->tx_buf);
521 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
522
523 a3700_spi->buf_len -= 4;
524 a3700_spi->tx_buf += 4;
525 } else {
526 /*
527 * If the remained buffer length is less than 4-bytes,
528 * we should pad the write buffer with all ones. So that
529 * it avoids overwrite the unexpected bytes following
530 * the last one.
531 */
532 val = GENMASK(31, 0);
533 while (a3700_spi->buf_len) {
534 val &= ~(0xff << (8 * i));
535 val |= *a3700_spi->tx_buf++ << (8 * i);
536 i++;
537 a3700_spi->buf_len--;
538
539 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG,
540 val);
541 }
542 break;
543 }
544 }
545
546 return 0;
547}
548
549static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi)
550{
551 u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
552
553 return (val & A3700_SPI_RFIFO_EMPTY);
554}
555
556static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi)
557{
558 u32 val;
559
560 while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) {
561 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
562 if (a3700_spi->buf_len >= 4) {
563 u32 data = le32_to_cpu(val);
564 memcpy(a3700_spi->rx_buf, &data, 4);
565
566 a3700_spi->buf_len -= 4;
567 a3700_spi->rx_buf += 4;
568 } else {
569 /*
570 * When remain bytes is not larger than 4, we should
571 * avoid memory overwriting and just write the left rx
572 * buffer bytes.
573 */
574 while (a3700_spi->buf_len) {
575 *a3700_spi->rx_buf = val & 0xff;
576 val >>= 8;
577
578 a3700_spi->buf_len--;
579 a3700_spi->rx_buf++;
580 }
581 }
582 }
583
584 return 0;
585}
586
587static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi)
588{
589 int timeout = A3700_SPI_TIMEOUT;
590 u32 val;
591
592 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
593 val |= A3700_SPI_XFER_STOP;
594 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
595
596 while (--timeout) {
597 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
598 if (!(val & A3700_SPI_XFER_START))
599 break;
600 udelay(1);
601 }
602
603 a3700_spi_fifo_flush(a3700_spi);
604
605 val &= ~A3700_SPI_XFER_STOP;
606 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
607}
608
609static int a3700_spi_prepare_message(struct spi_master *master,
610 struct spi_message *message)
611{
612 struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
613 struct spi_device *spi = message->spi;
614 int ret;
615
616 ret = clk_enable(a3700_spi->clk);
617 if (ret) {
618 dev_err(&spi->dev, "failed to enable clk with error %d\n", ret);
619 return ret;
620 }
621
622 /* Flush the FIFOs */
623 ret = a3700_spi_fifo_flush(a3700_spi);
624 if (ret)
625 return ret;
626
627 a3700_spi_bytelen_set(a3700_spi, 4);
628
629 return 0;
630}
631
632static int a3700_spi_transfer_one(struct spi_master *master,
633 struct spi_device *spi,
634 struct spi_transfer *xfer)
635{
636 struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
637 int ret = 0, timeout = A3700_SPI_TIMEOUT;
638 unsigned int nbits = 0;
639 u32 val;
640
641 a3700_spi_transfer_setup(spi, xfer);
642
643 a3700_spi->tx_buf = xfer->tx_buf;
644 a3700_spi->rx_buf = xfer->rx_buf;
645 a3700_spi->buf_len = xfer->len;
646
647 /* SPI transfer headers */
648 a3700_spi_header_set(a3700_spi);
649
650 if (xfer->tx_buf)
651 nbits = xfer->tx_nbits;
652 else if (xfer->rx_buf)
653 nbits = xfer->rx_nbits;
654
655 a3700_spi_pin_mode_set(a3700_spi, nbits);
656
657 if (xfer->rx_buf) {
658 /* Set read data length */
659 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG,
660 a3700_spi->buf_len);
661 /* Start READ transfer */
662 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
663 val &= ~A3700_SPI_RW_EN;
664 val |= A3700_SPI_XFER_START;
665 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
666 } else if (xfer->tx_buf) {
667 /* Start Write transfer */
668 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
669 val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN);
670 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
671
672 /*
673 * If there are data to be written to the SPI device, xmit_data
674 * flag is set true; otherwise the instruction in SPI_INSTR does
675 * not require data to be written to the SPI device, then
676 * xmit_data flag is set false.
677 */
678 a3700_spi->xmit_data = (a3700_spi->buf_len != 0);
679 }
680
681 while (a3700_spi->buf_len) {
682 if (a3700_spi->tx_buf) {
683 /* Wait wfifo ready */
684 if (!a3700_spi_transfer_wait(spi,
685 A3700_SPI_WFIFO_RDY)) {
686 dev_err(&spi->dev,
687 "wait wfifo ready timed out\n");
688 ret = -ETIMEDOUT;
689 goto error;
690 }
691 /* Fill up the wfifo */
692 ret = a3700_spi_fifo_write(a3700_spi);
693 if (ret)
694 goto error;
695 } else if (a3700_spi->rx_buf) {
696 /* Wait rfifo ready */
697 if (!a3700_spi_transfer_wait(spi,
698 A3700_SPI_RFIFO_RDY)) {
699 dev_err(&spi->dev,
700 "wait rfifo ready timed out\n");
701 ret = -ETIMEDOUT;
702 goto error;
703 }
704 /* Drain out the rfifo */
705 ret = a3700_spi_fifo_read(a3700_spi);
706 if (ret)
707 goto error;
708 }
709 }
710
711 /*
712 * Stop a write transfer in fifo mode:
713 * - wait all the bytes in wfifo to be shifted out
714 * - set XFER_STOP bit
715 * - wait XFER_START bit clear
716 * - clear XFER_STOP bit
717 * Stop a read transfer in fifo mode:
718 * - the hardware is to reset the XFER_START bit
719 * after the number of bytes indicated in DIN_CNT
720 * register
721 * - just wait XFER_START bit clear
722 */
723 if (a3700_spi->tx_buf) {
724 if (a3700_spi->xmit_data) {
725 /*
726 * If there are data written to the SPI device, wait
727 * until SPI_WFIFO_EMPTY is 1 to wait for all data to
728 * transfer out of write FIFO.
729 */
730 if (!a3700_spi_transfer_wait(spi,
731 A3700_SPI_WFIFO_EMPTY)) {
732 dev_err(&spi->dev, "wait wfifo empty timed out\n");
733 return -ETIMEDOUT;
734 }
735 } else {
736 /*
737 * If the instruction in SPI_INSTR does not require data
738 * to be written to the SPI device, wait until SPI_RDY
739 * is 1 for the SPI interface to be in idle.
740 */
741 if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) {
742 dev_err(&spi->dev, "wait xfer ready timed out\n");
743 return -ETIMEDOUT;
744 }
745 }
746
747 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
748 val |= A3700_SPI_XFER_STOP;
749 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
750 }
751
752 while (--timeout) {
753 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
754 if (!(val & A3700_SPI_XFER_START))
755 break;
756 udelay(1);
757 }
758
759 if (timeout == 0) {
760 dev_err(&spi->dev, "wait transfer start clear timed out\n");
761 ret = -ETIMEDOUT;
762 goto error;
763 }
764
765 val &= ~A3700_SPI_XFER_STOP;
766 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
767 goto out;
768
769error:
770 a3700_spi_transfer_abort_fifo(a3700_spi);
771out:
772 spi_finalize_current_transfer(master);
773
774 return ret;
775}
776
777static int a3700_spi_unprepare_message(struct spi_master *master,
778 struct spi_message *message)
779{
780 struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
781
782 clk_disable(a3700_spi->clk);
783
784 return 0;
785}
786
787static const struct of_device_id a3700_spi_dt_ids[] = {
788 { .compatible = "marvell,armada-3700-spi", .data = NULL },
789 {},
790};
791
792MODULE_DEVICE_TABLE(of, a3700_spi_dt_ids);
793
794static int a3700_spi_probe(struct platform_device *pdev)
795{
796 struct device *dev = &pdev->dev;
797 struct device_node *of_node = dev->of_node;
798 struct resource *res;
799 struct spi_master *master;
800 struct a3700_spi *spi;
801 u32 num_cs = 0;
f6f0083c 802 int irq, ret = 0;
5762ab71
RP		 803
804 master = spi_alloc_master(dev, sizeof(*spi));
805 if (!master) {
806 dev_err(dev, "master allocation failed\n");
807 ret = -ENOMEM;
808 goto out;
809 }
810
811 if (of_property_read_u32(of_node, "num-cs", &num_cs)) {
812 dev_err(dev, "could not find num-cs\n");
813 ret = -ENXIO;
814 goto error;
815 }
816
817 master->bus_num = pdev->id;
818 master->dev.of_node = of_node;
819 master->mode_bits = SPI_MODE_3;
820 master->num_chipselect = num_cs;
821 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(32);
822 master->prepare_message = a3700_spi_prepare_message;
823 master->transfer_one = a3700_spi_transfer_one;
824 master->unprepare_message = a3700_spi_unprepare_message;
825 master->set_cs = a3700_spi_set_cs;
826 master->flags = SPI_MASTER_HALF_DUPLEX;
827 master->mode_bits |= (SPI_RX_DUAL | SPI_RX_DUAL |
828 SPI_RX_QUAD | SPI_TX_QUAD);
829
830 platform_set_drvdata(pdev, master);
831
832 spi = spi_master_get_devdata(master);
833 memset(spi, 0, sizeof(struct a3700_spi));
834
835 spi->master = master;
836 spi->instr_cnt = A3700_INSTR_CNT;
837 spi->addr_cnt = A3700_ADDR_CNT;
838 spi->hdr_cnt = A3700_INSTR_CNT + A3700_ADDR_CNT +
839 A3700_DUMMY_CNT;
840
841 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
842 spi->base = devm_ioremap_resource(dev, res);
843 if (IS_ERR(spi->base)) {
844 ret = PTR_ERR(spi->base);
845 goto error;
846 }
847
f6f0083c
CIK		 848 irq = platform_get_irq(pdev, 0);
849 if (irq < 0) {
850 dev_err(dev, "could not get irq: %d\n", irq);
5762ab71
RP		 851 ret = -ENXIO;
852 goto error;
853 }
f6f0083c 854 spi->irq = irq;
5762ab71
RP		 855
856 init_completion(&spi->done);
857
858 spi->clk = devm_clk_get(dev, NULL);
859 if (IS_ERR(spi->clk)) {
860 dev_err(dev, "could not find clk: %ld\n", PTR_ERR(spi->clk));
861 goto error;
862 }
863
864 ret = clk_prepare(spi->clk);
865 if (ret) {
866 dev_err(dev, "could not prepare clk: %d\n", ret);
867 goto error;
868 }
869
870 ret = a3700_spi_init(spi);
871 if (ret)
872 goto error_clk;
873
874 ret = devm_request_irq(dev, spi->irq, a3700_spi_interrupt, 0,
875 dev_name(dev), master);
876 if (ret) {
877 dev_err(dev, "could not request IRQ: %d\n", ret);
878 goto error_clk;
879 }
880
881 ret = devm_spi_register_master(dev, master);
882 if (ret) {
883 dev_err(dev, "Failed to register master\n");
884 goto error_clk;
885 }
886
887 return 0;
888
889error_clk:
890 clk_disable_unprepare(spi->clk);
891error:
892 spi_master_put(master);
893out:
894 return ret;
895}
896
897static int a3700_spi_remove(struct platform_device *pdev)
898{
899 struct spi_master *master = platform_get_drvdata(pdev);
900 struct a3700_spi *spi = spi_master_get_devdata(master);
901
902 clk_unprepare(spi->clk);
903 spi_master_put(master);
904
905 return 0;
906}
907
908static struct platform_driver a3700_spi_driver = {
909 .driver = {
910 .name = DRIVER_NAME,
911 .owner = THIS_MODULE,
912 .of_match_table = of_match_ptr(a3700_spi_dt_ids),
913 },
914 .probe = a3700_spi_probe,
915 .remove = a3700_spi_remove,
916};
917
918module_platform_driver(a3700_spi_driver);
919
920MODULE_DESCRIPTION("Armada-3700 SPI driver");
921MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>");
922MODULE_LICENSE("GPL");
923MODULE_ALIAS("platform:" DRIVER_NAME);
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