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5762ab71 RP |
1 | /* |
2 | * Marvell Armada-3700 SPI controller driver | |
3 | * | |
4 | * Copyright (C) 2016 Marvell Ltd. | |
5 | * | |
6 | * Author: Wilson Ding <dingwei@marvell.com> | |
7 | * Author: Romain Perier <romain.perier@free-electrons.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/completion.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_irq.h> | |
24 | #include <linux/of_device.h> | |
25 | #include <linux/pinctrl/consumer.h> | |
26 | #include <linux/spi/spi.h> | |
27 | ||
28 | #define DRIVER_NAME "armada_3700_spi" | |
29 | ||
30 | #define A3700_SPI_TIMEOUT 10 | |
31 | ||
32 | /* SPI Register Offest */ | |
33 | #define A3700_SPI_IF_CTRL_REG 0x00 | |
34 | #define A3700_SPI_IF_CFG_REG 0x04 | |
35 | #define A3700_SPI_DATA_OUT_REG 0x08 | |
36 | #define A3700_SPI_DATA_IN_REG 0x0C | |
37 | #define A3700_SPI_IF_INST_REG 0x10 | |
38 | #define A3700_SPI_IF_ADDR_REG 0x14 | |
39 | #define A3700_SPI_IF_RMODE_REG 0x18 | |
40 | #define A3700_SPI_IF_HDR_CNT_REG 0x1C | |
41 | #define A3700_SPI_IF_DIN_CNT_REG 0x20 | |
42 | #define A3700_SPI_IF_TIME_REG 0x24 | |
43 | #define A3700_SPI_INT_STAT_REG 0x28 | |
44 | #define A3700_SPI_INT_MASK_REG 0x2C | |
45 | ||
46 | /* A3700_SPI_IF_CTRL_REG */ | |
47 | #define A3700_SPI_EN BIT(16) | |
48 | #define A3700_SPI_ADDR_NOT_CONFIG BIT(12) | |
49 | #define A3700_SPI_WFIFO_OVERFLOW BIT(11) | |
50 | #define A3700_SPI_WFIFO_UNDERFLOW BIT(10) | |
51 | #define A3700_SPI_RFIFO_OVERFLOW BIT(9) | |
52 | #define A3700_SPI_RFIFO_UNDERFLOW BIT(8) | |
53 | #define A3700_SPI_WFIFO_FULL BIT(7) | |
54 | #define A3700_SPI_WFIFO_EMPTY BIT(6) | |
55 | #define A3700_SPI_RFIFO_FULL BIT(5) | |
56 | #define A3700_SPI_RFIFO_EMPTY BIT(4) | |
57 | #define A3700_SPI_WFIFO_RDY BIT(3) | |
58 | #define A3700_SPI_RFIFO_RDY BIT(2) | |
59 | #define A3700_SPI_XFER_RDY BIT(1) | |
60 | #define A3700_SPI_XFER_DONE BIT(0) | |
61 | ||
62 | /* A3700_SPI_IF_CFG_REG */ | |
63 | #define A3700_SPI_WFIFO_THRS BIT(28) | |
64 | #define A3700_SPI_RFIFO_THRS BIT(24) | |
65 | #define A3700_SPI_AUTO_CS BIT(20) | |
66 | #define A3700_SPI_DMA_RD_EN BIT(18) | |
67 | #define A3700_SPI_FIFO_MODE BIT(17) | |
68 | #define A3700_SPI_SRST BIT(16) | |
69 | #define A3700_SPI_XFER_START BIT(15) | |
70 | #define A3700_SPI_XFER_STOP BIT(14) | |
71 | #define A3700_SPI_INST_PIN BIT(13) | |
72 | #define A3700_SPI_ADDR_PIN BIT(12) | |
73 | #define A3700_SPI_DATA_PIN1 BIT(11) | |
74 | #define A3700_SPI_DATA_PIN0 BIT(10) | |
75 | #define A3700_SPI_FIFO_FLUSH BIT(9) | |
76 | #define A3700_SPI_RW_EN BIT(8) | |
77 | #define A3700_SPI_CLK_POL BIT(7) | |
78 | #define A3700_SPI_CLK_PHA BIT(6) | |
79 | #define A3700_SPI_BYTE_LEN BIT(5) | |
80 | #define A3700_SPI_CLK_PRESCALE BIT(0) | |
81 | #define A3700_SPI_CLK_PRESCALE_MASK (0x1f) | |
82 | ||
83 | #define A3700_SPI_WFIFO_THRS_BIT 28 | |
84 | #define A3700_SPI_RFIFO_THRS_BIT 24 | |
85 | #define A3700_SPI_FIFO_THRS_MASK 0x7 | |
86 | ||
87 | #define A3700_SPI_DATA_PIN_MASK 0x3 | |
88 | ||
89 | /* A3700_SPI_IF_HDR_CNT_REG */ | |
90 | #define A3700_SPI_DUMMY_CNT_BIT 12 | |
91 | #define A3700_SPI_DUMMY_CNT_MASK 0x7 | |
92 | #define A3700_SPI_RMODE_CNT_BIT 8 | |
93 | #define A3700_SPI_RMODE_CNT_MASK 0x3 | |
94 | #define A3700_SPI_ADDR_CNT_BIT 4 | |
95 | #define A3700_SPI_ADDR_CNT_MASK 0x7 | |
96 | #define A3700_SPI_INSTR_CNT_BIT 0 | |
97 | #define A3700_SPI_INSTR_CNT_MASK 0x3 | |
98 | ||
99 | /* A3700_SPI_IF_TIME_REG */ | |
100 | #define A3700_SPI_CLK_CAPT_EDGE BIT(7) | |
101 | ||
102 | /* Flags and macros for struct a3700_spi */ | |
103 | #define A3700_INSTR_CNT 1 | |
104 | #define A3700_ADDR_CNT 3 | |
105 | #define A3700_DUMMY_CNT 1 | |
106 | ||
107 | struct a3700_spi { | |
108 | struct spi_master *master; | |
109 | void __iomem *base; | |
110 | struct clk *clk; | |
111 | unsigned int irq; | |
112 | unsigned int flags; | |
113 | bool xmit_data; | |
114 | const u8 *tx_buf; | |
115 | u8 *rx_buf; | |
116 | size_t buf_len; | |
117 | u8 byte_len; | |
118 | u32 wait_mask; | |
119 | struct completion done; | |
120 | u32 addr_cnt; | |
121 | u32 instr_cnt; | |
122 | size_t hdr_cnt; | |
123 | }; | |
124 | ||
125 | static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset) | |
126 | { | |
127 | return readl(a3700_spi->base + offset); | |
128 | } | |
129 | ||
130 | static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data) | |
131 | { | |
132 | writel(data, a3700_spi->base + offset); | |
133 | } | |
134 | ||
135 | static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi) | |
136 | { | |
137 | u32 val; | |
138 | ||
139 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
140 | val &= ~A3700_SPI_AUTO_CS; | |
141 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
142 | } | |
143 | ||
144 | static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs) | |
145 | { | |
146 | u32 val; | |
147 | ||
148 | val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); | |
149 | val |= (A3700_SPI_EN << cs); | |
150 | spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); | |
151 | } | |
152 | ||
153 | static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi, | |
154 | unsigned int cs) | |
155 | { | |
156 | u32 val; | |
157 | ||
158 | val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); | |
159 | val &= ~(A3700_SPI_EN << cs); | |
160 | spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); | |
161 | } | |
162 | ||
163 | static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi, | |
164 | unsigned int pin_mode) | |
165 | { | |
166 | u32 val; | |
167 | ||
168 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
169 | val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN); | |
170 | val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1); | |
171 | ||
172 | switch (pin_mode) { | |
cfd6693c | 173 | case SPI_NBITS_SINGLE: |
5762ab71 | 174 | break; |
cfd6693c | 175 | case SPI_NBITS_DUAL: |
5762ab71 RP |
176 | val |= A3700_SPI_DATA_PIN0; |
177 | break; | |
cfd6693c | 178 | case SPI_NBITS_QUAD: |
5762ab71 RP |
179 | val |= A3700_SPI_DATA_PIN1; |
180 | break; | |
181 | default: | |
182 | dev_err(&a3700_spi->master->dev, "wrong pin mode %u", pin_mode); | |
183 | return -EINVAL; | |
184 | } | |
185 | ||
186 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi) | |
192 | { | |
193 | u32 val; | |
194 | ||
195 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
196 | val |= A3700_SPI_FIFO_MODE; | |
197 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
198 | } | |
199 | ||
200 | static void a3700_spi_mode_set(struct a3700_spi *a3700_spi, | |
201 | unsigned int mode_bits) | |
202 | { | |
203 | u32 val; | |
204 | ||
205 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
206 | ||
207 | if (mode_bits & SPI_CPOL) | |
208 | val |= A3700_SPI_CLK_POL; | |
209 | else | |
210 | val &= ~A3700_SPI_CLK_POL; | |
211 | ||
212 | if (mode_bits & SPI_CPHA) | |
213 | val |= A3700_SPI_CLK_PHA; | |
214 | else | |
215 | val &= ~A3700_SPI_CLK_PHA; | |
216 | ||
217 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
218 | } | |
219 | ||
220 | static void a3700_spi_clock_set(struct a3700_spi *a3700_spi, | |
221 | unsigned int speed_hz, u16 mode) | |
222 | { | |
223 | u32 val; | |
224 | u32 prescale; | |
225 | ||
226 | prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz); | |
227 | ||
228 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
229 | val = val & ~A3700_SPI_CLK_PRESCALE_MASK; | |
230 | ||
231 | val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK); | |
232 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
233 | ||
234 | if (prescale <= 2) { | |
235 | val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG); | |
236 | val |= A3700_SPI_CLK_CAPT_EDGE; | |
237 | spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val); | |
238 | } | |
239 | ||
240 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
241 | val &= ~(A3700_SPI_CLK_POL | A3700_SPI_CLK_PHA); | |
242 | ||
243 | if (mode & SPI_CPOL) | |
244 | val |= A3700_SPI_CLK_POL; | |
245 | ||
246 | if (mode & SPI_CPHA) | |
247 | val |= A3700_SPI_CLK_PHA; | |
248 | ||
249 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
250 | } | |
251 | ||
252 | static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len) | |
253 | { | |
254 | u32 val; | |
255 | ||
256 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
257 | if (len == 4) | |
258 | val |= A3700_SPI_BYTE_LEN; | |
259 | else | |
260 | val &= ~A3700_SPI_BYTE_LEN; | |
261 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
262 | ||
263 | a3700_spi->byte_len = len; | |
264 | } | |
265 | ||
266 | static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi) | |
267 | { | |
268 | int timeout = A3700_SPI_TIMEOUT; | |
269 | u32 val; | |
270 | ||
271 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
272 | val |= A3700_SPI_FIFO_FLUSH; | |
273 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
274 | ||
275 | while (--timeout) { | |
276 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
277 | if (!(val & A3700_SPI_FIFO_FLUSH)) | |
278 | return 0; | |
279 | udelay(1); | |
280 | } | |
281 | ||
282 | return -ETIMEDOUT; | |
283 | } | |
284 | ||
285 | static int a3700_spi_init(struct a3700_spi *a3700_spi) | |
286 | { | |
287 | struct spi_master *master = a3700_spi->master; | |
288 | u32 val; | |
289 | int i, ret = 0; | |
290 | ||
291 | /* Reset SPI unit */ | |
292 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
293 | val |= A3700_SPI_SRST; | |
294 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
295 | ||
296 | udelay(A3700_SPI_TIMEOUT); | |
297 | ||
298 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
299 | val &= ~A3700_SPI_SRST; | |
300 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
301 | ||
302 | /* Disable AUTO_CS and deactivate all chip-selects */ | |
303 | a3700_spi_auto_cs_unset(a3700_spi); | |
304 | for (i = 0; i < master->num_chipselect; i++) | |
305 | a3700_spi_deactivate_cs(a3700_spi, i); | |
306 | ||
307 | /* Enable FIFO mode */ | |
308 | a3700_spi_fifo_mode_set(a3700_spi); | |
309 | ||
310 | /* Set SPI mode */ | |
311 | a3700_spi_mode_set(a3700_spi, master->mode_bits); | |
312 | ||
313 | /* Reset counters */ | |
314 | spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); | |
315 | spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0); | |
316 | ||
317 | /* Mask the interrupts and clear cause bits */ | |
318 | spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); | |
319 | spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U); | |
320 | ||
321 | return ret; | |
322 | } | |
323 | ||
324 | static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id) | |
325 | { | |
326 | struct spi_master *master = dev_id; | |
327 | struct a3700_spi *a3700_spi; | |
328 | u32 cause; | |
329 | ||
330 | a3700_spi = spi_master_get_devdata(master); | |
331 | ||
332 | /* Get interrupt causes */ | |
333 | cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG); | |
334 | ||
335 | if (!cause || !(a3700_spi->wait_mask & cause)) | |
336 | return IRQ_NONE; | |
337 | ||
338 | /* mask and acknowledge the SPI interrupts */ | |
339 | spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); | |
340 | spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause); | |
341 | ||
342 | /* Wake up the transfer */ | |
0cc059ab | 343 | complete(&a3700_spi->done); |
5762ab71 RP |
344 | |
345 | return IRQ_HANDLED; | |
346 | } | |
347 | ||
348 | static bool a3700_spi_wait_completion(struct spi_device *spi) | |
349 | { | |
350 | struct a3700_spi *a3700_spi; | |
351 | unsigned int timeout; | |
352 | unsigned int ctrl_reg; | |
353 | unsigned long timeout_jiffies; | |
354 | ||
355 | a3700_spi = spi_master_get_devdata(spi->master); | |
356 | ||
357 | /* SPI interrupt is edge-triggered, which means an interrupt will | |
358 | * be generated only when detecting a specific status bit changed | |
359 | * from '0' to '1'. So when we start waiting for a interrupt, we | |
360 | * need to check status bit in control reg first, if it is already 1, | |
361 | * then we do not need to wait for interrupt | |
362 | */ | |
363 | ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); | |
364 | if (a3700_spi->wait_mask & ctrl_reg) | |
365 | return true; | |
366 | ||
367 | reinit_completion(&a3700_spi->done); | |
368 | ||
369 | spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, | |
370 | a3700_spi->wait_mask); | |
371 | ||
372 | timeout_jiffies = msecs_to_jiffies(A3700_SPI_TIMEOUT); | |
373 | timeout = wait_for_completion_timeout(&a3700_spi->done, | |
374 | timeout_jiffies); | |
375 | ||
376 | a3700_spi->wait_mask = 0; | |
377 | ||
378 | if (timeout) | |
379 | return true; | |
380 | ||
381 | /* there might be the case that right after we checked the | |
382 | * status bits in this routine and before start to wait for | |
383 | * interrupt by wait_for_completion_timeout, the interrupt | |
384 | * happens, to avoid missing it we need to double check | |
385 | * status bits in control reg, if it is already 1, then | |
386 | * consider that we have the interrupt successfully and | |
387 | * return true. | |
388 | */ | |
389 | ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); | |
390 | if (a3700_spi->wait_mask & ctrl_reg) | |
391 | return true; | |
392 | ||
393 | spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); | |
394 | ||
395 | return true; | |
396 | } | |
397 | ||
398 | static bool a3700_spi_transfer_wait(struct spi_device *spi, | |
399 | unsigned int bit_mask) | |
400 | { | |
401 | struct a3700_spi *a3700_spi; | |
402 | ||
403 | a3700_spi = spi_master_get_devdata(spi->master); | |
404 | a3700_spi->wait_mask = bit_mask; | |
405 | ||
406 | return a3700_spi_wait_completion(spi); | |
407 | } | |
408 | ||
409 | static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi, | |
410 | unsigned int bytes) | |
411 | { | |
412 | u32 val; | |
413 | ||
414 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
415 | val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT); | |
416 | val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT; | |
417 | val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT); | |
418 | val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT; | |
419 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
420 | } | |
421 | ||
422 | static void a3700_spi_transfer_setup(struct spi_device *spi, | |
85798e15 | 423 | struct spi_transfer *xfer) |
5762ab71 RP |
424 | { |
425 | struct a3700_spi *a3700_spi; | |
426 | unsigned int byte_len; | |
427 | ||
428 | a3700_spi = spi_master_get_devdata(spi->master); | |
429 | ||
430 | a3700_spi_clock_set(a3700_spi, xfer->speed_hz, spi->mode); | |
431 | ||
432 | byte_len = xfer->bits_per_word >> 3; | |
433 | ||
434 | a3700_spi_fifo_thres_set(a3700_spi, byte_len); | |
435 | } | |
436 | ||
437 | static void a3700_spi_set_cs(struct spi_device *spi, bool enable) | |
438 | { | |
439 | struct a3700_spi *a3700_spi = spi_master_get_devdata(spi->master); | |
440 | ||
441 | if (!enable) | |
442 | a3700_spi_activate_cs(a3700_spi, spi->chip_select); | |
443 | else | |
444 | a3700_spi_deactivate_cs(a3700_spi, spi->chip_select); | |
445 | } | |
446 | ||
447 | static void a3700_spi_header_set(struct a3700_spi *a3700_spi) | |
448 | { | |
449 | u32 instr_cnt = 0, addr_cnt = 0, dummy_cnt = 0; | |
450 | u32 val = 0; | |
451 | ||
452 | /* Clear the header registers */ | |
453 | spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0); | |
454 | spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0); | |
455 | spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0); | |
456 | ||
457 | /* Set header counters */ | |
458 | if (a3700_spi->tx_buf) { | |
459 | if (a3700_spi->buf_len <= a3700_spi->instr_cnt) { | |
460 | instr_cnt = a3700_spi->buf_len; | |
461 | } else if (a3700_spi->buf_len <= (a3700_spi->instr_cnt + | |
462 | a3700_spi->addr_cnt)) { | |
463 | instr_cnt = a3700_spi->instr_cnt; | |
464 | addr_cnt = a3700_spi->buf_len - instr_cnt; | |
465 | } else if (a3700_spi->buf_len <= a3700_spi->hdr_cnt) { | |
466 | instr_cnt = a3700_spi->instr_cnt; | |
467 | addr_cnt = a3700_spi->addr_cnt; | |
468 | /* Need to handle the normal write case with 1 byte | |
469 | * data | |
470 | */ | |
471 | if (!a3700_spi->tx_buf[instr_cnt + addr_cnt]) | |
472 | dummy_cnt = a3700_spi->buf_len - instr_cnt - | |
473 | addr_cnt; | |
474 | } | |
475 | val |= ((instr_cnt & A3700_SPI_INSTR_CNT_MASK) | |
476 | << A3700_SPI_INSTR_CNT_BIT); | |
477 | val |= ((addr_cnt & A3700_SPI_ADDR_CNT_MASK) | |
478 | << A3700_SPI_ADDR_CNT_BIT); | |
479 | val |= ((dummy_cnt & A3700_SPI_DUMMY_CNT_MASK) | |
480 | << A3700_SPI_DUMMY_CNT_BIT); | |
481 | } | |
482 | spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val); | |
483 | ||
484 | /* Update the buffer length to be transferred */ | |
485 | a3700_spi->buf_len -= (instr_cnt + addr_cnt + dummy_cnt); | |
486 | ||
487 | /* Set Instruction */ | |
488 | val = 0; | |
489 | while (instr_cnt--) { | |
490 | val = (val << 8) | a3700_spi->tx_buf[0]; | |
491 | a3700_spi->tx_buf++; | |
492 | } | |
493 | spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, val); | |
494 | ||
495 | /* Set Address */ | |
496 | val = 0; | |
497 | while (addr_cnt--) { | |
498 | val = (val << 8) | a3700_spi->tx_buf[0]; | |
499 | a3700_spi->tx_buf++; | |
500 | } | |
501 | spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val); | |
502 | } | |
503 | ||
504 | static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi) | |
505 | { | |
506 | u32 val; | |
507 | ||
508 | val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); | |
509 | return (val & A3700_SPI_WFIFO_FULL); | |
510 | } | |
511 | ||
512 | static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi) | |
513 | { | |
514 | u32 val; | |
515 | int i = 0; | |
516 | ||
517 | while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) { | |
518 | val = 0; | |
519 | if (a3700_spi->buf_len >= 4) { | |
520 | val = cpu_to_le32(*(u32 *)a3700_spi->tx_buf); | |
521 | spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); | |
522 | ||
523 | a3700_spi->buf_len -= 4; | |
524 | a3700_spi->tx_buf += 4; | |
525 | } else { | |
526 | /* | |
527 | * If the remained buffer length is less than 4-bytes, | |
528 | * we should pad the write buffer with all ones. So that | |
529 | * it avoids overwrite the unexpected bytes following | |
530 | * the last one. | |
531 | */ | |
532 | val = GENMASK(31, 0); | |
533 | while (a3700_spi->buf_len) { | |
534 | val &= ~(0xff << (8 * i)); | |
535 | val |= *a3700_spi->tx_buf++ << (8 * i); | |
536 | i++; | |
537 | a3700_spi->buf_len--; | |
538 | ||
539 | spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, | |
540 | val); | |
541 | } | |
542 | break; | |
543 | } | |
544 | } | |
545 | ||
546 | return 0; | |
547 | } | |
548 | ||
549 | static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi) | |
550 | { | |
551 | u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); | |
552 | ||
553 | return (val & A3700_SPI_RFIFO_EMPTY); | |
554 | } | |
555 | ||
556 | static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi) | |
557 | { | |
558 | u32 val; | |
559 | ||
560 | while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) { | |
561 | val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); | |
562 | if (a3700_spi->buf_len >= 4) { | |
563 | u32 data = le32_to_cpu(val); | |
85798e15 | 564 | |
5762ab71 RP |
565 | memcpy(a3700_spi->rx_buf, &data, 4); |
566 | ||
567 | a3700_spi->buf_len -= 4; | |
568 | a3700_spi->rx_buf += 4; | |
569 | } else { | |
570 | /* | |
571 | * When remain bytes is not larger than 4, we should | |
572 | * avoid memory overwriting and just write the left rx | |
573 | * buffer bytes. | |
574 | */ | |
575 | while (a3700_spi->buf_len) { | |
576 | *a3700_spi->rx_buf = val & 0xff; | |
577 | val >>= 8; | |
578 | ||
579 | a3700_spi->buf_len--; | |
580 | a3700_spi->rx_buf++; | |
581 | } | |
582 | } | |
583 | } | |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
588 | static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi) | |
589 | { | |
590 | int timeout = A3700_SPI_TIMEOUT; | |
591 | u32 val; | |
592 | ||
593 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
594 | val |= A3700_SPI_XFER_STOP; | |
595 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
596 | ||
597 | while (--timeout) { | |
598 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
599 | if (!(val & A3700_SPI_XFER_START)) | |
600 | break; | |
601 | udelay(1); | |
602 | } | |
603 | ||
604 | a3700_spi_fifo_flush(a3700_spi); | |
605 | ||
606 | val &= ~A3700_SPI_XFER_STOP; | |
607 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
608 | } | |
609 | ||
610 | static int a3700_spi_prepare_message(struct spi_master *master, | |
611 | struct spi_message *message) | |
612 | { | |
613 | struct a3700_spi *a3700_spi = spi_master_get_devdata(master); | |
614 | struct spi_device *spi = message->spi; | |
615 | int ret; | |
616 | ||
617 | ret = clk_enable(a3700_spi->clk); | |
618 | if (ret) { | |
619 | dev_err(&spi->dev, "failed to enable clk with error %d\n", ret); | |
620 | return ret; | |
621 | } | |
622 | ||
623 | /* Flush the FIFOs */ | |
624 | ret = a3700_spi_fifo_flush(a3700_spi); | |
625 | if (ret) | |
626 | return ret; | |
627 | ||
628 | a3700_spi_bytelen_set(a3700_spi, 4); | |
629 | ||
630 | return 0; | |
631 | } | |
632 | ||
633 | static int a3700_spi_transfer_one(struct spi_master *master, | |
634 | struct spi_device *spi, | |
635 | struct spi_transfer *xfer) | |
636 | { | |
637 | struct a3700_spi *a3700_spi = spi_master_get_devdata(master); | |
638 | int ret = 0, timeout = A3700_SPI_TIMEOUT; | |
639 | unsigned int nbits = 0; | |
640 | u32 val; | |
641 | ||
642 | a3700_spi_transfer_setup(spi, xfer); | |
643 | ||
644 | a3700_spi->tx_buf = xfer->tx_buf; | |
645 | a3700_spi->rx_buf = xfer->rx_buf; | |
646 | a3700_spi->buf_len = xfer->len; | |
647 | ||
648 | /* SPI transfer headers */ | |
649 | a3700_spi_header_set(a3700_spi); | |
650 | ||
651 | if (xfer->tx_buf) | |
652 | nbits = xfer->tx_nbits; | |
653 | else if (xfer->rx_buf) | |
654 | nbits = xfer->rx_nbits; | |
655 | ||
656 | a3700_spi_pin_mode_set(a3700_spi, nbits); | |
657 | ||
658 | if (xfer->rx_buf) { | |
659 | /* Set read data length */ | |
660 | spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, | |
661 | a3700_spi->buf_len); | |
662 | /* Start READ transfer */ | |
663 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
664 | val &= ~A3700_SPI_RW_EN; | |
665 | val |= A3700_SPI_XFER_START; | |
666 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
667 | } else if (xfer->tx_buf) { | |
668 | /* Start Write transfer */ | |
669 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
670 | val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN); | |
671 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
672 | ||
673 | /* | |
674 | * If there are data to be written to the SPI device, xmit_data | |
675 | * flag is set true; otherwise the instruction in SPI_INSTR does | |
676 | * not require data to be written to the SPI device, then | |
677 | * xmit_data flag is set false. | |
678 | */ | |
679 | a3700_spi->xmit_data = (a3700_spi->buf_len != 0); | |
680 | } | |
681 | ||
682 | while (a3700_spi->buf_len) { | |
683 | if (a3700_spi->tx_buf) { | |
684 | /* Wait wfifo ready */ | |
685 | if (!a3700_spi_transfer_wait(spi, | |
686 | A3700_SPI_WFIFO_RDY)) { | |
687 | dev_err(&spi->dev, | |
688 | "wait wfifo ready timed out\n"); | |
689 | ret = -ETIMEDOUT; | |
690 | goto error; | |
691 | } | |
692 | /* Fill up the wfifo */ | |
693 | ret = a3700_spi_fifo_write(a3700_spi); | |
694 | if (ret) | |
695 | goto error; | |
696 | } else if (a3700_spi->rx_buf) { | |
697 | /* Wait rfifo ready */ | |
698 | if (!a3700_spi_transfer_wait(spi, | |
699 | A3700_SPI_RFIFO_RDY)) { | |
700 | dev_err(&spi->dev, | |
701 | "wait rfifo ready timed out\n"); | |
702 | ret = -ETIMEDOUT; | |
703 | goto error; | |
704 | } | |
705 | /* Drain out the rfifo */ | |
706 | ret = a3700_spi_fifo_read(a3700_spi); | |
707 | if (ret) | |
708 | goto error; | |
709 | } | |
710 | } | |
711 | ||
712 | /* | |
713 | * Stop a write transfer in fifo mode: | |
714 | * - wait all the bytes in wfifo to be shifted out | |
715 | * - set XFER_STOP bit | |
716 | * - wait XFER_START bit clear | |
717 | * - clear XFER_STOP bit | |
718 | * Stop a read transfer in fifo mode: | |
719 | * - the hardware is to reset the XFER_START bit | |
720 | * after the number of bytes indicated in DIN_CNT | |
721 | * register | |
722 | * - just wait XFER_START bit clear | |
723 | */ | |
724 | if (a3700_spi->tx_buf) { | |
725 | if (a3700_spi->xmit_data) { | |
726 | /* | |
727 | * If there are data written to the SPI device, wait | |
728 | * until SPI_WFIFO_EMPTY is 1 to wait for all data to | |
729 | * transfer out of write FIFO. | |
730 | */ | |
731 | if (!a3700_spi_transfer_wait(spi, | |
732 | A3700_SPI_WFIFO_EMPTY)) { | |
733 | dev_err(&spi->dev, "wait wfifo empty timed out\n"); | |
734 | return -ETIMEDOUT; | |
735 | } | |
736 | } else { | |
737 | /* | |
738 | * If the instruction in SPI_INSTR does not require data | |
739 | * to be written to the SPI device, wait until SPI_RDY | |
740 | * is 1 for the SPI interface to be in idle. | |
741 | */ | |
742 | if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) { | |
743 | dev_err(&spi->dev, "wait xfer ready timed out\n"); | |
744 | return -ETIMEDOUT; | |
745 | } | |
746 | } | |
747 | ||
748 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
749 | val |= A3700_SPI_XFER_STOP; | |
750 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
751 | } | |
752 | ||
753 | while (--timeout) { | |
754 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
755 | if (!(val & A3700_SPI_XFER_START)) | |
756 | break; | |
757 | udelay(1); | |
758 | } | |
759 | ||
760 | if (timeout == 0) { | |
761 | dev_err(&spi->dev, "wait transfer start clear timed out\n"); | |
762 | ret = -ETIMEDOUT; | |
763 | goto error; | |
764 | } | |
765 | ||
766 | val &= ~A3700_SPI_XFER_STOP; | |
767 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
768 | goto out; | |
769 | ||
770 | error: | |
771 | a3700_spi_transfer_abort_fifo(a3700_spi); | |
772 | out: | |
773 | spi_finalize_current_transfer(master); | |
774 | ||
775 | return ret; | |
776 | } | |
777 | ||
778 | static int a3700_spi_unprepare_message(struct spi_master *master, | |
779 | struct spi_message *message) | |
780 | { | |
781 | struct a3700_spi *a3700_spi = spi_master_get_devdata(master); | |
782 | ||
783 | clk_disable(a3700_spi->clk); | |
784 | ||
785 | return 0; | |
786 | } | |
787 | ||
788 | static const struct of_device_id a3700_spi_dt_ids[] = { | |
789 | { .compatible = "marvell,armada-3700-spi", .data = NULL }, | |
790 | {}, | |
791 | }; | |
792 | ||
793 | MODULE_DEVICE_TABLE(of, a3700_spi_dt_ids); | |
794 | ||
795 | static int a3700_spi_probe(struct platform_device *pdev) | |
796 | { | |
797 | struct device *dev = &pdev->dev; | |
798 | struct device_node *of_node = dev->of_node; | |
799 | struct resource *res; | |
800 | struct spi_master *master; | |
801 | struct a3700_spi *spi; | |
802 | u32 num_cs = 0; | |
f6f0083c | 803 | int irq, ret = 0; |
5762ab71 RP |
804 | |
805 | master = spi_alloc_master(dev, sizeof(*spi)); | |
806 | if (!master) { | |
807 | dev_err(dev, "master allocation failed\n"); | |
808 | ret = -ENOMEM; | |
809 | goto out; | |
810 | } | |
811 | ||
812 | if (of_property_read_u32(of_node, "num-cs", &num_cs)) { | |
813 | dev_err(dev, "could not find num-cs\n"); | |
814 | ret = -ENXIO; | |
815 | goto error; | |
816 | } | |
817 | ||
818 | master->bus_num = pdev->id; | |
819 | master->dev.of_node = of_node; | |
820 | master->mode_bits = SPI_MODE_3; | |
821 | master->num_chipselect = num_cs; | |
822 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(32); | |
823 | master->prepare_message = a3700_spi_prepare_message; | |
824 | master->transfer_one = a3700_spi_transfer_one; | |
825 | master->unprepare_message = a3700_spi_unprepare_message; | |
826 | master->set_cs = a3700_spi_set_cs; | |
827 | master->flags = SPI_MASTER_HALF_DUPLEX; | |
828 | master->mode_bits |= (SPI_RX_DUAL | SPI_RX_DUAL | | |
829 | SPI_RX_QUAD | SPI_TX_QUAD); | |
830 | ||
831 | platform_set_drvdata(pdev, master); | |
832 | ||
833 | spi = spi_master_get_devdata(master); | |
834 | memset(spi, 0, sizeof(struct a3700_spi)); | |
835 | ||
836 | spi->master = master; | |
837 | spi->instr_cnt = A3700_INSTR_CNT; | |
838 | spi->addr_cnt = A3700_ADDR_CNT; | |
839 | spi->hdr_cnt = A3700_INSTR_CNT + A3700_ADDR_CNT + | |
840 | A3700_DUMMY_CNT; | |
841 | ||
842 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
843 | spi->base = devm_ioremap_resource(dev, res); | |
844 | if (IS_ERR(spi->base)) { | |
845 | ret = PTR_ERR(spi->base); | |
846 | goto error; | |
847 | } | |
848 | ||
f6f0083c CIK |
849 | irq = platform_get_irq(pdev, 0); |
850 | if (irq < 0) { | |
851 | dev_err(dev, "could not get irq: %d\n", irq); | |
5762ab71 RP |
852 | ret = -ENXIO; |
853 | goto error; | |
854 | } | |
f6f0083c | 855 | spi->irq = irq; |
5762ab71 RP |
856 | |
857 | init_completion(&spi->done); | |
858 | ||
859 | spi->clk = devm_clk_get(dev, NULL); | |
860 | if (IS_ERR(spi->clk)) { | |
861 | dev_err(dev, "could not find clk: %ld\n", PTR_ERR(spi->clk)); | |
862 | goto error; | |
863 | } | |
864 | ||
865 | ret = clk_prepare(spi->clk); | |
866 | if (ret) { | |
867 | dev_err(dev, "could not prepare clk: %d\n", ret); | |
868 | goto error; | |
869 | } | |
870 | ||
871 | ret = a3700_spi_init(spi); | |
872 | if (ret) | |
873 | goto error_clk; | |
874 | ||
875 | ret = devm_request_irq(dev, spi->irq, a3700_spi_interrupt, 0, | |
876 | dev_name(dev), master); | |
877 | if (ret) { | |
878 | dev_err(dev, "could not request IRQ: %d\n", ret); | |
879 | goto error_clk; | |
880 | } | |
881 | ||
882 | ret = devm_spi_register_master(dev, master); | |
883 | if (ret) { | |
884 | dev_err(dev, "Failed to register master\n"); | |
885 | goto error_clk; | |
886 | } | |
887 | ||
888 | return 0; | |
889 | ||
890 | error_clk: | |
891 | clk_disable_unprepare(spi->clk); | |
892 | error: | |
893 | spi_master_put(master); | |
894 | out: | |
895 | return ret; | |
896 | } | |
897 | ||
898 | static int a3700_spi_remove(struct platform_device *pdev) | |
899 | { | |
900 | struct spi_master *master = platform_get_drvdata(pdev); | |
901 | struct a3700_spi *spi = spi_master_get_devdata(master); | |
902 | ||
903 | clk_unprepare(spi->clk); | |
5762ab71 RP |
904 | |
905 | return 0; | |
906 | } | |
907 | ||
908 | static struct platform_driver a3700_spi_driver = { | |
909 | .driver = { | |
910 | .name = DRIVER_NAME, | |
5762ab71 RP |
911 | .of_match_table = of_match_ptr(a3700_spi_dt_ids), |
912 | }, | |
913 | .probe = a3700_spi_probe, | |
914 | .remove = a3700_spi_remove, | |
915 | }; | |
916 | ||
917 | module_platform_driver(a3700_spi_driver); | |
918 | ||
919 | MODULE_DESCRIPTION("Armada-3700 SPI driver"); | |
920 | MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>"); | |
921 | MODULE_LICENSE("GPL"); | |
922 | MODULE_ALIAS("platform:" DRIVER_NAME); |