[mirror_ubuntu-zesty-kernel.git] / drivers / spi / spi-ath79.c

/*
 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
 *
 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 *
 * This driver has been based on the spi-gpio.c:
 *	Copyright (C) 2006,2008 David Brownell
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/clk.h>
#include <linux/err.h>

#include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ath79_spi_platform.h>

#define DRV_NAME	"ath79-spi"

#define ATH79_SPI_RRW_DELAY_FACTOR	12000
#define MHZ				(1000 * 1000)

struct ath79_spi {
	struct spi_bitbang	bitbang;
	u32			ioc_base;
	u32			reg_ctrl;
	void __iomem		*base;
	struct clk		*clk;
	unsigned		rrw_delay;
};

static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
{
	return ioread32(sp->base + reg);
}

static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)
{
	iowrite32(val, sp->base + reg);
}

static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
{
	return spi_master_get_devdata(spi->master);
}

static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
{
	if (nsecs > sp->rrw_delay)
		ndelay(nsecs - sp->rrw_delay);
}

static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
{
	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;

	if (is_active) {
		/* set initial clock polarity */
		if (spi->mode & SPI_CPOL)
			sp->ioc_base |= AR71XX_SPI_IOC_CLK;
		else
			sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;

		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
	}

	if (spi->chip_select) {
		struct ath79_spi_controller_data *cdata = spi->controller_data;

		/* SPI is normally active-low */
		gpio_set_value(cdata->gpio, cs_high);
	} else {
		if (cs_high)
			sp->ioc_base |= AR71XX_SPI_IOC_CS0;
		else
			sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;

		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
	}

}

static void ath79_spi_enable(struct ath79_spi *sp)
{
	/* enable GPIO mode */
	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);

	/* save CTRL register */
	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);

	/* TODO: setup speed? */
	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
}

static void ath79_spi_disable(struct ath79_spi *sp)
{
	/* restore CTRL register */
	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
	/* disable GPIO mode */
	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
}

static int ath79_spi_setup_cs(struct spi_device *spi)
{
	struct ath79_spi_controller_data *cdata;
	int status;

	cdata = spi->controller_data;
	if (spi->chip_select && !cdata)
		return -EINVAL;

	status = 0;
	if (spi->chip_select) {
		unsigned long flags;

		flags = GPIOF_DIR_OUT;
		if (spi->mode & SPI_CS_HIGH)
			flags |= GPIOF_INIT_LOW;
		else
			flags |= GPIOF_INIT_HIGH;

		status = gpio_request_one(cdata->gpio, flags,
					  dev_name(&spi->dev));
	}

	return status;
}

static void ath79_spi_cleanup_cs(struct spi_device *spi)
{
	if (spi->chip_select) {
		struct ath79_spi_controller_data *cdata = spi->controller_data;
		gpio_free(cdata->gpio);
	}
}

static int ath79_spi_setup(struct spi_device *spi)
{
	int status = 0;

	if (!spi->controller_state) {
		status = ath79_spi_setup_cs(spi);
		if (status)
			return status;
	}

	status = spi_bitbang_setup(spi);
	if (status && !spi->controller_state)
		ath79_spi_cleanup_cs(spi);

	return status;
}

static void ath79_spi_cleanup(struct spi_device *spi)
{
	ath79_spi_cleanup_cs(spi);
	spi_bitbang_cleanup(spi);
}

static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs,
			       u32 word, u8 bits)
{
	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	u32 ioc = sp->ioc_base;

	/* clock starts at inactive polarity */
	for (word <<= (32 - bits); likely(bits); bits--) {
		u32 out;

		if (word & (1 << 31))
			out = ioc | AR71XX_SPI_IOC_DO;
		else
			out = ioc & ~AR71XX_SPI_IOC_DO;

		/* setup MSB (to slave) on trailing edge */
		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
		ath79_spi_delay(sp, nsecs);
		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
		ath79_spi_delay(sp, nsecs);
		if (bits == 1)
			ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);

		word <<= 1;
	}

	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
}

static int ath79_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct ath79_spi *sp;
	struct ath79_spi_platform_data *pdata;
	struct resource	*r;
	unsigned long rate;
	int ret;

	master = spi_alloc_master(&pdev->dev, sizeof(*sp));
	if (master == NULL) {
		dev_err(&pdev->dev, "failed to allocate spi master\n");
		return -ENOMEM;
	}

	sp = spi_master_get_devdata(master);
	platform_set_drvdata(pdev, sp);

	pdata = dev_get_platdata(&pdev->dev);

	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
	master->setup = ath79_spi_setup;
	master->cleanup = ath79_spi_cleanup;
	if (pdata) {
		master->bus_num = pdata->bus_num;
		master->num_chipselect = pdata->num_chipselect;
	}

	sp->bitbang.master = master;
	sp->bitbang.chipselect = ath79_spi_chipselect;
	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
	sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
	sp->bitbang.flags = SPI_CS_HIGH;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (r == NULL) {
		ret = -ENOENT;
		goto err_put_master;
	}

	sp->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
	if (!sp->base) {
		ret = -ENXIO;
		goto err_put_master;
	}

	sp->clk = devm_clk_get(&pdev->dev, "ahb");
	if (IS_ERR(sp->clk)) {
		ret = PTR_ERR(sp->clk);
		goto err_put_master;
	}

	ret = clk_enable(sp->clk);
	if (ret)
		goto err_put_master;

	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
	if (!rate) {
		ret = -EINVAL;
		goto err_clk_disable;
	}

	sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
		sp->rrw_delay);

	ath79_spi_enable(sp);
	ret = spi_bitbang_start(&sp->bitbang);
	if (ret)
		goto err_disable;

	return 0;

err_disable:
	ath79_spi_disable(sp);
err_clk_disable:
	clk_disable(sp->clk);
err_put_master:
	spi_master_put(sp->bitbang.master);

	return ret;
}

static int ath79_spi_remove(struct platform_device *pdev)
{
	struct ath79_spi *sp = platform_get_drvdata(pdev);

	spi_bitbang_stop(&sp->bitbang);
	ath79_spi_disable(sp);
	clk_disable(sp->clk);
	spi_master_put(sp->bitbang.master);

	return 0;
}

static void ath79_spi_shutdown(struct platform_device *pdev)
{
	ath79_spi_remove(pdev);
}

static struct platform_driver ath79_spi_driver = {
	.probe		= ath79_spi_probe,
	.remove		= ath79_spi_remove,
	.shutdown	= ath79_spi_shutdown,
	.driver		= {
		.name	= DRV_NAME,
		.owner	= THIS_MODULE,
	},
};
module_platform_driver(ath79_spi_driver);

MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
8efaef4d GJ	1	/*
	2	* SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
	3	*
	4	* Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
	5	*
	6	* This driver has been based on the spi-gpio.c:
	7	* Copyright (C) 2006,2008 David Brownell
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	*/
	14
	15	#include <linux/kernel.h>
807cc4b1	16	#include <linux/module.h>
8efaef4d GJ	17	#include <linux/delay.h>
	18	#include <linux/spinlock.h>
	19	#include <linux/workqueue.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/io.h>
	22	#include <linux/spi/spi.h>
	23	#include <linux/spi/spi_bitbang.h>
	24	#include <linux/bitops.h>
	25	#include <linux/gpio.h>
440114fd GJ	26	#include <linux/clk.h>
440114fd GJ	27	#include <linux/err.h>
8efaef4d GJ	28
	29	#include <asm/mach-ath79/ar71xx_regs.h>
	30	#include <asm/mach-ath79/ath79_spi_platform.h>
	31
	32	#define DRV_NAME "ath79-spi"
	33
440114fd GJ	34	#define ATH79_SPI_RRW_DELAY_FACTOR 12000
	35	#define MHZ (1000 * 1000)
	36
8efaef4d GJ	37	struct ath79_spi {
	38	struct spi_bitbang bitbang;
	39	u32 ioc_base;
	40	u32 reg_ctrl;
	41	void __iomem *base;
440114fd GJ	42	struct clk *clk;
440114fd GJ	43	unsigned rrw_delay;
8efaef4d GJ	44	};
	45
	46	static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
	47	{
	48	return ioread32(sp->base + reg);
	49	}
	50
	51	static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)
	52	{
	53	iowrite32(val, sp->base + reg);
	54	}
	55
	56	static inline struct ath79_spi ath79_spidev_to_sp(struct spi_device spi)
	57	{
	58	return spi_master_get_devdata(spi->master);
	59	}
	60
440114fd GJ	61	static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
	62	{
	63	if (nsecs > sp->rrw_delay)
	64	ndelay(nsecs - sp->rrw_delay);
	65	}
	66
8efaef4d GJ	67	static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
	68	{
	69	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	70	int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
	71
	72	if (is_active) {
	73	/* set initial clock polarity */
	74	if (spi->mode & SPI_CPOL)
	75	sp->ioc_base \|= AR71XX_SPI_IOC_CLK;
	76	else
	77	sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;
	78
	79	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
	80	}
	81
	82	if (spi->chip_select) {
	83	struct ath79_spi_controller_data *cdata = spi->controller_data;
	84
	85	/* SPI is normally active-low */
	86	gpio_set_value(cdata->gpio, cs_high);
	87	} else {
	88	if (cs_high)
	89	sp->ioc_base \|= AR71XX_SPI_IOC_CS0;
	90	else
	91	sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
	92
	93	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
	94	}
	95
	96	}
	97
c4a31f43	98	static void ath79_spi_enable(struct ath79_spi *sp)
8efaef4d	99	{
8efaef4d GJ	100	/* enable GPIO mode */
	101	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
	102
	103	/* save CTRL register */
	104	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
	105	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
	106
	107	/* TODO: setup speed? */
	108	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
c4a31f43 GJ	109	}
	110
	111	static void ath79_spi_disable(struct ath79_spi *sp)
	112	{
	113	/* restore CTRL register */
	114	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
	115	/* disable GPIO mode */
	116	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
	117	}
	118
	119	static int ath79_spi_setup_cs(struct spi_device *spi)
	120	{
	121	struct ath79_spi_controller_data *cdata;
	122	int status;
	123
	124	cdata = spi->controller_data;
	125	if (spi->chip_select && !cdata)
	126	return -EINVAL;
8efaef4d	127
95d79419	128	status = 0;
8efaef4d	129	if (spi->chip_select) {
95d79419 GJ	130	unsigned long flags;
	131
	132	flags = GPIOF_DIR_OUT;
	133	if (spi->mode & SPI_CS_HIGH)
95d79419	134	flags \|= GPIOF_INIT_LOW;
61d1cf16 GJ	135	else
61d1cf16 GJ	136	flags \|= GPIOF_INIT_HIGH;
95d79419 GJ	137
	138	status = gpio_request_one(cdata->gpio, flags,
	139	dev_name(&spi->dev));
8efaef4d GJ	140	}
8efaef4d GJ	141
95d79419	142	return status;
8efaef4d GJ	143	}
	144
	145	static void ath79_spi_cleanup_cs(struct spi_device *spi)
	146	{
8efaef4d GJ	147	if (spi->chip_select) {
	148	struct ath79_spi_controller_data *cdata = spi->controller_data;
	149	gpio_free(cdata->gpio);
	150	}
8efaef4d GJ	151	}
	152
	153	static int ath79_spi_setup(struct spi_device *spi)
	154	{
	155	int status = 0;
	156
8efaef4d GJ	157	if (!spi->controller_state) {
	158	status = ath79_spi_setup_cs(spi);
	159	if (status)
	160	return status;
	161	}
	162
	163	status = spi_bitbang_setup(spi);
	164	if (status && !spi->controller_state)
	165	ath79_spi_cleanup_cs(spi);
	166
	167	return status;
	168	}
	169
	170	static void ath79_spi_cleanup(struct spi_device *spi)
	171	{
	172	ath79_spi_cleanup_cs(spi);
	173	spi_bitbang_cleanup(spi);
	174	}
	175
	176	static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs,
	177	u32 word, u8 bits)
	178	{
	179	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	180	u32 ioc = sp->ioc_base;
	181
	182	/* clock starts at inactive polarity */
	183	for (word <<= (32 - bits); likely(bits); bits--) {
	184	u32 out;
	185
	186	if (word & (1 << 31))
	187	out = ioc \| AR71XX_SPI_IOC_DO;
	188	else
	189	out = ioc & ~AR71XX_SPI_IOC_DO;
	190
	191	/* setup MSB (to slave) on trailing edge */
	192	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
440114fd	193	ath79_spi_delay(sp, nsecs);
8efaef4d	194	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out \| AR71XX_SPI_IOC_CLK);
440114fd	195	ath79_spi_delay(sp, nsecs);
72611db0 GJ	196	if (bits == 1)
72611db0 GJ	197	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
8efaef4d GJ	198
	199	word <<= 1;
	200	}
	201
	202	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
	203	}
	204
fd4a319b	205	static int ath79_spi_probe(struct platform_device *pdev)
8efaef4d GJ	206	{
	207	struct spi_master *master;
	208	struct ath79_spi *sp;
	209	struct ath79_spi_platform_data *pdata;
	210	struct resource *r;
440114fd	211	unsigned long rate;
8efaef4d GJ	212	int ret;
	213
	214	master = spi_alloc_master(&pdev->dev, sizeof(*sp));
	215	if (master == NULL) {
	216	dev_err(&pdev->dev, "failed to allocate spi master\n");
	217	return -ENOMEM;
	218	}
	219
	220	sp = spi_master_get_devdata(master);
	221	platform_set_drvdata(pdev, sp);
	222
8074cf06	223	pdata = dev_get_platdata(&pdev->dev);
8efaef4d	224
24778be2	225	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
8efaef4d GJ	226	master->setup = ath79_spi_setup;
	227	master->cleanup = ath79_spi_cleanup;
	228	if (pdata) {
	229	master->bus_num = pdata->bus_num;
	230	master->num_chipselect = pdata->num_chipselect;
8efaef4d GJ	231	}
8efaef4d GJ	232
94c69f76	233	sp->bitbang.master = master;
8efaef4d GJ	234	sp->bitbang.chipselect = ath79_spi_chipselect;
	235	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
	236	sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
	237	sp->bitbang.flags = SPI_CS_HIGH;
	238
	239	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	240	if (r == NULL) {
	241	ret = -ENOENT;
	242	goto err_put_master;
	243	}
	244
a6f4c8e0	245	sp->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
8efaef4d GJ	246	if (!sp->base) {
	247	ret = -ENXIO;
	248	goto err_put_master;
	249	}
	250
a6f4c8e0	251	sp->clk = devm_clk_get(&pdev->dev, "ahb");
440114fd GJ	252	if (IS_ERR(sp->clk)) {
440114fd GJ	253	ret = PTR_ERR(sp->clk);
a6f4c8e0	254	goto err_put_master;
440114fd GJ	255	}
	256
	257	ret = clk_enable(sp->clk);
	258	if (ret)
a6f4c8e0	259	goto err_put_master;
440114fd GJ	260
	261	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
	262	if (!rate) {
	263	ret = -EINVAL;
	264	goto err_clk_disable;
	265	}
	266
	267	sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
	268	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
	269	sp->rrw_delay);
	270
c4a31f43	271	ath79_spi_enable(sp);
8efaef4d GJ	272	ret = spi_bitbang_start(&sp->bitbang);
8efaef4d GJ	273	if (ret)
c4a31f43	274	goto err_disable;
8efaef4d GJ	275
	276	return 0;
	277
c4a31f43 GJ	278	err_disable:
c4a31f43 GJ	279	ath79_spi_disable(sp);
440114fd GJ	280	err_clk_disable:
440114fd GJ	281	clk_disable(sp->clk);
8efaef4d	282	err_put_master:
8efaef4d GJ	283	spi_master_put(sp->bitbang.master);
	284
	285	return ret;
	286	}
	287
fd4a319b	288	static int ath79_spi_remove(struct platform_device *pdev)
8efaef4d GJ	289	{
	290	struct ath79_spi *sp = platform_get_drvdata(pdev);
	291
	292	spi_bitbang_stop(&sp->bitbang);
c4a31f43	293	ath79_spi_disable(sp);
440114fd	294	clk_disable(sp->clk);
8efaef4d GJ	295	spi_master_put(sp->bitbang.master);
	296
	297	return 0;
	298	}
	299
7410e848 GJ	300	static void ath79_spi_shutdown(struct platform_device *pdev)
	301	{
	302	ath79_spi_remove(pdev);
	303	}
	304
8efaef4d GJ	305	static struct platform_driver ath79_spi_driver = {
8efaef4d GJ	306	.probe = ath79_spi_probe,
fd4a319b	307	.remove = ath79_spi_remove,
7410e848	308	.shutdown = ath79_spi_shutdown,
8efaef4d GJ	309	.driver = {
	310	.name = DRV_NAME,
	311	.owner = THIS_MODULE,
	312	},
	313	};
940ab889	314	module_platform_driver(ath79_spi_driver);
8efaef4d GJ	315
	316	MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
	317	MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
	318	MODULE_LICENSE("GPL v2");
	319	MODULE_ALIAS("platform:" DRV_NAME);