[mirror_ubuntu-artful-kernel.git] / drivers / spi / spi-ath79.c

/*
 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
 *
 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 *
 * This driver has been based on the spi-gpio.c:
 *	Copyright (C) 2006,2008 David Brownell
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/clk.h>
#include <linux/err.h>

#include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ath79_spi_platform.h>

#define DRV_NAME	"ath79-spi"

#define ATH79_SPI_RRW_DELAY_FACTOR	12000
#define MHZ				(1000 * 1000)

struct ath79_spi {
	struct spi_bitbang	bitbang;
	u32			ioc_base;
	u32			reg_ctrl;
	void __iomem		*base;
	struct clk		*clk;
	unsigned		rrw_delay;
};

static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
{
	return ioread32(sp->base + reg);
}

static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)
{
	iowrite32(val, sp->base + reg);
}

static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
{
	return spi_master_get_devdata(spi->master);
}

static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
{
	if (nsecs > sp->rrw_delay)
		ndelay(nsecs - sp->rrw_delay);
}

static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
{
	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;

	if (is_active) {
		/* set initial clock polarity */
		if (spi->mode & SPI_CPOL)
			sp->ioc_base |= AR71XX_SPI_IOC_CLK;
		else
			sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;

		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
	}

	if (gpio_is_valid(spi->cs_gpio)) {
		/* SPI is normally active-low */
		gpio_set_value_cansleep(spi->cs_gpio, cs_high);
	} else {
		u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);

		if (cs_high)
			sp->ioc_base |= cs_bit;
		else
			sp->ioc_base &= ~cs_bit;

		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
	}

}

static void ath79_spi_enable(struct ath79_spi *sp)
{
	/* enable GPIO mode */
	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);

	/* save CTRL register */
	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);

	/* TODO: setup speed? */
	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
}

static void ath79_spi_disable(struct ath79_spi *sp)
{
	/* restore CTRL register */
	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
	/* disable GPIO mode */
	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
}

static int ath79_spi_setup_cs(struct spi_device *spi)
{
	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	int status;

	status = 0;
	if (gpio_is_valid(spi->cs_gpio)) {
		unsigned long flags;

		flags = GPIOF_DIR_OUT;
		if (spi->mode & SPI_CS_HIGH)
			flags |= GPIOF_INIT_LOW;
		else
			flags |= GPIOF_INIT_HIGH;

		status = gpio_request_one(spi->cs_gpio, flags,
					  dev_name(&spi->dev));
	} else {
		u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);

		if (spi->mode & SPI_CS_HIGH)
			sp->ioc_base &= ~cs_bit;
		else
			sp->ioc_base |= cs_bit;

		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
	}

	return status;
}

static void ath79_spi_cleanup_cs(struct spi_device *spi)
{
	if (gpio_is_valid(spi->cs_gpio)) {
		gpio_free(spi->cs_gpio);
	}
}

static int ath79_spi_setup(struct spi_device *spi)
{
	int status = 0;

	if (!spi->controller_state) {
		status = ath79_spi_setup_cs(spi);
		if (status)
			return status;
	}

	status = spi_bitbang_setup(spi);
	if (status && !spi->controller_state)
		ath79_spi_cleanup_cs(spi);

	return status;
}

static void ath79_spi_cleanup(struct spi_device *spi)
{
	ath79_spi_cleanup_cs(spi);
	spi_bitbang_cleanup(spi);
}

static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs,
			       u32 word, u8 bits)
{
	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	u32 ioc = sp->ioc_base;

	/* clock starts at inactive polarity */
	for (word <<= (32 - bits); likely(bits); bits--) {
		u32 out;

		if (word & (1 << 31))
			out = ioc | AR71XX_SPI_IOC_DO;
		else
			out = ioc & ~AR71XX_SPI_IOC_DO;

		/* setup MSB (to slave) on trailing edge */
		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
		ath79_spi_delay(sp, nsecs);
		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
		ath79_spi_delay(sp, nsecs);
		if (bits == 1)
			ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);

		word <<= 1;
	}

	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
}

static int ath79_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct ath79_spi *sp;
	struct ath79_spi_platform_data *pdata;
	struct resource	*r;
	unsigned long rate;
	int ret;

	master = spi_alloc_master(&pdev->dev, sizeof(*sp));
	if (master == NULL) {
		dev_err(&pdev->dev, "failed to allocate spi master\n");
		return -ENOMEM;
	}

	sp = spi_master_get_devdata(master);
	master->dev.of_node = pdev->dev.of_node;
	platform_set_drvdata(pdev, sp);

	pdata = dev_get_platdata(&pdev->dev);

	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
	master->setup = ath79_spi_setup;
	master->cleanup = ath79_spi_cleanup;
	if (pdata) {
		master->bus_num = pdata->bus_num;
		master->num_chipselect = pdata->num_chipselect;
	}

	sp->bitbang.master = master;
	sp->bitbang.chipselect = ath79_spi_chipselect;
	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
	sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
	sp->bitbang.flags = SPI_CS_HIGH;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	sp->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(sp->base)) {
		ret = PTR_ERR(sp->base);
		goto err_put_master;
	}

	sp->clk = devm_clk_get(&pdev->dev, "ahb");
	if (IS_ERR(sp->clk)) {
		ret = PTR_ERR(sp->clk);
		goto err_put_master;
	}

	ret = clk_prepare_enable(sp->clk);
	if (ret)
		goto err_put_master;

	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
	if (!rate) {
		ret = -EINVAL;
		goto err_clk_disable;
	}

	sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
		sp->rrw_delay);

	ath79_spi_enable(sp);
	ret = spi_bitbang_start(&sp->bitbang);
	if (ret)
		goto err_disable;

	return 0;

err_disable:
	ath79_spi_disable(sp);
err_clk_disable:
	clk_disable_unprepare(sp->clk);
err_put_master:
	spi_master_put(sp->bitbang.master);

	return ret;
}

static int ath79_spi_remove(struct platform_device *pdev)
{
	struct ath79_spi *sp = platform_get_drvdata(pdev);

	spi_bitbang_stop(&sp->bitbang);
	ath79_spi_disable(sp);
	clk_disable_unprepare(sp->clk);
	spi_master_put(sp->bitbang.master);

	return 0;
}

static void ath79_spi_shutdown(struct platform_device *pdev)
{
	ath79_spi_remove(pdev);
}

static const struct of_device_id ath79_spi_of_match[] = {
	{ .compatible = "qca,ar7100-spi", },
	{ },
};
MODULE_DEVICE_TABLE(of, ath79_spi_of_match);

static struct platform_driver ath79_spi_driver = {
	.probe		= ath79_spi_probe,
	.remove		= ath79_spi_remove,
	.shutdown	= ath79_spi_shutdown,
	.driver		= {
		.name	= DRV_NAME,
		.of_match_table = ath79_spi_of_match,
	},
};
module_platform_driver(ath79_spi_driver);

MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
8efaef4d GJ	1	/*
	2	* SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
	3	*
	4	* Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
	5	*
	6	* This driver has been based on the spi-gpio.c:
	7	* Copyright (C) 2006,2008 David Brownell
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	*/
	14
	15	#include <linux/kernel.h>
807cc4b1	16	#include <linux/module.h>
8efaef4d GJ	17	#include <linux/delay.h>
8efaef4d GJ	18	#include <linux/spinlock.h>
8efaef4d GJ	19	#include <linux/platform_device.h>
	20	#include <linux/io.h>
	21	#include <linux/spi/spi.h>
	22	#include <linux/spi/spi_bitbang.h>
	23	#include <linux/bitops.h>
	24	#include <linux/gpio.h>
440114fd GJ	25	#include <linux/clk.h>
440114fd GJ	26	#include <linux/err.h>
8efaef4d GJ	27
	28	#include <asm/mach-ath79/ar71xx_regs.h>
	29	#include <asm/mach-ath79/ath79_spi_platform.h>
	30
	31	#define DRV_NAME "ath79-spi"
	32
440114fd GJ	33	#define ATH79_SPI_RRW_DELAY_FACTOR 12000
	34	#define MHZ (1000 * 1000)
	35
8efaef4d GJ	36	struct ath79_spi {
	37	struct spi_bitbang bitbang;
	38	u32 ioc_base;
	39	u32 reg_ctrl;
	40	void __iomem *base;
440114fd GJ	41	struct clk *clk;
440114fd GJ	42	unsigned rrw_delay;
8efaef4d GJ	43	};
	44
	45	static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
	46	{
	47	return ioread32(sp->base + reg);
	48	}
	49
	50	static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)
	51	{
	52	iowrite32(val, sp->base + reg);
	53	}
	54
	55	static inline struct ath79_spi ath79_spidev_to_sp(struct spi_device spi)
	56	{
	57	return spi_master_get_devdata(spi->master);
	58	}
	59
440114fd GJ	60	static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
	61	{
	62	if (nsecs > sp->rrw_delay)
	63	ndelay(nsecs - sp->rrw_delay);
	64	}
	65
8efaef4d GJ	66	static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
	67	{
	68	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	69	int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
	70
	71	if (is_active) {
	72	/* set initial clock polarity */
	73	if (spi->mode & SPI_CPOL)
	74	sp->ioc_base \|= AR71XX_SPI_IOC_CLK;
	75	else
	76	sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;
	77
	78	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
	79	}
	80
22c76326	81	if (gpio_is_valid(spi->cs_gpio)) {
8efaef4d	82	/* SPI is normally active-low */
91829a9a	83	gpio_set_value_cansleep(spi->cs_gpio, cs_high);
8efaef4d	84	} else {
22c76326 FF	85	u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
22c76326 FF	86
8efaef4d	87	if (cs_high)
22c76326	88	sp->ioc_base \|= cs_bit;
8efaef4d	89	else
22c76326	90	sp->ioc_base &= ~cs_bit;
8efaef4d GJ	91
	92	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
	93	}
	94
	95	}
	96
c4a31f43	97	static void ath79_spi_enable(struct ath79_spi *sp)
8efaef4d	98	{
8efaef4d GJ	99	/* enable GPIO mode */
	100	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
	101
	102	/* save CTRL register */
	103	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
	104	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
	105
	106	/* TODO: setup speed? */
	107	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
c4a31f43 GJ	108	}
	109
	110	static void ath79_spi_disable(struct ath79_spi *sp)
	111	{
	112	/* restore CTRL register */
	113	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
	114	/* disable GPIO mode */
	115	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
	116	}
	117
	118	static int ath79_spi_setup_cs(struct spi_device *spi)
	119	{
83f0f398	120	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
c4a31f43 GJ	121	int status;
c4a31f43 GJ	122
95d79419	123	status = 0;
22c76326	124	if (gpio_is_valid(spi->cs_gpio)) {
95d79419 GJ	125	unsigned long flags;
	126
	127	flags = GPIOF_DIR_OUT;
	128	if (spi->mode & SPI_CS_HIGH)
95d79419	129	flags \|= GPIOF_INIT_LOW;
61d1cf16 GJ	130	else
61d1cf16 GJ	131	flags \|= GPIOF_INIT_HIGH;
95d79419	132
85f62476	133	status = gpio_request_one(spi->cs_gpio, flags,
95d79419	134	dev_name(&spi->dev));
83f0f398	135	} else {
22c76326 FF	136	u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
22c76326 FF	137
83f0f398	138	if (spi->mode & SPI_CS_HIGH)
22c76326	139	sp->ioc_base &= ~cs_bit;
83f0f398	140	else
22c76326	141	sp->ioc_base \|= cs_bit;
83f0f398 AB	142
83f0f398 AB	143	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
8efaef4d GJ	144	}
8efaef4d GJ	145
95d79419	146	return status;
8efaef4d GJ	147	}
	148
	149	static void ath79_spi_cleanup_cs(struct spi_device *spi)
	150	{
22c76326	151	if (gpio_is_valid(spi->cs_gpio)) {
85f62476	152	gpio_free(spi->cs_gpio);
8efaef4d	153	}
8efaef4d GJ	154	}
	155
	156	static int ath79_spi_setup(struct spi_device *spi)
	157	{
	158	int status = 0;
	159
8efaef4d GJ	160	if (!spi->controller_state) {
	161	status = ath79_spi_setup_cs(spi);
	162	if (status)
	163	return status;
	164	}
	165
	166	status = spi_bitbang_setup(spi);
	167	if (status && !spi->controller_state)
	168	ath79_spi_cleanup_cs(spi);
	169
	170	return status;
	171	}
	172
	173	static void ath79_spi_cleanup(struct spi_device *spi)
	174	{
	175	ath79_spi_cleanup_cs(spi);
	176	spi_bitbang_cleanup(spi);
	177	}
	178
	179	static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs,
	180	u32 word, u8 bits)
	181	{
	182	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	183	u32 ioc = sp->ioc_base;
	184
	185	/* clock starts at inactive polarity */
	186	for (word <<= (32 - bits); likely(bits); bits--) {
	187	u32 out;
	188
	189	if (word & (1 << 31))
	190	out = ioc \| AR71XX_SPI_IOC_DO;
	191	else
	192	out = ioc & ~AR71XX_SPI_IOC_DO;
	193
	194	/* setup MSB (to slave) on trailing edge */
	195	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
440114fd	196	ath79_spi_delay(sp, nsecs);
8efaef4d	197	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out \| AR71XX_SPI_IOC_CLK);
440114fd	198	ath79_spi_delay(sp, nsecs);
72611db0 GJ	199	if (bits == 1)
72611db0 GJ	200	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
8efaef4d GJ	201
	202	word <<= 1;
	203	}
	204
	205	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
	206	}
	207
fd4a319b	208	static int ath79_spi_probe(struct platform_device *pdev)
8efaef4d GJ	209	{
	210	struct spi_master *master;
	211	struct ath79_spi *sp;
	212	struct ath79_spi_platform_data *pdata;
	213	struct resource *r;
440114fd	214	unsigned long rate;
8efaef4d GJ	215	int ret;
	216
	217	master = spi_alloc_master(&pdev->dev, sizeof(*sp));
	218	if (master == NULL) {
	219	dev_err(&pdev->dev, "failed to allocate spi master\n");
	220	return -ENOMEM;
	221	}
	222
	223	sp = spi_master_get_devdata(master);
85f62476	224	master->dev.of_node = pdev->dev.of_node;
8efaef4d GJ	225	platform_set_drvdata(pdev, sp);
8efaef4d GJ	226
8074cf06	227	pdata = dev_get_platdata(&pdev->dev);
8efaef4d	228
24778be2	229	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
8efaef4d GJ	230	master->setup = ath79_spi_setup;
	231	master->cleanup = ath79_spi_cleanup;
	232	if (pdata) {
	233	master->bus_num = pdata->bus_num;
	234	master->num_chipselect = pdata->num_chipselect;
8efaef4d GJ	235	}
8efaef4d GJ	236
94c69f76	237	sp->bitbang.master = master;
8efaef4d GJ	238	sp->bitbang.chipselect = ath79_spi_chipselect;
	239	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
	240	sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
	241	sp->bitbang.flags = SPI_CS_HIGH;
	242
	243	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b7a2a1c0 HK	244	sp->base = devm_ioremap_resource(&pdev->dev, r);
	245	if (IS_ERR(sp->base)) {
	246	ret = PTR_ERR(sp->base);
8efaef4d GJ	247	goto err_put_master;
	248	}
	249
a6f4c8e0	250	sp->clk = devm_clk_get(&pdev->dev, "ahb");
440114fd GJ	251	if (IS_ERR(sp->clk)) {
440114fd GJ	252	ret = PTR_ERR(sp->clk);
a6f4c8e0	253	goto err_put_master;
440114fd GJ	254	}
440114fd GJ	255
3e19acdc	256	ret = clk_prepare_enable(sp->clk);
440114fd	257	if (ret)
a6f4c8e0	258	goto err_put_master;
440114fd GJ	259
	260	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
	261	if (!rate) {
	262	ret = -EINVAL;
	263	goto err_clk_disable;
	264	}
	265
	266	sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
	267	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
	268	sp->rrw_delay);
	269
c4a31f43	270	ath79_spi_enable(sp);
8efaef4d GJ	271	ret = spi_bitbang_start(&sp->bitbang);
8efaef4d GJ	272	if (ret)
c4a31f43	273	goto err_disable;
8efaef4d GJ	274
	275	return 0;
	276
c4a31f43 GJ	277	err_disable:
c4a31f43 GJ	278	ath79_spi_disable(sp);
440114fd	279	err_clk_disable:
3e19acdc	280	clk_disable_unprepare(sp->clk);
8efaef4d	281	err_put_master:
8efaef4d GJ	282	spi_master_put(sp->bitbang.master);
	283
	284	return ret;
	285	}
	286
fd4a319b	287	static int ath79_spi_remove(struct platform_device *pdev)
8efaef4d GJ	288	{
	289	struct ath79_spi *sp = platform_get_drvdata(pdev);
	290
	291	spi_bitbang_stop(&sp->bitbang);
c4a31f43	292	ath79_spi_disable(sp);
3e19acdc	293	clk_disable_unprepare(sp->clk);
8efaef4d GJ	294	spi_master_put(sp->bitbang.master);
	295
	296	return 0;
	297	}
	298
7410e848 GJ	299	static void ath79_spi_shutdown(struct platform_device *pdev)
	300	{
	301	ath79_spi_remove(pdev);
	302	}
	303
85f62476 AB	304	static const struct of_device_id ath79_spi_of_match[] = {
	305	{ .compatible = "qca,ar7100-spi", },
	306	{ },
	307	};
d7a32394	308	MODULE_DEVICE_TABLE(of, ath79_spi_of_match);
85f62476	309
8efaef4d GJ	310	static struct platform_driver ath79_spi_driver = {
8efaef4d GJ	311	.probe = ath79_spi_probe,
fd4a319b	312	.remove = ath79_spi_remove,
7410e848	313	.shutdown = ath79_spi_shutdown,
8efaef4d GJ	314	.driver = {
8efaef4d GJ	315	.name = DRV_NAME,
85f62476	316	.of_match_table = ath79_spi_of_match,
8efaef4d GJ	317	},
8efaef4d GJ	318	};
940ab889	319	module_platform_driver(ath79_spi_driver);
8efaef4d GJ	320
	321	MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
	322	MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
	323	MODULE_LICENSE("GPL v2");
	324	MODULE_ALIAS("platform:" DRV_NAME);