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754ce4f2 HS |
1 | /* |
2 | * Driver for Atmel AT32 and AT91 SPI Controllers | |
3 | * | |
4 | * Copyright (C) 2006 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/clk.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/spi/spi.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
bcd2360c | 22 | #include <linux/platform_data/atmel.h> |
850a5b67 | 23 | #include <linux/of.h> |
754ce4f2 | 24 | |
d4820b74 WY |
25 | #include <linux/io.h> |
26 | #include <linux/gpio.h> | |
bb2d1c36 | 27 | |
ca632f55 GL |
28 | /* SPI register offsets */ |
29 | #define SPI_CR 0x0000 | |
30 | #define SPI_MR 0x0004 | |
31 | #define SPI_RDR 0x0008 | |
32 | #define SPI_TDR 0x000c | |
33 | #define SPI_SR 0x0010 | |
34 | #define SPI_IER 0x0014 | |
35 | #define SPI_IDR 0x0018 | |
36 | #define SPI_IMR 0x001c | |
37 | #define SPI_CSR0 0x0030 | |
38 | #define SPI_CSR1 0x0034 | |
39 | #define SPI_CSR2 0x0038 | |
40 | #define SPI_CSR3 0x003c | |
d4820b74 | 41 | #define SPI_VERSION 0x00fc |
ca632f55 GL |
42 | #define SPI_RPR 0x0100 |
43 | #define SPI_RCR 0x0104 | |
44 | #define SPI_TPR 0x0108 | |
45 | #define SPI_TCR 0x010c | |
46 | #define SPI_RNPR 0x0110 | |
47 | #define SPI_RNCR 0x0114 | |
48 | #define SPI_TNPR 0x0118 | |
49 | #define SPI_TNCR 0x011c | |
50 | #define SPI_PTCR 0x0120 | |
51 | #define SPI_PTSR 0x0124 | |
52 | ||
53 | /* Bitfields in CR */ | |
54 | #define SPI_SPIEN_OFFSET 0 | |
55 | #define SPI_SPIEN_SIZE 1 | |
56 | #define SPI_SPIDIS_OFFSET 1 | |
57 | #define SPI_SPIDIS_SIZE 1 | |
58 | #define SPI_SWRST_OFFSET 7 | |
59 | #define SPI_SWRST_SIZE 1 | |
60 | #define SPI_LASTXFER_OFFSET 24 | |
61 | #define SPI_LASTXFER_SIZE 1 | |
62 | ||
63 | /* Bitfields in MR */ | |
64 | #define SPI_MSTR_OFFSET 0 | |
65 | #define SPI_MSTR_SIZE 1 | |
66 | #define SPI_PS_OFFSET 1 | |
67 | #define SPI_PS_SIZE 1 | |
68 | #define SPI_PCSDEC_OFFSET 2 | |
69 | #define SPI_PCSDEC_SIZE 1 | |
70 | #define SPI_FDIV_OFFSET 3 | |
71 | #define SPI_FDIV_SIZE 1 | |
72 | #define SPI_MODFDIS_OFFSET 4 | |
73 | #define SPI_MODFDIS_SIZE 1 | |
d4820b74 WY |
74 | #define SPI_WDRBT_OFFSET 5 |
75 | #define SPI_WDRBT_SIZE 1 | |
ca632f55 GL |
76 | #define SPI_LLB_OFFSET 7 |
77 | #define SPI_LLB_SIZE 1 | |
78 | #define SPI_PCS_OFFSET 16 | |
79 | #define SPI_PCS_SIZE 4 | |
80 | #define SPI_DLYBCS_OFFSET 24 | |
81 | #define SPI_DLYBCS_SIZE 8 | |
82 | ||
83 | /* Bitfields in RDR */ | |
84 | #define SPI_RD_OFFSET 0 | |
85 | #define SPI_RD_SIZE 16 | |
86 | ||
87 | /* Bitfields in TDR */ | |
88 | #define SPI_TD_OFFSET 0 | |
89 | #define SPI_TD_SIZE 16 | |
90 | ||
91 | /* Bitfields in SR */ | |
92 | #define SPI_RDRF_OFFSET 0 | |
93 | #define SPI_RDRF_SIZE 1 | |
94 | #define SPI_TDRE_OFFSET 1 | |
95 | #define SPI_TDRE_SIZE 1 | |
96 | #define SPI_MODF_OFFSET 2 | |
97 | #define SPI_MODF_SIZE 1 | |
98 | #define SPI_OVRES_OFFSET 3 | |
99 | #define SPI_OVRES_SIZE 1 | |
100 | #define SPI_ENDRX_OFFSET 4 | |
101 | #define SPI_ENDRX_SIZE 1 | |
102 | #define SPI_ENDTX_OFFSET 5 | |
103 | #define SPI_ENDTX_SIZE 1 | |
104 | #define SPI_RXBUFF_OFFSET 6 | |
105 | #define SPI_RXBUFF_SIZE 1 | |
106 | #define SPI_TXBUFE_OFFSET 7 | |
107 | #define SPI_TXBUFE_SIZE 1 | |
108 | #define SPI_NSSR_OFFSET 8 | |
109 | #define SPI_NSSR_SIZE 1 | |
110 | #define SPI_TXEMPTY_OFFSET 9 | |
111 | #define SPI_TXEMPTY_SIZE 1 | |
112 | #define SPI_SPIENS_OFFSET 16 | |
113 | #define SPI_SPIENS_SIZE 1 | |
114 | ||
115 | /* Bitfields in CSR0 */ | |
116 | #define SPI_CPOL_OFFSET 0 | |
117 | #define SPI_CPOL_SIZE 1 | |
118 | #define SPI_NCPHA_OFFSET 1 | |
119 | #define SPI_NCPHA_SIZE 1 | |
120 | #define SPI_CSAAT_OFFSET 3 | |
121 | #define SPI_CSAAT_SIZE 1 | |
122 | #define SPI_BITS_OFFSET 4 | |
123 | #define SPI_BITS_SIZE 4 | |
124 | #define SPI_SCBR_OFFSET 8 | |
125 | #define SPI_SCBR_SIZE 8 | |
126 | #define SPI_DLYBS_OFFSET 16 | |
127 | #define SPI_DLYBS_SIZE 8 | |
128 | #define SPI_DLYBCT_OFFSET 24 | |
129 | #define SPI_DLYBCT_SIZE 8 | |
130 | ||
131 | /* Bitfields in RCR */ | |
132 | #define SPI_RXCTR_OFFSET 0 | |
133 | #define SPI_RXCTR_SIZE 16 | |
134 | ||
135 | /* Bitfields in TCR */ | |
136 | #define SPI_TXCTR_OFFSET 0 | |
137 | #define SPI_TXCTR_SIZE 16 | |
138 | ||
139 | /* Bitfields in RNCR */ | |
140 | #define SPI_RXNCR_OFFSET 0 | |
141 | #define SPI_RXNCR_SIZE 16 | |
142 | ||
143 | /* Bitfields in TNCR */ | |
144 | #define SPI_TXNCR_OFFSET 0 | |
145 | #define SPI_TXNCR_SIZE 16 | |
146 | ||
147 | /* Bitfields in PTCR */ | |
148 | #define SPI_RXTEN_OFFSET 0 | |
149 | #define SPI_RXTEN_SIZE 1 | |
150 | #define SPI_RXTDIS_OFFSET 1 | |
151 | #define SPI_RXTDIS_SIZE 1 | |
152 | #define SPI_TXTEN_OFFSET 8 | |
153 | #define SPI_TXTEN_SIZE 1 | |
154 | #define SPI_TXTDIS_OFFSET 9 | |
155 | #define SPI_TXTDIS_SIZE 1 | |
156 | ||
157 | /* Constants for BITS */ | |
158 | #define SPI_BITS_8_BPT 0 | |
159 | #define SPI_BITS_9_BPT 1 | |
160 | #define SPI_BITS_10_BPT 2 | |
161 | #define SPI_BITS_11_BPT 3 | |
162 | #define SPI_BITS_12_BPT 4 | |
163 | #define SPI_BITS_13_BPT 5 | |
164 | #define SPI_BITS_14_BPT 6 | |
165 | #define SPI_BITS_15_BPT 7 | |
166 | #define SPI_BITS_16_BPT 8 | |
167 | ||
168 | /* Bit manipulation macros */ | |
169 | #define SPI_BIT(name) \ | |
170 | (1 << SPI_##name##_OFFSET) | |
171 | #define SPI_BF(name,value) \ | |
172 | (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET) | |
173 | #define SPI_BFEXT(name,value) \ | |
174 | (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1)) | |
175 | #define SPI_BFINS(name,value,old) \ | |
176 | ( ((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \ | |
177 | | SPI_BF(name,value)) | |
178 | ||
179 | /* Register access macros */ | |
180 | #define spi_readl(port,reg) \ | |
181 | __raw_readl((port)->regs + SPI_##reg) | |
182 | #define spi_writel(port,reg,value) \ | |
183 | __raw_writel((value), (port)->regs + SPI_##reg) | |
184 | ||
d4820b74 WY |
185 | struct atmel_spi_caps { |
186 | bool is_spi2; | |
187 | bool has_wdrbt; | |
188 | bool has_dma_support; | |
189 | }; | |
754ce4f2 HS |
190 | |
191 | /* | |
192 | * The core SPI transfer engine just talks to a register bank to set up | |
193 | * DMA transfers; transfer queue progress is driven by IRQs. The clock | |
194 | * framework provides the base clock, subdivided for each spi_device. | |
754ce4f2 HS |
195 | */ |
196 | struct atmel_spi { | |
197 | spinlock_t lock; | |
198 | ||
199 | void __iomem *regs; | |
200 | int irq; | |
201 | struct clk *clk; | |
202 | struct platform_device *pdev; | |
defbd3b4 | 203 | struct spi_device *stay; |
754ce4f2 HS |
204 | |
205 | u8 stopping; | |
206 | struct list_head queue; | |
207 | struct spi_transfer *current_transfer; | |
154443c7 SE |
208 | unsigned long current_remaining_bytes; |
209 | struct spi_transfer *next_transfer; | |
210 | unsigned long next_remaining_bytes; | |
754ce4f2 HS |
211 | |
212 | void *buffer; | |
213 | dma_addr_t buffer_dma; | |
d4820b74 WY |
214 | |
215 | struct atmel_spi_caps caps; | |
754ce4f2 HS |
216 | }; |
217 | ||
5ee36c98 HS |
218 | /* Controller-specific per-slave state */ |
219 | struct atmel_spi_device { | |
220 | unsigned int npcs_pin; | |
221 | u32 csr; | |
222 | }; | |
223 | ||
754ce4f2 HS |
224 | #define BUFFER_SIZE PAGE_SIZE |
225 | #define INVALID_DMA_ADDRESS 0xffffffff | |
226 | ||
5bfa26ca HS |
227 | /* |
228 | * Version 2 of the SPI controller has | |
229 | * - CR.LASTXFER | |
230 | * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero) | |
231 | * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs) | |
232 | * - SPI_CSRx.CSAAT | |
233 | * - SPI_CSRx.SBCR allows faster clocking | |
5bfa26ca | 234 | */ |
d4820b74 | 235 | static bool atmel_spi_is_v2(struct atmel_spi *as) |
5bfa26ca | 236 | { |
d4820b74 | 237 | return as->caps.is_spi2; |
5bfa26ca HS |
238 | } |
239 | ||
754ce4f2 HS |
240 | /* |
241 | * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby | |
242 | * they assume that spi slave device state will not change on deselect, so | |
defbd3b4 DB |
243 | * that automagic deselection is OK. ("NPCSx rises if no data is to be |
244 | * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer | |
245 | * controllers have CSAAT and friends. | |
754ce4f2 | 246 | * |
defbd3b4 DB |
247 | * Since the CSAAT functionality is a bit weird on newer controllers as |
248 | * well, we use GPIO to control nCSx pins on all controllers, updating | |
249 | * MR.PCS to avoid confusing the controller. Using GPIOs also lets us | |
250 | * support active-high chipselects despite the controller's belief that | |
251 | * only active-low devices/systems exists. | |
252 | * | |
253 | * However, at91rm9200 has a second erratum whereby nCS0 doesn't work | |
254 | * right when driven with GPIO. ("Mode Fault does not allow more than one | |
255 | * Master on Chip Select 0.") No workaround exists for that ... so for | |
256 | * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH, | |
257 | * and (c) will trigger that first erratum in some cases. | |
5ee36c98 HS |
258 | * |
259 | * TODO: Test if the atmel_spi_is_v2() branch below works on | |
260 | * AT91RM9200 if we use some other register than CSR0. However, don't | |
261 | * do this unconditionally since AP7000 has an errata where the BITS | |
262 | * field in CSR0 overrides all other CSRs. | |
754ce4f2 HS |
263 | */ |
264 | ||
defbd3b4 | 265 | static void cs_activate(struct atmel_spi *as, struct spi_device *spi) |
754ce4f2 | 266 | { |
5ee36c98 | 267 | struct atmel_spi_device *asd = spi->controller_state; |
754ce4f2 | 268 | unsigned active = spi->mode & SPI_CS_HIGH; |
defbd3b4 DB |
269 | u32 mr; |
270 | ||
d4820b74 | 271 | if (atmel_spi_is_v2(as)) { |
5ee36c98 HS |
272 | /* |
273 | * Always use CSR0. This ensures that the clock | |
274 | * switches to the correct idle polarity before we | |
275 | * toggle the CS. | |
276 | */ | |
277 | spi_writel(as, CSR0, asd->csr); | |
d4820b74 WY |
278 | if (as->caps.has_wdrbt) { |
279 | spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(WDRBT) | |
280 | | SPI_BIT(MODFDIS) | SPI_BIT(MSTR)); | |
281 | } else { | |
282 | spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(MODFDIS) | |
5ee36c98 | 283 | | SPI_BIT(MSTR)); |
d4820b74 | 284 | } |
5ee36c98 HS |
285 | mr = spi_readl(as, MR); |
286 | gpio_set_value(asd->npcs_pin, active); | |
287 | } else { | |
288 | u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0; | |
289 | int i; | |
290 | u32 csr; | |
291 | ||
292 | /* Make sure clock polarity is correct */ | |
293 | for (i = 0; i < spi->master->num_chipselect; i++) { | |
294 | csr = spi_readl(as, CSR0 + 4 * i); | |
295 | if ((csr ^ cpol) & SPI_BIT(CPOL)) | |
296 | spi_writel(as, CSR0 + 4 * i, | |
297 | csr ^ SPI_BIT(CPOL)); | |
298 | } | |
299 | ||
300 | mr = spi_readl(as, MR); | |
301 | mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr); | |
302 | if (spi->chip_select != 0) | |
303 | gpio_set_value(asd->npcs_pin, active); | |
304 | spi_writel(as, MR, mr); | |
305 | } | |
defbd3b4 DB |
306 | |
307 | dev_dbg(&spi->dev, "activate %u%s, mr %08x\n", | |
5ee36c98 | 308 | asd->npcs_pin, active ? " (high)" : "", |
defbd3b4 | 309 | mr); |
754ce4f2 HS |
310 | } |
311 | ||
defbd3b4 | 312 | static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi) |
754ce4f2 | 313 | { |
5ee36c98 | 314 | struct atmel_spi_device *asd = spi->controller_state; |
754ce4f2 | 315 | unsigned active = spi->mode & SPI_CS_HIGH; |
defbd3b4 DB |
316 | u32 mr; |
317 | ||
318 | /* only deactivate *this* device; sometimes transfers to | |
319 | * another device may be active when this routine is called. | |
320 | */ | |
321 | mr = spi_readl(as, MR); | |
322 | if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) { | |
323 | mr = SPI_BFINS(PCS, 0xf, mr); | |
324 | spi_writel(as, MR, mr); | |
325 | } | |
754ce4f2 | 326 | |
defbd3b4 | 327 | dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n", |
5ee36c98 | 328 | asd->npcs_pin, active ? " (low)" : "", |
defbd3b4 DB |
329 | mr); |
330 | ||
d4820b74 | 331 | if (atmel_spi_is_v2(as) || spi->chip_select != 0) |
5ee36c98 | 332 | gpio_set_value(asd->npcs_pin, !active); |
754ce4f2 HS |
333 | } |
334 | ||
154443c7 SE |
335 | static inline int atmel_spi_xfer_is_last(struct spi_message *msg, |
336 | struct spi_transfer *xfer) | |
337 | { | |
338 | return msg->transfers.prev == &xfer->transfer_list; | |
339 | } | |
340 | ||
341 | static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer) | |
342 | { | |
343 | return xfer->delay_usecs == 0 && !xfer->cs_change; | |
344 | } | |
345 | ||
346 | static void atmel_spi_next_xfer_data(struct spi_master *master, | |
347 | struct spi_transfer *xfer, | |
348 | dma_addr_t *tx_dma, | |
349 | dma_addr_t *rx_dma, | |
350 | u32 *plen) | |
351 | { | |
352 | struct atmel_spi *as = spi_master_get_devdata(master); | |
353 | u32 len = *plen; | |
354 | ||
355 | /* use scratch buffer only when rx or tx data is unspecified */ | |
356 | if (xfer->rx_buf) | |
6aed4ee9 | 357 | *rx_dma = xfer->rx_dma + xfer->len - *plen; |
154443c7 SE |
358 | else { |
359 | *rx_dma = as->buffer_dma; | |
360 | if (len > BUFFER_SIZE) | |
361 | len = BUFFER_SIZE; | |
362 | } | |
363 | if (xfer->tx_buf) | |
6aed4ee9 | 364 | *tx_dma = xfer->tx_dma + xfer->len - *plen; |
154443c7 SE |
365 | else { |
366 | *tx_dma = as->buffer_dma; | |
367 | if (len > BUFFER_SIZE) | |
368 | len = BUFFER_SIZE; | |
369 | memset(as->buffer, 0, len); | |
370 | dma_sync_single_for_device(&as->pdev->dev, | |
371 | as->buffer_dma, len, DMA_TO_DEVICE); | |
372 | } | |
373 | ||
374 | *plen = len; | |
375 | } | |
376 | ||
754ce4f2 HS |
377 | /* |
378 | * Submit next transfer for DMA. | |
379 | * lock is held, spi irq is blocked | |
380 | */ | |
381 | static void atmel_spi_next_xfer(struct spi_master *master, | |
382 | struct spi_message *msg) | |
383 | { | |
384 | struct atmel_spi *as = spi_master_get_devdata(master); | |
385 | struct spi_transfer *xfer; | |
dc329442 GK |
386 | u32 len, remaining; |
387 | u32 ieval; | |
754ce4f2 HS |
388 | dma_addr_t tx_dma, rx_dma; |
389 | ||
154443c7 SE |
390 | if (!as->current_transfer) |
391 | xfer = list_entry(msg->transfers.next, | |
392 | struct spi_transfer, transfer_list); | |
393 | else if (!as->next_transfer) | |
394 | xfer = list_entry(as->current_transfer->transfer_list.next, | |
395 | struct spi_transfer, transfer_list); | |
396 | else | |
397 | xfer = NULL; | |
398 | ||
399 | if (xfer) { | |
dc329442 GK |
400 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); |
401 | ||
154443c7 SE |
402 | len = xfer->len; |
403 | atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); | |
404 | remaining = xfer->len - len; | |
405 | ||
406 | spi_writel(as, RPR, rx_dma); | |
407 | spi_writel(as, TPR, tx_dma); | |
408 | ||
409 | if (msg->spi->bits_per_word > 8) | |
410 | len >>= 1; | |
411 | spi_writel(as, RCR, len); | |
412 | spi_writel(as, TCR, len); | |
8bacb219 HS |
413 | |
414 | dev_dbg(&msg->spi->dev, | |
415 | " start xfer %p: len %u tx %p/%08x rx %p/%08x\n", | |
416 | xfer, xfer->len, xfer->tx_buf, xfer->tx_dma, | |
417 | xfer->rx_buf, xfer->rx_dma); | |
154443c7 SE |
418 | } else { |
419 | xfer = as->next_transfer; | |
420 | remaining = as->next_remaining_bytes; | |
754ce4f2 HS |
421 | } |
422 | ||
154443c7 SE |
423 | as->current_transfer = xfer; |
424 | as->current_remaining_bytes = remaining; | |
754ce4f2 | 425 | |
154443c7 SE |
426 | if (remaining > 0) |
427 | len = remaining; | |
8bacb219 HS |
428 | else if (!atmel_spi_xfer_is_last(msg, xfer) |
429 | && atmel_spi_xfer_can_be_chained(xfer)) { | |
154443c7 SE |
430 | xfer = list_entry(xfer->transfer_list.next, |
431 | struct spi_transfer, transfer_list); | |
432 | len = xfer->len; | |
433 | } else | |
434 | xfer = NULL; | |
754ce4f2 | 435 | |
154443c7 | 436 | as->next_transfer = xfer; |
754ce4f2 | 437 | |
154443c7 | 438 | if (xfer) { |
dc329442 GK |
439 | u32 total; |
440 | ||
154443c7 SE |
441 | total = len; |
442 | atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); | |
443 | as->next_remaining_bytes = total - len; | |
754ce4f2 | 444 | |
154443c7 SE |
445 | spi_writel(as, RNPR, rx_dma); |
446 | spi_writel(as, TNPR, tx_dma); | |
754ce4f2 | 447 | |
154443c7 SE |
448 | if (msg->spi->bits_per_word > 8) |
449 | len >>= 1; | |
450 | spi_writel(as, RNCR, len); | |
451 | spi_writel(as, TNCR, len); | |
8bacb219 HS |
452 | |
453 | dev_dbg(&msg->spi->dev, | |
454 | " next xfer %p: len %u tx %p/%08x rx %p/%08x\n", | |
455 | xfer, xfer->len, xfer->tx_buf, xfer->tx_dma, | |
456 | xfer->rx_buf, xfer->rx_dma); | |
dc329442 | 457 | ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES); |
154443c7 SE |
458 | } else { |
459 | spi_writel(as, RNCR, 0); | |
460 | spi_writel(as, TNCR, 0); | |
dc329442 | 461 | ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES); |
154443c7 SE |
462 | } |
463 | ||
464 | /* REVISIT: We're waiting for ENDRX before we start the next | |
754ce4f2 HS |
465 | * transfer because we need to handle some difficult timing |
466 | * issues otherwise. If we wait for ENDTX in one transfer and | |
467 | * then starts waiting for ENDRX in the next, it's difficult | |
468 | * to tell the difference between the ENDRX interrupt we're | |
469 | * actually waiting for and the ENDRX interrupt of the | |
470 | * previous transfer. | |
471 | * | |
472 | * It should be doable, though. Just not now... | |
473 | */ | |
dc329442 | 474 | spi_writel(as, IER, ieval); |
754ce4f2 HS |
475 | spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); |
476 | } | |
477 | ||
478 | static void atmel_spi_next_message(struct spi_master *master) | |
479 | { | |
480 | struct atmel_spi *as = spi_master_get_devdata(master); | |
481 | struct spi_message *msg; | |
defbd3b4 | 482 | struct spi_device *spi; |
754ce4f2 HS |
483 | |
484 | BUG_ON(as->current_transfer); | |
485 | ||
486 | msg = list_entry(as->queue.next, struct spi_message, queue); | |
defbd3b4 | 487 | spi = msg->spi; |
754ce4f2 | 488 | |
49dce689 | 489 | dev_dbg(master->dev.parent, "start message %p for %s\n", |
6c7377ab | 490 | msg, dev_name(&spi->dev)); |
defbd3b4 DB |
491 | |
492 | /* select chip if it's not still active */ | |
493 | if (as->stay) { | |
494 | if (as->stay != spi) { | |
495 | cs_deactivate(as, as->stay); | |
496 | cs_activate(as, spi); | |
497 | } | |
498 | as->stay = NULL; | |
499 | } else | |
500 | cs_activate(as, spi); | |
754ce4f2 HS |
501 | |
502 | atmel_spi_next_xfer(master, msg); | |
503 | } | |
504 | ||
8da0859a DB |
505 | /* |
506 | * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma: | |
507 | * - The buffer is either valid for CPU access, else NULL | |
b595076a | 508 | * - If the buffer is valid, so is its DMA address |
8da0859a | 509 | * |
b595076a | 510 | * This driver manages the dma address unless message->is_dma_mapped. |
8da0859a DB |
511 | */ |
512 | static int | |
754ce4f2 HS |
513 | atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer) |
514 | { | |
8da0859a DB |
515 | struct device *dev = &as->pdev->dev; |
516 | ||
754ce4f2 | 517 | xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS; |
8da0859a | 518 | if (xfer->tx_buf) { |
214b574a JCPV |
519 | /* tx_buf is a const void* where we need a void * for the dma |
520 | * mapping */ | |
521 | void *nonconst_tx = (void *)xfer->tx_buf; | |
522 | ||
8da0859a | 523 | xfer->tx_dma = dma_map_single(dev, |
214b574a | 524 | nonconst_tx, xfer->len, |
754ce4f2 | 525 | DMA_TO_DEVICE); |
8d8bb39b | 526 | if (dma_mapping_error(dev, xfer->tx_dma)) |
8da0859a DB |
527 | return -ENOMEM; |
528 | } | |
529 | if (xfer->rx_buf) { | |
530 | xfer->rx_dma = dma_map_single(dev, | |
754ce4f2 HS |
531 | xfer->rx_buf, xfer->len, |
532 | DMA_FROM_DEVICE); | |
8d8bb39b | 533 | if (dma_mapping_error(dev, xfer->rx_dma)) { |
8da0859a DB |
534 | if (xfer->tx_buf) |
535 | dma_unmap_single(dev, | |
536 | xfer->tx_dma, xfer->len, | |
537 | DMA_TO_DEVICE); | |
538 | return -ENOMEM; | |
539 | } | |
540 | } | |
541 | return 0; | |
754ce4f2 HS |
542 | } |
543 | ||
544 | static void atmel_spi_dma_unmap_xfer(struct spi_master *master, | |
545 | struct spi_transfer *xfer) | |
546 | { | |
547 | if (xfer->tx_dma != INVALID_DMA_ADDRESS) | |
49dce689 | 548 | dma_unmap_single(master->dev.parent, xfer->tx_dma, |
754ce4f2 HS |
549 | xfer->len, DMA_TO_DEVICE); |
550 | if (xfer->rx_dma != INVALID_DMA_ADDRESS) | |
49dce689 | 551 | dma_unmap_single(master->dev.parent, xfer->rx_dma, |
754ce4f2 HS |
552 | xfer->len, DMA_FROM_DEVICE); |
553 | } | |
554 | ||
555 | static void | |
556 | atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as, | |
defbd3b4 | 557 | struct spi_message *msg, int status, int stay) |
754ce4f2 | 558 | { |
defbd3b4 DB |
559 | if (!stay || status < 0) |
560 | cs_deactivate(as, msg->spi); | |
561 | else | |
562 | as->stay = msg->spi; | |
563 | ||
754ce4f2 HS |
564 | list_del(&msg->queue); |
565 | msg->status = status; | |
566 | ||
49dce689 | 567 | dev_dbg(master->dev.parent, |
754ce4f2 HS |
568 | "xfer complete: %u bytes transferred\n", |
569 | msg->actual_length); | |
570 | ||
571 | spin_unlock(&as->lock); | |
572 | msg->complete(msg->context); | |
573 | spin_lock(&as->lock); | |
574 | ||
575 | as->current_transfer = NULL; | |
154443c7 | 576 | as->next_transfer = NULL; |
754ce4f2 HS |
577 | |
578 | /* continue if needed */ | |
579 | if (list_empty(&as->queue) || as->stopping) | |
580 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
581 | else | |
582 | atmel_spi_next_message(master); | |
583 | } | |
584 | ||
585 | static irqreturn_t | |
586 | atmel_spi_interrupt(int irq, void *dev_id) | |
587 | { | |
588 | struct spi_master *master = dev_id; | |
589 | struct atmel_spi *as = spi_master_get_devdata(master); | |
590 | struct spi_message *msg; | |
591 | struct spi_transfer *xfer; | |
592 | u32 status, pending, imr; | |
593 | int ret = IRQ_NONE; | |
594 | ||
595 | spin_lock(&as->lock); | |
596 | ||
597 | xfer = as->current_transfer; | |
598 | msg = list_entry(as->queue.next, struct spi_message, queue); | |
599 | ||
600 | imr = spi_readl(as, IMR); | |
601 | status = spi_readl(as, SR); | |
602 | pending = status & imr; | |
603 | ||
604 | if (pending & SPI_BIT(OVRES)) { | |
605 | int timeout; | |
606 | ||
607 | ret = IRQ_HANDLED; | |
608 | ||
dc329442 | 609 | spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) |
754ce4f2 HS |
610 | | SPI_BIT(OVRES))); |
611 | ||
612 | /* | |
613 | * When we get an overrun, we disregard the current | |
614 | * transfer. Data will not be copied back from any | |
615 | * bounce buffer and msg->actual_len will not be | |
616 | * updated with the last xfer. | |
617 | * | |
618 | * We will also not process any remaning transfers in | |
619 | * the message. | |
620 | * | |
621 | * First, stop the transfer and unmap the DMA buffers. | |
622 | */ | |
623 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
624 | if (!msg->is_dma_mapped) | |
625 | atmel_spi_dma_unmap_xfer(master, xfer); | |
626 | ||
627 | /* REVISIT: udelay in irq is unfriendly */ | |
628 | if (xfer->delay_usecs) | |
629 | udelay(xfer->delay_usecs); | |
630 | ||
dc329442 | 631 | dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n", |
754ce4f2 HS |
632 | spi_readl(as, TCR), spi_readl(as, RCR)); |
633 | ||
634 | /* | |
635 | * Clean up DMA registers and make sure the data | |
636 | * registers are empty. | |
637 | */ | |
638 | spi_writel(as, RNCR, 0); | |
639 | spi_writel(as, TNCR, 0); | |
640 | spi_writel(as, RCR, 0); | |
641 | spi_writel(as, TCR, 0); | |
642 | for (timeout = 1000; timeout; timeout--) | |
643 | if (spi_readl(as, SR) & SPI_BIT(TXEMPTY)) | |
644 | break; | |
645 | if (!timeout) | |
49dce689 | 646 | dev_warn(master->dev.parent, |
754ce4f2 HS |
647 | "timeout waiting for TXEMPTY"); |
648 | while (spi_readl(as, SR) & SPI_BIT(RDRF)) | |
649 | spi_readl(as, RDR); | |
650 | ||
651 | /* Clear any overrun happening while cleaning up */ | |
652 | spi_readl(as, SR); | |
653 | ||
defbd3b4 | 654 | atmel_spi_msg_done(master, as, msg, -EIO, 0); |
dc329442 | 655 | } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) { |
754ce4f2 HS |
656 | ret = IRQ_HANDLED; |
657 | ||
658 | spi_writel(as, IDR, pending); | |
659 | ||
154443c7 | 660 | if (as->current_remaining_bytes == 0) { |
754ce4f2 HS |
661 | msg->actual_length += xfer->len; |
662 | ||
663 | if (!msg->is_dma_mapped) | |
664 | atmel_spi_dma_unmap_xfer(master, xfer); | |
665 | ||
666 | /* REVISIT: udelay in irq is unfriendly */ | |
667 | if (xfer->delay_usecs) | |
668 | udelay(xfer->delay_usecs); | |
669 | ||
154443c7 | 670 | if (atmel_spi_xfer_is_last(msg, xfer)) { |
754ce4f2 | 671 | /* report completed message */ |
defbd3b4 DB |
672 | atmel_spi_msg_done(master, as, msg, 0, |
673 | xfer->cs_change); | |
754ce4f2 HS |
674 | } else { |
675 | if (xfer->cs_change) { | |
defbd3b4 | 676 | cs_deactivate(as, msg->spi); |
754ce4f2 | 677 | udelay(1); |
defbd3b4 | 678 | cs_activate(as, msg->spi); |
754ce4f2 HS |
679 | } |
680 | ||
681 | /* | |
682 | * Not done yet. Submit the next transfer. | |
683 | * | |
684 | * FIXME handle protocol options for xfer | |
685 | */ | |
686 | atmel_spi_next_xfer(master, msg); | |
687 | } | |
688 | } else { | |
689 | /* | |
690 | * Keep going, we still have data to send in | |
691 | * the current transfer. | |
692 | */ | |
693 | atmel_spi_next_xfer(master, msg); | |
694 | } | |
695 | } | |
696 | ||
697 | spin_unlock(&as->lock); | |
698 | ||
699 | return ret; | |
700 | } | |
701 | ||
754ce4f2 HS |
702 | static int atmel_spi_setup(struct spi_device *spi) |
703 | { | |
704 | struct atmel_spi *as; | |
5ee36c98 | 705 | struct atmel_spi_device *asd; |
754ce4f2 HS |
706 | u32 scbr, csr; |
707 | unsigned int bits = spi->bits_per_word; | |
592e7bf8 | 708 | unsigned long bus_hz; |
754ce4f2 HS |
709 | unsigned int npcs_pin; |
710 | int ret; | |
711 | ||
712 | as = spi_master_get_devdata(spi->master); | |
713 | ||
714 | if (as->stopping) | |
715 | return -ESHUTDOWN; | |
716 | ||
717 | if (spi->chip_select > spi->master->num_chipselect) { | |
718 | dev_dbg(&spi->dev, | |
719 | "setup: invalid chipselect %u (%u defined)\n", | |
720 | spi->chip_select, spi->master->num_chipselect); | |
721 | return -EINVAL; | |
722 | } | |
723 | ||
754ce4f2 HS |
724 | if (bits < 8 || bits > 16) { |
725 | dev_dbg(&spi->dev, | |
726 | "setup: invalid bits_per_word %u (8 to 16)\n", | |
727 | bits); | |
728 | return -EINVAL; | |
729 | } | |
730 | ||
defbd3b4 | 731 | /* see notes above re chipselect */ |
d4820b74 | 732 | if (!atmel_spi_is_v2(as) |
defbd3b4 DB |
733 | && spi->chip_select == 0 |
734 | && (spi->mode & SPI_CS_HIGH)) { | |
735 | dev_dbg(&spi->dev, "setup: can't be active-high\n"); | |
736 | return -EINVAL; | |
737 | } | |
738 | ||
5bfa26ca | 739 | /* v1 chips start out at half the peripheral bus speed. */ |
754ce4f2 | 740 | bus_hz = clk_get_rate(as->clk); |
d4820b74 | 741 | if (!atmel_spi_is_v2(as)) |
592e7bf8 HS |
742 | bus_hz /= 2; |
743 | ||
754ce4f2 | 744 | if (spi->max_speed_hz) { |
592e7bf8 HS |
745 | /* |
746 | * Calculate the lowest divider that satisfies the | |
747 | * constraint, assuming div32/fdiv/mbz == 0. | |
748 | */ | |
749 | scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz); | |
750 | ||
751 | /* | |
752 | * If the resulting divider doesn't fit into the | |
753 | * register bitfield, we can't satisfy the constraint. | |
754 | */ | |
754ce4f2 | 755 | if (scbr >= (1 << SPI_SCBR_SIZE)) { |
8da0859a DB |
756 | dev_dbg(&spi->dev, |
757 | "setup: %d Hz too slow, scbr %u; min %ld Hz\n", | |
758 | spi->max_speed_hz, scbr, bus_hz/255); | |
754ce4f2 HS |
759 | return -EINVAL; |
760 | } | |
761 | } else | |
592e7bf8 | 762 | /* speed zero means "as slow as possible" */ |
754ce4f2 | 763 | scbr = 0xff; |
754ce4f2 HS |
764 | |
765 | csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8); | |
766 | if (spi->mode & SPI_CPOL) | |
767 | csr |= SPI_BIT(CPOL); | |
768 | if (!(spi->mode & SPI_CPHA)) | |
769 | csr |= SPI_BIT(NCPHA); | |
770 | ||
1eed29df HS |
771 | /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs. |
772 | * | |
773 | * DLYBCT would add delays between words, slowing down transfers. | |
774 | * It could potentially be useful to cope with DMA bottlenecks, but | |
775 | * in those cases it's probably best to just use a lower bitrate. | |
776 | */ | |
777 | csr |= SPI_BF(DLYBS, 0); | |
778 | csr |= SPI_BF(DLYBCT, 0); | |
754ce4f2 HS |
779 | |
780 | /* chipselect must have been muxed as GPIO (e.g. in board setup) */ | |
781 | npcs_pin = (unsigned int)spi->controller_data; | |
850a5b67 JCPV |
782 | |
783 | if (gpio_is_valid(spi->cs_gpio)) | |
784 | npcs_pin = spi->cs_gpio; | |
785 | ||
5ee36c98 HS |
786 | asd = spi->controller_state; |
787 | if (!asd) { | |
788 | asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL); | |
789 | if (!asd) | |
790 | return -ENOMEM; | |
791 | ||
6c7377ab | 792 | ret = gpio_request(npcs_pin, dev_name(&spi->dev)); |
5ee36c98 HS |
793 | if (ret) { |
794 | kfree(asd); | |
754ce4f2 | 795 | return ret; |
5ee36c98 HS |
796 | } |
797 | ||
798 | asd->npcs_pin = npcs_pin; | |
799 | spi->controller_state = asd; | |
28735a72 | 800 | gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH)); |
defbd3b4 DB |
801 | } else { |
802 | unsigned long flags; | |
803 | ||
804 | spin_lock_irqsave(&as->lock, flags); | |
805 | if (as->stay == spi) | |
806 | as->stay = NULL; | |
807 | cs_deactivate(as, spi); | |
808 | spin_unlock_irqrestore(&as->lock, flags); | |
754ce4f2 HS |
809 | } |
810 | ||
5ee36c98 HS |
811 | asd->csr = csr; |
812 | ||
754ce4f2 HS |
813 | dev_dbg(&spi->dev, |
814 | "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n", | |
592e7bf8 | 815 | bus_hz / scbr, bits, spi->mode, spi->chip_select, csr); |
754ce4f2 | 816 | |
d4820b74 | 817 | if (!atmel_spi_is_v2(as)) |
5ee36c98 | 818 | spi_writel(as, CSR0 + 4 * spi->chip_select, csr); |
754ce4f2 HS |
819 | |
820 | return 0; | |
821 | } | |
822 | ||
823 | static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg) | |
824 | { | |
825 | struct atmel_spi *as; | |
826 | struct spi_transfer *xfer; | |
827 | unsigned long flags; | |
49dce689 | 828 | struct device *controller = spi->master->dev.parent; |
b9d228f9 MB |
829 | u8 bits; |
830 | struct atmel_spi_device *asd; | |
754ce4f2 HS |
831 | |
832 | as = spi_master_get_devdata(spi->master); | |
833 | ||
834 | dev_dbg(controller, "new message %p submitted for %s\n", | |
6c7377ab | 835 | msg, dev_name(&spi->dev)); |
754ce4f2 | 836 | |
5b96f172 | 837 | if (unlikely(list_empty(&msg->transfers))) |
754ce4f2 HS |
838 | return -EINVAL; |
839 | ||
840 | if (as->stopping) | |
841 | return -ESHUTDOWN; | |
842 | ||
843 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
06719814 | 844 | if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) { |
754ce4f2 HS |
845 | dev_dbg(&spi->dev, "missing rx or tx buf\n"); |
846 | return -EINVAL; | |
847 | } | |
848 | ||
b9d228f9 MB |
849 | if (xfer->bits_per_word) { |
850 | asd = spi->controller_state; | |
851 | bits = (asd->csr >> 4) & 0xf; | |
852 | if (bits != xfer->bits_per_word - 8) { | |
853 | dev_dbg(&spi->dev, "you can't yet change " | |
ee2007d2 | 854 | "bits_per_word in transfers\n"); |
b9d228f9 MB |
855 | return -ENOPROTOOPT; |
856 | } | |
857 | } | |
858 | ||
754ce4f2 | 859 | /* FIXME implement these protocol options!! */ |
b9d228f9 | 860 | if (xfer->speed_hz) { |
754ce4f2 HS |
861 | dev_dbg(&spi->dev, "no protocol options yet\n"); |
862 | return -ENOPROTOOPT; | |
863 | } | |
754ce4f2 | 864 | |
8da0859a DB |
865 | /* |
866 | * DMA map early, for performance (empties dcache ASAP) and | |
867 | * better fault reporting. This is a DMA-only driver. | |
868 | * | |
869 | * NOTE that if dma_unmap_single() ever starts to do work on | |
870 | * platforms supported by this driver, we would need to clean | |
871 | * up mappings for previously-mapped transfers. | |
872 | */ | |
873 | if (!msg->is_dma_mapped) { | |
874 | if (atmel_spi_dma_map_xfer(as, xfer) < 0) | |
875 | return -ENOMEM; | |
876 | } | |
754ce4f2 HS |
877 | } |
878 | ||
defbd3b4 | 879 | #ifdef VERBOSE |
754ce4f2 HS |
880 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
881 | dev_dbg(controller, | |
882 | " xfer %p: len %u tx %p/%08x rx %p/%08x\n", | |
883 | xfer, xfer->len, | |
884 | xfer->tx_buf, xfer->tx_dma, | |
885 | xfer->rx_buf, xfer->rx_dma); | |
886 | } | |
defbd3b4 | 887 | #endif |
754ce4f2 HS |
888 | |
889 | msg->status = -EINPROGRESS; | |
890 | msg->actual_length = 0; | |
891 | ||
892 | spin_lock_irqsave(&as->lock, flags); | |
893 | list_add_tail(&msg->queue, &as->queue); | |
894 | if (!as->current_transfer) | |
895 | atmel_spi_next_message(spi->master); | |
896 | spin_unlock_irqrestore(&as->lock, flags); | |
897 | ||
898 | return 0; | |
899 | } | |
900 | ||
bb2d1c36 | 901 | static void atmel_spi_cleanup(struct spi_device *spi) |
754ce4f2 | 902 | { |
defbd3b4 | 903 | struct atmel_spi *as = spi_master_get_devdata(spi->master); |
5ee36c98 | 904 | struct atmel_spi_device *asd = spi->controller_state; |
defbd3b4 DB |
905 | unsigned gpio = (unsigned) spi->controller_data; |
906 | unsigned long flags; | |
907 | ||
5ee36c98 | 908 | if (!asd) |
defbd3b4 DB |
909 | return; |
910 | ||
911 | spin_lock_irqsave(&as->lock, flags); | |
912 | if (as->stay == spi) { | |
913 | as->stay = NULL; | |
914 | cs_deactivate(as, spi); | |
915 | } | |
916 | spin_unlock_irqrestore(&as->lock, flags); | |
917 | ||
5ee36c98 | 918 | spi->controller_state = NULL; |
defbd3b4 | 919 | gpio_free(gpio); |
5ee36c98 | 920 | kfree(asd); |
754ce4f2 HS |
921 | } |
922 | ||
d4820b74 WY |
923 | static inline unsigned int atmel_get_version(struct atmel_spi *as) |
924 | { | |
925 | return spi_readl(as, VERSION) & 0x00000fff; | |
926 | } | |
927 | ||
928 | static void atmel_get_caps(struct atmel_spi *as) | |
929 | { | |
930 | unsigned int version; | |
931 | ||
932 | version = atmel_get_version(as); | |
933 | dev_info(&as->pdev->dev, "version: 0x%x\n", version); | |
934 | ||
935 | as->caps.is_spi2 = version > 0x121; | |
936 | as->caps.has_wdrbt = version >= 0x210; | |
937 | as->caps.has_dma_support = version >= 0x212; | |
938 | } | |
939 | ||
754ce4f2 HS |
940 | /*-------------------------------------------------------------------------*/ |
941 | ||
fd4a319b | 942 | static int atmel_spi_probe(struct platform_device *pdev) |
754ce4f2 HS |
943 | { |
944 | struct resource *regs; | |
945 | int irq; | |
946 | struct clk *clk; | |
947 | int ret; | |
948 | struct spi_master *master; | |
949 | struct atmel_spi *as; | |
950 | ||
951 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
952 | if (!regs) | |
953 | return -ENXIO; | |
954 | ||
955 | irq = platform_get_irq(pdev, 0); | |
956 | if (irq < 0) | |
957 | return irq; | |
958 | ||
959 | clk = clk_get(&pdev->dev, "spi_clk"); | |
960 | if (IS_ERR(clk)) | |
961 | return PTR_ERR(clk); | |
962 | ||
963 | /* setup spi core then atmel-specific driver state */ | |
964 | ret = -ENOMEM; | |
965 | master = spi_alloc_master(&pdev->dev, sizeof *as); | |
966 | if (!master) | |
967 | goto out_free; | |
968 | ||
e7db06b5 DB |
969 | /* the spi->mode bits understood by this driver: */ |
970 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
971 | ||
850a5b67 | 972 | master->dev.of_node = pdev->dev.of_node; |
754ce4f2 | 973 | master->bus_num = pdev->id; |
850a5b67 | 974 | master->num_chipselect = master->dev.of_node ? 0 : 4; |
754ce4f2 HS |
975 | master->setup = atmel_spi_setup; |
976 | master->transfer = atmel_spi_transfer; | |
977 | master->cleanup = atmel_spi_cleanup; | |
978 | platform_set_drvdata(pdev, master); | |
979 | ||
980 | as = spi_master_get_devdata(master); | |
981 | ||
8da0859a DB |
982 | /* |
983 | * Scratch buffer is used for throwaway rx and tx data. | |
984 | * It's coherent to minimize dcache pollution. | |
985 | */ | |
754ce4f2 HS |
986 | as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE, |
987 | &as->buffer_dma, GFP_KERNEL); | |
988 | if (!as->buffer) | |
989 | goto out_free; | |
990 | ||
991 | spin_lock_init(&as->lock); | |
992 | INIT_LIST_HEAD(&as->queue); | |
993 | as->pdev = pdev; | |
905aa0ae | 994 | as->regs = ioremap(regs->start, resource_size(regs)); |
754ce4f2 HS |
995 | if (!as->regs) |
996 | goto out_free_buffer; | |
997 | as->irq = irq; | |
998 | as->clk = clk; | |
754ce4f2 | 999 | |
d4820b74 WY |
1000 | atmel_get_caps(as); |
1001 | ||
754ce4f2 | 1002 | ret = request_irq(irq, atmel_spi_interrupt, 0, |
6c7377ab | 1003 | dev_name(&pdev->dev), master); |
754ce4f2 HS |
1004 | if (ret) |
1005 | goto out_unmap_regs; | |
1006 | ||
1007 | /* Initialize the hardware */ | |
1008 | clk_enable(clk); | |
1009 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
50d7d5bf | 1010 | spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ |
d4820b74 WY |
1011 | if (as->caps.has_wdrbt) { |
1012 | spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS) | |
1013 | | SPI_BIT(MSTR)); | |
1014 | } else { | |
1015 | spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); | |
1016 | } | |
754ce4f2 HS |
1017 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); |
1018 | spi_writel(as, CR, SPI_BIT(SPIEN)); | |
1019 | ||
1020 | /* go! */ | |
1021 | dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n", | |
1022 | (unsigned long)regs->start, irq); | |
1023 | ||
1024 | ret = spi_register_master(master); | |
1025 | if (ret) | |
1026 | goto out_reset_hw; | |
1027 | ||
1028 | return 0; | |
1029 | ||
1030 | out_reset_hw: | |
1031 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
50d7d5bf | 1032 | spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ |
754ce4f2 HS |
1033 | clk_disable(clk); |
1034 | free_irq(irq, master); | |
1035 | out_unmap_regs: | |
1036 | iounmap(as->regs); | |
1037 | out_free_buffer: | |
1038 | dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, | |
1039 | as->buffer_dma); | |
1040 | out_free: | |
1041 | clk_put(clk); | |
1042 | spi_master_put(master); | |
1043 | return ret; | |
1044 | } | |
1045 | ||
fd4a319b | 1046 | static int atmel_spi_remove(struct platform_device *pdev) |
754ce4f2 HS |
1047 | { |
1048 | struct spi_master *master = platform_get_drvdata(pdev); | |
1049 | struct atmel_spi *as = spi_master_get_devdata(master); | |
1050 | struct spi_message *msg; | |
1051 | ||
1052 | /* reset the hardware and block queue progress */ | |
1053 | spin_lock_irq(&as->lock); | |
1054 | as->stopping = 1; | |
1055 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
50d7d5bf | 1056 | spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ |
754ce4f2 HS |
1057 | spi_readl(as, SR); |
1058 | spin_unlock_irq(&as->lock); | |
1059 | ||
1060 | /* Terminate remaining queued transfers */ | |
1061 | list_for_each_entry(msg, &as->queue, queue) { | |
1062 | /* REVISIT unmapping the dma is a NOP on ARM and AVR32 | |
1063 | * but we shouldn't depend on that... | |
1064 | */ | |
1065 | msg->status = -ESHUTDOWN; | |
1066 | msg->complete(msg->context); | |
1067 | } | |
1068 | ||
1069 | dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, | |
1070 | as->buffer_dma); | |
1071 | ||
1072 | clk_disable(as->clk); | |
1073 | clk_put(as->clk); | |
1074 | free_irq(as->irq, master); | |
1075 | iounmap(as->regs); | |
1076 | ||
1077 | spi_unregister_master(master); | |
1078 | ||
1079 | return 0; | |
1080 | } | |
1081 | ||
1082 | #ifdef CONFIG_PM | |
1083 | ||
1084 | static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg) | |
1085 | { | |
1086 | struct spi_master *master = platform_get_drvdata(pdev); | |
1087 | struct atmel_spi *as = spi_master_get_devdata(master); | |
1088 | ||
1089 | clk_disable(as->clk); | |
1090 | return 0; | |
1091 | } | |
1092 | ||
1093 | static int atmel_spi_resume(struct platform_device *pdev) | |
1094 | { | |
1095 | struct spi_master *master = platform_get_drvdata(pdev); | |
1096 | struct atmel_spi *as = spi_master_get_devdata(master); | |
1097 | ||
1098 | clk_enable(as->clk); | |
1099 | return 0; | |
1100 | } | |
1101 | ||
1102 | #else | |
1103 | #define atmel_spi_suspend NULL | |
1104 | #define atmel_spi_resume NULL | |
1105 | #endif | |
1106 | ||
850a5b67 JCPV |
1107 | #if defined(CONFIG_OF) |
1108 | static const struct of_device_id atmel_spi_dt_ids[] = { | |
1109 | { .compatible = "atmel,at91rm9200-spi" }, | |
1110 | { /* sentinel */ } | |
1111 | }; | |
1112 | ||
1113 | MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids); | |
1114 | #endif | |
754ce4f2 HS |
1115 | |
1116 | static struct platform_driver atmel_spi_driver = { | |
1117 | .driver = { | |
1118 | .name = "atmel_spi", | |
1119 | .owner = THIS_MODULE, | |
850a5b67 | 1120 | .of_match_table = of_match_ptr(atmel_spi_dt_ids), |
754ce4f2 HS |
1121 | }, |
1122 | .suspend = atmel_spi_suspend, | |
1123 | .resume = atmel_spi_resume, | |
1cb201af | 1124 | .probe = atmel_spi_probe, |
2deff8d6 | 1125 | .remove = atmel_spi_remove, |
754ce4f2 | 1126 | }; |
940ab889 | 1127 | module_platform_driver(atmel_spi_driver); |
754ce4f2 HS |
1128 | |
1129 | MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver"); | |
e05503ef | 1130 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
754ce4f2 | 1131 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 1132 | MODULE_ALIAS("platform:atmel_spi"); |