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fa236a7e KD |
1 | /* |
2 | * Driver for Broadcom BRCMSTB, NSP, NS2, Cygnus SPI Controllers | |
3 | * | |
4 | * Copyright 2016 Broadcom | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License, version 2, as | |
8 | * published by the Free Software Foundation (the "GPL"). | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License version 2 (GPLv2) for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * version 2 (GPLv2) along with this source code. | |
17 | */ | |
18 | ||
19 | #include <linux/clk.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/device.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/io.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
fa236a7e KD |
28 | #include <linux/mtd/spi-nor.h> |
29 | #include <linux/of.h> | |
30 | #include <linux/of_irq.h> | |
31 | #include <linux/platform_device.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/spi/spi.h> | |
34 | #include <linux/sysfs.h> | |
35 | #include <linux/types.h> | |
36 | #include "spi-bcm-qspi.h" | |
37 | ||
38 | #define DRIVER_NAME "bcm_qspi" | |
39 | ||
4e3b2d23 KD |
40 | |
41 | /* BSPI register offsets */ | |
42 | #define BSPI_REVISION_ID 0x000 | |
43 | #define BSPI_SCRATCH 0x004 | |
44 | #define BSPI_MAST_N_BOOT_CTRL 0x008 | |
45 | #define BSPI_BUSY_STATUS 0x00c | |
46 | #define BSPI_INTR_STATUS 0x010 | |
47 | #define BSPI_B0_STATUS 0x014 | |
48 | #define BSPI_B0_CTRL 0x018 | |
49 | #define BSPI_B1_STATUS 0x01c | |
50 | #define BSPI_B1_CTRL 0x020 | |
51 | #define BSPI_STRAP_OVERRIDE_CTRL 0x024 | |
52 | #define BSPI_FLEX_MODE_ENABLE 0x028 | |
53 | #define BSPI_BITS_PER_CYCLE 0x02c | |
54 | #define BSPI_BITS_PER_PHASE 0x030 | |
55 | #define BSPI_CMD_AND_MODE_BYTE 0x034 | |
56 | #define BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038 | |
57 | #define BSPI_BSPI_XOR_VALUE 0x03c | |
58 | #define BSPI_BSPI_XOR_ENABLE 0x040 | |
59 | #define BSPI_BSPI_PIO_MODE_ENABLE 0x044 | |
60 | #define BSPI_BSPI_PIO_IODIR 0x048 | |
61 | #define BSPI_BSPI_PIO_DATA 0x04c | |
62 | ||
63 | /* RAF register offsets */ | |
64 | #define BSPI_RAF_START_ADDR 0x100 | |
65 | #define BSPI_RAF_NUM_WORDS 0x104 | |
66 | #define BSPI_RAF_CTRL 0x108 | |
67 | #define BSPI_RAF_FULLNESS 0x10c | |
68 | #define BSPI_RAF_WATERMARK 0x110 | |
69 | #define BSPI_RAF_STATUS 0x114 | |
70 | #define BSPI_RAF_READ_DATA 0x118 | |
71 | #define BSPI_RAF_WORD_CNT 0x11c | |
72 | #define BSPI_RAF_CURR_ADDR 0x120 | |
73 | ||
74 | /* Override mode masks */ | |
75 | #define BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE BIT(0) | |
76 | #define BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL BIT(1) | |
77 | #define BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE BIT(2) | |
78 | #define BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD BIT(3) | |
79 | #define BSPI_STRAP_OVERRIDE_CTRL_ENDAIN_MODE BIT(4) | |
80 | ||
81 | #define BSPI_ADDRLEN_3BYTES 3 | |
82 | #define BSPI_ADDRLEN_4BYTES 4 | |
83 | ||
84 | #define BSPI_RAF_STATUS_FIFO_EMPTY_MASK BIT(1) | |
85 | ||
86 | #define BSPI_RAF_CTRL_START_MASK BIT(0) | |
87 | #define BSPI_RAF_CTRL_CLEAR_MASK BIT(1) | |
88 | ||
89 | #define BSPI_BPP_MODE_SELECT_MASK BIT(8) | |
90 | #define BSPI_BPP_ADDR_SELECT_MASK BIT(16) | |
91 | ||
92 | #define BSPI_READ_LENGTH 256 | |
93 | ||
fa236a7e KD |
94 | /* MSPI register offsets */ |
95 | #define MSPI_SPCR0_LSB 0x000 | |
96 | #define MSPI_SPCR0_MSB 0x004 | |
97 | #define MSPI_SPCR1_LSB 0x008 | |
98 | #define MSPI_SPCR1_MSB 0x00c | |
99 | #define MSPI_NEWQP 0x010 | |
100 | #define MSPI_ENDQP 0x014 | |
101 | #define MSPI_SPCR2 0x018 | |
102 | #define MSPI_MSPI_STATUS 0x020 | |
103 | #define MSPI_CPTQP 0x024 | |
104 | #define MSPI_SPCR3 0x028 | |
105 | #define MSPI_TXRAM 0x040 | |
106 | #define MSPI_RXRAM 0x0c0 | |
107 | #define MSPI_CDRAM 0x140 | |
108 | #define MSPI_WRITE_LOCK 0x180 | |
109 | ||
110 | #define MSPI_MASTER_BIT BIT(7) | |
111 | ||
112 | #define MSPI_NUM_CDRAM 16 | |
113 | #define MSPI_CDRAM_CONT_BIT BIT(7) | |
114 | #define MSPI_CDRAM_BITSE_BIT BIT(6) | |
115 | #define MSPI_CDRAM_PCS 0xf | |
116 | ||
117 | #define MSPI_SPCR2_SPE BIT(6) | |
118 | #define MSPI_SPCR2_CONT_AFTER_CMD BIT(7) | |
119 | ||
120 | #define MSPI_MSPI_STATUS_SPIF BIT(0) | |
121 | ||
122 | #define INTR_BASE_BIT_SHIFT 0x02 | |
123 | #define INTR_COUNT 0x07 | |
124 | ||
125 | #define NUM_CHIPSELECT 4 | |
126 | #define QSPI_SPBR_MIN 8U | |
127 | #define QSPI_SPBR_MAX 255U | |
128 | ||
129 | #define OPCODE_DIOR 0xBB | |
130 | #define OPCODE_QIOR 0xEB | |
131 | #define OPCODE_DIOR_4B 0xBC | |
132 | #define OPCODE_QIOR_4B 0xEC | |
133 | ||
134 | #define MAX_CMD_SIZE 6 | |
135 | ||
136 | #define ADDR_4MB_MASK GENMASK(22, 0) | |
137 | ||
138 | /* stop at end of transfer, no other reason */ | |
139 | #define TRANS_STATUS_BREAK_NONE 0 | |
140 | /* stop at end of spi_message */ | |
141 | #define TRANS_STATUS_BREAK_EOM 1 | |
142 | /* stop at end of spi_transfer if delay */ | |
143 | #define TRANS_STATUS_BREAK_DELAY 2 | |
144 | /* stop at end of spi_transfer if cs_change */ | |
145 | #define TRANS_STATUS_BREAK_CS_CHANGE 4 | |
146 | /* stop if we run out of bytes */ | |
147 | #define TRANS_STATUS_BREAK_NO_BYTES 8 | |
148 | ||
149 | /* events that make us stop filling TX slots */ | |
150 | #define TRANS_STATUS_BREAK_TX (TRANS_STATUS_BREAK_EOM | \ | |
151 | TRANS_STATUS_BREAK_DELAY | \ | |
152 | TRANS_STATUS_BREAK_CS_CHANGE) | |
153 | ||
154 | /* events that make us deassert CS */ | |
155 | #define TRANS_STATUS_BREAK_DESELECT (TRANS_STATUS_BREAK_EOM | \ | |
156 | TRANS_STATUS_BREAK_CS_CHANGE) | |
157 | ||
158 | struct bcm_qspi_parms { | |
159 | u32 speed_hz; | |
160 | u8 mode; | |
161 | u8 bits_per_word; | |
162 | }; | |
163 | ||
4e3b2d23 KD |
164 | struct bcm_xfer_mode { |
165 | bool flex_mode; | |
166 | unsigned int width; | |
167 | unsigned int addrlen; | |
168 | unsigned int hp; | |
169 | }; | |
170 | ||
fa236a7e KD |
171 | enum base_type { |
172 | MSPI, | |
4e3b2d23 | 173 | BSPI, |
fa236a7e KD |
174 | CHIP_SELECT, |
175 | BASEMAX, | |
176 | }; | |
177 | ||
cc20a386 KD |
178 | enum irq_source { |
179 | SINGLE_L2, | |
180 | MUXED_L1, | |
181 | }; | |
182 | ||
fa236a7e KD |
183 | struct bcm_qspi_irq { |
184 | const char *irq_name; | |
185 | const irq_handler_t irq_handler; | |
cc20a386 | 186 | int irq_source; |
fa236a7e KD |
187 | u32 mask; |
188 | }; | |
189 | ||
190 | struct bcm_qspi_dev_id { | |
191 | const struct bcm_qspi_irq *irqp; | |
192 | void *dev; | |
193 | }; | |
194 | ||
195 | struct qspi_trans { | |
196 | struct spi_transfer *trans; | |
197 | int byte; | |
198 | }; | |
199 | ||
200 | struct bcm_qspi { | |
201 | struct platform_device *pdev; | |
202 | struct spi_master *master; | |
203 | struct clk *clk; | |
204 | u32 base_clk; | |
205 | u32 max_speed_hz; | |
206 | void __iomem *base[BASEMAX]; | |
cc20a386 KD |
207 | |
208 | /* Some SoCs provide custom interrupt status register(s) */ | |
209 | struct bcm_qspi_soc_intc *soc_intc; | |
210 | ||
fa236a7e KD |
211 | struct bcm_qspi_parms last_parms; |
212 | struct qspi_trans trans_pos; | |
213 | int curr_cs; | |
4e3b2d23 KD |
214 | int bspi_maj_rev; |
215 | int bspi_min_rev; | |
216 | int bspi_enabled; | |
217 | struct spi_flash_read_message *bspi_rf_msg; | |
218 | u32 bspi_rf_msg_idx; | |
219 | u32 bspi_rf_msg_len; | |
220 | u32 bspi_rf_msg_status; | |
221 | struct bcm_xfer_mode xfer_mode; | |
fa236a7e | 222 | u32 s3_strap_override_ctrl; |
4e3b2d23 | 223 | bool bspi_mode; |
fa236a7e KD |
224 | bool big_endian; |
225 | int num_irqs; | |
226 | struct bcm_qspi_dev_id *dev_ids; | |
227 | struct completion mspi_done; | |
4e3b2d23 | 228 | struct completion bspi_done; |
fa236a7e KD |
229 | }; |
230 | ||
4e3b2d23 KD |
231 | static inline bool has_bspi(struct bcm_qspi *qspi) |
232 | { | |
233 | return qspi->bspi_mode; | |
234 | } | |
235 | ||
fa236a7e KD |
236 | /* Read qspi controller register*/ |
237 | static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type, | |
238 | unsigned int offset) | |
239 | { | |
240 | return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset); | |
241 | } | |
242 | ||
243 | /* Write qspi controller register*/ | |
244 | static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type, | |
245 | unsigned int offset, unsigned int data) | |
246 | { | |
247 | bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset); | |
248 | } | |
249 | ||
4e3b2d23 KD |
250 | /* BSPI helpers */ |
251 | static int bcm_qspi_bspi_busy_poll(struct bcm_qspi *qspi) | |
252 | { | |
253 | int i; | |
254 | ||
255 | /* this should normally finish within 10us */ | |
256 | for (i = 0; i < 1000; i++) { | |
257 | if (!(bcm_qspi_read(qspi, BSPI, BSPI_BUSY_STATUS) & 1)) | |
258 | return 0; | |
259 | udelay(1); | |
260 | } | |
261 | dev_warn(&qspi->pdev->dev, "timeout waiting for !busy_status\n"); | |
262 | return -EIO; | |
263 | } | |
264 | ||
265 | static inline bool bcm_qspi_bspi_ver_three(struct bcm_qspi *qspi) | |
266 | { | |
267 | if (qspi->bspi_maj_rev < 4) | |
268 | return true; | |
269 | return false; | |
270 | } | |
271 | ||
272 | static void bcm_qspi_bspi_flush_prefetch_buffers(struct bcm_qspi *qspi) | |
273 | { | |
274 | bcm_qspi_bspi_busy_poll(qspi); | |
275 | /* Force rising edge for the b0/b1 'flush' field */ | |
276 | bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 1); | |
277 | bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 1); | |
278 | bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0); | |
279 | bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0); | |
280 | } | |
281 | ||
282 | static int bcm_qspi_bspi_lr_is_fifo_empty(struct bcm_qspi *qspi) | |
283 | { | |
284 | return (bcm_qspi_read(qspi, BSPI, BSPI_RAF_STATUS) & | |
285 | BSPI_RAF_STATUS_FIFO_EMPTY_MASK); | |
286 | } | |
287 | ||
288 | static inline u32 bcm_qspi_bspi_lr_read_fifo(struct bcm_qspi *qspi) | |
289 | { | |
290 | u32 data = bcm_qspi_read(qspi, BSPI, BSPI_RAF_READ_DATA); | |
291 | ||
292 | /* BSPI v3 LR is LE only, convert data to host endianness */ | |
293 | if (bcm_qspi_bspi_ver_three(qspi)) | |
294 | data = le32_to_cpu(data); | |
295 | ||
296 | return data; | |
297 | } | |
298 | ||
299 | static inline void bcm_qspi_bspi_lr_start(struct bcm_qspi *qspi) | |
300 | { | |
301 | bcm_qspi_bspi_busy_poll(qspi); | |
302 | bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL, | |
303 | BSPI_RAF_CTRL_START_MASK); | |
304 | } | |
305 | ||
306 | static inline void bcm_qspi_bspi_lr_clear(struct bcm_qspi *qspi) | |
307 | { | |
308 | bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL, | |
309 | BSPI_RAF_CTRL_CLEAR_MASK); | |
310 | bcm_qspi_bspi_flush_prefetch_buffers(qspi); | |
311 | } | |
312 | ||
313 | static void bcm_qspi_bspi_lr_data_read(struct bcm_qspi *qspi) | |
314 | { | |
315 | u32 *buf = (u32 *)qspi->bspi_rf_msg->buf; | |
316 | u32 data = 0; | |
317 | ||
318 | dev_dbg(&qspi->pdev->dev, "xfer %p rx %p rxlen %d\n", qspi->bspi_rf_msg, | |
319 | qspi->bspi_rf_msg->buf, qspi->bspi_rf_msg_len); | |
320 | while (!bcm_qspi_bspi_lr_is_fifo_empty(qspi)) { | |
321 | data = bcm_qspi_bspi_lr_read_fifo(qspi); | |
322 | if (likely(qspi->bspi_rf_msg_len >= 4) && | |
323 | IS_ALIGNED((uintptr_t)buf, 4)) { | |
324 | buf[qspi->bspi_rf_msg_idx++] = data; | |
325 | qspi->bspi_rf_msg_len -= 4; | |
326 | } else { | |
327 | /* Read out remaining bytes, make sure*/ | |
328 | u8 *cbuf = (u8 *)&buf[qspi->bspi_rf_msg_idx]; | |
329 | ||
330 | data = cpu_to_le32(data); | |
331 | while (qspi->bspi_rf_msg_len) { | |
332 | *cbuf++ = (u8)data; | |
333 | data >>= 8; | |
334 | qspi->bspi_rf_msg_len--; | |
335 | } | |
336 | } | |
337 | } | |
338 | } | |
339 | ||
340 | static void bcm_qspi_bspi_set_xfer_params(struct bcm_qspi *qspi, u8 cmd_byte, | |
341 | int bpp, int bpc, int flex_mode) | |
342 | { | |
343 | bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0); | |
344 | bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_CYCLE, bpc); | |
345 | bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_PHASE, bpp); | |
346 | bcm_qspi_write(qspi, BSPI, BSPI_CMD_AND_MODE_BYTE, cmd_byte); | |
347 | bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, flex_mode); | |
348 | } | |
349 | ||
350 | static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi, int width, | |
351 | int addrlen, int hp) | |
352 | { | |
353 | int bpc = 0, bpp = 0; | |
354 | u8 command = SPINOR_OP_READ_FAST; | |
355 | int flex_mode = 1, rv = 0; | |
356 | bool spans_4byte = false; | |
357 | ||
358 | dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n", | |
359 | width, addrlen, hp); | |
360 | ||
361 | if (addrlen == BSPI_ADDRLEN_4BYTES) { | |
362 | bpp = BSPI_BPP_ADDR_SELECT_MASK; | |
363 | spans_4byte = true; | |
364 | } | |
365 | ||
366 | bpp |= 8; | |
367 | ||
368 | switch (width) { | |
369 | case SPI_NBITS_SINGLE: | |
370 | if (addrlen == BSPI_ADDRLEN_3BYTES) | |
371 | /* default mode, does not need flex_cmd */ | |
372 | flex_mode = 0; | |
373 | else | |
374 | command = SPINOR_OP_READ4_FAST; | |
375 | break; | |
376 | case SPI_NBITS_DUAL: | |
377 | bpc = 0x00000001; | |
378 | if (hp) { | |
379 | bpc |= 0x00010100; /* address and mode are 2-bit */ | |
380 | bpp = BSPI_BPP_MODE_SELECT_MASK; | |
381 | command = OPCODE_DIOR; | |
382 | if (spans_4byte) | |
383 | command = OPCODE_DIOR_4B; | |
384 | } else { | |
385 | command = SPINOR_OP_READ_1_1_2; | |
386 | if (spans_4byte) | |
387 | command = SPINOR_OP_READ4_1_1_2; | |
388 | } | |
389 | break; | |
390 | case SPI_NBITS_QUAD: | |
391 | bpc = 0x00000002; | |
392 | if (hp) { | |
393 | bpc |= 0x00020200; /* address and mode are 4-bit */ | |
394 | bpp = 4; /* dummy cycles */ | |
395 | bpp |= BSPI_BPP_ADDR_SELECT_MASK; | |
396 | command = OPCODE_QIOR; | |
397 | if (spans_4byte) | |
398 | command = OPCODE_QIOR_4B; | |
399 | } else { | |
400 | command = SPINOR_OP_READ_1_1_4; | |
401 | if (spans_4byte) | |
402 | command = SPINOR_OP_READ4_1_1_4; | |
403 | } | |
404 | break; | |
405 | default: | |
406 | rv = -EINVAL; | |
407 | break; | |
408 | } | |
409 | ||
410 | if (rv == 0) | |
411 | bcm_qspi_bspi_set_xfer_params(qspi, command, bpp, bpc, | |
412 | flex_mode); | |
413 | ||
414 | return rv; | |
415 | } | |
416 | ||
417 | static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi, int width, | |
418 | int addrlen, int hp) | |
419 | { | |
420 | u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL); | |
421 | ||
422 | dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n", | |
423 | width, addrlen, hp); | |
424 | ||
425 | switch (width) { | |
426 | case SPI_NBITS_SINGLE: | |
427 | /* clear quad/dual mode */ | |
428 | data &= ~(BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD | | |
429 | BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL); | |
430 | break; | |
431 | ||
432 | case SPI_NBITS_QUAD: | |
433 | /* clear dual mode and set quad mode */ | |
434 | data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL; | |
435 | data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD; | |
436 | break; | |
437 | case SPI_NBITS_DUAL: | |
438 | /* clear quad mode set dual mode */ | |
439 | data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD; | |
440 | data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL; | |
441 | break; | |
442 | default: | |
443 | return -EINVAL; | |
444 | } | |
445 | ||
446 | if (addrlen == BSPI_ADDRLEN_4BYTES) | |
447 | /* set 4byte mode*/ | |
448 | data |= BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE; | |
449 | else | |
450 | /* clear 4 byte mode */ | |
451 | data &= ~BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE; | |
452 | ||
453 | /* set the override mode */ | |
454 | data |= BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE; | |
455 | bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data); | |
456 | bcm_qspi_bspi_set_xfer_params(qspi, SPINOR_OP_READ_FAST, 0, 0, 0); | |
457 | ||
458 | return 0; | |
459 | } | |
460 | ||
461 | static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi, | |
462 | int width, int addrlen, int hp) | |
463 | { | |
464 | int error = 0; | |
465 | ||
466 | /* default mode */ | |
467 | qspi->xfer_mode.flex_mode = true; | |
468 | ||
469 | if (!bcm_qspi_bspi_ver_three(qspi)) { | |
470 | u32 val, mask; | |
471 | ||
472 | val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL); | |
473 | mask = BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE; | |
474 | if (val & mask || qspi->s3_strap_override_ctrl & mask) { | |
475 | qspi->xfer_mode.flex_mode = false; | |
476 | bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, | |
477 | 0); | |
478 | ||
479 | if ((val | qspi->s3_strap_override_ctrl) & | |
480 | BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL) | |
481 | width = SPI_NBITS_DUAL; | |
482 | else if ((val | qspi->s3_strap_override_ctrl) & | |
483 | BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD) | |
484 | width = SPI_NBITS_QUAD; | |
485 | ||
486 | error = bcm_qspi_bspi_set_override(qspi, width, addrlen, | |
487 | hp); | |
488 | } | |
489 | } | |
490 | ||
491 | if (qspi->xfer_mode.flex_mode) | |
492 | error = bcm_qspi_bspi_set_flex_mode(qspi, width, addrlen, hp); | |
493 | ||
494 | if (error) { | |
495 | dev_warn(&qspi->pdev->dev, | |
496 | "INVALID COMBINATION: width=%d addrlen=%d hp=%d\n", | |
497 | width, addrlen, hp); | |
498 | } else if (qspi->xfer_mode.width != width || | |
499 | qspi->xfer_mode.addrlen != addrlen || | |
500 | qspi->xfer_mode.hp != hp) { | |
501 | qspi->xfer_mode.width = width; | |
502 | qspi->xfer_mode.addrlen = addrlen; | |
503 | qspi->xfer_mode.hp = hp; | |
504 | dev_dbg(&qspi->pdev->dev, | |
505 | "cs:%d %d-lane output, %d-byte address%s\n", | |
506 | qspi->curr_cs, | |
507 | qspi->xfer_mode.width, | |
508 | qspi->xfer_mode.addrlen, | |
509 | qspi->xfer_mode.hp != -1 ? ", hp mode" : ""); | |
510 | } | |
511 | ||
512 | return error; | |
513 | } | |
514 | ||
515 | static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi) | |
516 | { | |
517 | if (!has_bspi(qspi) || (qspi->bspi_enabled)) | |
518 | return; | |
519 | ||
520 | qspi->bspi_enabled = 1; | |
521 | if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1) == 0) | |
522 | return; | |
523 | ||
524 | bcm_qspi_bspi_flush_prefetch_buffers(qspi); | |
525 | udelay(1); | |
526 | bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 0); | |
527 | udelay(1); | |
528 | } | |
529 | ||
530 | static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi) | |
531 | { | |
532 | if (!has_bspi(qspi) || (!qspi->bspi_enabled)) | |
533 | return; | |
534 | ||
535 | qspi->bspi_enabled = 0; | |
536 | if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1)) | |
537 | return; | |
538 | ||
539 | bcm_qspi_bspi_busy_poll(qspi); | |
540 | bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 1); | |
541 | udelay(1); | |
542 | } | |
543 | ||
fa236a7e KD |
544 | static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs) |
545 | { | |
546 | u32 data = 0; | |
547 | ||
548 | if (qspi->curr_cs == cs) | |
549 | return; | |
550 | if (qspi->base[CHIP_SELECT]) { | |
551 | data = bcm_qspi_read(qspi, CHIP_SELECT, 0); | |
552 | data = (data & ~0xff) | (1 << cs); | |
553 | bcm_qspi_write(qspi, CHIP_SELECT, 0, data); | |
554 | usleep_range(10, 20); | |
555 | } | |
556 | qspi->curr_cs = cs; | |
557 | } | |
558 | ||
559 | /* MSPI helpers */ | |
560 | static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi, | |
561 | const struct bcm_qspi_parms *xp) | |
562 | { | |
563 | u32 spcr, spbr = 0; | |
564 | ||
565 | if (xp->speed_hz) | |
566 | spbr = qspi->base_clk / (2 * xp->speed_hz); | |
567 | ||
568 | spcr = clamp_val(spbr, QSPI_SPBR_MIN, QSPI_SPBR_MAX); | |
569 | bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr); | |
570 | ||
571 | spcr = MSPI_MASTER_BIT; | |
572 | /* for 16 bit the data should be zero */ | |
573 | if (xp->bits_per_word != 16) | |
574 | spcr |= xp->bits_per_word << 2; | |
575 | spcr |= xp->mode & 3; | |
576 | bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr); | |
577 | ||
578 | qspi->last_parms = *xp; | |
579 | } | |
580 | ||
581 | static void bcm_qspi_update_parms(struct bcm_qspi *qspi, | |
582 | struct spi_device *spi, | |
583 | struct spi_transfer *trans) | |
584 | { | |
585 | struct bcm_qspi_parms xp; | |
586 | ||
587 | xp.speed_hz = trans->speed_hz; | |
588 | xp.bits_per_word = trans->bits_per_word; | |
589 | xp.mode = spi->mode; | |
590 | ||
591 | bcm_qspi_hw_set_parms(qspi, &xp); | |
592 | } | |
593 | ||
594 | static int bcm_qspi_setup(struct spi_device *spi) | |
595 | { | |
596 | struct bcm_qspi_parms *xp; | |
597 | ||
598 | if (spi->bits_per_word > 16) | |
599 | return -EINVAL; | |
600 | ||
601 | xp = spi_get_ctldata(spi); | |
602 | if (!xp) { | |
603 | xp = kzalloc(sizeof(*xp), GFP_KERNEL); | |
604 | if (!xp) | |
605 | return -ENOMEM; | |
606 | spi_set_ctldata(spi, xp); | |
607 | } | |
608 | xp->speed_hz = spi->max_speed_hz; | |
609 | xp->mode = spi->mode; | |
610 | ||
611 | if (spi->bits_per_word) | |
612 | xp->bits_per_word = spi->bits_per_word; | |
613 | else | |
614 | xp->bits_per_word = 8; | |
615 | ||
616 | return 0; | |
617 | } | |
618 | ||
619 | static int update_qspi_trans_byte_count(struct bcm_qspi *qspi, | |
620 | struct qspi_trans *qt, int flags) | |
621 | { | |
622 | int ret = TRANS_STATUS_BREAK_NONE; | |
623 | ||
624 | /* count the last transferred bytes */ | |
625 | if (qt->trans->bits_per_word <= 8) | |
626 | qt->byte++; | |
627 | else | |
628 | qt->byte += 2; | |
629 | ||
630 | if (qt->byte >= qt->trans->len) { | |
631 | /* we're at the end of the spi_transfer */ | |
632 | ||
633 | /* in TX mode, need to pause for a delay or CS change */ | |
634 | if (qt->trans->delay_usecs && | |
635 | (flags & TRANS_STATUS_BREAK_DELAY)) | |
636 | ret |= TRANS_STATUS_BREAK_DELAY; | |
637 | if (qt->trans->cs_change && | |
638 | (flags & TRANS_STATUS_BREAK_CS_CHANGE)) | |
639 | ret |= TRANS_STATUS_BREAK_CS_CHANGE; | |
640 | if (ret) | |
641 | goto done; | |
642 | ||
643 | dev_dbg(&qspi->pdev->dev, "advance msg exit\n"); | |
644 | if (spi_transfer_is_last(qspi->master, qt->trans)) | |
645 | ret = TRANS_STATUS_BREAK_EOM; | |
646 | else | |
647 | ret = TRANS_STATUS_BREAK_NO_BYTES; | |
648 | ||
649 | qt->trans = NULL; | |
650 | } | |
651 | ||
652 | done: | |
653 | dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n", | |
654 | qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret); | |
655 | return ret; | |
656 | } | |
657 | ||
658 | static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot) | |
659 | { | |
660 | u32 slot_offset = MSPI_RXRAM + (slot << 3) + 0x4; | |
661 | ||
662 | /* mask out reserved bits */ | |
663 | return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff; | |
664 | } | |
665 | ||
666 | static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot) | |
667 | { | |
668 | u32 reg_offset = MSPI_RXRAM; | |
669 | u32 lsb_offset = reg_offset + (slot << 3) + 0x4; | |
670 | u32 msb_offset = reg_offset + (slot << 3); | |
671 | ||
672 | return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) | | |
673 | ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8); | |
674 | } | |
675 | ||
676 | static void read_from_hw(struct bcm_qspi *qspi, int slots) | |
677 | { | |
678 | struct qspi_trans tp; | |
679 | int slot; | |
680 | ||
4e3b2d23 KD |
681 | bcm_qspi_disable_bspi(qspi); |
682 | ||
fa236a7e KD |
683 | if (slots > MSPI_NUM_CDRAM) { |
684 | /* should never happen */ | |
685 | dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__); | |
686 | return; | |
687 | } | |
688 | ||
689 | tp = qspi->trans_pos; | |
690 | ||
691 | for (slot = 0; slot < slots; slot++) { | |
692 | if (tp.trans->bits_per_word <= 8) { | |
693 | u8 *buf = tp.trans->rx_buf; | |
694 | ||
695 | if (buf) | |
696 | buf[tp.byte] = read_rxram_slot_u8(qspi, slot); | |
697 | dev_dbg(&qspi->pdev->dev, "RD %02x\n", | |
698 | buf ? buf[tp.byte] : 0xff); | |
699 | } else { | |
700 | u16 *buf = tp.trans->rx_buf; | |
701 | ||
702 | if (buf) | |
703 | buf[tp.byte / 2] = read_rxram_slot_u16(qspi, | |
704 | slot); | |
705 | dev_dbg(&qspi->pdev->dev, "RD %04x\n", | |
706 | buf ? buf[tp.byte] : 0xffff); | |
707 | } | |
708 | ||
709 | update_qspi_trans_byte_count(qspi, &tp, | |
710 | TRANS_STATUS_BREAK_NONE); | |
711 | } | |
712 | ||
713 | qspi->trans_pos = tp; | |
714 | } | |
715 | ||
716 | static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot, | |
717 | u8 val) | |
718 | { | |
719 | u32 reg_offset = MSPI_TXRAM + (slot << 3); | |
720 | ||
721 | /* mask out reserved bits */ | |
722 | bcm_qspi_write(qspi, MSPI, reg_offset, val); | |
723 | } | |
724 | ||
725 | static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot, | |
726 | u16 val) | |
727 | { | |
728 | u32 reg_offset = MSPI_TXRAM; | |
729 | u32 msb_offset = reg_offset + (slot << 3); | |
730 | u32 lsb_offset = reg_offset + (slot << 3) + 0x4; | |
731 | ||
732 | bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8)); | |
733 | bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff)); | |
734 | } | |
735 | ||
736 | static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot) | |
737 | { | |
738 | return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2)); | |
739 | } | |
740 | ||
741 | static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val) | |
742 | { | |
743 | bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val); | |
744 | } | |
745 | ||
746 | /* Return number of slots written */ | |
747 | static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi) | |
748 | { | |
749 | struct qspi_trans tp; | |
750 | int slot = 0, tstatus = 0; | |
751 | u32 mspi_cdram = 0; | |
752 | ||
4e3b2d23 | 753 | bcm_qspi_disable_bspi(qspi); |
fa236a7e KD |
754 | tp = qspi->trans_pos; |
755 | bcm_qspi_update_parms(qspi, spi, tp.trans); | |
756 | ||
757 | /* Run until end of transfer or reached the max data */ | |
758 | while (!tstatus && slot < MSPI_NUM_CDRAM) { | |
759 | if (tp.trans->bits_per_word <= 8) { | |
760 | const u8 *buf = tp.trans->tx_buf; | |
761 | u8 val = buf ? buf[tp.byte] : 0xff; | |
762 | ||
763 | write_txram_slot_u8(qspi, slot, val); | |
764 | dev_dbg(&qspi->pdev->dev, "WR %02x\n", val); | |
765 | } else { | |
766 | const u16 *buf = tp.trans->tx_buf; | |
767 | u16 val = buf ? buf[tp.byte / 2] : 0xffff; | |
768 | ||
769 | write_txram_slot_u16(qspi, slot, val); | |
770 | dev_dbg(&qspi->pdev->dev, "WR %04x\n", val); | |
771 | } | |
772 | mspi_cdram = MSPI_CDRAM_CONT_BIT; | |
773 | mspi_cdram |= (~(1 << spi->chip_select) & | |
774 | MSPI_CDRAM_PCS); | |
775 | mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 : | |
776 | MSPI_CDRAM_BITSE_BIT); | |
777 | ||
778 | write_cdram_slot(qspi, slot, mspi_cdram); | |
779 | ||
780 | tstatus = update_qspi_trans_byte_count(qspi, &tp, | |
781 | TRANS_STATUS_BREAK_TX); | |
782 | slot++; | |
783 | } | |
784 | ||
785 | if (!slot) { | |
786 | dev_err(&qspi->pdev->dev, "%s: no data to send?", __func__); | |
787 | goto done; | |
788 | } | |
789 | ||
790 | dev_dbg(&qspi->pdev->dev, "submitting %d slots\n", slot); | |
791 | bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0); | |
792 | bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1); | |
793 | ||
794 | if (tstatus & TRANS_STATUS_BREAK_DESELECT) { | |
795 | mspi_cdram = read_cdram_slot(qspi, slot - 1) & | |
796 | ~MSPI_CDRAM_CONT_BIT; | |
797 | write_cdram_slot(qspi, slot - 1, mspi_cdram); | |
798 | } | |
799 | ||
4e3b2d23 KD |
800 | if (has_bspi(qspi)) |
801 | bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1); | |
802 | ||
fa236a7e KD |
803 | /* Must flush previous writes before starting MSPI operation */ |
804 | mb(); | |
805 | /* Set cont | spe | spifie */ | |
806 | bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0); | |
807 | ||
808 | done: | |
809 | return slot; | |
810 | } | |
811 | ||
4e3b2d23 KD |
812 | static int bcm_qspi_bspi_flash_read(struct spi_device *spi, |
813 | struct spi_flash_read_message *msg) | |
814 | { | |
815 | struct bcm_qspi *qspi = spi_master_get_devdata(spi->master); | |
816 | u32 addr = 0, len, len_words; | |
817 | int ret = 0; | |
818 | unsigned long timeo = msecs_to_jiffies(100); | |
cc20a386 | 819 | struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; |
4e3b2d23 KD |
820 | |
821 | if (bcm_qspi_bspi_ver_three(qspi)) | |
822 | if (msg->addr_width == BSPI_ADDRLEN_4BYTES) | |
823 | return -EIO; | |
824 | ||
825 | bcm_qspi_chip_select(qspi, spi->chip_select); | |
826 | bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0); | |
827 | ||
828 | /* | |
829 | * when using flex mode mode we need to send | |
830 | * the upper address byte to bspi | |
831 | */ | |
832 | if (bcm_qspi_bspi_ver_three(qspi) == false) { | |
833 | addr = msg->from & 0xff000000; | |
834 | bcm_qspi_write(qspi, BSPI, | |
835 | BSPI_BSPI_FLASH_UPPER_ADDR_BYTE, addr); | |
836 | } | |
837 | ||
838 | if (!qspi->xfer_mode.flex_mode) | |
839 | addr = msg->from; | |
840 | else | |
841 | addr = msg->from & 0x00ffffff; | |
842 | ||
843 | /* set BSPI RAF buffer max read length */ | |
844 | len = msg->len; | |
845 | if (len > BSPI_READ_LENGTH) | |
846 | len = BSPI_READ_LENGTH; | |
847 | ||
848 | if (bcm_qspi_bspi_ver_three(qspi) == true) | |
849 | addr = (addr + 0xc00000) & 0xffffff; | |
850 | ||
851 | reinit_completion(&qspi->bspi_done); | |
852 | bcm_qspi_enable_bspi(qspi); | |
853 | len_words = (len + 3) >> 2; | |
854 | qspi->bspi_rf_msg = msg; | |
855 | qspi->bspi_rf_msg_status = 0; | |
856 | qspi->bspi_rf_msg_idx = 0; | |
857 | qspi->bspi_rf_msg_len = len; | |
858 | dev_dbg(&qspi->pdev->dev, "bspi xfr addr 0x%x len 0x%x", addr, len); | |
859 | ||
860 | bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr); | |
861 | bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words); | |
862 | bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0); | |
863 | ||
cc20a386 KD |
864 | if (qspi->soc_intc) { |
865 | /* | |
866 | * clear soc MSPI and BSPI interrupts and enable | |
867 | * BSPI interrupts. | |
868 | */ | |
869 | soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE); | |
870 | soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true); | |
871 | } | |
872 | ||
4e3b2d23 KD |
873 | /* Must flush previous writes before starting BSPI operation */ |
874 | mb(); | |
875 | ||
876 | bcm_qspi_bspi_lr_start(qspi); | |
877 | if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) { | |
878 | dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n"); | |
879 | ret = -ETIMEDOUT; | |
880 | } else { | |
881 | /* set the return length for the caller */ | |
882 | msg->retlen = len; | |
883 | } | |
884 | ||
885 | return ret; | |
886 | } | |
887 | ||
888 | static int bcm_qspi_flash_read(struct spi_device *spi, | |
889 | struct spi_flash_read_message *msg) | |
890 | { | |
891 | struct bcm_qspi *qspi = spi_master_get_devdata(spi->master); | |
892 | int ret = 0; | |
893 | bool mspi_read = false; | |
894 | u32 io_width, addrlen, addr, len; | |
895 | u_char *buf; | |
896 | ||
897 | buf = msg->buf; | |
898 | addr = msg->from; | |
899 | len = msg->len; | |
900 | ||
901 | if (bcm_qspi_bspi_ver_three(qspi) == true) { | |
902 | /* | |
903 | * The address coming into this function is a raw flash offset. | |
904 | * But for BSPI <= V3, we need to convert it to a remapped BSPI | |
905 | * address. If it crosses a 4MB boundary, just revert back to | |
906 | * using MSPI. | |
907 | */ | |
908 | addr = (addr + 0xc00000) & 0xffffff; | |
909 | ||
910 | if ((~ADDR_4MB_MASK & addr) ^ | |
911 | (~ADDR_4MB_MASK & (addr + len - 1))) | |
912 | mspi_read = true; | |
913 | } | |
914 | ||
915 | /* non-aligned and very short transfers are handled by MSPI */ | |
916 | if (!IS_ALIGNED((uintptr_t)addr, 4) || !IS_ALIGNED((uintptr_t)buf, 4) || | |
917 | len < 4) | |
918 | mspi_read = true; | |
919 | ||
920 | if (mspi_read) | |
921 | /* this will make the m25p80 read to fallback to mspi read */ | |
922 | return -EAGAIN; | |
923 | ||
924 | io_width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE; | |
925 | addrlen = msg->addr_width; | |
926 | ret = bcm_qspi_bspi_set_mode(qspi, io_width, addrlen, -1); | |
927 | ||
928 | if (!ret) | |
929 | ret = bcm_qspi_bspi_flash_read(spi, msg); | |
930 | ||
931 | return ret; | |
932 | } | |
933 | ||
fa236a7e KD |
934 | static int bcm_qspi_transfer_one(struct spi_master *master, |
935 | struct spi_device *spi, | |
936 | struct spi_transfer *trans) | |
937 | { | |
938 | struct bcm_qspi *qspi = spi_master_get_devdata(master); | |
939 | int slots; | |
940 | unsigned long timeo = msecs_to_jiffies(100); | |
941 | ||
942 | bcm_qspi_chip_select(qspi, spi->chip_select); | |
943 | qspi->trans_pos.trans = trans; | |
944 | qspi->trans_pos.byte = 0; | |
945 | ||
946 | while (qspi->trans_pos.byte < trans->len) { | |
947 | reinit_completion(&qspi->mspi_done); | |
948 | ||
949 | slots = write_to_hw(qspi, spi); | |
950 | if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) { | |
951 | dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n"); | |
952 | return -ETIMEDOUT; | |
953 | } | |
954 | ||
955 | read_from_hw(qspi, slots); | |
956 | } | |
957 | ||
958 | return 0; | |
959 | } | |
960 | ||
961 | static void bcm_qspi_cleanup(struct spi_device *spi) | |
962 | { | |
963 | struct bcm_qspi_parms *xp = spi_get_ctldata(spi); | |
964 | ||
965 | kfree(xp); | |
966 | } | |
967 | ||
968 | static irqreturn_t bcm_qspi_mspi_l2_isr(int irq, void *dev_id) | |
969 | { | |
970 | struct bcm_qspi_dev_id *qspi_dev_id = dev_id; | |
971 | struct bcm_qspi *qspi = qspi_dev_id->dev; | |
972 | u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS); | |
973 | ||
974 | if (status & MSPI_MSPI_STATUS_SPIF) { | |
cc20a386 | 975 | struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; |
fa236a7e KD |
976 | /* clear interrupt */ |
977 | status &= ~MSPI_MSPI_STATUS_SPIF; | |
978 | bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status); | |
cc20a386 KD |
979 | if (qspi->soc_intc) |
980 | soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_DONE); | |
fa236a7e KD |
981 | complete(&qspi->mspi_done); |
982 | return IRQ_HANDLED; | |
fa236a7e | 983 | } |
4e3b2d23 KD |
984 | |
985 | return IRQ_NONE; | |
986 | } | |
987 | ||
988 | static irqreturn_t bcm_qspi_bspi_lr_l2_isr(int irq, void *dev_id) | |
989 | { | |
990 | struct bcm_qspi_dev_id *qspi_dev_id = dev_id; | |
991 | struct bcm_qspi *qspi = qspi_dev_id->dev; | |
cc20a386 KD |
992 | struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; |
993 | u32 status = qspi_dev_id->irqp->mask; | |
4e3b2d23 KD |
994 | |
995 | if (qspi->bspi_enabled && qspi->bspi_rf_msg) { | |
996 | bcm_qspi_bspi_lr_data_read(qspi); | |
997 | if (qspi->bspi_rf_msg_len == 0) { | |
998 | qspi->bspi_rf_msg = NULL; | |
cc20a386 KD |
999 | if (qspi->soc_intc) { |
1000 | /* disable soc BSPI interrupt */ | |
1001 | soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, | |
1002 | false); | |
1003 | /* indicate done */ | |
1004 | status = INTR_BSPI_LR_SESSION_DONE_MASK; | |
1005 | } | |
1006 | ||
4e3b2d23 KD |
1007 | if (qspi->bspi_rf_msg_status) |
1008 | bcm_qspi_bspi_lr_clear(qspi); | |
1009 | else | |
1010 | bcm_qspi_bspi_flush_prefetch_buffers(qspi); | |
1011 | } | |
cc20a386 KD |
1012 | |
1013 | if (qspi->soc_intc) | |
1014 | /* clear soc BSPI interrupt */ | |
1015 | soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_DONE); | |
4e3b2d23 KD |
1016 | } |
1017 | ||
cc20a386 | 1018 | status &= INTR_BSPI_LR_SESSION_DONE_MASK; |
4e3b2d23 KD |
1019 | if (qspi->bspi_enabled && status && qspi->bspi_rf_msg_len == 0) |
1020 | complete(&qspi->bspi_done); | |
1021 | ||
1022 | return IRQ_HANDLED; | |
1023 | } | |
1024 | ||
1025 | static irqreturn_t bcm_qspi_bspi_lr_err_l2_isr(int irq, void *dev_id) | |
1026 | { | |
1027 | struct bcm_qspi_dev_id *qspi_dev_id = dev_id; | |
1028 | struct bcm_qspi *qspi = qspi_dev_id->dev; | |
cc20a386 | 1029 | struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; |
4e3b2d23 KD |
1030 | |
1031 | dev_err(&qspi->pdev->dev, "BSPI INT error\n"); | |
1032 | qspi->bspi_rf_msg_status = -EIO; | |
cc20a386 KD |
1033 | if (qspi->soc_intc) |
1034 | /* clear soc interrupt */ | |
1035 | soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_ERR); | |
1036 | ||
4e3b2d23 KD |
1037 | complete(&qspi->bspi_done); |
1038 | return IRQ_HANDLED; | |
fa236a7e KD |
1039 | } |
1040 | ||
cc20a386 KD |
1041 | static irqreturn_t bcm_qspi_l1_isr(int irq, void *dev_id) |
1042 | { | |
1043 | struct bcm_qspi_dev_id *qspi_dev_id = dev_id; | |
1044 | struct bcm_qspi *qspi = qspi_dev_id->dev; | |
1045 | struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; | |
1046 | irqreturn_t ret = IRQ_NONE; | |
1047 | ||
1048 | if (soc_intc) { | |
1049 | u32 status = soc_intc->bcm_qspi_get_int_status(soc_intc); | |
1050 | ||
1051 | if (status & MSPI_DONE) | |
1052 | ret = bcm_qspi_mspi_l2_isr(irq, dev_id); | |
1053 | else if (status & BSPI_DONE) | |
1054 | ret = bcm_qspi_bspi_lr_l2_isr(irq, dev_id); | |
1055 | else if (status & BSPI_ERR) | |
1056 | ret = bcm_qspi_bspi_lr_err_l2_isr(irq, dev_id); | |
1057 | } | |
1058 | ||
1059 | return ret; | |
1060 | } | |
1061 | ||
fa236a7e | 1062 | static const struct bcm_qspi_irq qspi_irq_tab[] = { |
4e3b2d23 KD |
1063 | { |
1064 | .irq_name = "spi_lr_fullness_reached", | |
1065 | .irq_handler = bcm_qspi_bspi_lr_l2_isr, | |
1066 | .mask = INTR_BSPI_LR_FULLNESS_REACHED_MASK, | |
1067 | }, | |
1068 | { | |
1069 | .irq_name = "spi_lr_session_aborted", | |
1070 | .irq_handler = bcm_qspi_bspi_lr_err_l2_isr, | |
1071 | .mask = INTR_BSPI_LR_SESSION_ABORTED_MASK, | |
1072 | }, | |
1073 | { | |
1074 | .irq_name = "spi_lr_impatient", | |
1075 | .irq_handler = bcm_qspi_bspi_lr_err_l2_isr, | |
1076 | .mask = INTR_BSPI_LR_IMPATIENT_MASK, | |
1077 | }, | |
1078 | { | |
1079 | .irq_name = "spi_lr_session_done", | |
1080 | .irq_handler = bcm_qspi_bspi_lr_l2_isr, | |
1081 | .mask = INTR_BSPI_LR_SESSION_DONE_MASK, | |
1082 | }, | |
1083 | #ifdef QSPI_INT_DEBUG | |
1084 | /* this interrupt is for debug purposes only, dont request irq */ | |
1085 | { | |
1086 | .irq_name = "spi_lr_overread", | |
1087 | .irq_handler = bcm_qspi_bspi_lr_err_l2_isr, | |
1088 | .mask = INTR_BSPI_LR_OVERREAD_MASK, | |
1089 | }, | |
1090 | #endif | |
fa236a7e KD |
1091 | { |
1092 | .irq_name = "mspi_done", | |
1093 | .irq_handler = bcm_qspi_mspi_l2_isr, | |
1094 | .mask = INTR_MSPI_DONE_MASK, | |
1095 | }, | |
1096 | { | |
1097 | .irq_name = "mspi_halted", | |
1098 | .irq_handler = bcm_qspi_mspi_l2_isr, | |
1099 | .mask = INTR_MSPI_HALTED_MASK, | |
1100 | }, | |
cc20a386 KD |
1101 | { |
1102 | /* single muxed L1 interrupt source */ | |
1103 | .irq_name = "spi_l1_intr", | |
1104 | .irq_handler = bcm_qspi_l1_isr, | |
1105 | .irq_source = MUXED_L1, | |
1106 | .mask = QSPI_INTERRUPTS_ALL, | |
1107 | }, | |
fa236a7e KD |
1108 | }; |
1109 | ||
4e3b2d23 KD |
1110 | static void bcm_qspi_bspi_init(struct bcm_qspi *qspi) |
1111 | { | |
1112 | u32 val = 0; | |
1113 | ||
1114 | val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID); | |
1115 | qspi->bspi_maj_rev = (val >> 8) & 0xff; | |
1116 | qspi->bspi_min_rev = val & 0xff; | |
1117 | if (!(bcm_qspi_bspi_ver_three(qspi))) { | |
1118 | /* Force mapping of BSPI address -> flash offset */ | |
1119 | bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_VALUE, 0); | |
1120 | bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_ENABLE, 1); | |
1121 | } | |
1122 | qspi->bspi_enabled = 1; | |
1123 | bcm_qspi_disable_bspi(qspi); | |
1124 | bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0); | |
1125 | bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0); | |
1126 | } | |
1127 | ||
fa236a7e KD |
1128 | static void bcm_qspi_hw_init(struct bcm_qspi *qspi) |
1129 | { | |
1130 | struct bcm_qspi_parms parms; | |
1131 | ||
1132 | bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0); | |
1133 | bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0); | |
1134 | bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0); | |
1135 | bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0); | |
1136 | bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20); | |
1137 | ||
1138 | parms.mode = SPI_MODE_3; | |
1139 | parms.bits_per_word = 8; | |
1140 | parms.speed_hz = qspi->max_speed_hz; | |
1141 | bcm_qspi_hw_set_parms(qspi, &parms); | |
4e3b2d23 KD |
1142 | |
1143 | if (has_bspi(qspi)) | |
1144 | bcm_qspi_bspi_init(qspi); | |
fa236a7e KD |
1145 | } |
1146 | ||
1147 | static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi) | |
1148 | { | |
1149 | bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0); | |
4e3b2d23 KD |
1150 | if (has_bspi(qspi)) |
1151 | bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0); | |
1152 | ||
fa236a7e KD |
1153 | } |
1154 | ||
1155 | static const struct of_device_id bcm_qspi_of_match[] = { | |
1156 | { .compatible = "brcm,spi-bcm-qspi" }, | |
1157 | {}, | |
1158 | }; | |
1159 | MODULE_DEVICE_TABLE(of, bcm_qspi_of_match); | |
1160 | ||
1161 | int bcm_qspi_probe(struct platform_device *pdev, | |
4e3b2d23 | 1162 | struct bcm_qspi_soc_intc *soc_intc) |
fa236a7e KD |
1163 | { |
1164 | struct device *dev = &pdev->dev; | |
1165 | struct bcm_qspi *qspi; | |
1166 | struct spi_master *master; | |
1167 | struct resource *res; | |
1168 | int irq, ret = 0, num_ints = 0; | |
1169 | u32 val; | |
1170 | const char *name = NULL; | |
1171 | int num_irqs = ARRAY_SIZE(qspi_irq_tab); | |
1172 | ||
1173 | /* We only support device-tree instantiation */ | |
1174 | if (!dev->of_node) | |
1175 | return -ENODEV; | |
1176 | ||
1177 | if (!of_match_node(bcm_qspi_of_match, dev->of_node)) | |
1178 | return -ENODEV; | |
1179 | ||
1180 | master = spi_alloc_master(dev, sizeof(struct bcm_qspi)); | |
1181 | if (!master) { | |
1182 | dev_err(dev, "error allocating spi_master\n"); | |
1183 | return -ENOMEM; | |
1184 | } | |
1185 | ||
1186 | qspi = spi_master_get_devdata(master); | |
1187 | qspi->pdev = pdev; | |
1188 | qspi->trans_pos.trans = NULL; | |
1189 | qspi->trans_pos.byte = 0; | |
1190 | qspi->master = master; | |
1191 | ||
1192 | master->bus_num = -1; | |
1193 | master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD; | |
1194 | master->setup = bcm_qspi_setup; | |
1195 | master->transfer_one = bcm_qspi_transfer_one; | |
4e3b2d23 | 1196 | master->spi_flash_read = bcm_qspi_flash_read; |
fa236a7e KD |
1197 | master->cleanup = bcm_qspi_cleanup; |
1198 | master->dev.of_node = dev->of_node; | |
1199 | master->num_chipselect = NUM_CHIPSELECT; | |
1200 | ||
1201 | qspi->big_endian = of_device_is_big_endian(dev->of_node); | |
1202 | ||
1203 | if (!of_property_read_u32(dev->of_node, "num-cs", &val)) | |
1204 | master->num_chipselect = val; | |
1205 | ||
1206 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hif_mspi"); | |
1207 | if (!res) | |
1208 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
1209 | "mspi"); | |
1210 | ||
1211 | if (res) { | |
1212 | qspi->base[MSPI] = devm_ioremap_resource(dev, res); | |
1213 | if (IS_ERR(qspi->base[MSPI])) { | |
1214 | ret = PTR_ERR(qspi->base[MSPI]); | |
1215 | goto qspi_probe_err; | |
1216 | } | |
1217 | } else { | |
1218 | goto qspi_probe_err; | |
1219 | } | |
1220 | ||
4e3b2d23 KD |
1221 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi"); |
1222 | if (res) { | |
1223 | qspi->base[BSPI] = devm_ioremap_resource(dev, res); | |
1224 | if (IS_ERR(qspi->base[BSPI])) { | |
1225 | ret = PTR_ERR(qspi->base[BSPI]); | |
1226 | goto qspi_probe_err; | |
1227 | } | |
1228 | qspi->bspi_mode = true; | |
1229 | } else { | |
1230 | qspi->bspi_mode = false; | |
1231 | } | |
1232 | ||
1233 | dev_info(dev, "using %smspi mode\n", qspi->bspi_mode ? "bspi-" : ""); | |
1234 | ||
fa236a7e KD |
1235 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_reg"); |
1236 | if (res) { | |
1237 | qspi->base[CHIP_SELECT] = devm_ioremap_resource(dev, res); | |
1238 | if (IS_ERR(qspi->base[CHIP_SELECT])) { | |
1239 | ret = PTR_ERR(qspi->base[CHIP_SELECT]); | |
1240 | goto qspi_probe_err; | |
1241 | } | |
1242 | } | |
1243 | ||
1244 | qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id), | |
1245 | GFP_KERNEL); | |
3bf3eb2b WY |
1246 | if (!qspi->dev_ids) { |
1247 | ret = -ENOMEM; | |
fa236a7e KD |
1248 | goto qspi_probe_err; |
1249 | } | |
1250 | ||
1251 | for (val = 0; val < num_irqs; val++) { | |
1252 | irq = -1; | |
1253 | name = qspi_irq_tab[val].irq_name; | |
cc20a386 KD |
1254 | if (qspi_irq_tab[val].irq_source == SINGLE_L2) { |
1255 | /* get the l2 interrupts */ | |
1256 | irq = platform_get_irq_byname(pdev, name); | |
1257 | } else if (!num_ints && soc_intc) { | |
1258 | /* all mspi, bspi intrs muxed to one L1 intr */ | |
1259 | irq = platform_get_irq(pdev, 0); | |
1260 | } | |
fa236a7e KD |
1261 | |
1262 | if (irq >= 0) { | |
1263 | ret = devm_request_irq(&pdev->dev, irq, | |
1264 | qspi_irq_tab[val].irq_handler, 0, | |
1265 | name, | |
1266 | &qspi->dev_ids[val]); | |
1267 | if (ret < 0) { | |
1268 | dev_err(&pdev->dev, "IRQ %s not found\n", name); | |
1269 | goto qspi_probe_err; | |
1270 | } | |
1271 | ||
1272 | qspi->dev_ids[val].dev = qspi; | |
1273 | qspi->dev_ids[val].irqp = &qspi_irq_tab[val]; | |
1274 | num_ints++; | |
1275 | dev_dbg(&pdev->dev, "registered IRQ %s %d\n", | |
1276 | qspi_irq_tab[val].irq_name, | |
1277 | irq); | |
1278 | } | |
1279 | } | |
1280 | ||
1281 | if (!num_ints) { | |
1282 | dev_err(&pdev->dev, "no IRQs registered, cannot init driver\n"); | |
71b8f350 | 1283 | ret = -EINVAL; |
fa236a7e KD |
1284 | goto qspi_probe_err; |
1285 | } | |
1286 | ||
cc20a386 KD |
1287 | /* |
1288 | * Some SoCs integrate spi controller (e.g., its interrupt bits) | |
1289 | * in specific ways | |
1290 | */ | |
1291 | if (soc_intc) { | |
1292 | qspi->soc_intc = soc_intc; | |
1293 | soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true); | |
1294 | } else { | |
1295 | qspi->soc_intc = NULL; | |
1296 | } | |
1297 | ||
fa236a7e KD |
1298 | qspi->clk = devm_clk_get(&pdev->dev, NULL); |
1299 | if (IS_ERR(qspi->clk)) { | |
1300 | dev_warn(dev, "unable to get clock\n"); | |
71b8f350 | 1301 | ret = PTR_ERR(qspi->clk); |
fa236a7e KD |
1302 | goto qspi_probe_err; |
1303 | } | |
1304 | ||
1305 | ret = clk_prepare_enable(qspi->clk); | |
1306 | if (ret) { | |
1307 | dev_err(dev, "failed to prepare clock\n"); | |
1308 | goto qspi_probe_err; | |
1309 | } | |
1310 | ||
1311 | qspi->base_clk = clk_get_rate(qspi->clk); | |
1312 | qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2); | |
1313 | ||
1314 | bcm_qspi_hw_init(qspi); | |
1315 | init_completion(&qspi->mspi_done); | |
4e3b2d23 | 1316 | init_completion(&qspi->bspi_done); |
fa236a7e KD |
1317 | qspi->curr_cs = -1; |
1318 | ||
1319 | platform_set_drvdata(pdev, qspi); | |
4e3b2d23 KD |
1320 | |
1321 | qspi->xfer_mode.width = -1; | |
1322 | qspi->xfer_mode.addrlen = -1; | |
1323 | qspi->xfer_mode.hp = -1; | |
1324 | ||
fa236a7e KD |
1325 | ret = devm_spi_register_master(&pdev->dev, master); |
1326 | if (ret < 0) { | |
1327 | dev_err(dev, "can't register master\n"); | |
1328 | goto qspi_reg_err; | |
1329 | } | |
1330 | ||
1331 | return 0; | |
1332 | ||
1333 | qspi_reg_err: | |
1334 | bcm_qspi_hw_uninit(qspi); | |
1335 | clk_disable_unprepare(qspi->clk); | |
1336 | qspi_probe_err: | |
1337 | spi_master_put(master); | |
1338 | kfree(qspi->dev_ids); | |
1339 | return ret; | |
1340 | } | |
1341 | /* probe function to be called by SoC specific platform driver probe */ | |
1342 | EXPORT_SYMBOL_GPL(bcm_qspi_probe); | |
1343 | ||
1344 | int bcm_qspi_remove(struct platform_device *pdev) | |
1345 | { | |
1346 | struct bcm_qspi *qspi = platform_get_drvdata(pdev); | |
1347 | ||
1348 | platform_set_drvdata(pdev, NULL); | |
1349 | bcm_qspi_hw_uninit(qspi); | |
1350 | clk_disable_unprepare(qspi->clk); | |
1351 | kfree(qspi->dev_ids); | |
1352 | spi_unregister_master(qspi->master); | |
1353 | ||
1354 | return 0; | |
1355 | } | |
1356 | /* function to be called by SoC specific platform driver remove() */ | |
1357 | EXPORT_SYMBOL_GPL(bcm_qspi_remove); | |
1358 | ||
a0319f8b | 1359 | static int __maybe_unused bcm_qspi_suspend(struct device *dev) |
fa236a7e KD |
1360 | { |
1361 | struct bcm_qspi *qspi = dev_get_drvdata(dev); | |
1362 | ||
1363 | spi_master_suspend(qspi->master); | |
1364 | clk_disable(qspi->clk); | |
1365 | bcm_qspi_hw_uninit(qspi); | |
1366 | ||
1367 | return 0; | |
1368 | }; | |
1369 | ||
a0319f8b | 1370 | static int __maybe_unused bcm_qspi_resume(struct device *dev) |
fa236a7e KD |
1371 | { |
1372 | struct bcm_qspi *qspi = dev_get_drvdata(dev); | |
1373 | int ret = 0; | |
1374 | ||
1375 | bcm_qspi_hw_init(qspi); | |
1376 | bcm_qspi_chip_select(qspi, qspi->curr_cs); | |
cc20a386 KD |
1377 | if (qspi->soc_intc) |
1378 | /* enable MSPI interrupt */ | |
1379 | qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE, | |
1380 | true); | |
1381 | ||
fa236a7e KD |
1382 | ret = clk_enable(qspi->clk); |
1383 | if (!ret) | |
1384 | spi_master_resume(qspi->master); | |
1385 | ||
1386 | return ret; | |
1387 | } | |
fa236a7e | 1388 | |
a0319f8b AB |
1389 | SIMPLE_DEV_PM_OPS(bcm_qspi_pm_ops, bcm_qspi_suspend, bcm_qspi_resume); |
1390 | ||
fa236a7e KD |
1391 | /* pm_ops to be called by SoC specific platform driver */ |
1392 | EXPORT_SYMBOL_GPL(bcm_qspi_pm_ops); | |
1393 | ||
1394 | MODULE_AUTHOR("Kamal Dasu"); | |
1395 | MODULE_DESCRIPTION("Broadcom QSPI driver"); | |
1396 | MODULE_LICENSE("GPL v2"); | |
1397 | MODULE_ALIAS("platform:" DRIVER_NAME); |