[mirror_ubuntu-artful-kernel.git] / drivers / spi / spi-bcm63xx-hsspi.c

/*
 * Broadcom BCM63XX High Speed SPI Controller driver
 *
 * Copyright 2000-2010 Broadcom Corporation
 * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>
#include <linux/mutex.h>
#include <linux/of.h>

#define HSSPI_GLOBAL_CTRL_REG			0x0
#define GLOBAL_CTRL_CS_POLARITY_SHIFT		0
#define GLOBAL_CTRL_CS_POLARITY_MASK		0x000000ff
#define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT		8
#define GLOBAL_CTRL_PLL_CLK_CTRL_MASK		0x0000ff00
#define GLOBAL_CTRL_CLK_GATE_SSOFF		BIT(16)
#define GLOBAL_CTRL_CLK_POLARITY		BIT(17)
#define GLOBAL_CTRL_MOSI_IDLE			BIT(18)

#define HSSPI_GLOBAL_EXT_TRIGGER_REG		0x4

#define HSSPI_INT_STATUS_REG			0x8
#define HSSPI_INT_STATUS_MASKED_REG		0xc
#define HSSPI_INT_MASK_REG			0x10

#define HSSPI_PINGx_CMD_DONE(i)			BIT((i * 8) + 0)
#define HSSPI_PINGx_RX_OVER(i)			BIT((i * 8) + 1)
#define HSSPI_PINGx_TX_UNDER(i)			BIT((i * 8) + 2)
#define HSSPI_PINGx_POLL_TIMEOUT(i)		BIT((i * 8) + 3)
#define HSSPI_PINGx_CTRL_INVAL(i)		BIT((i * 8) + 4)

#define HSSPI_INT_CLEAR_ALL			0xff001f1f

#define HSSPI_PINGPONG_COMMAND_REG(x)		(0x80 + (x) * 0x40)
#define PINGPONG_CMD_COMMAND_MASK		0xf
#define PINGPONG_COMMAND_NOOP			0
#define PINGPONG_COMMAND_START_NOW		1
#define PINGPONG_COMMAND_START_TRIGGER		2
#define PINGPONG_COMMAND_HALT			3
#define PINGPONG_COMMAND_FLUSH			4
#define PINGPONG_CMD_PROFILE_SHIFT		8
#define PINGPONG_CMD_SS_SHIFT			12

#define HSSPI_PINGPONG_STATUS_REG(x)		(0x84 + (x) * 0x40)

#define HSSPI_PROFILE_CLK_CTRL_REG(x)		(0x100 + (x) * 0x20)
#define CLK_CTRL_FREQ_CTRL_MASK			0x0000ffff
#define CLK_CTRL_SPI_CLK_2X_SEL			BIT(14)
#define CLK_CTRL_ACCUM_RST_ON_LOOP		BIT(15)

#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x)	(0x104 + (x) * 0x20)
#define SIGNAL_CTRL_LATCH_RISING		BIT(12)
#define SIGNAL_CTRL_LAUNCH_RISING		BIT(13)
#define SIGNAL_CTRL_ASYNC_INPUT_PATH		BIT(16)

#define HSSPI_PROFILE_MODE_CTRL_REG(x)		(0x108 + (x) * 0x20)
#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT	8
#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT	12
#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT	16
#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT	18
#define MODE_CTRL_MODE_3WIRE			BIT(20)
#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT		24

#define HSSPI_FIFO_REG(x)			(0x200 + (x) * 0x200)


#define HSSPI_OP_MULTIBIT			BIT(11)
#define HSSPI_OP_CODE_SHIFT			13
#define HSSPI_OP_SLEEP				(0 << HSSPI_OP_CODE_SHIFT)
#define HSSPI_OP_READ_WRITE			(1 << HSSPI_OP_CODE_SHIFT)
#define HSSPI_OP_WRITE				(2 << HSSPI_OP_CODE_SHIFT)
#define HSSPI_OP_READ				(3 << HSSPI_OP_CODE_SHIFT)
#define HSSPI_OP_SETIRQ				(4 << HSSPI_OP_CODE_SHIFT)

#define HSSPI_BUFFER_LEN			512
#define HSSPI_OPCODE_LEN			2

#define HSSPI_MAX_PREPEND_LEN			15

#define HSSPI_MAX_SYNC_CLOCK			30000000

#define HSSPI_SPI_MAX_CS			8
#define HSSPI_BUS_NUM				1 /* 0 is legacy SPI */

struct bcm63xx_hsspi {
	struct completion done;
	struct mutex bus_mutex;

	struct platform_device *pdev;
	struct clk *clk;
	void __iomem *regs;
	u8 __iomem *fifo;

	u32 speed_hz;
	u8 cs_polarity;
};

static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned cs,
				 bool active)
{
	u32 reg;

	mutex_lock(&bs->bus_mutex);
	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);

	reg &= ~BIT(cs);
	if (active == !(bs->cs_polarity & BIT(cs)))
		reg |= BIT(cs);

	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	mutex_unlock(&bs->bus_mutex);
}

static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
				  struct spi_device *spi, int hz)
{
	unsigned profile = spi->chip_select;
	u32 reg;

	reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
	__raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
		     bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));

	reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
	if (hz > HSSPI_MAX_SYNC_CLOCK)
		reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
	else
		reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
	__raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));

	mutex_lock(&bs->bus_mutex);
	/* setup clock polarity */
	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	reg &= ~GLOBAL_CTRL_CLK_POLARITY;
	if (spi->mode & SPI_CPOL)
		reg |= GLOBAL_CTRL_CLK_POLARITY;
	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	mutex_unlock(&bs->bus_mutex);
}

static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
{
	struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
	unsigned chip_select = spi->chip_select;
	u16 opcode = 0;
	int pending = t->len;
	int step_size = HSSPI_BUFFER_LEN;
	const u8 *tx = t->tx_buf;
	u8 *rx = t->rx_buf;

	bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
	bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);

	if (tx && rx)
		opcode = HSSPI_OP_READ_WRITE;
	else if (tx)
		opcode = HSSPI_OP_WRITE;
	else if (rx)
		opcode = HSSPI_OP_READ;

	if (opcode != HSSPI_OP_READ)
		step_size -= HSSPI_OPCODE_LEN;

	if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
	    (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL))
		opcode |= HSSPI_OP_MULTIBIT;

	__raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT |
		     1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff,
		     bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));

	while (pending > 0) {
		int curr_step = min_t(int, step_size, pending);

		reinit_completion(&bs->done);
		if (tx) {
			memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
			tx += curr_step;
		}

		__raw_writew(opcode | curr_step, bs->fifo);

		/* enable interrupt */
		__raw_writel(HSSPI_PINGx_CMD_DONE(0),
			     bs->regs + HSSPI_INT_MASK_REG);

		/* start the transfer */
		__raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT |
			     chip_select << PINGPONG_CMD_PROFILE_SHIFT |
			     PINGPONG_COMMAND_START_NOW,
			     bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));

		if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
			dev_err(&bs->pdev->dev, "transfer timed out!\n");
			return -ETIMEDOUT;
		}

		if (rx) {
			memcpy_fromio(rx, bs->fifo, curr_step);
			rx += curr_step;
		}

		pending -= curr_step;
	}

	return 0;
}

static int bcm63xx_hsspi_setup(struct spi_device *spi)
{
	struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
	u32 reg;

	reg = __raw_readl(bs->regs +
			  HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
	reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
	if (spi->mode & SPI_CPHA)
		reg |= SIGNAL_CTRL_LAUNCH_RISING;
	else
		reg |= SIGNAL_CTRL_LATCH_RISING;
	__raw_writel(reg, bs->regs +
		     HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));

	mutex_lock(&bs->bus_mutex);
	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);

	/* only change actual polarities if there is no transfer */
	if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
		if (spi->mode & SPI_CS_HIGH)
			reg |= BIT(spi->chip_select);
		else
			reg &= ~BIT(spi->chip_select);
		__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	}

	if (spi->mode & SPI_CS_HIGH)
		bs->cs_polarity |= BIT(spi->chip_select);
	else
		bs->cs_polarity &= ~BIT(spi->chip_select);

	mutex_unlock(&bs->bus_mutex);

	return 0;
}

static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
				      struct spi_message *msg)
{
	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
	struct spi_transfer *t;
	struct spi_device *spi = msg->spi;
	int status = -EINVAL;
	int dummy_cs;
	u32 reg;

	/* This controller does not support keeping CS active during idle.
	 * To work around this, we use the following ugly hack:
	 *
	 * a. Invert the target chip select's polarity so it will be active.
	 * b. Select a "dummy" chip select to use as the hardware target.
	 * c. Invert the dummy chip select's polarity so it will be inactive
	 *    during the actual transfers.
	 * d. Tell the hardware to send to the dummy chip select. Thanks to
	 *    the multiplexed nature of SPI the actual target will receive
	 *    the transfer and we see its response.
	 *
	 * e. At the end restore the polarities again to their default values.
	 */

	dummy_cs = !spi->chip_select;
	bcm63xx_hsspi_set_cs(bs, dummy_cs, true);

	list_for_each_entry(t, &msg->transfers, transfer_list) {
		status = bcm63xx_hsspi_do_txrx(spi, t);
		if (status)
			break;

		msg->actual_length += t->len;

		if (t->delay_usecs)
			udelay(t->delay_usecs);

		if (t->cs_change)
			bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
	}

	mutex_lock(&bs->bus_mutex);
	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK;
	reg |= bs->cs_polarity;
	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	mutex_unlock(&bs->bus_mutex);

	msg->status = status;
	spi_finalize_current_message(master);

	return 0;
}

static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
{
	struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id;

	if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
		return IRQ_NONE;

	__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);

	complete(&bs->done);

	return IRQ_HANDLED;
}

static int bcm63xx_hsspi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct bcm63xx_hsspi *bs;
	struct resource *res_mem;
	void __iomem *regs;
	struct device *dev = &pdev->dev;
	struct clk *clk;
	int irq, ret;
	u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "no irq\n");
		return -ENXIO;
	}

	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	regs = devm_ioremap_resource(dev, res_mem);
	if (IS_ERR(regs))
		return PTR_ERR(regs);

	clk = devm_clk_get(dev, "hsspi");

	if (IS_ERR(clk))
		return PTR_ERR(clk);

	rate = clk_get_rate(clk);
	if (!rate) {
		struct clk *pll_clk = devm_clk_get(dev, "pll");

		if (IS_ERR(pll_clk))
			return PTR_ERR(pll_clk);

		rate = clk_get_rate(pll_clk);
		if (!rate)
			return -EINVAL;
	}

	ret = clk_prepare_enable(clk);
	if (ret)
		return ret;

	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
	if (!master) {
		ret = -ENOMEM;
		goto out_disable_clk;
	}

	bs = spi_master_get_devdata(master);
	bs->pdev = pdev;
	bs->clk = clk;
	bs->regs = regs;
	bs->speed_hz = rate;
	bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));

	mutex_init(&bs->bus_mutex);
	init_completion(&bs->done);

	master->dev.of_node = dev->of_node;
	if (!dev->of_node)
		master->bus_num = HSSPI_BUS_NUM;

	of_property_read_u32(dev->of_node, "num-cs", &num_cs);
	if (num_cs > 8) {
		dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
			 num_cs);
		num_cs = HSSPI_SPI_MAX_CS;
	}
	master->num_chipselect = num_cs;
	master->setup = bcm63xx_hsspi_setup;
	master->transfer_one_message = bcm63xx_hsspi_transfer_one;
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
			    SPI_RX_DUAL | SPI_TX_DUAL;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->auto_runtime_pm = true;

	platform_set_drvdata(pdev, master);

	/* Initialize the hardware */
	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);

	/* clean up any pending interrupts */
	__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);

	/* read out default CS polarities */
	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
	__raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
		     bs->regs + HSSPI_GLOBAL_CTRL_REG);

	ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
			       pdev->name, bs);

	if (ret)
		goto out_put_master;

	/* register and we are done */
	ret = devm_spi_register_master(dev, master);
	if (ret)
		goto out_put_master;

	return 0;

out_put_master:
	spi_master_put(master);
out_disable_clk:
	clk_disable_unprepare(clk);
	return ret;
}


static int bcm63xx_hsspi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);

	/* reset the hardware and block queue progress */
	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
	clk_disable_unprepare(bs->clk);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int bcm63xx_hsspi_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);

	spi_master_suspend(master);
	clk_disable_unprepare(bs->clk);

	return 0;
}

static int bcm63xx_hsspi_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
	int ret;

	ret = clk_prepare_enable(bs->clk);
	if (ret)
		return ret;

	spi_master_resume(master);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend,
			 bcm63xx_hsspi_resume);

static const struct of_device_id bcm63xx_hsspi_of_match[] = {
	{ .compatible = "brcm,bcm6328-hsspi", },
	{ },
};
MODULE_DEVICE_TABLE(of, bcm63xx_hsspi_of_match);

static struct platform_driver bcm63xx_hsspi_driver = {
	.driver = {
		.name	= "bcm63xx-hsspi",
		.pm	= &bcm63xx_hsspi_pm_ops,
		.of_match_table = bcm63xx_hsspi_of_match,
	},
	.probe		= bcm63xx_hsspi_probe,
	.remove		= bcm63xx_hsspi_remove,
};

module_platform_driver(bcm63xx_hsspi_driver);

MODULE_ALIAS("platform:bcm63xx_hsspi");
MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver");
MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
142168eb JG	1	/*
	2	* Broadcom BCM63XX High Speed SPI Controller driver
	3	*
	4	* Copyright 2000-2010 Broadcom Corporation
	5	* Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
	6	*
	7	* Licensed under the GNU/GPL. See COPYING for details.
	8	*/
	9
	10	#include <linux/kernel.h>
	11	#include <linux/init.h>
	12	#include <linux/io.h>
	13	#include <linux/clk.h>
	14	#include <linux/module.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/delay.h>
	17	#include <linux/dma-mapping.h>
	18	#include <linux/err.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/spi/spi.h>
142168eb	21	#include <linux/mutex.h>
7ab24635	22	#include <linux/of.h>
142168eb JG	23
	24	#define HSSPI_GLOBAL_CTRL_REG 0x0
	25	#define GLOBAL_CTRL_CS_POLARITY_SHIFT 0
	26	#define GLOBAL_CTRL_CS_POLARITY_MASK 0x000000ff
	27	#define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT 8
	28	#define GLOBAL_CTRL_PLL_CLK_CTRL_MASK 0x0000ff00
	29	#define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16)
	30	#define GLOBAL_CTRL_CLK_POLARITY BIT(17)
	31	#define GLOBAL_CTRL_MOSI_IDLE BIT(18)
	32
	33	#define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4
	34
	35	#define HSSPI_INT_STATUS_REG 0x8
	36	#define HSSPI_INT_STATUS_MASKED_REG 0xc
	37	#define HSSPI_INT_MASK_REG 0x10
	38
	39	#define HSSPI_PINGx_CMD_DONE(i) BIT((i * 8) + 0)
	40	#define HSSPI_PINGx_RX_OVER(i) BIT((i * 8) + 1)
	41	#define HSSPI_PINGx_TX_UNDER(i) BIT((i * 8) + 2)
	42	#define HSSPI_PINGx_POLL_TIMEOUT(i) BIT((i * 8) + 3)
	43	#define HSSPI_PINGx_CTRL_INVAL(i) BIT((i * 8) + 4)
	44
	45	#define HSSPI_INT_CLEAR_ALL 0xff001f1f
	46
	47	#define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40)
	48	#define PINGPONG_CMD_COMMAND_MASK 0xf
	49	#define PINGPONG_COMMAND_NOOP 0
	50	#define PINGPONG_COMMAND_START_NOW 1
	51	#define PINGPONG_COMMAND_START_TRIGGER 2
	52	#define PINGPONG_COMMAND_HALT 3
	53	#define PINGPONG_COMMAND_FLUSH 4
	54	#define PINGPONG_CMD_PROFILE_SHIFT 8
	55	#define PINGPONG_CMD_SS_SHIFT 12
	56
	57	#define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40)
	58
	59	#define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20)
	60	#define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff
	61	#define CLK_CTRL_SPI_CLK_2X_SEL BIT(14)
	62	#define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15)
	63
	64	#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20)
	65	#define SIGNAL_CTRL_LATCH_RISING BIT(12)
	66	#define SIGNAL_CTRL_LAUNCH_RISING BIT(13)
	67	#define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16)
	68
	69	#define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20)
	70	#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8
	71	#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12
	72	#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16
	73	#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18
	74	#define MODE_CTRL_MODE_3WIRE BIT(20)
	75	#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24
	76
	77	#define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200)
	78
	79
f4d86223	80	#define HSSPI_OP_MULTIBIT BIT(11)
142168eb JG	81	#define HSSPI_OP_CODE_SHIFT 13
	82	#define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT)
	83	#define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT)
	84	#define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT)
	85	#define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT)
	86	#define HSSPI_OP_SETIRQ (4 << HSSPI_OP_CODE_SHIFT)
	87
	88	#define HSSPI_BUFFER_LEN 512
	89	#define HSSPI_OPCODE_LEN 2
	90
	91	#define HSSPI_MAX_PREPEND_LEN 15
	92
	93	#define HSSPI_MAX_SYNC_CLOCK 30000000
	94
7ab24635	95	#define HSSPI_SPI_MAX_CS 8
142168eb JG	96	#define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
	97
	98	struct bcm63xx_hsspi {
	99	struct completion done;
	100	struct mutex bus_mutex;
	101
	102	struct platform_device *pdev;
	103	struct clk *clk;
	104	void __iomem *regs;
	105	u8 __iomem *fifo;
	106
	107	u32 speed_hz;
	108	u8 cs_polarity;
	109	};
	110
	111	static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned cs,
	112	bool active)
	113	{
	114	u32 reg;
	115
	116	mutex_lock(&bs->bus_mutex);
	117	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	118
	119	reg &= ~BIT(cs);
	120	if (active == !(bs->cs_polarity & BIT(cs)))
	121	reg \|= BIT(cs);
	122
	123	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	124	mutex_unlock(&bs->bus_mutex);
	125	}
	126
	127	static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
	128	struct spi_device *spi, int hz)
	129	{
	130	unsigned profile = spi->chip_select;
	131	u32 reg;
	132
	133	reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
	134	__raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP \| reg,
	135	bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
	136
	137	reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
	138	if (hz > HSSPI_MAX_SYNC_CLOCK)
	139	reg \|= SIGNAL_CTRL_ASYNC_INPUT_PATH;
	140	else
	141	reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
	142	__raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
	143
	144	mutex_lock(&bs->bus_mutex);
	145	/* setup clock polarity */
	146	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	147	reg &= ~GLOBAL_CTRL_CLK_POLARITY;
	148	if (spi->mode & SPI_CPOL)
	149	reg \|= GLOBAL_CTRL_CLK_POLARITY;
	150	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	151	mutex_unlock(&bs->bus_mutex);
	152	}
	153
	154	static int bcm63xx_hsspi_do_txrx(struct spi_device spi, struct spi_transfer t)
	155	{
	156	struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
	157	unsigned chip_select = spi->chip_select;
	158	u16 opcode = 0;
	159	int pending = t->len;
160	int step_size = HSSPI_BUFFER_LEN;
161	const u8 *tx = t->tx_buf;
162	u8 *rx = t->rx_buf;
163
164	bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
165	bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
166
167	if (tx && rx)
168	opcode = HSSPI_OP_READ_WRITE;
169	else if (tx)
170	opcode = HSSPI_OP_WRITE;
171	else if (rx)
172	opcode = HSSPI_OP_READ;
173
174	if (opcode != HSSPI_OP_READ)
175	step_size -= HSSPI_OPCODE_LEN;
176
f4d86223 JG	177	if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) \|\|
	178	(opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL))
	179	opcode \|= HSSPI_OP_MULTIBIT;
	180
	181	__raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT \|
	182	1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT \| 0xff,
142168eb JG	183	bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
	184
	185	while (pending > 0) {
	186	int curr_step = min_t(int, step_size, pending);
	187
aa0fe826	188	reinit_completion(&bs->done);
142168eb JG	189	if (tx) {
	190	memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
	191	tx += curr_step;
	192	}
	193
	194	__raw_writew(opcode \| curr_step, bs->fifo);
	195
	196	/* enable interrupt */
	197	__raw_writel(HSSPI_PINGx_CMD_DONE(0),
	198	bs->regs + HSSPI_INT_MASK_REG);
	199
	200	/* start the transfer */
	201	__raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT \|
	202	chip_select << PINGPONG_CMD_PROFILE_SHIFT \|
	203	PINGPONG_COMMAND_START_NOW,
	204	bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
	205
	206	if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
	207	dev_err(&bs->pdev->dev, "transfer timed out!\n");
	208	return -ETIMEDOUT;
	209	}
	210
	211	if (rx) {
	212	memcpy_fromio(rx, bs->fifo, curr_step);
	213	rx += curr_step;
	214	}
	215
	216	pending -= curr_step;
	217	}
	218
	219	return 0;
	220	}
	221
	222	static int bcm63xx_hsspi_setup(struct spi_device *spi)
	223	{
	224	struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
	225	u32 reg;
	226
	227	reg = __raw_readl(bs->regs +
	228	HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
	229	reg &= ~(SIGNAL_CTRL_LAUNCH_RISING \| SIGNAL_CTRL_LATCH_RISING);
	230	if (spi->mode & SPI_CPHA)
	231	reg \|= SIGNAL_CTRL_LAUNCH_RISING;
	232	else
	233	reg \|= SIGNAL_CTRL_LATCH_RISING;
	234	__raw_writel(reg, bs->regs +
	235	HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
	236
	237	mutex_lock(&bs->bus_mutex);
	238	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	239
	240	/* only change actual polarities if there is no transfer */
	241	if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
	242	if (spi->mode & SPI_CS_HIGH)
	243	reg \|= BIT(spi->chip_select);
	244	else
	245	reg &= ~BIT(spi->chip_select);
	246	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	247	}
	248
	249	if (spi->mode & SPI_CS_HIGH)
	250	bs->cs_polarity \|= BIT(spi->chip_select);
	251	else
	252	bs->cs_polarity &= ~BIT(spi->chip_select);
253
254	mutex_unlock(&bs->bus_mutex);
255
256	return 0;
257	}
258
259	static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
260	struct spi_message *msg)
261	{
262	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
263	struct spi_transfer *t;
264	struct spi_device *spi = msg->spi;
265	int status = -EINVAL;
266	int dummy_cs;
267	u32 reg;
268
269	/* This controller does not support keeping CS active during idle.
270	* To work around this, we use the following ugly hack:
271	*
272	* a. Invert the target chip select's polarity so it will be active.
273	* b. Select a "dummy" chip select to use as the hardware target.
274	* c. Invert the dummy chip select's polarity so it will be inactive
275	* during the actual transfers.
276	* d. Tell the hardware to send to the dummy chip select. Thanks to
277	* the multiplexed nature of SPI the actual target will receive
278	* the transfer and we see its response.
279	*
280	* e. At the end restore the polarities again to their default values.
281	*/
282
283	dummy_cs = !spi->chip_select;
284	bcm63xx_hsspi_set_cs(bs, dummy_cs, true);
285
286	list_for_each_entry(t, &msg->transfers, transfer_list) {
287	status = bcm63xx_hsspi_do_txrx(spi, t);
288	if (status)
289	break;
290
291	msg->actual_length += t->len;
292
293	if (t->delay_usecs)
294	udelay(t->delay_usecs);
295
296	if (t->cs_change)
297	bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
298	}
299
300	mutex_lock(&bs->bus_mutex);
301	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
302	reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK;
303	reg \|= bs->cs_polarity;
304	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
305	mutex_unlock(&bs->bus_mutex);
306
307	msg->status = status;
308	spi_finalize_current_message(master);
309
310	return 0;
311	}
312
313	static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
314	{
315	struct bcm63xx_hsspi bs = (struct bcm63xx_hsspi )dev_id;
316
317	if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
318	return IRQ_NONE;
319
320	__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
321	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
322
323	complete(&bs->done);
324
325	return IRQ_HANDLED;
326	}
327
328	static int bcm63xx_hsspi_probe(struct platform_device *pdev)
329	{
330	struct spi_master *master;
331	struct bcm63xx_hsspi *bs;
332	struct resource *res_mem;
333	void __iomem *regs;
334	struct device *dev = &pdev->dev;
335	struct clk *clk;
336	int irq, ret;
7ab24635	337	u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;
142168eb JG	338
	339	irq = platform_get_irq(pdev, 0);
	340	if (irq < 0) {
	341	dev_err(dev, "no irq\n");
	342	return -ENXIO;
	343	}
	344
	345	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
87917528	346	regs = devm_ioremap_resource(dev, res_mem);
142168eb JG	347	if (IS_ERR(regs))
	348	return PTR_ERR(regs);
	349
b1bdd4f8	350	clk = devm_clk_get(dev, "hsspi");
142168eb JG	351
	352	if (IS_ERR(clk))
	353	return PTR_ERR(clk);
	354
	355	rate = clk_get_rate(clk);
ff18e1ef JG	356	if (!rate) {
	357	struct clk *pll_clk = devm_clk_get(dev, "pll");
	358
	359	if (IS_ERR(pll_clk))
	360	return PTR_ERR(pll_clk);
	361
	362	rate = clk_get_rate(pll_clk);
	363	if (!rate)
	364	return -EINVAL;
	365	}
142168eb	366
dea5de1b JG	367	ret = clk_prepare_enable(clk);
	368	if (ret)
	369	return ret;
142168eb JG	370
	371	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
	372	if (!master) {
	373	ret = -ENOMEM;
	374	goto out_disable_clk;
	375	}
	376
	377	bs = spi_master_get_devdata(master);
	378	bs->pdev = pdev;
	379	bs->clk = clk;
	380	bs->regs = regs;
	381	bs->speed_hz = rate;
	382	bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
	383
	384	mutex_init(&bs->bus_mutex);
aa0fe826	385	init_completion(&bs->done);
142168eb	386
7ab24635 JG	387	master->dev.of_node = dev->of_node;
	388	if (!dev->of_node)
	389	master->bus_num = HSSPI_BUS_NUM;
	390
	391	of_property_read_u32(dev->of_node, "num-cs", &num_cs);
	392	if (num_cs > 8) {
	393	dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
	394	num_cs);
	395	num_cs = HSSPI_SPI_MAX_CS;
	396	}
	397	master->num_chipselect = num_cs;
142168eb JG	398	master->setup = bcm63xx_hsspi_setup;
142168eb JG	399	master->transfer_one_message = bcm63xx_hsspi_transfer_one;
f4d86223 JG	400	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \|
f4d86223 JG	401	SPI_RX_DUAL \| SPI_TX_DUAL;
142168eb JG	402	master->bits_per_word_mask = SPI_BPW_MASK(8);
	403	master->auto_runtime_pm = true;
	404
	405	platform_set_drvdata(pdev, master);
	406
	407	/* Initialize the hardware */
	408	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
	409
	410	/* clean up any pending interrupts */
	411	__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
	412
	413	/* read out default CS polarities */
	414	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	415	bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
	416	__raw_writel(reg \| GLOBAL_CTRL_CLK_GATE_SSOFF,
	417	bs->regs + HSSPI_GLOBAL_CTRL_REG);
	418
	419	ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
	420	pdev->name, bs);
	421
	422	if (ret)
	423	goto out_put_master;
	424
	425	/* register and we are done */
7d255695	426	ret = devm_spi_register_master(dev, master);
142168eb JG	427	if (ret)
	428	goto out_put_master;
	429
	430	return 0;
	431
	432	out_put_master:
	433	spi_master_put(master);
	434	out_disable_clk:
	435	clk_disable_unprepare(clk);
142168eb JG	436	return ret;
	437	}
	438
	439
	440	static int bcm63xx_hsspi_remove(struct platform_device *pdev)
	441	{
	442	struct spi_master *master = platform_get_drvdata(pdev);
	443	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
	444
142168eb JG	445	/* reset the hardware and block queue progress */
	446	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
	447	clk_disable_unprepare(bs->clk);
142168eb JG	448
	449	return 0;
	450	}
	451
937ebf9c	452	#ifdef CONFIG_PM_SLEEP
142168eb JG	453	static int bcm63xx_hsspi_suspend(struct device *dev)
	454	{
	455	struct spi_master *master = dev_get_drvdata(dev);
	456	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
	457
	458	spi_master_suspend(master);
937ebf9c	459	clk_disable_unprepare(bs->clk);
142168eb JG	460
	461	return 0;
	462	}
	463
	464	static int bcm63xx_hsspi_resume(struct device *dev)
	465	{
	466	struct spi_master *master = dev_get_drvdata(dev);
	467	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
937ebf9c JG	468	int ret;
	469
	470	ret = clk_prepare_enable(bs->clk);
	471	if (ret)
	472	return ret;
142168eb	473
142168eb JG	474	spi_master_resume(master);
	475
	476	return 0;
	477	}
937ebf9c	478	#endif
142168eb	479
1480916e JH	480	static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend,
1480916e JH	481	bcm63xx_hsspi_resume);
142168eb	482
7ab24635 JG	483	static const struct of_device_id bcm63xx_hsspi_of_match[] = {
	484	{ .compatible = "brcm,bcm6328-hsspi", },
	485	{ },
	486	};
0b85a842	487	MODULE_DEVICE_TABLE(of, bcm63xx_hsspi_of_match);
7ab24635	488
142168eb JG	489	static struct platform_driver bcm63xx_hsspi_driver = {
	490	.driver = {
	491	.name = "bcm63xx-hsspi",
937ebf9c	492	.pm = &bcm63xx_hsspi_pm_ops,
7ab24635	493	.of_match_table = bcm63xx_hsspi_of_match,
142168eb JG	494	},
	495	.probe = bcm63xx_hsspi_probe,
	496	.remove = bcm63xx_hsspi_remove,
	497	};
	498
	499	module_platform_driver(bcm63xx_hsspi_driver);
	500
	501	MODULE_ALIAS("platform:bcm63xx_hsspi");
	502	MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver");
	503	MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
	504	MODULE_LICENSE("GPL");