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9c3e7375 CC |
1 | /* |
2 | * SPI bus via the Blackfin SPORT peripheral | |
3 | * | |
4 | * Enter bugs at http://blackfin.uclinux.org/ | |
5 | * | |
6 | * Copyright 2009-2011 Analog Devices Inc. | |
7 | * | |
8 | * Licensed under the GPL-2 or later. | |
9 | */ | |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/gpio.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/ioport.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/errno.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/spi/spi.h> | |
23 | #include <linux/workqueue.h> | |
24 | ||
25 | #include <asm/portmux.h> | |
26 | #include <asm/bfin5xx_spi.h> | |
27 | #include <asm/blackfin.h> | |
28 | #include <asm/bfin_sport.h> | |
29 | #include <asm/cacheflush.h> | |
30 | ||
31 | #define DRV_NAME "bfin-sport-spi" | |
32 | #define DRV_DESC "SPI bus via the Blackfin SPORT" | |
33 | ||
34 | MODULE_AUTHOR("Cliff Cai"); | |
35 | MODULE_DESCRIPTION(DRV_DESC); | |
36 | MODULE_LICENSE("GPL"); | |
37 | MODULE_ALIAS("platform:bfin-sport-spi"); | |
38 | ||
39 | enum bfin_sport_spi_state { | |
40 | START_STATE, | |
41 | RUNNING_STATE, | |
42 | DONE_STATE, | |
43 | ERROR_STATE, | |
44 | }; | |
45 | ||
46 | struct bfin_sport_spi_master_data; | |
47 | ||
48 | struct bfin_sport_transfer_ops { | |
49 | void (*write) (struct bfin_sport_spi_master_data *); | |
50 | void (*read) (struct bfin_sport_spi_master_data *); | |
51 | void (*duplex) (struct bfin_sport_spi_master_data *); | |
52 | }; | |
53 | ||
54 | struct bfin_sport_spi_master_data { | |
55 | /* Driver model hookup */ | |
56 | struct device *dev; | |
57 | ||
58 | /* SPI framework hookup */ | |
59 | struct spi_master *master; | |
60 | ||
61 | /* Regs base of SPI controller */ | |
62 | struct sport_register __iomem *regs; | |
63 | int err_irq; | |
64 | ||
65 | /* Pin request list */ | |
66 | u16 *pin_req; | |
67 | ||
68 | /* Driver message queue */ | |
69 | struct workqueue_struct *workqueue; | |
70 | struct work_struct pump_messages; | |
71 | spinlock_t lock; | |
72 | struct list_head queue; | |
73 | int busy; | |
74 | bool run; | |
75 | ||
76 | /* Message Transfer pump */ | |
77 | struct tasklet_struct pump_transfers; | |
78 | ||
79 | /* Current message transfer state info */ | |
80 | enum bfin_sport_spi_state state; | |
81 | struct spi_message *cur_msg; | |
82 | struct spi_transfer *cur_transfer; | |
83 | struct bfin_sport_spi_slave_data *cur_chip; | |
84 | union { | |
85 | void *tx; | |
86 | u8 *tx8; | |
87 | u16 *tx16; | |
88 | }; | |
89 | void *tx_end; | |
90 | union { | |
91 | void *rx; | |
92 | u8 *rx8; | |
93 | u16 *rx16; | |
94 | }; | |
95 | void *rx_end; | |
96 | ||
97 | int cs_change; | |
98 | struct bfin_sport_transfer_ops *ops; | |
99 | }; | |
100 | ||
101 | struct bfin_sport_spi_slave_data { | |
102 | u16 ctl_reg; | |
103 | u16 baud; | |
104 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ | |
105 | u32 cs_gpio; | |
106 | u16 idle_tx_val; | |
107 | struct bfin_sport_transfer_ops *ops; | |
108 | }; | |
109 | ||
110 | static void | |
111 | bfin_sport_spi_enable(struct bfin_sport_spi_master_data *drv_data) | |
112 | { | |
113 | bfin_write_or(&drv_data->regs->tcr1, TSPEN); | |
114 | bfin_write_or(&drv_data->regs->rcr1, TSPEN); | |
115 | SSYNC(); | |
116 | } | |
117 | ||
118 | static void | |
119 | bfin_sport_spi_disable(struct bfin_sport_spi_master_data *drv_data) | |
120 | { | |
121 | bfin_write_and(&drv_data->regs->tcr1, ~TSPEN); | |
122 | bfin_write_and(&drv_data->regs->rcr1, ~TSPEN); | |
123 | SSYNC(); | |
124 | } | |
125 | ||
126 | /* Caculate the SPI_BAUD register value based on input HZ */ | |
127 | static u16 | |
128 | bfin_sport_hz_to_spi_baud(u32 speed_hz) | |
129 | { | |
130 | u_long clk, sclk = get_sclk(); | |
131 | int div = (sclk / (2 * speed_hz)) - 1; | |
132 | ||
133 | if (div < 0) | |
134 | div = 0; | |
135 | ||
136 | clk = sclk / (2 * (div + 1)); | |
137 | ||
138 | if (clk > speed_hz) | |
139 | div++; | |
140 | ||
141 | return div; | |
142 | } | |
143 | ||
144 | /* Chip select operation functions for cs_change flag */ | |
145 | static void | |
146 | bfin_sport_spi_cs_active(struct bfin_sport_spi_slave_data *chip) | |
147 | { | |
148 | gpio_direction_output(chip->cs_gpio, 0); | |
149 | } | |
150 | ||
151 | static void | |
152 | bfin_sport_spi_cs_deactive(struct bfin_sport_spi_slave_data *chip) | |
153 | { | |
154 | gpio_direction_output(chip->cs_gpio, 1); | |
155 | /* Move delay here for consistency */ | |
156 | if (chip->cs_chg_udelay) | |
157 | udelay(chip->cs_chg_udelay); | |
158 | } | |
159 | ||
160 | static void | |
161 | bfin_sport_spi_stat_poll_complete(struct bfin_sport_spi_master_data *drv_data) | |
162 | { | |
163 | unsigned long timeout = jiffies + HZ; | |
164 | while (!(bfin_read(&drv_data->regs->stat) & RXNE)) { | |
165 | if (!time_before(jiffies, timeout)) | |
166 | break; | |
167 | } | |
168 | } | |
169 | ||
170 | static void | |
171 | bfin_sport_spi_u8_writer(struct bfin_sport_spi_master_data *drv_data) | |
172 | { | |
173 | u16 dummy; | |
174 | ||
175 | while (drv_data->tx < drv_data->tx_end) { | |
176 | bfin_write(&drv_data->regs->tx16, *drv_data->tx8++); | |
177 | bfin_sport_spi_stat_poll_complete(drv_data); | |
178 | dummy = bfin_read(&drv_data->regs->rx16); | |
179 | } | |
180 | } | |
181 | ||
182 | static void | |
183 | bfin_sport_spi_u8_reader(struct bfin_sport_spi_master_data *drv_data) | |
184 | { | |
185 | u16 tx_val = drv_data->cur_chip->idle_tx_val; | |
186 | ||
187 | while (drv_data->rx < drv_data->rx_end) { | |
188 | bfin_write(&drv_data->regs->tx16, tx_val); | |
189 | bfin_sport_spi_stat_poll_complete(drv_data); | |
190 | *drv_data->rx8++ = bfin_read(&drv_data->regs->rx16); | |
191 | } | |
192 | } | |
193 | ||
194 | static void | |
195 | bfin_sport_spi_u8_duplex(struct bfin_sport_spi_master_data *drv_data) | |
196 | { | |
197 | while (drv_data->rx < drv_data->rx_end) { | |
198 | bfin_write(&drv_data->regs->tx16, *drv_data->tx8++); | |
199 | bfin_sport_spi_stat_poll_complete(drv_data); | |
200 | *drv_data->rx8++ = bfin_read(&drv_data->regs->rx16); | |
201 | } | |
202 | } | |
203 | ||
204 | static struct bfin_sport_transfer_ops bfin_sport_transfer_ops_u8 = { | |
205 | .write = bfin_sport_spi_u8_writer, | |
206 | .read = bfin_sport_spi_u8_reader, | |
207 | .duplex = bfin_sport_spi_u8_duplex, | |
208 | }; | |
209 | ||
210 | static void | |
211 | bfin_sport_spi_u16_writer(struct bfin_sport_spi_master_data *drv_data) | |
212 | { | |
213 | u16 dummy; | |
214 | ||
215 | while (drv_data->tx < drv_data->tx_end) { | |
216 | bfin_write(&drv_data->regs->tx16, *drv_data->tx16++); | |
217 | bfin_sport_spi_stat_poll_complete(drv_data); | |
218 | dummy = bfin_read(&drv_data->regs->rx16); | |
219 | } | |
220 | } | |
221 | ||
222 | static void | |
223 | bfin_sport_spi_u16_reader(struct bfin_sport_spi_master_data *drv_data) | |
224 | { | |
225 | u16 tx_val = drv_data->cur_chip->idle_tx_val; | |
226 | ||
227 | while (drv_data->rx < drv_data->rx_end) { | |
228 | bfin_write(&drv_data->regs->tx16, tx_val); | |
229 | bfin_sport_spi_stat_poll_complete(drv_data); | |
230 | *drv_data->rx16++ = bfin_read(&drv_data->regs->rx16); | |
231 | } | |
232 | } | |
233 | ||
234 | static void | |
235 | bfin_sport_spi_u16_duplex(struct bfin_sport_spi_master_data *drv_data) | |
236 | { | |
237 | while (drv_data->rx < drv_data->rx_end) { | |
238 | bfin_write(&drv_data->regs->tx16, *drv_data->tx16++); | |
239 | bfin_sport_spi_stat_poll_complete(drv_data); | |
240 | *drv_data->rx16++ = bfin_read(&drv_data->regs->rx16); | |
241 | } | |
242 | } | |
243 | ||
244 | static struct bfin_sport_transfer_ops bfin_sport_transfer_ops_u16 = { | |
245 | .write = bfin_sport_spi_u16_writer, | |
246 | .read = bfin_sport_spi_u16_reader, | |
247 | .duplex = bfin_sport_spi_u16_duplex, | |
248 | }; | |
249 | ||
250 | /* stop controller and re-config current chip */ | |
251 | static void | |
252 | bfin_sport_spi_restore_state(struct bfin_sport_spi_master_data *drv_data) | |
253 | { | |
254 | struct bfin_sport_spi_slave_data *chip = drv_data->cur_chip; | |
9c3e7375 CC |
255 | |
256 | bfin_sport_spi_disable(drv_data); | |
257 | dev_dbg(drv_data->dev, "restoring spi ctl state\n"); | |
258 | ||
259 | bfin_write(&drv_data->regs->tcr1, chip->ctl_reg); | |
9c3e7375 | 260 | bfin_write(&drv_data->regs->tclkdiv, chip->baud); |
9c3e7375 CC |
261 | SSYNC(); |
262 | ||
263 | bfin_write(&drv_data->regs->rcr1, chip->ctl_reg & ~(ITCLK | ITFS)); | |
9c3e7375 CC |
264 | SSYNC(); |
265 | ||
266 | bfin_sport_spi_cs_active(chip); | |
267 | } | |
268 | ||
269 | /* test if there is more transfer to be done */ | |
270 | static enum bfin_sport_spi_state | |
271 | bfin_sport_spi_next_transfer(struct bfin_sport_spi_master_data *drv_data) | |
272 | { | |
273 | struct spi_message *msg = drv_data->cur_msg; | |
274 | struct spi_transfer *trans = drv_data->cur_transfer; | |
275 | ||
276 | /* Move to next transfer */ | |
277 | if (trans->transfer_list.next != &msg->transfers) { | |
278 | drv_data->cur_transfer = | |
279 | list_entry(trans->transfer_list.next, | |
280 | struct spi_transfer, transfer_list); | |
281 | return RUNNING_STATE; | |
282 | } | |
283 | ||
284 | return DONE_STATE; | |
285 | } | |
286 | ||
287 | /* | |
288 | * caller already set message->status; | |
289 | * dma and pio irqs are blocked give finished message back | |
290 | */ | |
291 | static void | |
292 | bfin_sport_spi_giveback(struct bfin_sport_spi_master_data *drv_data) | |
293 | { | |
294 | struct bfin_sport_spi_slave_data *chip = drv_data->cur_chip; | |
295 | unsigned long flags; | |
296 | struct spi_message *msg; | |
297 | ||
298 | spin_lock_irqsave(&drv_data->lock, flags); | |
299 | msg = drv_data->cur_msg; | |
300 | drv_data->state = START_STATE; | |
301 | drv_data->cur_msg = NULL; | |
302 | drv_data->cur_transfer = NULL; | |
303 | drv_data->cur_chip = NULL; | |
304 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
305 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
306 | ||
307 | if (!drv_data->cs_change) | |
308 | bfin_sport_spi_cs_deactive(chip); | |
309 | ||
310 | if (msg->complete) | |
311 | msg->complete(msg->context); | |
312 | } | |
313 | ||
314 | static irqreturn_t | |
315 | sport_err_handler(int irq, void *dev_id) | |
316 | { | |
317 | struct bfin_sport_spi_master_data *drv_data = dev_id; | |
318 | u16 status; | |
319 | ||
320 | dev_dbg(drv_data->dev, "%s enter\n", __func__); | |
321 | status = bfin_read(&drv_data->regs->stat) & (TOVF | TUVF | ROVF | RUVF); | |
322 | ||
323 | if (status) { | |
324 | bfin_write(&drv_data->regs->stat, status); | |
325 | SSYNC(); | |
326 | ||
327 | bfin_sport_spi_disable(drv_data); | |
328 | dev_err(drv_data->dev, "status error:%s%s%s%s\n", | |
329 | status & TOVF ? " TOVF" : "", | |
330 | status & TUVF ? " TUVF" : "", | |
331 | status & ROVF ? " ROVF" : "", | |
332 | status & RUVF ? " RUVF" : ""); | |
333 | } | |
334 | ||
335 | return IRQ_HANDLED; | |
336 | } | |
337 | ||
338 | static void | |
339 | bfin_sport_spi_pump_transfers(unsigned long data) | |
340 | { | |
341 | struct bfin_sport_spi_master_data *drv_data = (void *)data; | |
342 | struct spi_message *message = NULL; | |
343 | struct spi_transfer *transfer = NULL; | |
344 | struct spi_transfer *previous = NULL; | |
345 | struct bfin_sport_spi_slave_data *chip = NULL; | |
346 | unsigned int bits_per_word; | |
347 | u32 tranf_success = 1; | |
348 | u32 transfer_speed; | |
349 | u8 full_duplex = 0; | |
350 | ||
351 | /* Get current state information */ | |
352 | message = drv_data->cur_msg; | |
353 | transfer = drv_data->cur_transfer; | |
354 | chip = drv_data->cur_chip; | |
355 | ||
356 | if (transfer->speed_hz) | |
357 | transfer_speed = bfin_sport_hz_to_spi_baud(transfer->speed_hz); | |
358 | else | |
359 | transfer_speed = chip->baud; | |
360 | bfin_write(&drv_data->regs->tclkdiv, transfer_speed); | |
361 | SSYNC(); | |
362 | ||
363 | /* | |
364 | * if msg is error or done, report it back using complete() callback | |
365 | */ | |
366 | ||
367 | /* Handle for abort */ | |
368 | if (drv_data->state == ERROR_STATE) { | |
369 | dev_dbg(drv_data->dev, "transfer: we've hit an error\n"); | |
370 | message->status = -EIO; | |
371 | bfin_sport_spi_giveback(drv_data); | |
372 | return; | |
373 | } | |
374 | ||
375 | /* Handle end of message */ | |
376 | if (drv_data->state == DONE_STATE) { | |
377 | dev_dbg(drv_data->dev, "transfer: all done!\n"); | |
378 | message->status = 0; | |
379 | bfin_sport_spi_giveback(drv_data); | |
380 | return; | |
381 | } | |
382 | ||
383 | /* Delay if requested at end of transfer */ | |
384 | if (drv_data->state == RUNNING_STATE) { | |
385 | dev_dbg(drv_data->dev, "transfer: still running ...\n"); | |
386 | previous = list_entry(transfer->transfer_list.prev, | |
387 | struct spi_transfer, transfer_list); | |
388 | if (previous->delay_usecs) | |
389 | udelay(previous->delay_usecs); | |
390 | } | |
391 | ||
392 | if (transfer->len == 0) { | |
393 | /* Move to next transfer of this msg */ | |
394 | drv_data->state = bfin_sport_spi_next_transfer(drv_data); | |
395 | /* Schedule next transfer tasklet */ | |
396 | tasklet_schedule(&drv_data->pump_transfers); | |
397 | } | |
398 | ||
399 | if (transfer->tx_buf != NULL) { | |
400 | drv_data->tx = (void *)transfer->tx_buf; | |
401 | drv_data->tx_end = drv_data->tx + transfer->len; | |
402 | dev_dbg(drv_data->dev, "tx_buf is %p, tx_end is %p\n", | |
403 | transfer->tx_buf, drv_data->tx_end); | |
404 | } else | |
405 | drv_data->tx = NULL; | |
406 | ||
407 | if (transfer->rx_buf != NULL) { | |
408 | full_duplex = transfer->tx_buf != NULL; | |
409 | drv_data->rx = transfer->rx_buf; | |
410 | drv_data->rx_end = drv_data->rx + transfer->len; | |
411 | dev_dbg(drv_data->dev, "rx_buf is %p, rx_end is %p\n", | |
412 | transfer->rx_buf, drv_data->rx_end); | |
413 | } else | |
414 | drv_data->rx = NULL; | |
415 | ||
416 | drv_data->cs_change = transfer->cs_change; | |
417 | ||
418 | /* Bits per word setup */ | |
766ed704 | 419 | bits_per_word = transfer->bits_per_word; |
24778be2 | 420 | if (bits_per_word == 16) |
9c3e7375 | 421 | drv_data->ops = &bfin_sport_transfer_ops_u16; |
8d9d2a4b SJ |
422 | else |
423 | drv_data->ops = &bfin_sport_transfer_ops_u8; | |
488e1a9d SJ |
424 | bfin_write(&drv_data->regs->tcr2, bits_per_word - 1); |
425 | bfin_write(&drv_data->regs->tfsdiv, bits_per_word - 1); | |
426 | bfin_write(&drv_data->regs->rcr2, bits_per_word - 1); | |
9c3e7375 CC |
427 | |
428 | drv_data->state = RUNNING_STATE; | |
429 | ||
430 | if (drv_data->cs_change) | |
431 | bfin_sport_spi_cs_active(chip); | |
432 | ||
433 | dev_dbg(drv_data->dev, | |
434 | "now pumping a transfer: width is %d, len is %d\n", | |
435 | bits_per_word, transfer->len); | |
436 | ||
437 | /* PIO mode write then read */ | |
438 | dev_dbg(drv_data->dev, "doing IO transfer\n"); | |
439 | ||
440 | bfin_sport_spi_enable(drv_data); | |
441 | if (full_duplex) { | |
442 | /* full duplex mode */ | |
443 | BUG_ON((drv_data->tx_end - drv_data->tx) != | |
444 | (drv_data->rx_end - drv_data->rx)); | |
445 | drv_data->ops->duplex(drv_data); | |
446 | ||
447 | if (drv_data->tx != drv_data->tx_end) | |
448 | tranf_success = 0; | |
449 | } else if (drv_data->tx != NULL) { | |
450 | /* write only half duplex */ | |
451 | ||
452 | drv_data->ops->write(drv_data); | |
453 | ||
454 | if (drv_data->tx != drv_data->tx_end) | |
455 | tranf_success = 0; | |
456 | } else if (drv_data->rx != NULL) { | |
457 | /* read only half duplex */ | |
458 | ||
459 | drv_data->ops->read(drv_data); | |
460 | if (drv_data->rx != drv_data->rx_end) | |
461 | tranf_success = 0; | |
462 | } | |
463 | bfin_sport_spi_disable(drv_data); | |
464 | ||
465 | if (!tranf_success) { | |
466 | dev_dbg(drv_data->dev, "IO write error!\n"); | |
467 | drv_data->state = ERROR_STATE; | |
468 | } else { | |
886db6ac | 469 | /* Update total byte transferred */ |
9c3e7375 CC |
470 | message->actual_length += transfer->len; |
471 | /* Move to next transfer of this msg */ | |
472 | drv_data->state = bfin_sport_spi_next_transfer(drv_data); | |
473 | if (drv_data->cs_change) | |
474 | bfin_sport_spi_cs_deactive(chip); | |
475 | } | |
476 | ||
477 | /* Schedule next transfer tasklet */ | |
478 | tasklet_schedule(&drv_data->pump_transfers); | |
479 | } | |
480 | ||
481 | /* pop a msg from queue and kick off real transfer */ | |
482 | static void | |
483 | bfin_sport_spi_pump_messages(struct work_struct *work) | |
484 | { | |
485 | struct bfin_sport_spi_master_data *drv_data; | |
486 | unsigned long flags; | |
487 | struct spi_message *next_msg; | |
488 | ||
489 | drv_data = container_of(work, struct bfin_sport_spi_master_data, pump_messages); | |
490 | ||
491 | /* Lock queue and check for queue work */ | |
492 | spin_lock_irqsave(&drv_data->lock, flags); | |
493 | if (list_empty(&drv_data->queue) || !drv_data->run) { | |
494 | /* pumper kicked off but no work to do */ | |
495 | drv_data->busy = 0; | |
496 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
497 | return; | |
498 | } | |
499 | ||
500 | /* Make sure we are not already running a message */ | |
501 | if (drv_data->cur_msg) { | |
502 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
503 | return; | |
504 | } | |
505 | ||
506 | /* Extract head of queue */ | |
507 | next_msg = list_entry(drv_data->queue.next, | |
508 | struct spi_message, queue); | |
509 | ||
510 | drv_data->cur_msg = next_msg; | |
511 | ||
512 | /* Setup the SSP using the per chip configuration */ | |
513 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
514 | ||
515 | list_del_init(&drv_data->cur_msg->queue); | |
516 | ||
517 | /* Initialize message state */ | |
518 | drv_data->cur_msg->state = START_STATE; | |
519 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
520 | struct spi_transfer, transfer_list); | |
521 | bfin_sport_spi_restore_state(drv_data); | |
522 | dev_dbg(drv_data->dev, "got a message to pump, " | |
523 | "state is set to: baud %d, cs_gpio %i, ctl 0x%x\n", | |
524 | drv_data->cur_chip->baud, drv_data->cur_chip->cs_gpio, | |
525 | drv_data->cur_chip->ctl_reg); | |
526 | ||
527 | dev_dbg(drv_data->dev, | |
528 | "the first transfer len is %d\n", | |
529 | drv_data->cur_transfer->len); | |
530 | ||
531 | /* Mark as busy and launch transfers */ | |
532 | tasklet_schedule(&drv_data->pump_transfers); | |
533 | ||
534 | drv_data->busy = 1; | |
535 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
536 | } | |
537 | ||
538 | /* | |
539 | * got a msg to transfer, queue it in drv_data->queue. | |
540 | * And kick off message pumper | |
541 | */ | |
542 | static int | |
543 | bfin_sport_spi_transfer(struct spi_device *spi, struct spi_message *msg) | |
544 | { | |
545 | struct bfin_sport_spi_master_data *drv_data = spi_master_get_devdata(spi->master); | |
546 | unsigned long flags; | |
547 | ||
548 | spin_lock_irqsave(&drv_data->lock, flags); | |
549 | ||
550 | if (!drv_data->run) { | |
551 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
552 | return -ESHUTDOWN; | |
553 | } | |
554 | ||
555 | msg->actual_length = 0; | |
556 | msg->status = -EINPROGRESS; | |
557 | msg->state = START_STATE; | |
558 | ||
559 | dev_dbg(&spi->dev, "adding an msg in transfer()\n"); | |
560 | list_add_tail(&msg->queue, &drv_data->queue); | |
561 | ||
562 | if (drv_data->run && !drv_data->busy) | |
563 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
564 | ||
565 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | /* Called every time common spi devices change state */ | |
571 | static int | |
572 | bfin_sport_spi_setup(struct spi_device *spi) | |
573 | { | |
574 | struct bfin_sport_spi_slave_data *chip, *first = NULL; | |
575 | int ret; | |
576 | ||
577 | /* Only alloc (or use chip_info) on first setup */ | |
578 | chip = spi_get_ctldata(spi); | |
579 | if (chip == NULL) { | |
580 | struct bfin5xx_spi_chip *chip_info; | |
581 | ||
582 | chip = first = kzalloc(sizeof(*chip), GFP_KERNEL); | |
583 | if (!chip) | |
584 | return -ENOMEM; | |
585 | ||
586 | /* platform chip_info isn't required */ | |
587 | chip_info = spi->controller_data; | |
588 | if (chip_info) { | |
589 | /* | |
590 | * DITFS and TDTYPE are only thing we don't set, but | |
591 | * they probably shouldn't be changed by people. | |
592 | */ | |
593 | if (chip_info->ctl_reg || chip_info->enable_dma) { | |
594 | ret = -EINVAL; | |
595 | dev_err(&spi->dev, "don't set ctl_reg/enable_dma fields"); | |
596 | goto error; | |
597 | } | |
598 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; | |
599 | chip->idle_tx_val = chip_info->idle_tx_val; | |
9c3e7375 CC |
600 | } |
601 | } | |
602 | ||
9c3e7375 CC |
603 | /* translate common spi framework into our register |
604 | * following configure contents are same for tx and rx. | |
605 | */ | |
606 | ||
607 | if (spi->mode & SPI_CPHA) | |
608 | chip->ctl_reg &= ~TCKFE; | |
609 | else | |
610 | chip->ctl_reg |= TCKFE; | |
611 | ||
612 | if (spi->mode & SPI_LSB_FIRST) | |
613 | chip->ctl_reg |= TLSBIT; | |
614 | else | |
615 | chip->ctl_reg &= ~TLSBIT; | |
616 | ||
617 | /* Sport in master mode */ | |
618 | chip->ctl_reg |= ITCLK | ITFS | TFSR | LATFS | LTFS; | |
619 | ||
620 | chip->baud = bfin_sport_hz_to_spi_baud(spi->max_speed_hz); | |
621 | ||
622 | chip->cs_gpio = spi->chip_select; | |
623 | ret = gpio_request(chip->cs_gpio, spi->modalias); | |
624 | if (ret) | |
625 | goto error; | |
626 | ||
627 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d\n", | |
628 | spi->modalias, spi->bits_per_word); | |
629 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, GPIO is %i\n", | |
630 | chip->ctl_reg, spi->chip_select); | |
631 | ||
632 | spi_set_ctldata(spi, chip); | |
633 | ||
634 | bfin_sport_spi_cs_deactive(chip); | |
635 | ||
636 | return ret; | |
637 | ||
638 | error: | |
639 | kfree(first); | |
640 | return ret; | |
641 | } | |
642 | ||
643 | /* | |
644 | * callback for spi framework. | |
645 | * clean driver specific data | |
646 | */ | |
647 | static void | |
648 | bfin_sport_spi_cleanup(struct spi_device *spi) | |
649 | { | |
650 | struct bfin_sport_spi_slave_data *chip = spi_get_ctldata(spi); | |
651 | ||
652 | if (!chip) | |
653 | return; | |
654 | ||
655 | gpio_free(chip->cs_gpio); | |
656 | ||
657 | kfree(chip); | |
658 | } | |
659 | ||
660 | static int | |
661 | bfin_sport_spi_init_queue(struct bfin_sport_spi_master_data *drv_data) | |
662 | { | |
663 | INIT_LIST_HEAD(&drv_data->queue); | |
664 | spin_lock_init(&drv_data->lock); | |
665 | ||
666 | drv_data->run = false; | |
667 | drv_data->busy = 0; | |
668 | ||
669 | /* init transfer tasklet */ | |
670 | tasklet_init(&drv_data->pump_transfers, | |
671 | bfin_sport_spi_pump_transfers, (unsigned long)drv_data); | |
672 | ||
673 | /* init messages workqueue */ | |
674 | INIT_WORK(&drv_data->pump_messages, bfin_sport_spi_pump_messages); | |
675 | drv_data->workqueue = | |
676 | create_singlethread_workqueue(dev_name(drv_data->master->dev.parent)); | |
677 | if (drv_data->workqueue == NULL) | |
678 | return -EBUSY; | |
679 | ||
680 | return 0; | |
681 | } | |
682 | ||
683 | static int | |
684 | bfin_sport_spi_start_queue(struct bfin_sport_spi_master_data *drv_data) | |
685 | { | |
686 | unsigned long flags; | |
687 | ||
688 | spin_lock_irqsave(&drv_data->lock, flags); | |
689 | ||
690 | if (drv_data->run || drv_data->busy) { | |
691 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
692 | return -EBUSY; | |
693 | } | |
694 | ||
695 | drv_data->run = true; | |
696 | drv_data->cur_msg = NULL; | |
697 | drv_data->cur_transfer = NULL; | |
698 | drv_data->cur_chip = NULL; | |
699 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
700 | ||
701 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
702 | ||
703 | return 0; | |
704 | } | |
705 | ||
706 | static inline int | |
707 | bfin_sport_spi_stop_queue(struct bfin_sport_spi_master_data *drv_data) | |
708 | { | |
709 | unsigned long flags; | |
710 | unsigned limit = 500; | |
711 | int status = 0; | |
712 | ||
713 | spin_lock_irqsave(&drv_data->lock, flags); | |
714 | ||
715 | /* | |
716 | * This is a bit lame, but is optimized for the common execution path. | |
717 | * A wait_queue on the drv_data->busy could be used, but then the common | |
718 | * execution path (pump_messages) would be required to call wake_up or | |
719 | * friends on every SPI message. Do this instead | |
720 | */ | |
721 | drv_data->run = false; | |
722 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { | |
723 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
724 | msleep(10); | |
725 | spin_lock_irqsave(&drv_data->lock, flags); | |
726 | } | |
727 | ||
728 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
729 | status = -EBUSY; | |
730 | ||
731 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
732 | ||
733 | return status; | |
734 | } | |
735 | ||
736 | static inline int | |
737 | bfin_sport_spi_destroy_queue(struct bfin_sport_spi_master_data *drv_data) | |
738 | { | |
739 | int status; | |
740 | ||
741 | status = bfin_sport_spi_stop_queue(drv_data); | |
742 | if (status) | |
743 | return status; | |
744 | ||
745 | destroy_workqueue(drv_data->workqueue); | |
746 | ||
747 | return 0; | |
748 | } | |
749 | ||
fd4a319b | 750 | static int bfin_sport_spi_probe(struct platform_device *pdev) |
9c3e7375 CC |
751 | { |
752 | struct device *dev = &pdev->dev; | |
753 | struct bfin5xx_spi_master *platform_info; | |
754 | struct spi_master *master; | |
755 | struct resource *res, *ires; | |
756 | struct bfin_sport_spi_master_data *drv_data; | |
757 | int status; | |
758 | ||
8074cf06 | 759 | platform_info = dev_get_platdata(dev); |
9c3e7375 CC |
760 | |
761 | /* Allocate master with space for drv_data */ | |
762 | master = spi_alloc_master(dev, sizeof(*master) + 16); | |
763 | if (!master) { | |
764 | dev_err(dev, "cannot alloc spi_master\n"); | |
765 | return -ENOMEM; | |
766 | } | |
767 | ||
768 | drv_data = spi_master_get_devdata(master); | |
769 | drv_data->master = master; | |
770 | drv_data->dev = dev; | |
771 | drv_data->pin_req = platform_info->pin_req; | |
772 | ||
773 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; | |
24778be2 | 774 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); |
9c3e7375 CC |
775 | master->bus_num = pdev->id; |
776 | master->num_chipselect = platform_info->num_chipselect; | |
777 | master->cleanup = bfin_sport_spi_cleanup; | |
778 | master->setup = bfin_sport_spi_setup; | |
779 | master->transfer = bfin_sport_spi_transfer; | |
780 | ||
781 | /* Find and map our resources */ | |
782 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
783 | if (res == NULL) { | |
784 | dev_err(dev, "cannot get IORESOURCE_MEM\n"); | |
785 | status = -ENOENT; | |
786 | goto out_error_get_res; | |
787 | } | |
788 | ||
789 | drv_data->regs = ioremap(res->start, resource_size(res)); | |
790 | if (drv_data->regs == NULL) { | |
791 | dev_err(dev, "cannot map registers\n"); | |
792 | status = -ENXIO; | |
793 | goto out_error_ioremap; | |
794 | } | |
795 | ||
796 | ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
797 | if (!ires) { | |
798 | dev_err(dev, "cannot get IORESOURCE_IRQ\n"); | |
799 | status = -ENODEV; | |
800 | goto out_error_get_ires; | |
801 | } | |
802 | drv_data->err_irq = ires->start; | |
803 | ||
804 | /* Initial and start queue */ | |
805 | status = bfin_sport_spi_init_queue(drv_data); | |
806 | if (status) { | |
807 | dev_err(dev, "problem initializing queue\n"); | |
808 | goto out_error_queue_alloc; | |
809 | } | |
810 | ||
811 | status = bfin_sport_spi_start_queue(drv_data); | |
812 | if (status) { | |
813 | dev_err(dev, "problem starting queue\n"); | |
814 | goto out_error_queue_alloc; | |
815 | } | |
816 | ||
817 | status = request_irq(drv_data->err_irq, sport_err_handler, | |
818 | 0, "sport_spi_err", drv_data); | |
819 | if (status) { | |
820 | dev_err(dev, "unable to request sport err irq\n"); | |
821 | goto out_error_irq; | |
822 | } | |
823 | ||
824 | status = peripheral_request_list(drv_data->pin_req, DRV_NAME); | |
825 | if (status) { | |
826 | dev_err(dev, "requesting peripherals failed\n"); | |
827 | goto out_error_peripheral; | |
828 | } | |
829 | ||
830 | /* Register with the SPI framework */ | |
831 | platform_set_drvdata(pdev, drv_data); | |
832 | status = spi_register_master(master); | |
833 | if (status) { | |
834 | dev_err(dev, "problem registering spi master\n"); | |
835 | goto out_error_master; | |
836 | } | |
837 | ||
838 | dev_info(dev, "%s, regs_base@%p\n", DRV_DESC, drv_data->regs); | |
839 | return 0; | |
840 | ||
841 | out_error_master: | |
842 | peripheral_free_list(drv_data->pin_req); | |
843 | out_error_peripheral: | |
844 | free_irq(drv_data->err_irq, drv_data); | |
845 | out_error_irq: | |
846 | out_error_queue_alloc: | |
847 | bfin_sport_spi_destroy_queue(drv_data); | |
848 | out_error_get_ires: | |
849 | iounmap(drv_data->regs); | |
850 | out_error_ioremap: | |
851 | out_error_get_res: | |
852 | spi_master_put(master); | |
853 | ||
854 | return status; | |
855 | } | |
856 | ||
857 | /* stop hardware and remove the driver */ | |
fd4a319b | 858 | static int bfin_sport_spi_remove(struct platform_device *pdev) |
9c3e7375 CC |
859 | { |
860 | struct bfin_sport_spi_master_data *drv_data = platform_get_drvdata(pdev); | |
861 | int status = 0; | |
862 | ||
863 | if (!drv_data) | |
864 | return 0; | |
865 | ||
866 | /* Remove the queue */ | |
867 | status = bfin_sport_spi_destroy_queue(drv_data); | |
868 | if (status) | |
869 | return status; | |
870 | ||
871 | /* Disable the SSP at the peripheral and SOC level */ | |
872 | bfin_sport_spi_disable(drv_data); | |
873 | ||
874 | /* Disconnect from the SPI framework */ | |
875 | spi_unregister_master(drv_data->master); | |
876 | ||
877 | peripheral_free_list(drv_data->pin_req); | |
878 | ||
9c3e7375 CC |
879 | return 0; |
880 | } | |
881 | ||
882 | #ifdef CONFIG_PM | |
883 | static int | |
884 | bfin_sport_spi_suspend(struct platform_device *pdev, pm_message_t state) | |
885 | { | |
886 | struct bfin_sport_spi_master_data *drv_data = platform_get_drvdata(pdev); | |
887 | int status; | |
888 | ||
889 | status = bfin_sport_spi_stop_queue(drv_data); | |
890 | if (status) | |
891 | return status; | |
892 | ||
893 | /* stop hardware */ | |
894 | bfin_sport_spi_disable(drv_data); | |
895 | ||
896 | return status; | |
897 | } | |
898 | ||
899 | static int | |
900 | bfin_sport_spi_resume(struct platform_device *pdev) | |
901 | { | |
902 | struct bfin_sport_spi_master_data *drv_data = platform_get_drvdata(pdev); | |
903 | int status; | |
904 | ||
905 | /* Enable the SPI interface */ | |
906 | bfin_sport_spi_enable(drv_data); | |
907 | ||
908 | /* Start the queue running */ | |
909 | status = bfin_sport_spi_start_queue(drv_data); | |
910 | if (status) | |
911 | dev_err(drv_data->dev, "problem resuming queue\n"); | |
912 | ||
913 | return status; | |
914 | } | |
915 | #else | |
916 | # define bfin_sport_spi_suspend NULL | |
917 | # define bfin_sport_spi_resume NULL | |
918 | #endif | |
919 | ||
920 | static struct platform_driver bfin_sport_spi_driver = { | |
921 | .driver = { | |
922 | .name = DRV_NAME, | |
923 | .owner = THIS_MODULE, | |
924 | }, | |
925 | .probe = bfin_sport_spi_probe, | |
fd4a319b | 926 | .remove = bfin_sport_spi_remove, |
9c3e7375 CC |
927 | .suspend = bfin_sport_spi_suspend, |
928 | .resume = bfin_sport_spi_resume, | |
929 | }; | |
940ab889 | 930 | module_platform_driver(bfin_sport_spi_driver); |