]>
Commit | Line | Data |
---|---|---|
a5f6abd4 | 1 | /* |
26fdc1f0 | 2 | * Blackfin On-Chip SPI Driver |
a5f6abd4 | 3 | * |
9c0a788b | 4 | * Copyright 2004-2010 Analog Devices Inc. |
a5f6abd4 | 5 | * |
26fdc1f0 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
a5f6abd4 | 7 | * |
26fdc1f0 | 8 | * Licensed under the GPL-2 or later. |
a5f6abd4 WB |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
131b17d4 | 13 | #include <linux/delay.h> |
a5f6abd4 | 14 | #include <linux/device.h> |
e8304d04 | 15 | #include <linux/gpio.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
131b17d4 | 17 | #include <linux/io.h> |
a5f6abd4 | 18 | #include <linux/ioport.h> |
131b17d4 | 19 | #include <linux/irq.h> |
a5f6abd4 WB |
20 | #include <linux/errno.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/spi/spi.h> | |
25 | #include <linux/workqueue.h> | |
a5f6abd4 | 26 | |
a5f6abd4 | 27 | #include <asm/dma.h> |
131b17d4 | 28 | #include <asm/portmux.h> |
a5f6abd4 | 29 | #include <asm/bfin5xx_spi.h> |
8cf5858c VM |
30 | #include <asm/cacheflush.h> |
31 | ||
a32c691d BW |
32 | #define DRV_NAME "bfin-spi" |
33 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
138f97cd | 34 | #define DRV_DESC "Blackfin on-chip SPI Controller Driver" |
a32c691d BW |
35 | #define DRV_VERSION "1.0" |
36 | ||
37 | MODULE_AUTHOR(DRV_AUTHOR); | |
38 | MODULE_DESCRIPTION(DRV_DESC); | |
a5f6abd4 WB |
39 | MODULE_LICENSE("GPL"); |
40 | ||
bb90eb00 BW |
41 | #define START_STATE ((void *)0) |
42 | #define RUNNING_STATE ((void *)1) | |
43 | #define DONE_STATE ((void *)2) | |
44 | #define ERROR_STATE ((void *)-1) | |
a5f6abd4 | 45 | |
9c0a788b | 46 | struct bfin_spi_master_data; |
9c4542c7 | 47 | |
9c0a788b MF |
48 | struct bfin_spi_transfer_ops { |
49 | void (*write) (struct bfin_spi_master_data *); | |
50 | void (*read) (struct bfin_spi_master_data *); | |
51 | void (*duplex) (struct bfin_spi_master_data *); | |
9c4542c7 MF |
52 | }; |
53 | ||
9c0a788b | 54 | struct bfin_spi_master_data { |
a5f6abd4 WB |
55 | /* Driver model hookup */ |
56 | struct platform_device *pdev; | |
57 | ||
58 | /* SPI framework hookup */ | |
59 | struct spi_master *master; | |
60 | ||
bb90eb00 | 61 | /* Regs base of SPI controller */ |
47885ce8 | 62 | struct bfin_spi_regs __iomem *regs; |
bb90eb00 | 63 | |
003d9226 BW |
64 | /* Pin request list */ |
65 | u16 *pin_req; | |
66 | ||
a5f6abd4 WB |
67 | /* BFIN hookup */ |
68 | struct bfin5xx_spi_master *master_info; | |
69 | ||
a5f6abd4 WB |
70 | struct work_struct pump_messages; |
71 | spinlock_t lock; | |
72 | struct list_head queue; | |
73 | int busy; | |
f4f50c3f | 74 | bool running; |
a5f6abd4 WB |
75 | |
76 | /* Message Transfer pump */ | |
77 | struct tasklet_struct pump_transfers; | |
78 | ||
79 | /* Current message transfer state info */ | |
80 | struct spi_message *cur_msg; | |
81 | struct spi_transfer *cur_transfer; | |
9c0a788b | 82 | struct bfin_spi_slave_data *cur_chip; |
a5f6abd4 WB |
83 | size_t len_in_bytes; |
84 | size_t len; | |
85 | void *tx; | |
86 | void *tx_end; | |
87 | void *rx; | |
88 | void *rx_end; | |
bb90eb00 BW |
89 | |
90 | /* DMA stuffs */ | |
91 | int dma_channel; | |
a5f6abd4 | 92 | int dma_mapped; |
bb90eb00 | 93 | int dma_requested; |
a5f6abd4 WB |
94 | dma_addr_t rx_dma; |
95 | dma_addr_t tx_dma; | |
bb90eb00 | 96 | |
f6a6d966 YL |
97 | int irq_requested; |
98 | int spi_irq; | |
99 | ||
a5f6abd4 WB |
100 | size_t rx_map_len; |
101 | size_t tx_map_len; | |
102 | u8 n_bytes; | |
b052fd0a BS |
103 | u16 ctrl_reg; |
104 | u16 flag_reg; | |
105 | ||
fad91c89 | 106 | int cs_change; |
9c0a788b | 107 | const struct bfin_spi_transfer_ops *ops; |
a5f6abd4 WB |
108 | }; |
109 | ||
9c0a788b | 110 | struct bfin_spi_slave_data { |
a5f6abd4 WB |
111 | u16 ctl_reg; |
112 | u16 baud; | |
113 | u16 flag; | |
114 | ||
115 | u8 chip_select_num; | |
a5f6abd4 | 116 | u8 enable_dma; |
62310e51 | 117 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ |
42c78b2b | 118 | u32 cs_gpio; |
93b61bdd | 119 | u16 idle_tx_val; |
f6a6d966 | 120 | u8 pio_interrupt; /* use spi data irq */ |
9c0a788b | 121 | const struct bfin_spi_transfer_ops *ops; |
a5f6abd4 WB |
122 | }; |
123 | ||
9c0a788b | 124 | static void bfin_spi_enable(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 125 | { |
47885ce8 | 126 | bfin_write_or(&drv_data->regs->ctl, BIT_CTL_ENABLE); |
a5f6abd4 WB |
127 | } |
128 | ||
9c0a788b | 129 | static void bfin_spi_disable(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 130 | { |
47885ce8 | 131 | bfin_write_and(&drv_data->regs->ctl, ~BIT_CTL_ENABLE); |
a5f6abd4 WB |
132 | } |
133 | ||
134 | /* Caculate the SPI_BAUD register value based on input HZ */ | |
135 | static u16 hz_to_spi_baud(u32 speed_hz) | |
136 | { | |
137 | u_long sclk = get_sclk(); | |
138 | u16 spi_baud = (sclk / (2 * speed_hz)); | |
139 | ||
140 | if ((sclk % (2 * speed_hz)) > 0) | |
141 | spi_baud++; | |
142 | ||
7513e006 MH |
143 | if (spi_baud < MIN_SPI_BAUD_VAL) |
144 | spi_baud = MIN_SPI_BAUD_VAL; | |
145 | ||
a5f6abd4 WB |
146 | return spi_baud; |
147 | } | |
148 | ||
9c0a788b | 149 | static int bfin_spi_flush(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
150 | { |
151 | unsigned long limit = loops_per_jiffy << 1; | |
152 | ||
153 | /* wait for stop and clear stat */ | |
47885ce8 | 154 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF) && --limit) |
d8c05008 | 155 | cpu_relax(); |
a5f6abd4 | 156 | |
47885ce8 | 157 | bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); |
a5f6abd4 WB |
158 | |
159 | return limit; | |
160 | } | |
161 | ||
fad91c89 | 162 | /* Chip select operation functions for cs_change flag */ |
9c0a788b | 163 | static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip) |
fad91c89 | 164 | { |
47885ce8 MF |
165 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) |
166 | bfin_write_and(&drv_data->regs->flg, ~chip->flag); | |
167 | else | |
42c78b2b | 168 | gpio_set_value(chip->cs_gpio, 0); |
fad91c89 BW |
169 | } |
170 | ||
9c0a788b MF |
171 | static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data, |
172 | struct bfin_spi_slave_data *chip) | |
fad91c89 | 173 | { |
47885ce8 MF |
174 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) |
175 | bfin_write_or(&drv_data->regs->flg, chip->flag); | |
176 | else | |
42c78b2b | 177 | gpio_set_value(chip->cs_gpio, 1); |
62310e51 BW |
178 | |
179 | /* Move delay here for consistency */ | |
180 | if (chip->cs_chg_udelay) | |
181 | udelay(chip->cs_chg_udelay); | |
fad91c89 BW |
182 | } |
183 | ||
8221610e | 184 | /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */ |
9c0a788b MF |
185 | static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data, |
186 | struct bfin_spi_slave_data *chip) | |
8221610e | 187 | { |
47885ce8 MF |
188 | if (chip->chip_select_num < MAX_CTRL_CS) |
189 | bfin_write_or(&drv_data->regs->flg, chip->flag >> 8); | |
8221610e BS |
190 | } |
191 | ||
9c0a788b MF |
192 | static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data, |
193 | struct bfin_spi_slave_data *chip) | |
8221610e | 194 | { |
47885ce8 MF |
195 | if (chip->chip_select_num < MAX_CTRL_CS) |
196 | bfin_write_and(&drv_data->regs->flg, ~(chip->flag >> 8)); | |
8221610e BS |
197 | } |
198 | ||
a5f6abd4 | 199 | /* stop controller and re-config current chip*/ |
9c0a788b | 200 | static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 201 | { |
9c0a788b | 202 | struct bfin_spi_slave_data *chip = drv_data->cur_chip; |
12e17c42 | 203 | |
a5f6abd4 | 204 | /* Clear status and disable clock */ |
47885ce8 | 205 | bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); |
a5f6abd4 | 206 | bfin_spi_disable(drv_data); |
88b40369 | 207 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
a5f6abd4 | 208 | |
9677b0de BS |
209 | SSYNC(); |
210 | ||
5fec5b5a | 211 | /* Load the registers */ |
47885ce8 MF |
212 | bfin_write(&drv_data->regs->ctl, chip->ctl_reg); |
213 | bfin_write(&drv_data->regs->baud, chip->baud); | |
cc487e73 SZ |
214 | |
215 | bfin_spi_enable(drv_data); | |
138f97cd | 216 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 WB |
217 | } |
218 | ||
93b61bdd | 219 | /* used to kick off transfer in rx mode and read unwanted RX data */ |
9c0a788b | 220 | static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 221 | { |
47885ce8 | 222 | (void) bfin_read(&drv_data->regs->rdbr); |
a5f6abd4 WB |
223 | } |
224 | ||
9c0a788b | 225 | static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 226 | { |
93b61bdd WM |
227 | /* clear RXS (we check for RXS inside the loop) */ |
228 | bfin_spi_dummy_read(drv_data); | |
cc487e73 | 229 | |
a5f6abd4 | 230 | while (drv_data->tx < drv_data->tx_end) { |
47885ce8 | 231 | bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++))); |
93b61bdd WM |
232 | /* wait until transfer finished. |
233 | checking SPIF or TXS may not guarantee transfer completion */ | |
47885ce8 | 234 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
d8c05008 | 235 | cpu_relax(); |
93b61bdd WM |
236 | /* discard RX data and clear RXS */ |
237 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 238 | } |
a5f6abd4 WB |
239 | } |
240 | ||
9c0a788b | 241 | static void bfin_spi_u8_reader(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 242 | { |
93b61bdd | 243 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
a5f6abd4 | 244 | |
93b61bdd | 245 | /* discard old RX data and clear RXS */ |
138f97cd | 246 | bfin_spi_dummy_read(drv_data); |
cc487e73 | 247 | |
93b61bdd | 248 | while (drv_data->rx < drv_data->rx_end) { |
47885ce8 MF |
249 | bfin_write(&drv_data->regs->tdbr, tx_val); |
250 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) | |
d8c05008 | 251 | cpu_relax(); |
47885ce8 | 252 | *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr); |
a5f6abd4 | 253 | } |
a5f6abd4 WB |
254 | } |
255 | ||
9c0a788b | 256 | static void bfin_spi_u8_duplex(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 257 | { |
93b61bdd WM |
258 | /* discard old RX data and clear RXS */ |
259 | bfin_spi_dummy_read(drv_data); | |
260 | ||
a5f6abd4 | 261 | while (drv_data->rx < drv_data->rx_end) { |
47885ce8 MF |
262 | bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++))); |
263 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) | |
d8c05008 | 264 | cpu_relax(); |
47885ce8 | 265 | *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr); |
a5f6abd4 WB |
266 | } |
267 | } | |
268 | ||
9c0a788b | 269 | static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = { |
9c4542c7 MF |
270 | .write = bfin_spi_u8_writer, |
271 | .read = bfin_spi_u8_reader, | |
272 | .duplex = bfin_spi_u8_duplex, | |
273 | }; | |
274 | ||
9c0a788b | 275 | static void bfin_spi_u16_writer(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 276 | { |
93b61bdd WM |
277 | /* clear RXS (we check for RXS inside the loop) */ |
278 | bfin_spi_dummy_read(drv_data); | |
88b40369 | 279 | |
a5f6abd4 | 280 | while (drv_data->tx < drv_data->tx_end) { |
47885ce8 | 281 | bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx))); |
a5f6abd4 | 282 | drv_data->tx += 2; |
93b61bdd WM |
283 | /* wait until transfer finished. |
284 | checking SPIF or TXS may not guarantee transfer completion */ | |
47885ce8 | 285 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
93b61bdd WM |
286 | cpu_relax(); |
287 | /* discard RX data and clear RXS */ | |
288 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 289 | } |
a5f6abd4 WB |
290 | } |
291 | ||
9c0a788b | 292 | static void bfin_spi_u16_reader(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 293 | { |
93b61bdd | 294 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
cc487e73 | 295 | |
93b61bdd | 296 | /* discard old RX data and clear RXS */ |
138f97cd | 297 | bfin_spi_dummy_read(drv_data); |
a5f6abd4 | 298 | |
93b61bdd | 299 | while (drv_data->rx < drv_data->rx_end) { |
47885ce8 MF |
300 | bfin_write(&drv_data->regs->tdbr, tx_val); |
301 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) | |
d8c05008 | 302 | cpu_relax(); |
47885ce8 | 303 | *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr); |
a5f6abd4 WB |
304 | drv_data->rx += 2; |
305 | } | |
a5f6abd4 WB |
306 | } |
307 | ||
9c0a788b | 308 | static void bfin_spi_u16_duplex(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 309 | { |
93b61bdd WM |
310 | /* discard old RX data and clear RXS */ |
311 | bfin_spi_dummy_read(drv_data); | |
312 | ||
313 | while (drv_data->rx < drv_data->rx_end) { | |
47885ce8 | 314 | bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx))); |
93b61bdd | 315 | drv_data->tx += 2; |
47885ce8 | 316 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
d8c05008 | 317 | cpu_relax(); |
47885ce8 | 318 | *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr); |
a5f6abd4 | 319 | drv_data->rx += 2; |
a5f6abd4 WB |
320 | } |
321 | } | |
322 | ||
9c0a788b | 323 | static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = { |
9c4542c7 MF |
324 | .write = bfin_spi_u16_writer, |
325 | .read = bfin_spi_u16_reader, | |
326 | .duplex = bfin_spi_u16_duplex, | |
327 | }; | |
328 | ||
e3595405 | 329 | /* test if there is more transfer to be done */ |
9c0a788b | 330 | static void *bfin_spi_next_transfer(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
331 | { |
332 | struct spi_message *msg = drv_data->cur_msg; | |
333 | struct spi_transfer *trans = drv_data->cur_transfer; | |
334 | ||
335 | /* Move to next transfer */ | |
336 | if (trans->transfer_list.next != &msg->transfers) { | |
337 | drv_data->cur_transfer = | |
338 | list_entry(trans->transfer_list.next, | |
339 | struct spi_transfer, transfer_list); | |
340 | return RUNNING_STATE; | |
341 | } else | |
342 | return DONE_STATE; | |
343 | } | |
344 | ||
345 | /* | |
346 | * caller already set message->status; | |
347 | * dma and pio irqs are blocked give finished message back | |
348 | */ | |
9c0a788b | 349 | static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 350 | { |
9c0a788b | 351 | struct bfin_spi_slave_data *chip = drv_data->cur_chip; |
a5f6abd4 WB |
352 | unsigned long flags; |
353 | struct spi_message *msg; | |
354 | ||
355 | spin_lock_irqsave(&drv_data->lock, flags); | |
356 | msg = drv_data->cur_msg; | |
357 | drv_data->cur_msg = NULL; | |
358 | drv_data->cur_transfer = NULL; | |
359 | drv_data->cur_chip = NULL; | |
9b96f070 | 360 | schedule_work(&drv_data->pump_messages); |
a5f6abd4 WB |
361 | spin_unlock_irqrestore(&drv_data->lock, flags); |
362 | ||
a5f6abd4 WB |
363 | msg->state = NULL; |
364 | ||
fad91c89 | 365 | if (!drv_data->cs_change) |
138f97cd | 366 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 367 | |
b9b2a76a YL |
368 | /* Not stop spi in autobuffer mode */ |
369 | if (drv_data->tx_dma != 0xFFFF) | |
370 | bfin_spi_disable(drv_data); | |
371 | ||
a5f6abd4 WB |
372 | if (msg->complete) |
373 | msg->complete(msg->context); | |
374 | } | |
375 | ||
f6a6d966 YL |
376 | /* spi data irq handler */ |
377 | static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id) | |
378 | { | |
9c0a788b MF |
379 | struct bfin_spi_master_data *drv_data = dev_id; |
380 | struct bfin_spi_slave_data *chip = drv_data->cur_chip; | |
f6a6d966 YL |
381 | struct spi_message *msg = drv_data->cur_msg; |
382 | int n_bytes = drv_data->n_bytes; | |
4d676fc5 | 383 | int loop = 0; |
f6a6d966 YL |
384 | |
385 | /* wait until transfer finished. */ | |
47885ce8 | 386 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
f6a6d966 YL |
387 | cpu_relax(); |
388 | ||
389 | if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) || | |
390 | (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) { | |
391 | /* last read */ | |
392 | if (drv_data->rx) { | |
393 | dev_dbg(&drv_data->pdev->dev, "last read\n"); | |
128465ca | 394 | if (!(n_bytes % 2)) { |
4d676fc5 BL |
395 | u16 *buf = (u16 *)drv_data->rx; |
396 | for (loop = 0; loop < n_bytes / 2; loop++) | |
47885ce8 | 397 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
4d676fc5 BL |
398 | } else { |
399 | u8 *buf = (u8 *)drv_data->rx; | |
400 | for (loop = 0; loop < n_bytes; loop++) | |
47885ce8 | 401 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
4d676fc5 | 402 | } |
f6a6d966 YL |
403 | drv_data->rx += n_bytes; |
404 | } | |
405 | ||
406 | msg->actual_length += drv_data->len_in_bytes; | |
407 | if (drv_data->cs_change) | |
408 | bfin_spi_cs_deactive(drv_data, chip); | |
409 | /* Move to next transfer */ | |
410 | msg->state = bfin_spi_next_transfer(drv_data); | |
411 | ||
7370ed6b | 412 | disable_irq_nosync(drv_data->spi_irq); |
f6a6d966 YL |
413 | |
414 | /* Schedule transfer tasklet */ | |
415 | tasklet_schedule(&drv_data->pump_transfers); | |
416 | return IRQ_HANDLED; | |
417 | } | |
418 | ||
419 | if (drv_data->rx && drv_data->tx) { | |
420 | /* duplex */ | |
421 | dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n"); | |
128465ca | 422 | if (!(n_bytes % 2)) { |
4d676fc5 BL |
423 | u16 *buf = (u16 *)drv_data->rx; |
424 | u16 *buf2 = (u16 *)drv_data->tx; | |
425 | for (loop = 0; loop < n_bytes / 2; loop++) { | |
47885ce8 MF |
426 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
427 | bfin_write(&drv_data->regs->tdbr, *buf2++); | |
4d676fc5 BL |
428 | } |
429 | } else { | |
430 | u8 *buf = (u8 *)drv_data->rx; | |
431 | u8 *buf2 = (u8 *)drv_data->tx; | |
432 | for (loop = 0; loop < n_bytes; loop++) { | |
47885ce8 MF |
433 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
434 | bfin_write(&drv_data->regs->tdbr, *buf2++); | |
4d676fc5 | 435 | } |
f6a6d966 YL |
436 | } |
437 | } else if (drv_data->rx) { | |
438 | /* read */ | |
439 | dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n"); | |
128465ca | 440 | if (!(n_bytes % 2)) { |
4d676fc5 BL |
441 | u16 *buf = (u16 *)drv_data->rx; |
442 | for (loop = 0; loop < n_bytes / 2; loop++) { | |
47885ce8 MF |
443 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
444 | bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val); | |
4d676fc5 BL |
445 | } |
446 | } else { | |
447 | u8 *buf = (u8 *)drv_data->rx; | |
448 | for (loop = 0; loop < n_bytes; loop++) { | |
47885ce8 MF |
449 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
450 | bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val); | |
4d676fc5 BL |
451 | } |
452 | } | |
f6a6d966 YL |
453 | } else if (drv_data->tx) { |
454 | /* write */ | |
455 | dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n"); | |
128465ca | 456 | if (!(n_bytes % 2)) { |
4d676fc5 BL |
457 | u16 *buf = (u16 *)drv_data->tx; |
458 | for (loop = 0; loop < n_bytes / 2; loop++) { | |
47885ce8 MF |
459 | bfin_read(&drv_data->regs->rdbr); |
460 | bfin_write(&drv_data->regs->tdbr, *buf++); | |
4d676fc5 BL |
461 | } |
462 | } else { | |
463 | u8 *buf = (u8 *)drv_data->tx; | |
464 | for (loop = 0; loop < n_bytes; loop++) { | |
47885ce8 MF |
465 | bfin_read(&drv_data->regs->rdbr); |
466 | bfin_write(&drv_data->regs->tdbr, *buf++); | |
4d676fc5 BL |
467 | } |
468 | } | |
f6a6d966 YL |
469 | } |
470 | ||
471 | if (drv_data->tx) | |
472 | drv_data->tx += n_bytes; | |
473 | if (drv_data->rx) | |
474 | drv_data->rx += n_bytes; | |
475 | ||
476 | return IRQ_HANDLED; | |
477 | } | |
478 | ||
138f97cd | 479 | static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id) |
a5f6abd4 | 480 | { |
9c0a788b MF |
481 | struct bfin_spi_master_data *drv_data = dev_id; |
482 | struct bfin_spi_slave_data *chip = drv_data->cur_chip; | |
bb90eb00 | 483 | struct spi_message *msg = drv_data->cur_msg; |
aaaf939c | 484 | unsigned long timeout; |
d24bd1d0 | 485 | unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel); |
47885ce8 | 486 | u16 spistat = bfin_read(&drv_data->regs->stat); |
a5f6abd4 | 487 | |
d24bd1d0 MF |
488 | dev_dbg(&drv_data->pdev->dev, |
489 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
490 | dmastat, spistat); | |
491 | ||
782a8956 | 492 | if (drv_data->rx != NULL) { |
47885ce8 | 493 | u16 cr = bfin_read(&drv_data->regs->ctl); |
782a8956 MH |
494 | /* discard old RX data and clear RXS */ |
495 | bfin_spi_dummy_read(drv_data); | |
47885ce8 MF |
496 | bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_ENABLE); /* Disable SPI */ |
497 | bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_TIMOD); /* Restore State */ | |
498 | bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); /* Clear Status */ | |
782a8956 MH |
499 | } |
500 | ||
bb90eb00 | 501 | clear_dma_irqstat(drv_data->dma_channel); |
a5f6abd4 WB |
502 | |
503 | /* | |
d6fe89b0 BW |
504 | * wait for the last transaction shifted out. HRM states: |
505 | * at this point there may still be data in the SPI DMA FIFO waiting | |
506 | * to be transmitted ... software needs to poll TXS in the SPI_STAT | |
507 | * register until it goes low for 2 successive reads | |
a5f6abd4 WB |
508 | */ |
509 | if (drv_data->tx != NULL) { | |
47885ce8 MF |
510 | while ((bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS) || |
511 | (bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS)) | |
d8c05008 | 512 | cpu_relax(); |
a5f6abd4 WB |
513 | } |
514 | ||
aaaf939c MF |
515 | dev_dbg(&drv_data->pdev->dev, |
516 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
47885ce8 | 517 | dmastat, bfin_read(&drv_data->regs->stat)); |
aaaf939c MF |
518 | |
519 | timeout = jiffies + HZ; | |
47885ce8 | 520 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF)) |
aaaf939c | 521 | if (!time_before(jiffies, timeout)) { |
a1829d2b | 522 | dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF\n"); |
aaaf939c MF |
523 | break; |
524 | } else | |
525 | cpu_relax(); | |
a5f6abd4 | 526 | |
90008a64 | 527 | if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) { |
04b95d2f MF |
528 | msg->state = ERROR_STATE; |
529 | dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n"); | |
530 | } else { | |
531 | msg->actual_length += drv_data->len_in_bytes; | |
a5f6abd4 | 532 | |
04b95d2f | 533 | if (drv_data->cs_change) |
138f97cd | 534 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 535 | |
04b95d2f | 536 | /* Move to next transfer */ |
138f97cd | 537 | msg->state = bfin_spi_next_transfer(drv_data); |
04b95d2f | 538 | } |
a5f6abd4 WB |
539 | |
540 | /* Schedule transfer tasklet */ | |
541 | tasklet_schedule(&drv_data->pump_transfers); | |
542 | ||
543 | /* free the irq handler before next transfer */ | |
88b40369 BW |
544 | dev_dbg(&drv_data->pdev->dev, |
545 | "disable dma channel irq%d\n", | |
bb90eb00 | 546 | drv_data->dma_channel); |
a75bd65b | 547 | dma_disable_irq_nosync(drv_data->dma_channel); |
a5f6abd4 WB |
548 | |
549 | return IRQ_HANDLED; | |
550 | } | |
551 | ||
138f97cd | 552 | static void bfin_spi_pump_transfers(unsigned long data) |
a5f6abd4 | 553 | { |
9c0a788b | 554 | struct bfin_spi_master_data *drv_data = (struct bfin_spi_master_data *)data; |
a5f6abd4 WB |
555 | struct spi_message *message = NULL; |
556 | struct spi_transfer *transfer = NULL; | |
557 | struct spi_transfer *previous = NULL; | |
9c0a788b | 558 | struct bfin_spi_slave_data *chip = NULL; |
033f44bd | 559 | unsigned int bits_per_word; |
057f6061 | 560 | u16 cr, cr_width = 0, dma_width, dma_config; |
a5f6abd4 | 561 | u32 tranf_success = 1; |
8eeb12e5 | 562 | u8 full_duplex = 0; |
a5f6abd4 WB |
563 | |
564 | /* Get current state information */ | |
565 | message = drv_data->cur_msg; | |
566 | transfer = drv_data->cur_transfer; | |
567 | chip = drv_data->cur_chip; | |
092e1fda | 568 | |
a5f6abd4 WB |
569 | /* |
570 | * if msg is error or done, report it back using complete() callback | |
571 | */ | |
572 | ||
573 | /* Handle for abort */ | |
574 | if (message->state == ERROR_STATE) { | |
d24bd1d0 | 575 | dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n"); |
a5f6abd4 | 576 | message->status = -EIO; |
138f97cd | 577 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
578 | return; |
579 | } | |
580 | ||
581 | /* Handle end of message */ | |
582 | if (message->state == DONE_STATE) { | |
d24bd1d0 | 583 | dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); |
a5f6abd4 | 584 | message->status = 0; |
2431a815 | 585 | bfin_spi_flush(drv_data); |
138f97cd | 586 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
587 | return; |
588 | } | |
589 | ||
590 | /* Delay if requested at end of transfer */ | |
591 | if (message->state == RUNNING_STATE) { | |
d24bd1d0 | 592 | dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n"); |
a5f6abd4 WB |
593 | previous = list_entry(transfer->transfer_list.prev, |
594 | struct spi_transfer, transfer_list); | |
595 | if (previous->delay_usecs) | |
596 | udelay(previous->delay_usecs); | |
597 | } | |
598 | ||
ab09e040 | 599 | /* Flush any existing transfers that may be sitting in the hardware */ |
138f97cd | 600 | if (bfin_spi_flush(drv_data) == 0) { |
a5f6abd4 WB |
601 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
602 | message->status = -EIO; | |
138f97cd | 603 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
604 | return; |
605 | } | |
606 | ||
93b61bdd WM |
607 | if (transfer->len == 0) { |
608 | /* Move to next transfer of this msg */ | |
609 | message->state = bfin_spi_next_transfer(drv_data); | |
610 | /* Schedule next transfer tasklet */ | |
611 | tasklet_schedule(&drv_data->pump_transfers); | |
1974eba6 | 612 | return; |
93b61bdd WM |
613 | } |
614 | ||
a5f6abd4 WB |
615 | if (transfer->tx_buf != NULL) { |
616 | drv_data->tx = (void *)transfer->tx_buf; | |
617 | drv_data->tx_end = drv_data->tx + transfer->len; | |
88b40369 BW |
618 | dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n", |
619 | transfer->tx_buf, drv_data->tx_end); | |
a5f6abd4 WB |
620 | } else { |
621 | drv_data->tx = NULL; | |
622 | } | |
623 | ||
624 | if (transfer->rx_buf != NULL) { | |
8eeb12e5 | 625 | full_duplex = transfer->tx_buf != NULL; |
a5f6abd4 WB |
626 | drv_data->rx = transfer->rx_buf; |
627 | drv_data->rx_end = drv_data->rx + transfer->len; | |
88b40369 BW |
628 | dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", |
629 | transfer->rx_buf, drv_data->rx_end); | |
a5f6abd4 WB |
630 | } else { |
631 | drv_data->rx = NULL; | |
632 | } | |
633 | ||
634 | drv_data->rx_dma = transfer->rx_dma; | |
635 | drv_data->tx_dma = transfer->tx_dma; | |
636 | drv_data->len_in_bytes = transfer->len; | |
fad91c89 | 637 | drv_data->cs_change = transfer->cs_change; |
a5f6abd4 | 638 | |
092e1fda | 639 | /* Bits per word setup */ |
766ed704 | 640 | bits_per_word = transfer->bits_per_word; |
24778be2 | 641 | if (bits_per_word == 16) { |
4d676fc5 | 642 | drv_data->n_bytes = bits_per_word/8; |
5e8592dc MF |
643 | drv_data->len = (transfer->len) >> 1; |
644 | cr_width = BIT_CTL_WORDSIZE; | |
9c0a788b | 645 | drv_data->ops = &bfin_bfin_spi_transfer_ops_u16; |
24778be2 | 646 | } else if (bits_per_word == 8) { |
4d676fc5 BL |
647 | drv_data->n_bytes = bits_per_word/8; |
648 | drv_data->len = transfer->len; | |
4d676fc5 | 649 | drv_data->ops = &bfin_bfin_spi_transfer_ops_u8; |
092e1fda | 650 | } |
47885ce8 | 651 | cr = bfin_read(&drv_data->regs->ctl) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE); |
5e8592dc | 652 | cr |= cr_width; |
47885ce8 | 653 | bfin_write(&drv_data->regs->ctl, cr); |
092e1fda | 654 | |
4fb98efa | 655 | dev_dbg(&drv_data->pdev->dev, |
9c4542c7 | 656 | "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n", |
9c0a788b | 657 | drv_data->ops, chip->ops, &bfin_bfin_spi_transfer_ops_u8); |
a5f6abd4 | 658 | |
a5f6abd4 WB |
659 | message->state = RUNNING_STATE; |
660 | dma_config = 0; | |
661 | ||
95a8fde2 | 662 | bfin_write(&drv_data->regs->baud, hz_to_spi_baud(transfer->speed_hz)); |
092e1fda | 663 | |
47885ce8 | 664 | bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); |
e72dcde7 | 665 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 | 666 | |
88b40369 BW |
667 | dev_dbg(&drv_data->pdev->dev, |
668 | "now pumping a transfer: width is %d, len is %d\n", | |
5e8592dc | 669 | cr_width, transfer->len); |
a5f6abd4 WB |
670 | |
671 | /* | |
8cf5858c VM |
672 | * Try to map dma buffer and do a dma transfer. If successful use, |
673 | * different way to r/w according to the enable_dma settings and if | |
674 | * we are not doing a full duplex transfer (since the hardware does | |
675 | * not support full duplex DMA transfers). | |
a5f6abd4 | 676 | */ |
8eeb12e5 VM |
677 | if (!full_duplex && drv_data->cur_chip->enable_dma |
678 | && drv_data->len > 6) { | |
a5f6abd4 | 679 | |
11d6f599 | 680 | unsigned long dma_start_addr, flags; |
7aec3566 | 681 | |
bb90eb00 BW |
682 | disable_dma(drv_data->dma_channel); |
683 | clear_dma_irqstat(drv_data->dma_channel); | |
a5f6abd4 WB |
684 | |
685 | /* config dma channel */ | |
88b40369 | 686 | dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); |
7aec3566 | 687 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
5e8592dc | 688 | if (cr_width == BIT_CTL_WORDSIZE) { |
bb90eb00 | 689 | set_dma_x_modify(drv_data->dma_channel, 2); |
a5f6abd4 WB |
690 | dma_width = WDSIZE_16; |
691 | } else { | |
bb90eb00 | 692 | set_dma_x_modify(drv_data->dma_channel, 1); |
a5f6abd4 WB |
693 | dma_width = WDSIZE_8; |
694 | } | |
695 | ||
3f479a65 | 696 | /* poll for SPI completion before start */ |
47885ce8 | 697 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF)) |
d8c05008 | 698 | cpu_relax(); |
3f479a65 | 699 | |
a5f6abd4 WB |
700 | /* dirty hack for autobuffer DMA mode */ |
701 | if (drv_data->tx_dma == 0xFFFF) { | |
88b40369 BW |
702 | dev_dbg(&drv_data->pdev->dev, |
703 | "doing autobuffer DMA out.\n"); | |
a5f6abd4 WB |
704 | |
705 | /* no irq in autobuffer mode */ | |
706 | dma_config = | |
707 | (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); | |
bb90eb00 BW |
708 | set_dma_config(drv_data->dma_channel, dma_config); |
709 | set_dma_start_addr(drv_data->dma_channel, | |
a32c691d | 710 | (unsigned long)drv_data->tx); |
bb90eb00 | 711 | enable_dma(drv_data->dma_channel); |
a5f6abd4 | 712 | |
07612e5f | 713 | /* start SPI transfer */ |
47885ce8 | 714 | bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TIMOD_DMA_TX); |
07612e5f SZ |
715 | |
716 | /* just return here, there can only be one transfer | |
717 | * in this mode | |
718 | */ | |
a5f6abd4 | 719 | message->status = 0; |
138f97cd | 720 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
721 | return; |
722 | } | |
723 | ||
724 | /* In dma mode, rx or tx must be NULL in one transfer */ | |
7aec3566 | 725 | dma_config = (RESTART | dma_width | DI_EN); |
a5f6abd4 WB |
726 | if (drv_data->rx != NULL) { |
727 | /* set transfer mode, and enable SPI */ | |
d24bd1d0 MF |
728 | dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n", |
729 | drv_data->rx, drv_data->len_in_bytes); | |
a5f6abd4 | 730 | |
8cf5858c | 731 | /* invalidate caches, if needed */ |
67834fa9 | 732 | if (bfin_addr_dcacheable((unsigned long) drv_data->rx)) |
8cf5858c VM |
733 | invalidate_dcache_range((unsigned long) drv_data->rx, |
734 | (unsigned long) (drv_data->rx + | |
ace32865 | 735 | drv_data->len_in_bytes)); |
8cf5858c | 736 | |
7aec3566 MF |
737 | dma_config |= WNR; |
738 | dma_start_addr = (unsigned long)drv_data->rx; | |
b31e27a6 | 739 | cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT; |
07612e5f | 740 | |
a5f6abd4 | 741 | } else if (drv_data->tx != NULL) { |
88b40369 | 742 | dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); |
a5f6abd4 | 743 | |
8cf5858c | 744 | /* flush caches, if needed */ |
67834fa9 | 745 | if (bfin_addr_dcacheable((unsigned long) drv_data->tx)) |
8cf5858c VM |
746 | flush_dcache_range((unsigned long) drv_data->tx, |
747 | (unsigned long) (drv_data->tx + | |
ace32865 | 748 | drv_data->len_in_bytes)); |
8cf5858c | 749 | |
7aec3566 | 750 | dma_start_addr = (unsigned long)drv_data->tx; |
b31e27a6 | 751 | cr |= BIT_CTL_TIMOD_DMA_TX; |
7aec3566 MF |
752 | |
753 | } else | |
754 | BUG(); | |
755 | ||
11d6f599 MF |
756 | /* oh man, here there be monsters ... and i dont mean the |
757 | * fluffy cute ones from pixar, i mean the kind that'll eat | |
758 | * your data, kick your dog, and love it all. do *not* try | |
759 | * and change these lines unless you (1) heavily test DMA | |
760 | * with SPI flashes on a loaded system (e.g. ping floods), | |
761 | * (2) know just how broken the DMA engine interaction with | |
762 | * the SPI peripheral is, and (3) have someone else to blame | |
763 | * when you screw it all up anyways. | |
764 | */ | |
7aec3566 | 765 | set_dma_start_addr(drv_data->dma_channel, dma_start_addr); |
11d6f599 MF |
766 | set_dma_config(drv_data->dma_channel, dma_config); |
767 | local_irq_save(flags); | |
a963ea83 | 768 | SSYNC(); |
47885ce8 | 769 | bfin_write(&drv_data->regs->ctl, cr); |
a963ea83 | 770 | enable_dma(drv_data->dma_channel); |
11d6f599 MF |
771 | dma_enable_irq(drv_data->dma_channel); |
772 | local_irq_restore(flags); | |
07612e5f | 773 | |
f6a6d966 YL |
774 | return; |
775 | } | |
a5f6abd4 | 776 | |
5e8592dc MF |
777 | /* |
778 | * We always use SPI_WRITE mode (transfer starts with TDBR write). | |
779 | * SPI_READ mode (transfer starts with RDBR read) seems to have | |
780 | * problems with setting up the output value in TDBR prior to the | |
781 | * start of the transfer. | |
782 | */ | |
47885ce8 | 783 | bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TXMOD); |
5e8592dc | 784 | |
f6a6d966 | 785 | if (chip->pio_interrupt) { |
5e8592dc | 786 | /* SPI irq should have been disabled by now */ |
93b61bdd | 787 | |
f6a6d966 YL |
788 | /* discard old RX data and clear RXS */ |
789 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 790 | |
f6a6d966 YL |
791 | /* start transfer */ |
792 | if (drv_data->tx == NULL) | |
47885ce8 | 793 | bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val); |
f6a6d966 | 794 | else { |
4d676fc5 | 795 | int loop; |
24778be2 | 796 | if (bits_per_word == 16) { |
4d676fc5 BL |
797 | u16 *buf = (u16 *)drv_data->tx; |
798 | for (loop = 0; loop < bits_per_word / 16; | |
799 | loop++) { | |
47885ce8 | 800 | bfin_write(&drv_data->regs->tdbr, *buf++); |
4d676fc5 | 801 | } |
24778be2 | 802 | } else if (bits_per_word == 8) { |
4d676fc5 BL |
803 | u8 *buf = (u8 *)drv_data->tx; |
804 | for (loop = 0; loop < bits_per_word / 8; loop++) | |
47885ce8 | 805 | bfin_write(&drv_data->regs->tdbr, *buf++); |
4d676fc5 BL |
806 | } |
807 | ||
f6a6d966 YL |
808 | drv_data->tx += drv_data->n_bytes; |
809 | } | |
a5f6abd4 | 810 | |
f6a6d966 YL |
811 | /* once TDBR is empty, interrupt is triggered */ |
812 | enable_irq(drv_data->spi_irq); | |
813 | return; | |
814 | } | |
a5f6abd4 | 815 | |
f6a6d966 YL |
816 | /* IO mode */ |
817 | dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); | |
818 | ||
f6a6d966 YL |
819 | if (full_duplex) { |
820 | /* full duplex mode */ | |
821 | BUG_ON((drv_data->tx_end - drv_data->tx) != | |
822 | (drv_data->rx_end - drv_data->rx)); | |
823 | dev_dbg(&drv_data->pdev->dev, | |
824 | "IO duplex: cr is 0x%x\n", cr); | |
825 | ||
9c4542c7 | 826 | drv_data->ops->duplex(drv_data); |
f6a6d966 YL |
827 | |
828 | if (drv_data->tx != drv_data->tx_end) | |
829 | tranf_success = 0; | |
830 | } else if (drv_data->tx != NULL) { | |
831 | /* write only half duplex */ | |
832 | dev_dbg(&drv_data->pdev->dev, | |
833 | "IO write: cr is 0x%x\n", cr); | |
834 | ||
9c4542c7 | 835 | drv_data->ops->write(drv_data); |
f6a6d966 YL |
836 | |
837 | if (drv_data->tx != drv_data->tx_end) | |
838 | tranf_success = 0; | |
839 | } else if (drv_data->rx != NULL) { | |
840 | /* read only half duplex */ | |
841 | dev_dbg(&drv_data->pdev->dev, | |
842 | "IO read: cr is 0x%x\n", cr); | |
843 | ||
9c4542c7 | 844 | drv_data->ops->read(drv_data); |
f6a6d966 YL |
845 | if (drv_data->rx != drv_data->rx_end) |
846 | tranf_success = 0; | |
847 | } | |
a5f6abd4 | 848 | |
f6a6d966 YL |
849 | if (!tranf_success) { |
850 | dev_dbg(&drv_data->pdev->dev, | |
851 | "IO write error!\n"); | |
852 | message->state = ERROR_STATE; | |
853 | } else { | |
25985edc | 854 | /* Update total byte transferred */ |
f6a6d966 YL |
855 | message->actual_length += drv_data->len_in_bytes; |
856 | /* Move to next transfer of this msg */ | |
857 | message->state = bfin_spi_next_transfer(drv_data); | |
2431a815 SJ |
858 | if (drv_data->cs_change && message->state != DONE_STATE) { |
859 | bfin_spi_flush(drv_data); | |
f6a6d966 | 860 | bfin_spi_cs_deactive(drv_data, chip); |
2431a815 | 861 | } |
a5f6abd4 | 862 | } |
f6a6d966 YL |
863 | |
864 | /* Schedule next transfer tasklet */ | |
865 | tasklet_schedule(&drv_data->pump_transfers); | |
a5f6abd4 WB |
866 | } |
867 | ||
868 | /* pop a msg from queue and kick off real transfer */ | |
138f97cd | 869 | static void bfin_spi_pump_messages(struct work_struct *work) |
a5f6abd4 | 870 | { |
9c0a788b | 871 | struct bfin_spi_master_data *drv_data; |
a5f6abd4 WB |
872 | unsigned long flags; |
873 | ||
9c0a788b | 874 | drv_data = container_of(work, struct bfin_spi_master_data, pump_messages); |
131b17d4 | 875 | |
a5f6abd4 WB |
876 | /* Lock queue and check for queue work */ |
877 | spin_lock_irqsave(&drv_data->lock, flags); | |
f4f50c3f | 878 | if (list_empty(&drv_data->queue) || !drv_data->running) { |
a5f6abd4 WB |
879 | /* pumper kicked off but no work to do */ |
880 | drv_data->busy = 0; | |
881 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
882 | return; | |
883 | } | |
884 | ||
885 | /* Make sure we are not already running a message */ | |
886 | if (drv_data->cur_msg) { | |
887 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
888 | return; | |
889 | } | |
890 | ||
891 | /* Extract head of queue */ | |
892 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
893 | struct spi_message, queue); | |
5fec5b5a BW |
894 | |
895 | /* Setup the SSP using the per chip configuration */ | |
896 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
138f97cd | 897 | bfin_spi_restore_state(drv_data); |
5fec5b5a | 898 | |
a5f6abd4 WB |
899 | list_del_init(&drv_data->cur_msg->queue); |
900 | ||
901 | /* Initial message state */ | |
902 | drv_data->cur_msg->state = START_STATE; | |
903 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
904 | struct spi_transfer, transfer_list); | |
905 | ||
f6bd03a7 JN |
906 | dev_dbg(&drv_data->pdev->dev, |
907 | "got a message to pump, state is set to: baud " | |
908 | "%d, flag 0x%x, ctl 0x%x\n", | |
5fec5b5a BW |
909 | drv_data->cur_chip->baud, drv_data->cur_chip->flag, |
910 | drv_data->cur_chip->ctl_reg); | |
131b17d4 BW |
911 | |
912 | dev_dbg(&drv_data->pdev->dev, | |
88b40369 BW |
913 | "the first transfer len is %d\n", |
914 | drv_data->cur_transfer->len); | |
a5f6abd4 WB |
915 | |
916 | /* Mark as busy and launch transfers */ | |
917 | tasklet_schedule(&drv_data->pump_transfers); | |
918 | ||
919 | drv_data->busy = 1; | |
920 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
921 | } | |
922 | ||
923 | /* | |
924 | * got a msg to transfer, queue it in drv_data->queue. | |
925 | * And kick off message pumper | |
926 | */ | |
138f97cd | 927 | static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg) |
a5f6abd4 | 928 | { |
9c0a788b | 929 | struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master); |
a5f6abd4 WB |
930 | unsigned long flags; |
931 | ||
932 | spin_lock_irqsave(&drv_data->lock, flags); | |
933 | ||
f4f50c3f | 934 | if (!drv_data->running) { |
a5f6abd4 WB |
935 | spin_unlock_irqrestore(&drv_data->lock, flags); |
936 | return -ESHUTDOWN; | |
937 | } | |
938 | ||
939 | msg->actual_length = 0; | |
940 | msg->status = -EINPROGRESS; | |
941 | msg->state = START_STATE; | |
942 | ||
88b40369 | 943 | dev_dbg(&spi->dev, "adding an msg in transfer() \n"); |
a5f6abd4 WB |
944 | list_add_tail(&msg->queue, &drv_data->queue); |
945 | ||
f4f50c3f | 946 | if (drv_data->running && !drv_data->busy) |
9b96f070 | 947 | schedule_work(&drv_data->pump_messages); |
a5f6abd4 WB |
948 | |
949 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
950 | ||
951 | return 0; | |
952 | } | |
953 | ||
12e17c42 SZ |
954 | #define MAX_SPI_SSEL 7 |
955 | ||
ddc0bf13 | 956 | static const u16 ssel[][MAX_SPI_SSEL] = { |
12e17c42 SZ |
957 | {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, |
958 | P_SPI0_SSEL4, P_SPI0_SSEL5, | |
959 | P_SPI0_SSEL6, P_SPI0_SSEL7}, | |
960 | ||
961 | {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, | |
962 | P_SPI1_SSEL4, P_SPI1_SSEL5, | |
963 | P_SPI1_SSEL6, P_SPI1_SSEL7}, | |
964 | ||
965 | {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, | |
966 | P_SPI2_SSEL4, P_SPI2_SSEL5, | |
967 | P_SPI2_SSEL6, P_SPI2_SSEL7}, | |
968 | }; | |
969 | ||
ab09e040 | 970 | /* setup for devices (may be called multiple times -- not just first setup) */ |
138f97cd | 971 | static int bfin_spi_setup(struct spi_device *spi) |
a5f6abd4 | 972 | { |
ac01e97d | 973 | struct bfin5xx_spi_chip *chip_info; |
9c0a788b MF |
974 | struct bfin_spi_slave_data *chip = NULL; |
975 | struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master); | |
5b47bcd4 | 976 | u16 bfin_ctl_reg; |
ac01e97d | 977 | int ret = -EINVAL; |
a5f6abd4 | 978 | |
a5f6abd4 | 979 | /* Only alloc (or use chip_info) on first setup */ |
ac01e97d | 980 | chip_info = NULL; |
a5f6abd4 WB |
981 | chip = spi_get_ctldata(spi); |
982 | if (chip == NULL) { | |
ac01e97d DM |
983 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
984 | if (!chip) { | |
985 | dev_err(&spi->dev, "cannot allocate chip data\n"); | |
986 | ret = -ENOMEM; | |
987 | goto error; | |
988 | } | |
a5f6abd4 WB |
989 | |
990 | chip->enable_dma = 0; | |
991 | chip_info = spi->controller_data; | |
992 | } | |
993 | ||
5b47bcd4 MF |
994 | /* Let people set non-standard bits directly */ |
995 | bfin_ctl_reg = BIT_CTL_OPENDRAIN | BIT_CTL_EMISO | | |
996 | BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ; | |
997 | ||
a5f6abd4 WB |
998 | /* chip_info isn't always needed */ |
999 | if (chip_info) { | |
2ed35516 MF |
1000 | /* Make sure people stop trying to set fields via ctl_reg |
1001 | * when they should actually be using common SPI framework. | |
90008a64 | 1002 | * Currently we let through: WOM EMISO PSSE GM SZ. |
2ed35516 MF |
1003 | * Not sure if a user actually needs/uses any of these, |
1004 | * but let's assume (for now) they do. | |
1005 | */ | |
5b47bcd4 | 1006 | if (chip_info->ctl_reg & ~bfin_ctl_reg) { |
f6bd03a7 JN |
1007 | dev_err(&spi->dev, |
1008 | "do not set bits in ctl_reg that the SPI framework manages\n"); | |
ac01e97d | 1009 | goto error; |
2ed35516 | 1010 | } |
a5f6abd4 WB |
1011 | chip->enable_dma = chip_info->enable_dma != 0 |
1012 | && drv_data->master_info->enable_dma; | |
1013 | chip->ctl_reg = chip_info->ctl_reg; | |
a5f6abd4 | 1014 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; |
93b61bdd | 1015 | chip->idle_tx_val = chip_info->idle_tx_val; |
f6a6d966 | 1016 | chip->pio_interrupt = chip_info->pio_interrupt; |
5b47bcd4 MF |
1017 | } else { |
1018 | /* force a default base state */ | |
1019 | chip->ctl_reg &= bfin_ctl_reg; | |
033f44bd MF |
1020 | } |
1021 | ||
a5f6abd4 WB |
1022 | /* translate common spi framework into our register */ |
1023 | if (spi->mode & SPI_CPOL) | |
90008a64 | 1024 | chip->ctl_reg |= BIT_CTL_CPOL; |
a5f6abd4 | 1025 | if (spi->mode & SPI_CPHA) |
90008a64 | 1026 | chip->ctl_reg |= BIT_CTL_CPHA; |
a5f6abd4 | 1027 | if (spi->mode & SPI_LSB_FIRST) |
90008a64 | 1028 | chip->ctl_reg |= BIT_CTL_LSBF; |
a5f6abd4 | 1029 | /* we dont support running in slave mode (yet?) */ |
90008a64 | 1030 | chip->ctl_reg |= BIT_CTL_MASTER; |
a5f6abd4 | 1031 | |
a5f6abd4 WB |
1032 | /* |
1033 | * Notice: for blackfin, the speed_hz is the value of register | |
1034 | * SPI_BAUD, not the real baudrate | |
1035 | */ | |
1036 | chip->baud = hz_to_spi_baud(spi->max_speed_hz); | |
a5f6abd4 | 1037 | chip->chip_select_num = spi->chip_select; |
4190f6a5 BS |
1038 | if (chip->chip_select_num < MAX_CTRL_CS) { |
1039 | if (!(spi->mode & SPI_CPHA)) | |
f6bd03a7 JN |
1040 | dev_warn(&spi->dev, |
1041 | "Warning: SPI CPHA not set: Slave Select not under software control!\n" | |
1042 | "See Documentation/blackfin/bfin-spi-notes.txt\n"); | |
4190f6a5 | 1043 | |
d3cc71f7 | 1044 | chip->flag = (1 << spi->chip_select) << 8; |
4190f6a5 | 1045 | } else |
d3cc71f7 | 1046 | chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS; |
a5f6abd4 | 1047 | |
f6a6d966 | 1048 | if (chip->enable_dma && chip->pio_interrupt) { |
f6bd03a7 JN |
1049 | dev_err(&spi->dev, |
1050 | "enable_dma is set, do not set pio_interrupt\n"); | |
f6a6d966 YL |
1051 | goto error; |
1052 | } | |
ac01e97d DM |
1053 | /* |
1054 | * if any one SPI chip is registered and wants DMA, request the | |
1055 | * DMA channel for it | |
1056 | */ | |
1057 | if (chip->enable_dma && !drv_data->dma_requested) { | |
1058 | /* register dma irq handler */ | |
1059 | ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA"); | |
1060 | if (ret) { | |
1061 | dev_err(&spi->dev, | |
1062 | "Unable to request BlackFin SPI DMA channel\n"); | |
1063 | goto error; | |
1064 | } | |
1065 | drv_data->dma_requested = 1; | |
1066 | ||
1067 | ret = set_dma_callback(drv_data->dma_channel, | |
1068 | bfin_spi_dma_irq_handler, drv_data); | |
1069 | if (ret) { | |
1070 | dev_err(&spi->dev, "Unable to set dma callback\n"); | |
1071 | goto error; | |
1072 | } | |
1073 | dma_disable_irq(drv_data->dma_channel); | |
1074 | } | |
1075 | ||
f6a6d966 YL |
1076 | if (chip->pio_interrupt && !drv_data->irq_requested) { |
1077 | ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler, | |
38ada214 | 1078 | 0, "BFIN_SPI", drv_data); |
f6a6d966 YL |
1079 | if (ret) { |
1080 | dev_err(&spi->dev, "Unable to register spi IRQ\n"); | |
1081 | goto error; | |
1082 | } | |
1083 | drv_data->irq_requested = 1; | |
1084 | /* we use write mode, spi irq has to be disabled here */ | |
1085 | disable_irq(drv_data->spi_irq); | |
1086 | } | |
1087 | ||
d3cc71f7 | 1088 | if (chip->chip_select_num >= MAX_CTRL_CS) { |
73e1ac16 MH |
1089 | /* Only request on first setup */ |
1090 | if (spi_get_ctldata(spi) == NULL) { | |
1091 | ret = gpio_request(chip->cs_gpio, spi->modalias); | |
1092 | if (ret) { | |
1093 | dev_err(&spi->dev, "gpio_request() error\n"); | |
1094 | goto pin_error; | |
1095 | } | |
1096 | gpio_direction_output(chip->cs_gpio, 1); | |
ac01e97d | 1097 | } |
a5f6abd4 WB |
1098 | } |
1099 | ||
898eb71c | 1100 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", |
033f44bd | 1101 | spi->modalias, spi->bits_per_word, chip->enable_dma); |
88b40369 | 1102 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
a5f6abd4 WB |
1103 | chip->ctl_reg, chip->flag); |
1104 | ||
1105 | spi_set_ctldata(spi, chip); | |
1106 | ||
12e17c42 | 1107 | dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num); |
d3cc71f7 | 1108 | if (chip->chip_select_num < MAX_CTRL_CS) { |
ac01e97d DM |
1109 | ret = peripheral_request(ssel[spi->master->bus_num] |
1110 | [chip->chip_select_num-1], spi->modalias); | |
1111 | if (ret) { | |
1112 | dev_err(&spi->dev, "peripheral_request() error\n"); | |
1113 | goto pin_error; | |
1114 | } | |
1115 | } | |
12e17c42 | 1116 | |
8221610e | 1117 | bfin_spi_cs_enable(drv_data, chip); |
138f97cd | 1118 | bfin_spi_cs_deactive(drv_data, chip); |
07612e5f | 1119 | |
a5f6abd4 | 1120 | return 0; |
ac01e97d DM |
1121 | |
1122 | pin_error: | |
d3cc71f7 | 1123 | if (chip->chip_select_num >= MAX_CTRL_CS) |
ac01e97d DM |
1124 | gpio_free(chip->cs_gpio); |
1125 | else | |
1126 | peripheral_free(ssel[spi->master->bus_num] | |
1127 | [chip->chip_select_num - 1]); | |
1128 | error: | |
1129 | if (chip) { | |
1130 | if (drv_data->dma_requested) | |
1131 | free_dma(drv_data->dma_channel); | |
1132 | drv_data->dma_requested = 0; | |
1133 | ||
1134 | kfree(chip); | |
1135 | /* prevent free 'chip' twice */ | |
1136 | spi_set_ctldata(spi, NULL); | |
1137 | } | |
1138 | ||
1139 | return ret; | |
a5f6abd4 WB |
1140 | } |
1141 | ||
1142 | /* | |
1143 | * callback for spi framework. | |
1144 | * clean driver specific data | |
1145 | */ | |
138f97cd | 1146 | static void bfin_spi_cleanup(struct spi_device *spi) |
a5f6abd4 | 1147 | { |
9c0a788b MF |
1148 | struct bfin_spi_slave_data *chip = spi_get_ctldata(spi); |
1149 | struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master); | |
a5f6abd4 | 1150 | |
e7d02e3c MF |
1151 | if (!chip) |
1152 | return; | |
1153 | ||
d3cc71f7 | 1154 | if (chip->chip_select_num < MAX_CTRL_CS) { |
12e17c42 SZ |
1155 | peripheral_free(ssel[spi->master->bus_num] |
1156 | [chip->chip_select_num-1]); | |
8221610e | 1157 | bfin_spi_cs_disable(drv_data, chip); |
d3cc71f7 | 1158 | } else |
42c78b2b MH |
1159 | gpio_free(chip->cs_gpio); |
1160 | ||
a5f6abd4 | 1161 | kfree(chip); |
ac01e97d DM |
1162 | /* prevent free 'chip' twice */ |
1163 | spi_set_ctldata(spi, NULL); | |
a5f6abd4 WB |
1164 | } |
1165 | ||
c52d4e5f | 1166 | static int bfin_spi_init_queue(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
1167 | { |
1168 | INIT_LIST_HEAD(&drv_data->queue); | |
1169 | spin_lock_init(&drv_data->lock); | |
1170 | ||
f4f50c3f | 1171 | drv_data->running = false; |
a5f6abd4 WB |
1172 | drv_data->busy = 0; |
1173 | ||
1174 | /* init transfer tasklet */ | |
1175 | tasklet_init(&drv_data->pump_transfers, | |
138f97cd | 1176 | bfin_spi_pump_transfers, (unsigned long)drv_data); |
a5f6abd4 | 1177 | |
138f97cd | 1178 | INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages); |
a5f6abd4 WB |
1179 | |
1180 | return 0; | |
1181 | } | |
1182 | ||
c52d4e5f | 1183 | static int bfin_spi_start_queue(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
1184 | { |
1185 | unsigned long flags; | |
1186 | ||
1187 | spin_lock_irqsave(&drv_data->lock, flags); | |
1188 | ||
f4f50c3f | 1189 | if (drv_data->running || drv_data->busy) { |
a5f6abd4 WB |
1190 | spin_unlock_irqrestore(&drv_data->lock, flags); |
1191 | return -EBUSY; | |
1192 | } | |
1193 | ||
f4f50c3f | 1194 | drv_data->running = true; |
a5f6abd4 WB |
1195 | drv_data->cur_msg = NULL; |
1196 | drv_data->cur_transfer = NULL; | |
1197 | drv_data->cur_chip = NULL; | |
1198 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1199 | ||
9b96f070 | 1200 | schedule_work(&drv_data->pump_messages); |
a5f6abd4 WB |
1201 | |
1202 | return 0; | |
1203 | } | |
1204 | ||
c52d4e5f | 1205 | static int bfin_spi_stop_queue(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
1206 | { |
1207 | unsigned long flags; | |
1208 | unsigned limit = 500; | |
1209 | int status = 0; | |
1210 | ||
1211 | spin_lock_irqsave(&drv_data->lock, flags); | |
1212 | ||
1213 | /* | |
1214 | * This is a bit lame, but is optimized for the common execution path. | |
1215 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1216 | * execution path (pump_messages) would be required to call wake_up or | |
1217 | * friends on every SPI message. Do this instead | |
1218 | */ | |
f4f50c3f | 1219 | drv_data->running = false; |
850a28ec | 1220 | while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) { |
a5f6abd4 WB |
1221 | spin_unlock_irqrestore(&drv_data->lock, flags); |
1222 | msleep(10); | |
1223 | spin_lock_irqsave(&drv_data->lock, flags); | |
1224 | } | |
1225 | ||
1226 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1227 | status = -EBUSY; | |
1228 | ||
1229 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1230 | ||
1231 | return status; | |
1232 | } | |
1233 | ||
c52d4e5f | 1234 | static int bfin_spi_destroy_queue(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
1235 | { |
1236 | int status; | |
1237 | ||
138f97cd | 1238 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1239 | if (status != 0) |
1240 | return status; | |
1241 | ||
9b96f070 | 1242 | flush_work(&drv_data->pump_messages); |
a5f6abd4 WB |
1243 | |
1244 | return 0; | |
1245 | } | |
1246 | ||
2deff8d6 | 1247 | static int bfin_spi_probe(struct platform_device *pdev) |
a5f6abd4 WB |
1248 | { |
1249 | struct device *dev = &pdev->dev; | |
1250 | struct bfin5xx_spi_master *platform_info; | |
1251 | struct spi_master *master; | |
9c0a788b | 1252 | struct bfin_spi_master_data *drv_data; |
a32c691d | 1253 | struct resource *res; |
a5f6abd4 WB |
1254 | int status = 0; |
1255 | ||
8074cf06 | 1256 | platform_info = dev_get_platdata(dev); |
a5f6abd4 WB |
1257 | |
1258 | /* Allocate master with space for drv_data */ | |
2a045131 | 1259 | master = spi_alloc_master(dev, sizeof(*drv_data)); |
a5f6abd4 WB |
1260 | if (!master) { |
1261 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
1262 | return -ENOMEM; | |
1263 | } | |
131b17d4 | 1264 | |
a5f6abd4 WB |
1265 | drv_data = spi_master_get_devdata(master); |
1266 | drv_data->master = master; | |
1267 | drv_data->master_info = platform_info; | |
1268 | drv_data->pdev = pdev; | |
003d9226 | 1269 | drv_data->pin_req = platform_info->pin_req; |
a5f6abd4 | 1270 | |
e7db06b5 DB |
1271 | /* the spi->mode bits supported by this driver: */ |
1272 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; | |
24778be2 | 1273 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); |
a5f6abd4 WB |
1274 | master->bus_num = pdev->id; |
1275 | master->num_chipselect = platform_info->num_chipselect; | |
138f97cd MF |
1276 | master->cleanup = bfin_spi_cleanup; |
1277 | master->setup = bfin_spi_setup; | |
1278 | master->transfer = bfin_spi_transfer; | |
a5f6abd4 | 1279 | |
a32c691d BW |
1280 | /* Find and map our resources */ |
1281 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1282 | if (res == NULL) { | |
1283 | dev_err(dev, "Cannot get IORESOURCE_MEM\n"); | |
1284 | status = -ENOENT; | |
1285 | goto out_error_get_res; | |
1286 | } | |
1287 | ||
47885ce8 MF |
1288 | drv_data->regs = ioremap(res->start, resource_size(res)); |
1289 | if (drv_data->regs == NULL) { | |
a32c691d BW |
1290 | dev_err(dev, "Cannot map IO\n"); |
1291 | status = -ENXIO; | |
1292 | goto out_error_ioremap; | |
1293 | } | |
1294 | ||
f6a6d966 YL |
1295 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
1296 | if (res == NULL) { | |
a32c691d BW |
1297 | dev_err(dev, "No DMA channel specified\n"); |
1298 | status = -ENOENT; | |
f6a6d966 YL |
1299 | goto out_error_free_io; |
1300 | } | |
1301 | drv_data->dma_channel = res->start; | |
1302 | ||
1303 | drv_data->spi_irq = platform_get_irq(pdev, 0); | |
1304 | if (drv_data->spi_irq < 0) { | |
1305 | dev_err(dev, "No spi pio irq specified\n"); | |
1306 | status = -ENOENT; | |
1307 | goto out_error_free_io; | |
a32c691d BW |
1308 | } |
1309 | ||
a5f6abd4 | 1310 | /* Initial and start queue */ |
138f97cd | 1311 | status = bfin_spi_init_queue(drv_data); |
a5f6abd4 | 1312 | if (status != 0) { |
a32c691d | 1313 | dev_err(dev, "problem initializing queue\n"); |
a5f6abd4 WB |
1314 | goto out_error_queue_alloc; |
1315 | } | |
a32c691d | 1316 | |
138f97cd | 1317 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 | 1318 | if (status != 0) { |
a32c691d | 1319 | dev_err(dev, "problem starting queue\n"); |
a5f6abd4 WB |
1320 | goto out_error_queue_alloc; |
1321 | } | |
1322 | ||
f9e522ca VM |
1323 | status = peripheral_request_list(drv_data->pin_req, DRV_NAME); |
1324 | if (status != 0) { | |
1325 | dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); | |
1326 | goto out_error_queue_alloc; | |
1327 | } | |
1328 | ||
bb8beecd WM |
1329 | /* Reset SPI registers. If these registers were used by the boot loader, |
1330 | * the sky may fall on your head if you enable the dma controller. | |
1331 | */ | |
47885ce8 MF |
1332 | bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER); |
1333 | bfin_write(&drv_data->regs->flg, 0xFF00); | |
bb8beecd | 1334 | |
a5f6abd4 WB |
1335 | /* Register with the SPI framework */ |
1336 | platform_set_drvdata(pdev, drv_data); | |
1337 | status = spi_register_master(master); | |
1338 | if (status != 0) { | |
a32c691d | 1339 | dev_err(dev, "problem registering spi master\n"); |
a5f6abd4 WB |
1340 | goto out_error_queue_alloc; |
1341 | } | |
a32c691d | 1342 | |
47885ce8 MF |
1343 | dev_info(dev, "%s, Version %s, regs@%p, dma channel@%d\n", |
1344 | DRV_DESC, DRV_VERSION, drv_data->regs, | |
bb90eb00 | 1345 | drv_data->dma_channel); |
a5f6abd4 WB |
1346 | return status; |
1347 | ||
cc2f81a6 | 1348 | out_error_queue_alloc: |
138f97cd | 1349 | bfin_spi_destroy_queue(drv_data); |
f6a6d966 | 1350 | out_error_free_io: |
47885ce8 | 1351 | iounmap(drv_data->regs); |
a32c691d BW |
1352 | out_error_ioremap: |
1353 | out_error_get_res: | |
a5f6abd4 | 1354 | spi_master_put(master); |
cc2f81a6 | 1355 | |
a5f6abd4 WB |
1356 | return status; |
1357 | } | |
1358 | ||
1359 | /* stop hardware and remove the driver */ | |
fd4a319b | 1360 | static int bfin_spi_remove(struct platform_device *pdev) |
a5f6abd4 | 1361 | { |
9c0a788b | 1362 | struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1363 | int status = 0; |
1364 | ||
1365 | if (!drv_data) | |
1366 | return 0; | |
1367 | ||
1368 | /* Remove the queue */ | |
138f97cd | 1369 | status = bfin_spi_destroy_queue(drv_data); |
a5f6abd4 WB |
1370 | if (status != 0) |
1371 | return status; | |
1372 | ||
1373 | /* Disable the SSP at the peripheral and SOC level */ | |
1374 | bfin_spi_disable(drv_data); | |
1375 | ||
1376 | /* Release DMA */ | |
1377 | if (drv_data->master_info->enable_dma) { | |
bb90eb00 BW |
1378 | if (dma_channel_active(drv_data->dma_channel)) |
1379 | free_dma(drv_data->dma_channel); | |
a5f6abd4 WB |
1380 | } |
1381 | ||
f6a6d966 YL |
1382 | if (drv_data->irq_requested) { |
1383 | free_irq(drv_data->spi_irq, drv_data); | |
1384 | drv_data->irq_requested = 0; | |
1385 | } | |
1386 | ||
a5f6abd4 WB |
1387 | /* Disconnect from the SPI framework */ |
1388 | spi_unregister_master(drv_data->master); | |
1389 | ||
003d9226 | 1390 | peripheral_free_list(drv_data->pin_req); |
cc2f81a6 | 1391 | |
a5f6abd4 WB |
1392 | return 0; |
1393 | } | |
1394 | ||
fbbfd68b JH |
1395 | #ifdef CONFIG_PM_SLEEP |
1396 | static int bfin_spi_suspend(struct device *dev) | |
a5f6abd4 | 1397 | { |
fbbfd68b | 1398 | struct bfin_spi_master_data *drv_data = dev_get_drvdata(dev); |
a5f6abd4 WB |
1399 | int status = 0; |
1400 | ||
138f97cd | 1401 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1402 | if (status != 0) |
1403 | return status; | |
1404 | ||
47885ce8 MF |
1405 | drv_data->ctrl_reg = bfin_read(&drv_data->regs->ctl); |
1406 | drv_data->flag_reg = bfin_read(&drv_data->regs->flg); | |
b052fd0a BS |
1407 | |
1408 | /* | |
1409 | * reset SPI_CTL and SPI_FLG registers | |
1410 | */ | |
47885ce8 MF |
1411 | bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER); |
1412 | bfin_write(&drv_data->regs->flg, 0xFF00); | |
a5f6abd4 WB |
1413 | |
1414 | return 0; | |
1415 | } | |
1416 | ||
fbbfd68b | 1417 | static int bfin_spi_resume(struct device *dev) |
a5f6abd4 | 1418 | { |
fbbfd68b | 1419 | struct bfin_spi_master_data *drv_data = dev_get_drvdata(dev); |
a5f6abd4 WB |
1420 | int status = 0; |
1421 | ||
47885ce8 MF |
1422 | bfin_write(&drv_data->regs->ctl, drv_data->ctrl_reg); |
1423 | bfin_write(&drv_data->regs->flg, drv_data->flag_reg); | |
a5f6abd4 WB |
1424 | |
1425 | /* Start the queue running */ | |
138f97cd | 1426 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 | 1427 | if (status != 0) { |
fbbfd68b | 1428 | dev_err(dev, "problem starting queue (%d)\n", status); |
a5f6abd4 WB |
1429 | return status; |
1430 | } | |
1431 | ||
1432 | return 0; | |
1433 | } | |
fbbfd68b JH |
1434 | |
1435 | static SIMPLE_DEV_PM_OPS(bfin_spi_pm_ops, bfin_spi_suspend, bfin_spi_resume); | |
1436 | ||
1437 | #define BFIN_SPI_PM_OPS (&bfin_spi_pm_ops) | |
a5f6abd4 | 1438 | #else |
fbbfd68b JH |
1439 | #define BFIN_SPI_PM_OPS NULL |
1440 | #endif | |
a5f6abd4 | 1441 | |
7e38c3c4 | 1442 | MODULE_ALIAS("platform:bfin-spi"); |
138f97cd | 1443 | static struct platform_driver bfin_spi_driver = { |
fc3ba952 | 1444 | .driver = { |
a32c691d | 1445 | .name = DRV_NAME, |
fbbfd68b | 1446 | .pm = BFIN_SPI_PM_OPS, |
88b40369 | 1447 | }, |
db9371b8 | 1448 | .probe = bfin_spi_probe, |
fd4a319b | 1449 | .remove = bfin_spi_remove, |
a5f6abd4 WB |
1450 | }; |
1451 | ||
138f97cd | 1452 | static int __init bfin_spi_init(void) |
a5f6abd4 | 1453 | { |
db9371b8 | 1454 | return platform_driver_register(&bfin_spi_driver); |
a5f6abd4 | 1455 | } |
6f7c17f4 | 1456 | subsys_initcall(bfin_spi_init); |
a5f6abd4 | 1457 | |
138f97cd | 1458 | static void __exit bfin_spi_exit(void) |
a5f6abd4 | 1459 | { |
138f97cd | 1460 | platform_driver_unregister(&bfin_spi_driver); |
a5f6abd4 | 1461 | } |
138f97cd | 1462 | module_exit(bfin_spi_exit); |