[mirror_ubuntu-artful-kernel.git] / drivers / spi / spi-bitbang.c

/*
 * polling/bitbanging SPI master controller driver utilities
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>


/*----------------------------------------------------------------------*/

/*
 * FIRST PART (OPTIONAL):  word-at-a-time spi_transfer support.
 * Use this for GPIO or shift-register level hardware APIs.
 *
 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
 * to glue code.  These bitbang setup() and cleanup() routines are always
 * used, though maybe they're called from controller-aware code.
 *
 * chipselect() and friends may use spi_device->controller_data and
 * controller registers as appropriate.
 *
 *
 * NOTE:  SPI controller pins can often be used as GPIO pins instead,
 * which means you could use a bitbang driver either to get hardware
 * working quickly, or testing for differences that aren't speed related.
 */

struct spi_bitbang_cs {
	unsigned	nsecs;	/* (clock cycle time)/2 */
	u32		(*txrx_word)(struct spi_device *spi, unsigned nsecs,
					u32 word, u8 bits);
	unsigned	(*txrx_bufs)(struct spi_device *,
					u32 (*txrx_word)(
						struct spi_device *spi,
						unsigned nsecs,
						u32 word, u8 bits),
					unsigned, struct spi_transfer *);
};

static unsigned bitbang_txrx_8(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits),
	unsigned		ns,
	struct spi_transfer	*t
) {
	unsigned		bits = t->bits_per_word;
	unsigned		count = t->len;
	const u8		*tx = t->tx_buf;
	u8			*rx = t->rx_buf;

	while (likely(count > 0)) {
		u8		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits);
		if (rx)
			*rx++ = word;
		count -= 1;
	}
	return t->len - count;
}

static unsigned bitbang_txrx_16(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits),
	unsigned		ns,
	struct spi_transfer	*t
) {
	unsigned		bits = t->bits_per_word;
	unsigned		count = t->len;
	const u16		*tx = t->tx_buf;
	u16			*rx = t->rx_buf;

	while (likely(count > 1)) {
		u16		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits);
		if (rx)
			*rx++ = word;
		count -= 2;
	}
	return t->len - count;
}

static unsigned bitbang_txrx_32(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits),
	unsigned		ns,
	struct spi_transfer	*t
) {
	unsigned		bits = t->bits_per_word;
	unsigned		count = t->len;
	const u32		*tx = t->tx_buf;
	u32			*rx = t->rx_buf;

	while (likely(count > 3)) {
		u32		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits);
		if (rx)
			*rx++ = word;
		count -= 4;
	}
	return t->len - count;
}

int spi_bitbang_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	u8			bits_per_word;
	u32			hz;

	if (t) {
		bits_per_word = t->bits_per_word;
		hz = t->speed_hz;
	} else {
		bits_per_word = 0;
		hz = 0;
	}

	/* spi_transfer level calls that work per-word */
	if (!bits_per_word)
		bits_per_word = spi->bits_per_word;
	if (bits_per_word <= 8)
		cs->txrx_bufs = bitbang_txrx_8;
	else if (bits_per_word <= 16)
		cs->txrx_bufs = bitbang_txrx_16;
	else if (bits_per_word <= 32)
		cs->txrx_bufs = bitbang_txrx_32;
	else
		return -EINVAL;

	/* nsecs = (clock period)/2 */
	if (!hz)
		hz = spi->max_speed_hz;
	if (hz) {
		cs->nsecs = (1000000000/2) / hz;
		if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
			return -EINVAL;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);

/**
 * spi_bitbang_setup - default setup for per-word I/O loops
 */
int spi_bitbang_setup(struct spi_device *spi)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	struct spi_bitbang	*bitbang;
	unsigned long		flags;

	bitbang = spi_master_get_devdata(spi->master);

	if (!cs) {
		cs = kzalloc(sizeof(*cs), GFP_KERNEL);
		if (!cs)
			return -ENOMEM;
		spi->controller_state = cs;
	}

	/* per-word shift register access, in hardware or bitbanging */
	cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)];
	if (!cs->txrx_word)
		return -EINVAL;

	if (bitbang->setup_transfer) {
		int retval = bitbang->setup_transfer(spi, NULL);
		if (retval < 0)
			return retval;
	}

	dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs);

	/* NOTE we _need_ to call chipselect() early, ideally with adapter
	 * setup, unless the hardware defaults cooperate to avoid confusion
	 * between normal (active low) and inverted chipselects.
	 */

	/* deselect chip (low or high) */
	spin_lock_irqsave(&bitbang->lock, flags);
	if (!bitbang->busy) {
		bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
		ndelay(cs->nsecs);
	}
	spin_unlock_irqrestore(&bitbang->lock, flags);

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_setup);

/**
 * spi_bitbang_cleanup - default cleanup for per-word I/O loops
 */
void spi_bitbang_cleanup(struct spi_device *spi)
{
	kfree(spi->controller_state);
}
EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);

static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	unsigned		nsecs = cs->nsecs;

	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
}

/*----------------------------------------------------------------------*/

/*
 * SECOND PART ... simple transfer queue runner.
 *
 * This costs a task context per controller, running the queue by
 * performing each transfer in sequence.  Smarter hardware can queue
 * several DMA transfers at once, and process several controller queues
 * in parallel; this driver doesn't match such hardware very well.
 *
 * Drivers can provide word-at-a-time i/o primitives, or provide
 * transfer-at-a-time ones to leverage dma or fifo hardware.
 */

static int spi_bitbang_prepare_hardware(struct spi_master *spi)
{
	struct spi_bitbang	*bitbang;
	unsigned long		flags;

	bitbang = spi_master_get_devdata(spi);

	spin_lock_irqsave(&bitbang->lock, flags);
	bitbang->busy = 1;
	spin_unlock_irqrestore(&bitbang->lock, flags);

	return 0;
}

static int spi_bitbang_transfer_one(struct spi_master *master,
				    struct spi_message *m)
{
	struct spi_bitbang	*bitbang;
	unsigned		nsecs;
	struct spi_transfer	*t = NULL;
	unsigned		cs_change;
	int			status;
	int			do_setup = -1;
	struct spi_device	*spi = m->spi;

	bitbang = spi_master_get_devdata(master);

	/* FIXME this is made-up ... the correct value is known to
	 * word-at-a-time bitbang code, and presumably chipselect()
	 * should enforce these requirements too?
	 */
	nsecs = 100;

	cs_change = 1;
	status = 0;

	list_for_each_entry(t, &m->transfers, transfer_list) {

		/* override speed or wordsize? */
		if (t->speed_hz || t->bits_per_word)
			do_setup = 1;

		/* init (-1) or override (1) transfer params */
		if (do_setup != 0) {
			if (bitbang->setup_transfer) {
				status = bitbang->setup_transfer(spi, t);
				if (status < 0)
					break;
			}
			if (do_setup == -1)
				do_setup = 0;
		}

		/* set up default clock polarity, and activate chip;
		 * this implicitly updates clock and spi modes as
		 * previously recorded for this device via setup().
		 * (and also deselects any other chip that might be
		 * selected ...)
		 */
		if (cs_change) {
			bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
			ndelay(nsecs);
		}
		cs_change = t->cs_change;
		if (!t->tx_buf && !t->rx_buf && t->len) {
			status = -EINVAL;
			break;
		}

		/* transfer data.  the lower level code handles any
		 * new dma mappings it needs. our caller always gave
		 * us dma-safe buffers.
		 */
		if (t->len) {
			/* REVISIT dma API still needs a designated
			 * DMA_ADDR_INVALID; ~0 might be better.
			 */
			if (!m->is_dma_mapped)
				t->rx_dma = t->tx_dma = 0;
			status = bitbang->txrx_bufs(spi, t);
		}
		if (status > 0)
			m->actual_length += status;
		if (status != t->len) {
			/* always report some kind of error */
			if (status >= 0)
				status = -EREMOTEIO;
			break;
		}
		status = 0;

		/* protocol tweaks before next transfer */
		if (t->delay_usecs)
			udelay(t->delay_usecs);

		if (cs_change &&
		    !list_is_last(&t->transfer_list, &m->transfers)) {
			/* sometimes a short mid-message deselect of the chip
			 * may be needed to terminate a mode or command
			 */
			ndelay(nsecs);
			bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
			ndelay(nsecs);
		}
	}

	m->status = status;

	/* normally deactivate chipselect ... unless no error and
	 * cs_change has hinted that the next message will probably
	 * be for this chip too.
	 */
	if (!(status == 0 && cs_change)) {
		ndelay(nsecs);
		bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
		ndelay(nsecs);
	}

	spi_finalize_current_message(master);

	return status;
}

static int spi_bitbang_unprepare_hardware(struct spi_master *spi)
{
	struct spi_bitbang	*bitbang;
	unsigned long		flags;

	bitbang = spi_master_get_devdata(spi);

	spin_lock_irqsave(&bitbang->lock, flags);
	bitbang->busy = 0;
	spin_unlock_irqrestore(&bitbang->lock, flags);

	return 0;
}

/*----------------------------------------------------------------------*/

/**
 * spi_bitbang_start - start up a polled/bitbanging SPI master driver
 * @bitbang: driver handle
 *
 * Caller should have zero-initialized all parts of the structure, and then
 * provided callbacks for chip selection and I/O loops.  If the master has
 * a transfer method, its final step should call spi_bitbang_transfer; or,
 * that's the default if the transfer routine is not initialized.  It should
 * also set up the bus number and number of chipselects.
 *
 * For i/o loops, provide callbacks either per-word (for bitbanging, or for
 * hardware that basically exposes a shift register) or per-spi_transfer
 * (which takes better advantage of hardware like fifos or DMA engines).
 *
 * Drivers using per-word I/O loops should use (or call) spi_bitbang_setup,
 * spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi
 * master methods.  Those methods are the defaults if the bitbang->txrx_bufs
 * routine isn't initialized.
 *
 * This routine registers the spi_master, which will process requests in a
 * dedicated task, keeping IRQs unblocked most of the time.  To stop
 * processing those requests, call spi_bitbang_stop().
 *
 * On success, this routine will take a reference to master. The caller is
 * responsible for calling spi_bitbang_stop() to decrement the reference and
 * spi_master_put() as counterpart of spi_alloc_master() to prevent a memory
 * leak.
 */
int spi_bitbang_start(struct spi_bitbang *bitbang)
{
	struct spi_master *master = bitbang->master;
	int ret;

	if (!master || !bitbang->chipselect)
		return -EINVAL;

	spin_lock_init(&bitbang->lock);

	if (!master->mode_bits)
		master->mode_bits = SPI_CPOL | SPI_CPHA | bitbang->flags;

	if (master->transfer || master->transfer_one_message)
		return -EINVAL;

	master->prepare_transfer_hardware = spi_bitbang_prepare_hardware;
	master->unprepare_transfer_hardware = spi_bitbang_unprepare_hardware;
	master->transfer_one_message = spi_bitbang_transfer_one;

	if (!bitbang->txrx_bufs) {
		bitbang->use_dma = 0;
		bitbang->txrx_bufs = spi_bitbang_bufs;
		if (!master->setup) {
			if (!bitbang->setup_transfer)
				bitbang->setup_transfer =
					 spi_bitbang_setup_transfer;
			master->setup = spi_bitbang_setup;
			master->cleanup = spi_bitbang_cleanup;
		}
	}

	/* driver may get busy before register() returns, especially
	 * if someone registered boardinfo for devices
	 */
	ret = spi_register_master(spi_master_get(master));
	if (ret)
		spi_master_put(master);

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_start);

/**
 * spi_bitbang_stop - stops the task providing spi communication
 */
void spi_bitbang_stop(struct spi_bitbang *bitbang)
{
	spi_unregister_master(bitbang->master);
}
EXPORT_SYMBOL_GPL(spi_bitbang_stop);

MODULE_LICENSE("GPL");
Commit	Line	Data
9904f22a	1	/*
ca632f55	2	* polling/bitbanging SPI master controller driver utilities
9904f22a DB	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
9904f22a DB	13	*/
9904f22a DB	14
9904f22a DB	15	#include <linux/spinlock.h>
	16	#include <linux/workqueue.h>
	17	#include <linux/interrupt.h>
d7614de4	18	#include <linux/module.h>
9904f22a DB	19	#include <linux/delay.h>
	20	#include <linux/errno.h>
	21	#include <linux/platform_device.h>
5a0e3ad6	22	#include <linux/slab.h>
9904f22a DB	23
	24	#include <linux/spi/spi.h>
	25	#include <linux/spi/spi_bitbang.h>
	26
	27
	28	/----------------------------------------------------------------------/
	29
	30	/*
	31	* FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
	32	* Use this for GPIO or shift-register level hardware APIs.
	33	*
	34	* spi_bitbang_cs is in spi_device->controller_state, which is unavailable
	35	* to glue code. These bitbang setup() and cleanup() routines are always
	36	* used, though maybe they're called from controller-aware code.
	37	*
03ddcbc5	38	* chipselect() and friends may use spi_device->controller_data and
9904f22a DB	39	* controller registers as appropriate.
	40	*
	41	*
	42	* NOTE: SPI controller pins can often be used as GPIO pins instead,
	43	* which means you could use a bitbang driver either to get hardware
	44	* working quickly, or testing for differences that aren't speed related.
	45	*/
	46
	47	struct spi_bitbang_cs {
	48	unsigned nsecs; /* (clock cycle time)/2 */
	49	u32 (txrx_word)(struct spi_device spi, unsigned nsecs,
	50	u32 word, u8 bits);
	51	unsigned (txrx_bufs)(struct spi_device ,
	52	u32 (*txrx_word)(
	53	struct spi_device *spi,
	54	unsigned nsecs,
	55	u32 word, u8 bits),
	56	unsigned, struct spi_transfer *);
	57	};
	58
	59	static unsigned bitbang_txrx_8(
	60	struct spi_device *spi,
	61	u32 (txrx_word)(struct spi_device spi,
	62	unsigned nsecs,
	63	u32 word, u8 bits),
	64	unsigned ns,
	65	struct spi_transfer *t
	66	) {
766ed704	67	unsigned bits = t->bits_per_word;
9904f22a DB	68	unsigned count = t->len;
	69	const u8 *tx = t->tx_buf;
	70	u8 *rx = t->rx_buf;
	71
	72	while (likely(count > 0)) {
	73	u8 word = 0;
	74
	75	if (tx)
	76	word = *tx++;
	77	word = txrx_word(spi, ns, word, bits);
	78	if (rx)
	79	*rx++ = word;
	80	count -= 1;
	81	}
	82	return t->len - count;
	83	}
	84
	85	static unsigned bitbang_txrx_16(
	86	struct spi_device *spi,
	87	u32 (txrx_word)(struct spi_device spi,
	88	unsigned nsecs,
	89	u32 word, u8 bits),
	90	unsigned ns,
	91	struct spi_transfer *t
	92	) {
766ed704	93	unsigned bits = t->bits_per_word;
9904f22a DB	94	unsigned count = t->len;
	95	const u16 *tx = t->tx_buf;
	96	u16 *rx = t->rx_buf;
	97
	98	while (likely(count > 1)) {
	99	u16 word = 0;
	100
	101	if (tx)
	102	word = *tx++;
	103	word = txrx_word(spi, ns, word, bits);
	104	if (rx)
	105	*rx++ = word;
	106	count -= 2;
	107	}
	108	return t->len - count;
	109	}
	110
	111	static unsigned bitbang_txrx_32(
	112	struct spi_device *spi,
	113	u32 (txrx_word)(struct spi_device spi,
	114	unsigned nsecs,
	115	u32 word, u8 bits),
	116	unsigned ns,
	117	struct spi_transfer *t
	118	) {
766ed704	119	unsigned bits = t->bits_per_word;
9904f22a DB	120	unsigned count = t->len;
	121	const u32 *tx = t->tx_buf;
	122	u32 *rx = t->rx_buf;
	123
	124	while (likely(count > 3)) {
	125	u32 word = 0;
	126
	127	if (tx)
	128	word = *tx++;
	129	word = txrx_word(spi, ns, word, bits);
	130	if (rx)
	131	*rx++ = word;
	132	count -= 4;
	133	}
	134	return t->len - count;
	135	}
	136
ff9f4771	137	int spi_bitbang_setup_transfer(struct spi_device spi, struct spi_transfer t)
4cff33f9 ID	138	{
	139	struct spi_bitbang_cs *cs = spi->controller_state;
	140	u8 bits_per_word;
	141	u32 hz;
	142
	143	if (t) {
	144	bits_per_word = t->bits_per_word;
	145	hz = t->speed_hz;
	146	} else {
	147	bits_per_word = 0;
	148	hz = 0;
	149	}
	150
	151	/* spi_transfer level calls that work per-word */
	152	if (!bits_per_word)
	153	bits_per_word = spi->bits_per_word;
	154	if (bits_per_word <= 8)
	155	cs->txrx_bufs = bitbang_txrx_8;
	156	else if (bits_per_word <= 16)
	157	cs->txrx_bufs = bitbang_txrx_16;
	158	else if (bits_per_word <= 32)
	159	cs->txrx_bufs = bitbang_txrx_32;
	160	else
	161	return -EINVAL;
	162
	163	/* nsecs = (clock period)/2 */
	164	if (!hz)
	165	hz = spi->max_speed_hz;
1e316d75 DB	166	if (hz) {
	167	cs->nsecs = (1000000000/2) / hz;
	168	if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
	169	return -EINVAL;
	170	}
4cff33f9 ID	171
	172	return 0;
	173	}
ff9f4771	174	EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);
4cff33f9	175
9904f22a DB	176	/**
	177	* spi_bitbang_setup - default setup for per-word I/O loops
	178	*/
	179	int spi_bitbang_setup(struct spi_device *spi)
	180	{
	181	struct spi_bitbang_cs *cs = spi->controller_state;
	182	struct spi_bitbang *bitbang;
d52df2e2	183	unsigned long flags;
9904f22a	184
ccf77cc4 DB	185	bitbang = spi_master_get_devdata(spi->master);
ccf77cc4 DB	186
9904f22a	187	if (!cs) {
cff93c58	188	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
9904f22a DB	189	if (!cs)
	190	return -ENOMEM;
	191	spi->controller_state = cs;
	192	}
9904f22a	193
9904f22a DB	194	/* per-word shift register access, in hardware or bitbanging */
	195	cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL\|SPI_CPHA)];
	196	if (!cs->txrx_word)
	197	return -EINVAL;
	198
7d0ec8b6 PN	199	if (bitbang->setup_transfer) {
	200	int retval = bitbang->setup_transfer(spi, NULL);
	201	if (retval < 0)
	202	return retval;
	203	}
9904f22a	204
7d077197	205	dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs);
9904f22a DB	206
	207	/* NOTE we _need_ to call chipselect() early, ideally with adapter
	208	* setup, unless the hardware defaults cooperate to avoid confusion
	209	* between normal (active low) and inverted chipselects.
	210	*/
	211
	212	/* deselect chip (low or high) */
d52df2e2	213	spin_lock_irqsave(&bitbang->lock, flags);
9904f22a	214	if (!bitbang->busy) {
8275c642	215	bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
9904f22a DB	216	ndelay(cs->nsecs);
9904f22a DB	217	}
d52df2e2	218	spin_unlock_irqrestore(&bitbang->lock, flags);
9904f22a DB	219
	220	return 0;
	221	}
	222	EXPORT_SYMBOL_GPL(spi_bitbang_setup);
	223
	224	/**
	225	* spi_bitbang_cleanup - default cleanup for per-word I/O loops
	226	*/
0ffa0285	227	void spi_bitbang_cleanup(struct spi_device *spi)
9904f22a DB	228	{
	229	kfree(spi->controller_state);
	230	}
	231	EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
	232
	233	static int spi_bitbang_bufs(struct spi_device spi, struct spi_transfer t)
	234	{
	235	struct spi_bitbang_cs *cs = spi->controller_state;
	236	unsigned nsecs = cs->nsecs;
	237
	238	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
	239	}
	240
	241	/----------------------------------------------------------------------/
	242
	243	/*
	244	* SECOND PART ... simple transfer queue runner.
	245	*
	246	* This costs a task context per controller, running the queue by
	247	* performing each transfer in sequence. Smarter hardware can queue
	248	* several DMA transfers at once, and process several controller queues
	249	* in parallel; this driver doesn't match such hardware very well.
	250	*
	251	* Drivers can provide word-at-a-time i/o primitives, or provide
	252	* transfer-at-a-time ones to leverage dma or fifo hardware.
	253	*/
2025172e MB	254
	255	static int spi_bitbang_prepare_hardware(struct spi_master *spi)
	256	{
cff93c58	257	struct spi_bitbang *bitbang;
2025172e MB	258	unsigned long flags;
	259
	260	bitbang = spi_master_get_devdata(spi);
	261
	262	spin_lock_irqsave(&bitbang->lock, flags);
	263	bitbang->busy = 1;
	264	spin_unlock_irqrestore(&bitbang->lock, flags);
	265
	266	return 0;
	267	}
	268
d60990d5	269	static int spi_bitbang_transfer_one(struct spi_master *master,
91b30858	270	struct spi_message *m)
9904f22a	271	{
cff93c58	272	struct spi_bitbang *bitbang;
91b30858 MB	273	unsigned nsecs;
91b30858 MB	274	struct spi_transfer *t = NULL;
91b30858 MB	275	unsigned cs_change;
	276	int status;
	277	int do_setup = -1;
d60990d5	278	struct spi_device *spi = m->spi;
9904f22a	279
d60990d5	280	bitbang = spi_master_get_devdata(master);
9904f22a	281
91b30858 MB	282	/* FIXME this is made-up ... the correct value is known to
	283	* word-at-a-time bitbang code, and presumably chipselect()
	284	* should enforce these requirements too?
	285	*/
	286	nsecs = 100;
9904f22a	287
91b30858 MB	288	cs_change = 1;
91b30858 MB	289	status = 0;
9904f22a	290
cff93c58	291	list_for_each_entry(t, &m->transfers, transfer_list) {
9904f22a	292
91b30858 MB	293	/* override speed or wordsize? */
	294	if (t->speed_hz \|\| t->bits_per_word)
	295	do_setup = 1;
9904f22a	296
91b30858 MB	297	/* init (-1) or override (1) transfer params */
91b30858 MB	298	if (do_setup != 0) {
7d0ec8b6 PN	299	if (bitbang->setup_transfer) {
	300	status = bitbang->setup_transfer(spi, t);
	301	if (status < 0)
	302	break;
	303	}
91b30858 MB	304	if (do_setup == -1)
91b30858 MB	305	do_setup = 0;
9904f22a DB	306	}
9904f22a DB	307
91b30858 MB	308	/* set up default clock polarity, and activate chip;
	309	* this implicitly updates clock and spi modes as
	310	* previously recorded for this device via setup().
	311	* (and also deselects any other chip that might be
	312	* selected ...)
	313	*/
	314	if (cs_change) {
	315	bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
	316	ndelay(nsecs);
	317	}
	318	cs_change = t->cs_change;
	319	if (!t->tx_buf && !t->rx_buf && t->len) {
	320	status = -EINVAL;
	321	break;
	322	}
9904f22a	323
91b30858 MB	324	/* transfer data. the lower level code handles any
	325	* new dma mappings it needs. our caller always gave
	326	* us dma-safe buffers.
8275c642	327	*/
91b30858 MB	328	if (t->len) {
	329	/* REVISIT dma API still needs a designated
	330	* DMA_ADDR_INVALID; ~0 might be better.
	331	*/
	332	if (!m->is_dma_mapped)
	333	t->rx_dma = t->tx_dma = 0;
	334	status = bitbang->txrx_bufs(spi, t);
	335	}
	336	if (status > 0)
	337	m->actual_length += status;
	338	if (status != t->len) {
	339	/* always report some kind of error */
	340	if (status >= 0)
	341	status = -EREMOTEIO;
	342	break;
	343	}
	344	status = 0;
	345
	346	/* protocol tweaks before next transfer */
	347	if (t->delay_usecs)
	348	udelay(t->delay_usecs);
	349
cff93c58 JH	350	if (cs_change &&
cff93c58 JH	351	!list_is_last(&t->transfer_list, &m->transfers)) {
91b30858 MB	352	/* sometimes a short mid-message deselect of the chip
	353	* may be needed to terminate a mode or command
	354	*/
8275c642 VW	355	ndelay(nsecs);
	356	bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
	357	ndelay(nsecs);
	358	}
91b30858 MB	359	}
	360
	361	m->status = status;
91b30858 MB	362
	363	/* normally deactivate chipselect ... unless no error and
	364	* cs_change has hinted that the next message will probably
	365	* be for this chip too.
	366	*/
	367	if (!(status == 0 && cs_change)) {
	368	ndelay(nsecs);
	369	bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
	370	ndelay(nsecs);
	371	}
	372
d60990d5	373	spi_finalize_current_message(master);
9904f22a	374
2025172e	375	return status;
9904f22a DB	376	}
9904f22a DB	377
2025172e	378	static int spi_bitbang_unprepare_hardware(struct spi_master *spi)
9904f22a	379	{
cff93c58	380	struct spi_bitbang *bitbang;
9904f22a	381	unsigned long flags;
9904f22a	382
2025172e	383	bitbang = spi_master_get_devdata(spi);
9904f22a DB	384
9904f22a DB	385	spin_lock_irqsave(&bitbang->lock, flags);
2025172e	386	bitbang->busy = 0;
9904f22a DB	387	spin_unlock_irqrestore(&bitbang->lock, flags);
9904f22a DB	388
2025172e	389	return 0;
9904f22a	390	}
9904f22a DB	391
	392	/----------------------------------------------------------------------/
	393
	394	/**
	395	* spi_bitbang_start - start up a polled/bitbanging SPI master driver
	396	* @bitbang: driver handle
	397	*
	398	* Caller should have zero-initialized all parts of the structure, and then
	399	* provided callbacks for chip selection and I/O loops. If the master has
	400	* a transfer method, its final step should call spi_bitbang_transfer; or,
	401	* that's the default if the transfer routine is not initialized. It should
	402	* also set up the bus number and number of chipselects.
	403	*
	404	* For i/o loops, provide callbacks either per-word (for bitbanging, or for
	405	* hardware that basically exposes a shift register) or per-spi_transfer
	406	* (which takes better advantage of hardware like fifos or DMA engines).
	407	*
7f8c7619 HPN	408	* Drivers using per-word I/O loops should use (or call) spi_bitbang_setup,
	409	* spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi
	410	* master methods. Those methods are the defaults if the bitbang->txrx_bufs
	411	* routine isn't initialized.
9904f22a DB	412	*
	413	* This routine registers the spi_master, which will process requests in a
	414	* dedicated task, keeping IRQs unblocked most of the time. To stop
	415	* processing those requests, call spi_bitbang_stop().
702a4879 AL	416	*
	417	* On success, this routine will take a reference to master. The caller is
	418	* responsible for calling spi_bitbang_stop() to decrement the reference and
	419	* spi_master_put() as counterpart of spi_alloc_master() to prevent a memory
	420	* leak.
9904f22a DB	421	*/
	422	int spi_bitbang_start(struct spi_bitbang *bitbang)
	423	{
7a5d8ca1	424	struct spi_master *master = bitbang->master;
702a4879	425	int ret;
9904f22a	426
7a5d8ca1	427	if (!master \|\| !bitbang->chipselect)
9904f22a DB	428	return -EINVAL;
9904f22a DB	429
9904f22a	430	spin_lock_init(&bitbang->lock);
9904f22a	431
7a5d8ca1 GL	432	if (!master->mode_bits)
7a5d8ca1 GL	433	master->mode_bits = SPI_CPOL \| SPI_CPHA \| bitbang->flags;
e7db06b5	434
2025172e MB	435	if (master->transfer \|\| master->transfer_one_message)
	436	return -EINVAL;
	437
	438	master->prepare_transfer_hardware = spi_bitbang_prepare_hardware;
	439	master->unprepare_transfer_hardware = spi_bitbang_unprepare_hardware;
	440	master->transfer_one_message = spi_bitbang_transfer_one;
	441
9904f22a DB	442	if (!bitbang->txrx_bufs) {
	443	bitbang->use_dma = 0;
	444	bitbang->txrx_bufs = spi_bitbang_bufs;
7a5d8ca1	445	if (!master->setup) {
ff9f4771 KG	446	if (!bitbang->setup_transfer)
	447	bitbang->setup_transfer =
	448	spi_bitbang_setup_transfer;
7a5d8ca1 GL	449	master->setup = spi_bitbang_setup;
7a5d8ca1 GL	450	master->cleanup = spi_bitbang_cleanup;
9904f22a	451	}
52ade736	452	}
9904f22a DB	453
	454	/* driver may get busy before register() returns, especially
	455	* if someone registered boardinfo for devices
	456	*/
702a4879 AL	457	ret = spi_register_master(spi_master_get(master));
	458	if (ret)
	459	spi_master_put(master);
	460
	461	return 0;
9904f22a DB	462	}
	463	EXPORT_SYMBOL_GPL(spi_bitbang_start);
	464
	465	/**
	466	* spi_bitbang_stop - stops the task providing spi communication
	467	*/
d9721ae1	468	void spi_bitbang_stop(struct spi_bitbang *bitbang)
9904f22a	469	{
a836f585	470	spi_unregister_master(bitbang->master);
9904f22a DB	471	}
	472	EXPORT_SYMBOL_GPL(spi_bitbang_stop);
	473
	474	MODULE_LICENSE("GPL");
	475