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spi/bitbang: Factor out message transfer from message pump loop
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CommitLineData
9904f22a 1/*
ca632f55 2 * polling/bitbanging SPI master controller driver utilities
9904f22a
DB
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
9904f22a
DB
19#include <linux/init.h>
20#include <linux/spinlock.h>
21#include <linux/workqueue.h>
22#include <linux/interrupt.h>
d7614de4 23#include <linux/module.h>
9904f22a
DB
24#include <linux/delay.h>
25#include <linux/errno.h>
26#include <linux/platform_device.h>
5a0e3ad6 27#include <linux/slab.h>
9904f22a
DB
28
29#include <linux/spi/spi.h>
30#include <linux/spi/spi_bitbang.h>
31
32
33/*----------------------------------------------------------------------*/
34
35/*
36 * FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
37 * Use this for GPIO or shift-register level hardware APIs.
38 *
39 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
40 * to glue code. These bitbang setup() and cleanup() routines are always
41 * used, though maybe they're called from controller-aware code.
42 *
43 * chipselect() and friends may use use spi_device->controller_data and
44 * controller registers as appropriate.
45 *
46 *
47 * NOTE: SPI controller pins can often be used as GPIO pins instead,
48 * which means you could use a bitbang driver either to get hardware
49 * working quickly, or testing for differences that aren't speed related.
50 */
51
52struct spi_bitbang_cs {
53 unsigned nsecs; /* (clock cycle time)/2 */
54 u32 (*txrx_word)(struct spi_device *spi, unsigned nsecs,
55 u32 word, u8 bits);
56 unsigned (*txrx_bufs)(struct spi_device *,
57 u32 (*txrx_word)(
58 struct spi_device *spi,
59 unsigned nsecs,
60 u32 word, u8 bits),
61 unsigned, struct spi_transfer *);
62};
63
64static unsigned bitbang_txrx_8(
65 struct spi_device *spi,
66 u32 (*txrx_word)(struct spi_device *spi,
67 unsigned nsecs,
68 u32 word, u8 bits),
69 unsigned ns,
70 struct spi_transfer *t
71) {
766ed704 72 unsigned bits = t->bits_per_word;
9904f22a
DB
73 unsigned count = t->len;
74 const u8 *tx = t->tx_buf;
75 u8 *rx = t->rx_buf;
76
77 while (likely(count > 0)) {
78 u8 word = 0;
79
80 if (tx)
81 word = *tx++;
82 word = txrx_word(spi, ns, word, bits);
83 if (rx)
84 *rx++ = word;
85 count -= 1;
86 }
87 return t->len - count;
88}
89
90static unsigned bitbang_txrx_16(
91 struct spi_device *spi,
92 u32 (*txrx_word)(struct spi_device *spi,
93 unsigned nsecs,
94 u32 word, u8 bits),
95 unsigned ns,
96 struct spi_transfer *t
97) {
766ed704 98 unsigned bits = t->bits_per_word;
9904f22a
DB
99 unsigned count = t->len;
100 const u16 *tx = t->tx_buf;
101 u16 *rx = t->rx_buf;
102
103 while (likely(count > 1)) {
104 u16 word = 0;
105
106 if (tx)
107 word = *tx++;
108 word = txrx_word(spi, ns, word, bits);
109 if (rx)
110 *rx++ = word;
111 count -= 2;
112 }
113 return t->len - count;
114}
115
116static unsigned bitbang_txrx_32(
117 struct spi_device *spi,
118 u32 (*txrx_word)(struct spi_device *spi,
119 unsigned nsecs,
120 u32 word, u8 bits),
121 unsigned ns,
122 struct spi_transfer *t
123) {
766ed704 124 unsigned bits = t->bits_per_word;
9904f22a
DB
125 unsigned count = t->len;
126 const u32 *tx = t->tx_buf;
127 u32 *rx = t->rx_buf;
128
129 while (likely(count > 3)) {
130 u32 word = 0;
131
132 if (tx)
133 word = *tx++;
134 word = txrx_word(spi, ns, word, bits);
135 if (rx)
136 *rx++ = word;
137 count -= 4;
138 }
139 return t->len - count;
140}
141
ff9f4771 142int spi_bitbang_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
4cff33f9
ID
143{
144 struct spi_bitbang_cs *cs = spi->controller_state;
145 u8 bits_per_word;
146 u32 hz;
147
148 if (t) {
149 bits_per_word = t->bits_per_word;
150 hz = t->speed_hz;
151 } else {
152 bits_per_word = 0;
153 hz = 0;
154 }
155
156 /* spi_transfer level calls that work per-word */
157 if (!bits_per_word)
158 bits_per_word = spi->bits_per_word;
159 if (bits_per_word <= 8)
160 cs->txrx_bufs = bitbang_txrx_8;
161 else if (bits_per_word <= 16)
162 cs->txrx_bufs = bitbang_txrx_16;
163 else if (bits_per_word <= 32)
164 cs->txrx_bufs = bitbang_txrx_32;
165 else
166 return -EINVAL;
167
168 /* nsecs = (clock period)/2 */
169 if (!hz)
170 hz = spi->max_speed_hz;
1e316d75
DB
171 if (hz) {
172 cs->nsecs = (1000000000/2) / hz;
173 if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
174 return -EINVAL;
175 }
4cff33f9
ID
176
177 return 0;
178}
ff9f4771 179EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);
4cff33f9 180
9904f22a
DB
181/**
182 * spi_bitbang_setup - default setup for per-word I/O loops
183 */
184int spi_bitbang_setup(struct spi_device *spi)
185{
186 struct spi_bitbang_cs *cs = spi->controller_state;
187 struct spi_bitbang *bitbang;
4cff33f9 188 int retval;
d52df2e2 189 unsigned long flags;
9904f22a 190
ccf77cc4
DB
191 bitbang = spi_master_get_devdata(spi->master);
192
9904f22a 193 if (!cs) {
e94b1766 194 cs = kzalloc(sizeof *cs, GFP_KERNEL);
9904f22a
DB
195 if (!cs)
196 return -ENOMEM;
197 spi->controller_state = cs;
198 }
9904f22a 199
9904f22a
DB
200 /* per-word shift register access, in hardware or bitbanging */
201 cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)];
202 if (!cs->txrx_word)
203 return -EINVAL;
204
7f8c7619 205 retval = bitbang->setup_transfer(spi, NULL);
4cff33f9
ID
206 if (retval < 0)
207 return retval;
9904f22a 208
7d077197 209 dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs);
9904f22a
DB
210
211 /* NOTE we _need_ to call chipselect() early, ideally with adapter
212 * setup, unless the hardware defaults cooperate to avoid confusion
213 * between normal (active low) and inverted chipselects.
214 */
215
216 /* deselect chip (low or high) */
d52df2e2 217 spin_lock_irqsave(&bitbang->lock, flags);
9904f22a 218 if (!bitbang->busy) {
8275c642 219 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
9904f22a
DB
220 ndelay(cs->nsecs);
221 }
d52df2e2 222 spin_unlock_irqrestore(&bitbang->lock, flags);
9904f22a
DB
223
224 return 0;
225}
226EXPORT_SYMBOL_GPL(spi_bitbang_setup);
227
228/**
229 * spi_bitbang_cleanup - default cleanup for per-word I/O loops
230 */
0ffa0285 231void spi_bitbang_cleanup(struct spi_device *spi)
9904f22a
DB
232{
233 kfree(spi->controller_state);
234}
235EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
236
237static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
238{
239 struct spi_bitbang_cs *cs = spi->controller_state;
240 unsigned nsecs = cs->nsecs;
241
242 return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
243}
244
245/*----------------------------------------------------------------------*/
246
247/*
248 * SECOND PART ... simple transfer queue runner.
249 *
250 * This costs a task context per controller, running the queue by
251 * performing each transfer in sequence. Smarter hardware can queue
252 * several DMA transfers at once, and process several controller queues
253 * in parallel; this driver doesn't match such hardware very well.
254 *
255 * Drivers can provide word-at-a-time i/o primitives, or provide
256 * transfer-at-a-time ones to leverage dma or fifo hardware.
257 */
91b30858
MB
258static int spi_bitbang_transfer_one(struct spi_device *spi,
259 struct spi_message *m)
9904f22a 260{
91b30858
MB
261 struct spi_bitbang *bitbang;
262 unsigned nsecs;
263 struct spi_transfer *t = NULL;
264 unsigned tmp;
265 unsigned cs_change;
266 int status;
267 int do_setup = -1;
9904f22a 268
91b30858 269 bitbang = spi_master_get_devdata(spi->master);
9904f22a 270
91b30858
MB
271 /* FIXME this is made-up ... the correct value is known to
272 * word-at-a-time bitbang code, and presumably chipselect()
273 * should enforce these requirements too?
274 */
275 nsecs = 100;
9904f22a 276
91b30858
MB
277 tmp = 0;
278 cs_change = 1;
279 status = 0;
9904f22a 280
91b30858 281 list_for_each_entry (t, &m->transfers, transfer_list) {
9904f22a 282
91b30858
MB
283 /* override speed or wordsize? */
284 if (t->speed_hz || t->bits_per_word)
285 do_setup = 1;
9904f22a 286
91b30858
MB
287 /* init (-1) or override (1) transfer params */
288 if (do_setup != 0) {
289 status = bitbang->setup_transfer(spi, t);
290 if (status < 0)
9904f22a 291 break;
91b30858
MB
292 if (do_setup == -1)
293 do_setup = 0;
9904f22a
DB
294 }
295
91b30858
MB
296 /* set up default clock polarity, and activate chip;
297 * this implicitly updates clock and spi modes as
298 * previously recorded for this device via setup().
299 * (and also deselects any other chip that might be
300 * selected ...)
301 */
302 if (cs_change) {
303 bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
304 ndelay(nsecs);
305 }
306 cs_change = t->cs_change;
307 if (!t->tx_buf && !t->rx_buf && t->len) {
308 status = -EINVAL;
309 break;
310 }
9904f22a 311
91b30858
MB
312 /* transfer data. the lower level code handles any
313 * new dma mappings it needs. our caller always gave
314 * us dma-safe buffers.
8275c642 315 */
91b30858
MB
316 if (t->len) {
317 /* REVISIT dma API still needs a designated
318 * DMA_ADDR_INVALID; ~0 might be better.
319 */
320 if (!m->is_dma_mapped)
321 t->rx_dma = t->tx_dma = 0;
322 status = bitbang->txrx_bufs(spi, t);
323 }
324 if (status > 0)
325 m->actual_length += status;
326 if (status != t->len) {
327 /* always report some kind of error */
328 if (status >= 0)
329 status = -EREMOTEIO;
330 break;
331 }
332 status = 0;
333
334 /* protocol tweaks before next transfer */
335 if (t->delay_usecs)
336 udelay(t->delay_usecs);
337
338 if (cs_change && !list_is_last(&t->transfer_list, &m->transfers)) {
339 /* sometimes a short mid-message deselect of the chip
340 * may be needed to terminate a mode or command
341 */
8275c642
VW
342 ndelay(nsecs);
343 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
344 ndelay(nsecs);
345 }
91b30858
MB
346 }
347
348 m->status = status;
349 m->complete(m->context);
350
351 /* normally deactivate chipselect ... unless no error and
352 * cs_change has hinted that the next message will probably
353 * be for this chip too.
354 */
355 if (!(status == 0 && cs_change)) {
356 ndelay(nsecs);
357 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
358 ndelay(nsecs);
359 }
360
361 return status;
362}
363
364static void bitbang_work(struct work_struct *work)
365{
366 struct spi_bitbang *bitbang =
367 container_of(work, struct spi_bitbang, work);
368 unsigned long flags;
369 struct spi_message *m, *_m;
370
371 spin_lock_irqsave(&bitbang->lock, flags);
372 bitbang->busy = 1;
373 list_for_each_entry_safe(m, _m, &bitbang->queue, queue) {
374 list_del(&m->queue);
375 spin_unlock_irqrestore(&bitbang->lock, flags);
376
377 spi_bitbang_transfer_one(m->spi, m);
9904f22a
DB
378
379 spin_lock_irqsave(&bitbang->lock, flags);
380 }
381 bitbang->busy = 0;
382 spin_unlock_irqrestore(&bitbang->lock, flags);
383}
384
385/**
386 * spi_bitbang_transfer - default submit to transfer queue
387 */
874b3158 388static int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m)
9904f22a
DB
389{
390 struct spi_bitbang *bitbang;
391 unsigned long flags;
1e316d75 392 int status = 0;
9904f22a
DB
393
394 m->actual_length = 0;
395 m->status = -EINPROGRESS;
396
397 bitbang = spi_master_get_devdata(spi->master);
9904f22a
DB
398
399 spin_lock_irqsave(&bitbang->lock, flags);
1e316d75
DB
400 if (!spi->max_speed_hz)
401 status = -ENETDOWN;
402 else {
403 list_add_tail(&m->queue, &bitbang->queue);
404 queue_work(bitbang->workqueue, &bitbang->work);
405 }
9904f22a
DB
406 spin_unlock_irqrestore(&bitbang->lock, flags);
407
1e316d75 408 return status;
9904f22a 409}
9904f22a
DB
410
411/*----------------------------------------------------------------------*/
412
413/**
414 * spi_bitbang_start - start up a polled/bitbanging SPI master driver
415 * @bitbang: driver handle
416 *
417 * Caller should have zero-initialized all parts of the structure, and then
418 * provided callbacks for chip selection and I/O loops. If the master has
419 * a transfer method, its final step should call spi_bitbang_transfer; or,
420 * that's the default if the transfer routine is not initialized. It should
421 * also set up the bus number and number of chipselects.
422 *
423 * For i/o loops, provide callbacks either per-word (for bitbanging, or for
424 * hardware that basically exposes a shift register) or per-spi_transfer
425 * (which takes better advantage of hardware like fifos or DMA engines).
426 *
7f8c7619
HPN
427 * Drivers using per-word I/O loops should use (or call) spi_bitbang_setup,
428 * spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi
429 * master methods. Those methods are the defaults if the bitbang->txrx_bufs
430 * routine isn't initialized.
9904f22a
DB
431 *
432 * This routine registers the spi_master, which will process requests in a
433 * dedicated task, keeping IRQs unblocked most of the time. To stop
434 * processing those requests, call spi_bitbang_stop().
435 */
436int spi_bitbang_start(struct spi_bitbang *bitbang)
437{
7a5d8ca1
GL
438 struct spi_master *master = bitbang->master;
439 int status;
9904f22a 440
7a5d8ca1 441 if (!master || !bitbang->chipselect)
9904f22a
DB
442 return -EINVAL;
443
c4028958 444 INIT_WORK(&bitbang->work, bitbang_work);
9904f22a
DB
445 spin_lock_init(&bitbang->lock);
446 INIT_LIST_HEAD(&bitbang->queue);
447
7a5d8ca1
GL
448 if (!master->mode_bits)
449 master->mode_bits = SPI_CPOL | SPI_CPHA | bitbang->flags;
e7db06b5 450
7a5d8ca1
GL
451 if (!master->transfer)
452 master->transfer = spi_bitbang_transfer;
9904f22a
DB
453 if (!bitbang->txrx_bufs) {
454 bitbang->use_dma = 0;
455 bitbang->txrx_bufs = spi_bitbang_bufs;
7a5d8ca1 456 if (!master->setup) {
ff9f4771
KG
457 if (!bitbang->setup_transfer)
458 bitbang->setup_transfer =
459 spi_bitbang_setup_transfer;
7a5d8ca1
GL
460 master->setup = spi_bitbang_setup;
461 master->cleanup = spi_bitbang_cleanup;
9904f22a 462 }
7a5d8ca1 463 } else if (!master->setup)
9904f22a 464 return -EINVAL;
7a5d8ca1 465 if (master->transfer == spi_bitbang_transfer &&
ea3065df
SH
466 !bitbang->setup_transfer)
467 return -EINVAL;
9904f22a
DB
468
469 /* this task is the only thing to touch the SPI bits */
470 bitbang->busy = 0;
471 bitbang->workqueue = create_singlethread_workqueue(
7a5d8ca1 472 dev_name(master->dev.parent));
9904f22a
DB
473 if (bitbang->workqueue == NULL) {
474 status = -EBUSY;
475 goto err1;
476 }
477
478 /* driver may get busy before register() returns, especially
479 * if someone registered boardinfo for devices
480 */
7a5d8ca1 481 status = spi_register_master(master);
9904f22a
DB
482 if (status < 0)
483 goto err2;
484
485 return status;
486
487err2:
488 destroy_workqueue(bitbang->workqueue);
489err1:
490 return status;
491}
492EXPORT_SYMBOL_GPL(spi_bitbang_start);
493
494/**
495 * spi_bitbang_stop - stops the task providing spi communication
496 */
497int spi_bitbang_stop(struct spi_bitbang *bitbang)
498{
a836f585 499 spi_unregister_master(bitbang->master);
9904f22a 500
a836f585 501 WARN_ON(!list_empty(&bitbang->queue));
9904f22a
DB
502
503 destroy_workqueue(bitbang->workqueue);
504
9904f22a
DB
505 return 0;
506}
507EXPORT_SYMBOL_GPL(spi_bitbang_stop);
508
509MODULE_LICENSE("GPL");
510