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spi: davinci: do not use DMA if transfer length is less than 16
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CommitLineData
358934a6
SP
1/*
2 * Copyright (C) 2009 Texas Instruments.
43abb11b 3 * Copyright (C) 2010 EF Johnson Technologies
358934a6
SP
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
358934a6
SP
14 */
15
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19#include <linux/module.h>
20#include <linux/delay.h>
21#include <linux/platform_device.h>
22#include <linux/err.h>
23#include <linux/clk.h>
048177ce 24#include <linux/dmaengine.h>
358934a6 25#include <linux/dma-mapping.h>
aae7147d
MK
26#include <linux/of.h>
27#include <linux/of_device.h>
a88e34ea 28#include <linux/of_gpio.h>
358934a6
SP
29#include <linux/spi/spi.h>
30#include <linux/spi/spi_bitbang.h>
5a0e3ad6 31#include <linux/slab.h>
358934a6 32
ec2a0833 33#include <linux/platform_data/spi-davinci.h>
358934a6 34
358934a6
SP
35#define CS_DEFAULT 0xFF
36
358934a6
SP
37#define SPIFMT_PHASE_MASK BIT(16)
38#define SPIFMT_POLARITY_MASK BIT(17)
39#define SPIFMT_DISTIMER_MASK BIT(18)
40#define SPIFMT_SHIFTDIR_MASK BIT(20)
41#define SPIFMT_WAITENA_MASK BIT(21)
42#define SPIFMT_PARITYENA_MASK BIT(22)
43#define SPIFMT_ODD_PARITY_MASK BIT(23)
44#define SPIFMT_WDELAY_MASK 0x3f000000u
45#define SPIFMT_WDELAY_SHIFT 24
7fe0092b 46#define SPIFMT_PRESCALE_SHIFT 8
358934a6 47
358934a6
SP
48/* SPIPC0 */
49#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
50#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
51#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
52#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
358934a6
SP
53
54#define SPIINT_MASKALL 0x0101035F
e0d205e9
BN
55#define SPIINT_MASKINT 0x0000015F
56#define SPI_INTLVL_1 0x000001FF
57#define SPI_INTLVL_0 0x00000000
358934a6 58
cfbc5d1d
BN
59/* SPIDAT1 (upper 16 bit defines) */
60#define SPIDAT1_CSHOLD_MASK BIT(12)
365a7bb3 61#define SPIDAT1_WDEL BIT(10)
cfbc5d1d
BN
62
63/* SPIGCR1 */
358934a6
SP
64#define SPIGCR1_CLKMOD_MASK BIT(1)
65#define SPIGCR1_MASTER_MASK BIT(0)
3f27b57c 66#define SPIGCR1_POWERDOWN_MASK BIT(8)
358934a6 67#define SPIGCR1_LOOPBACK_MASK BIT(16)
8e206f1c 68#define SPIGCR1_SPIENA_MASK BIT(24)
358934a6
SP
69
70/* SPIBUF */
71#define SPIBUF_TXFULL_MASK BIT(29)
72#define SPIBUF_RXEMPTY_MASK BIT(31)
73
7abbf23c
BN
74/* SPIDELAY */
75#define SPIDELAY_C2TDELAY_SHIFT 24
76#define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
77#define SPIDELAY_T2CDELAY_SHIFT 16
78#define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
79#define SPIDELAY_T2EDELAY_SHIFT 8
80#define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
81#define SPIDELAY_C2EDELAY_SHIFT 0
82#define SPIDELAY_C2EDELAY_MASK 0xFF
83
358934a6
SP
84/* Error Masks */
85#define SPIFLG_DLEN_ERR_MASK BIT(0)
86#define SPIFLG_TIMEOUT_MASK BIT(1)
87#define SPIFLG_PARERR_MASK BIT(2)
88#define SPIFLG_DESYNC_MASK BIT(3)
89#define SPIFLG_BITERR_MASK BIT(4)
90#define SPIFLG_OVRRUN_MASK BIT(6)
358934a6 91#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
839c996c
BN
92#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
93 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
94 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
95 | SPIFLG_OVRRUN_MASK)
8e206f1c 96
358934a6 97#define SPIINT_DMA_REQ_EN BIT(16)
358934a6 98
358934a6
SP
99/* SPI Controller registers */
100#define SPIGCR0 0x00
101#define SPIGCR1 0x04
102#define SPIINT 0x08
103#define SPILVL 0x0c
104#define SPIFLG 0x10
105#define SPIPC0 0x14
358934a6
SP
106#define SPIDAT1 0x3c
107#define SPIBUF 0x40
358934a6
SP
108#define SPIDELAY 0x48
109#define SPIDEF 0x4c
110#define SPIFMT0 0x50
358934a6 111
0718b764
FI
112#define DMA_MIN_BYTES 16
113
358934a6
SP
114/* SPI Controller driver's private data. */
115struct davinci_spi {
116 struct spi_bitbang bitbang;
117 struct clk *clk;
118
119 u8 version;
120 resource_size_t pbase;
121 void __iomem *base;
e0d205e9
BN
122 u32 irq;
123 struct completion done;
358934a6
SP
124
125 const void *tx;
126 void *rx;
e0d205e9
BN
127 int rcount;
128 int wcount;
048177ce
MP
129
130 struct dma_chan *dma_rx;
131 struct dma_chan *dma_tx;
048177ce 132
aae7147d 133 struct davinci_spi_platform_data pdata;
358934a6
SP
134
135 void (*get_rx)(u32 rx_data, struct davinci_spi *);
136 u32 (*get_tx)(struct davinci_spi *);
137
7480e755 138 u8 *bytes_per_word;
fa466c91
FCJ
139
140 u8 prescaler_limit;
358934a6
SP
141};
142
53a31b07
BN
143static struct davinci_spi_config davinci_spi_default_cfg;
144
212d4b69 145static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
358934a6 146{
212d4b69
SN
147 if (dspi->rx) {
148 u8 *rx = dspi->rx;
53d454a1 149 *rx++ = (u8)data;
212d4b69 150 dspi->rx = rx;
53d454a1 151 }
358934a6
SP
152}
153
212d4b69 154static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
358934a6 155{
212d4b69
SN
156 if (dspi->rx) {
157 u16 *rx = dspi->rx;
53d454a1 158 *rx++ = (u16)data;
212d4b69 159 dspi->rx = rx;
53d454a1 160 }
358934a6
SP
161}
162
212d4b69 163static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
358934a6 164{
53d454a1 165 u32 data = 0;
859c3377 166
212d4b69
SN
167 if (dspi->tx) {
168 const u8 *tx = dspi->tx;
859c3377 169
53d454a1 170 data = *tx++;
212d4b69 171 dspi->tx = tx;
53d454a1 172 }
358934a6
SP
173 return data;
174}
175
212d4b69 176static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
358934a6 177{
53d454a1 178 u32 data = 0;
859c3377 179
212d4b69
SN
180 if (dspi->tx) {
181 const u16 *tx = dspi->tx;
859c3377 182
53d454a1 183 data = *tx++;
212d4b69 184 dspi->tx = tx;
53d454a1 185 }
358934a6
SP
186 return data;
187}
188
189static inline void set_io_bits(void __iomem *addr, u32 bits)
190{
191 u32 v = ioread32(addr);
192
193 v |= bits;
194 iowrite32(v, addr);
195}
196
197static inline void clear_io_bits(void __iomem *addr, u32 bits)
198{
199 u32 v = ioread32(addr);
200
201 v &= ~bits;
202 iowrite32(v, addr);
203}
204
358934a6
SP
205/*
206 * Interface to control the chip select signal
207 */
208static void davinci_spi_chipselect(struct spi_device *spi, int value)
209{
212d4b69 210 struct davinci_spi *dspi;
358934a6 211 struct davinci_spi_platform_data *pdata;
365a7bb3 212 struct davinci_spi_config *spicfg = spi->controller_data;
7978b8c3 213 u8 chip_sel = spi->chip_select;
212d4b69 214 u16 spidat1 = CS_DEFAULT;
358934a6 215
212d4b69 216 dspi = spi_master_get_devdata(spi->master);
aae7147d 217 pdata = &dspi->pdata;
358934a6 218
365a7bb3
MK
219 /* program delay transfers if tx_delay is non zero */
220 if (spicfg->wdelay)
221 spidat1 |= SPIDAT1_WDEL;
222
358934a6
SP
223 /*
224 * Board specific chip select logic decides the polarity and cs
225 * line for the controller
226 */
8cae0424 227 if (spi->cs_gpio >= 0) {
23853973 228 if (value == BITBANG_CS_ACTIVE)
8cae0424 229 gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH);
23853973 230 else
8cae0424
LB
231 gpio_set_value(spi->cs_gpio,
232 !(spi->mode & SPI_CS_HIGH));
23853973
BN
233 } else {
234 if (value == BITBANG_CS_ACTIVE) {
212d4b69
SN
235 spidat1 |= SPIDAT1_CSHOLD_MASK;
236 spidat1 &= ~(0x1 << chip_sel);
23853973 237 }
23853973 238 }
365a7bb3
MK
239
240 iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
358934a6
SP
241}
242
7fe0092b
BN
243/**
244 * davinci_spi_get_prescale - Calculates the correct prescale value
245 * @maxspeed_hz: the maximum rate the SPI clock can run at
246 *
247 * This function calculates the prescale value that generates a clock rate
248 * less than or equal to the specified maximum.
249 *
bba732d8 250 * Returns: calculated prescale value for easy programming into SPI registers
7fe0092b
BN
251 * or negative error number if valid prescalar cannot be updated.
252 */
212d4b69 253static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
7fe0092b
BN
254 u32 max_speed_hz)
255{
256 int ret;
257
bba732d8
FCJ
258 /* Subtract 1 to match what will be programmed into SPI register. */
259 ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1;
7fe0092b 260
fa466c91 261 if (ret < dspi->prescaler_limit || ret > 255)
7fe0092b
BN
262 return -EINVAL;
263
bba732d8 264 return ret;
7fe0092b
BN
265}
266
358934a6
SP
267/**
268 * davinci_spi_setup_transfer - This functions will determine transfer method
269 * @spi: spi device on which data transfer to be done
270 * @t: spi transfer in which transfer info is filled
271 *
272 * This function determines data transfer method (8/16/32 bit transfer).
273 * It will also set the SPI Clock Control register according to
274 * SPI slave device freq.
275 */
276static int davinci_spi_setup_transfer(struct spi_device *spi,
277 struct spi_transfer *t)
278{
279
212d4b69 280 struct davinci_spi *dspi;
25f33512 281 struct davinci_spi_config *spicfg;
358934a6 282 u8 bits_per_word = 0;
32ea3944
SK
283 u32 hz = 0, spifmt = 0;
284 int prescale;
358934a6 285
212d4b69 286 dspi = spi_master_get_devdata(spi->master);
365a7bb3 287 spicfg = spi->controller_data;
25f33512
BN
288 if (!spicfg)
289 spicfg = &davinci_spi_default_cfg;
358934a6
SP
290
291 if (t) {
292 bits_per_word = t->bits_per_word;
293 hz = t->speed_hz;
294 }
295
296 /* if bits_per_word is not set then set it default */
297 if (!bits_per_word)
298 bits_per_word = spi->bits_per_word;
299
300 /*
301 * Assign function pointer to appropriate transfer method
302 * 8bit, 16bit or 32bit transfer
303 */
24778be2 304 if (bits_per_word <= 8) {
212d4b69
SN
305 dspi->get_rx = davinci_spi_rx_buf_u8;
306 dspi->get_tx = davinci_spi_tx_buf_u8;
307 dspi->bytes_per_word[spi->chip_select] = 1;
24778be2 308 } else {
212d4b69
SN
309 dspi->get_rx = davinci_spi_rx_buf_u16;
310 dspi->get_tx = davinci_spi_tx_buf_u16;
311 dspi->bytes_per_word[spi->chip_select] = 2;
24778be2 312 }
358934a6
SP
313
314 if (!hz)
315 hz = spi->max_speed_hz;
316
25f33512
BN
317 /* Set up SPIFMTn register, unique to this chipselect. */
318
212d4b69 319 prescale = davinci_spi_get_prescale(dspi, hz);
7fe0092b
BN
320 if (prescale < 0)
321 return prescale;
322
25f33512
BN
323 spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
324
325 if (spi->mode & SPI_LSB_FIRST)
326 spifmt |= SPIFMT_SHIFTDIR_MASK;
327
328 if (spi->mode & SPI_CPOL)
329 spifmt |= SPIFMT_POLARITY_MASK;
330
331 if (!(spi->mode & SPI_CPHA))
332 spifmt |= SPIFMT_PHASE_MASK;
333
365a7bb3
MK
334 /*
335 * Assume wdelay is used only on SPI peripherals that has this field
336 * in SPIFMTn register and when it's configured from board file or DT.
337 */
338 if (spicfg->wdelay)
339 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
340 & SPIFMT_WDELAY_MASK);
341
25f33512
BN
342 /*
343 * Version 1 hardware supports two basic SPI modes:
344 * - Standard SPI mode uses 4 pins, with chipselect
345 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
346 * (distinct from SPI_3WIRE, with just one data wire;
347 * or similar variants without MOSI or without MISO)
348 *
349 * Version 2 hardware supports an optional handshaking signal,
350 * so it can support two more modes:
351 * - 5 pin SPI variant is standard SPI plus SPI_READY
352 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
353 */
354
212d4b69 355 if (dspi->version == SPI_VERSION_2) {
25f33512 356
7abbf23c
BN
357 u32 delay = 0;
358
25f33512
BN
359 if (spicfg->odd_parity)
360 spifmt |= SPIFMT_ODD_PARITY_MASK;
361
362 if (spicfg->parity_enable)
363 spifmt |= SPIFMT_PARITYENA_MASK;
364
7abbf23c 365 if (spicfg->timer_disable) {
25f33512 366 spifmt |= SPIFMT_DISTIMER_MASK;
7abbf23c
BN
367 } else {
368 delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
369 & SPIDELAY_C2TDELAY_MASK;
370 delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
371 & SPIDELAY_T2CDELAY_MASK;
372 }
25f33512 373
7abbf23c 374 if (spi->mode & SPI_READY) {
25f33512 375 spifmt |= SPIFMT_WAITENA_MASK;
7abbf23c
BN
376 delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
377 & SPIDELAY_T2EDELAY_MASK;
378 delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
379 & SPIDELAY_C2EDELAY_MASK;
380 }
381
212d4b69 382 iowrite32(delay, dspi->base + SPIDELAY);
25f33512
BN
383 }
384
212d4b69 385 iowrite32(spifmt, dspi->base + SPIFMT0);
358934a6
SP
386
387 return 0;
388}
389
365a7bb3
MK
390static int davinci_spi_of_setup(struct spi_device *spi)
391{
392 struct davinci_spi_config *spicfg = spi->controller_data;
393 struct device_node *np = spi->dev.of_node;
3e2e1258 394 struct davinci_spi *dspi = spi_master_get_devdata(spi->master);
365a7bb3
MK
395 u32 prop;
396
397 if (spicfg == NULL && np) {
398 spicfg = kzalloc(sizeof(*spicfg), GFP_KERNEL);
399 if (!spicfg)
400 return -ENOMEM;
401 *spicfg = davinci_spi_default_cfg;
402 /* override with dt configured values */
403 if (!of_property_read_u32(np, "ti,spi-wdelay", &prop))
404 spicfg->wdelay = (u8)prop;
405 spi->controller_data = spicfg;
3e2e1258
FP
406
407 if (dspi->dma_rx && dspi->dma_tx)
408 spicfg->io_type = SPI_IO_TYPE_DMA;
365a7bb3
MK
409 }
410
411 return 0;
412}
413
358934a6
SP
414/**
415 * davinci_spi_setup - This functions will set default transfer method
416 * @spi: spi device on which data transfer to be done
417 *
418 * This functions sets the default transfer method.
419 */
358934a6
SP
420static int davinci_spi_setup(struct spi_device *spi)
421{
b23a5d46 422 int retval = 0;
212d4b69 423 struct davinci_spi *dspi;
be88471b 424 struct davinci_spi_platform_data *pdata;
a88e34ea
MK
425 struct spi_master *master = spi->master;
426 struct device_node *np = spi->dev.of_node;
427 bool internal_cs = true;
358934a6 428
212d4b69 429 dspi = spi_master_get_devdata(spi->master);
aae7147d 430 pdata = &dspi->pdata;
358934a6 431
be88471b 432 if (!(spi->mode & SPI_NO_CS)) {
a88e34ea 433 if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) {
8936decd
GS
434 retval = gpio_direction_output(
435 spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
a88e34ea
MK
436 internal_cs = false;
437 } else if (pdata->chip_sel &&
438 spi->chip_select < pdata->num_chipselect &&
439 pdata->chip_sel[spi->chip_select] != SPI_INTERN_CS) {
c0600140 440 spi->cs_gpio = pdata->chip_sel[spi->chip_select];
8936decd
GS
441 retval = gpio_direction_output(
442 spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
a88e34ea
MK
443 internal_cs = false;
444 }
be88471b 445
3f2dad99
GS
446 if (retval) {
447 dev_err(&spi->dev, "GPIO %d setup failed (%d)\n",
448 spi->cs_gpio, retval);
449 return retval;
450 }
c0600140 451
3f2dad99
GS
452 if (internal_cs)
453 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
454 }
a88e34ea 455
be88471b 456 if (spi->mode & SPI_READY)
212d4b69 457 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
be88471b
BN
458
459 if (spi->mode & SPI_LOOP)
212d4b69 460 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
be88471b 461 else
212d4b69 462 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
be88471b 463
365a7bb3
MK
464 return davinci_spi_of_setup(spi);
465}
466
467static void davinci_spi_cleanup(struct spi_device *spi)
468{
469 struct davinci_spi_config *spicfg = spi->controller_data;
470
471 spi->controller_data = NULL;
472 if (spi->dev.of_node)
473 kfree(spicfg);
358934a6
SP
474}
475
8aedbf58
FP
476static bool davinci_spi_can_dma(struct spi_master *master,
477 struct spi_device *spi,
478 struct spi_transfer *xfer)
479{
480 struct davinci_spi_config *spicfg = spi->controller_data;
481 bool can_dma = false;
482
483 if (spicfg)
0718b764
FI
484 can_dma = (spicfg->io_type == SPI_IO_TYPE_DMA) &&
485 (xfer->len >= DMA_MIN_BYTES);
8aedbf58
FP
486
487 return can_dma;
488}
489
212d4b69 490static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
358934a6 491{
212d4b69 492 struct device *sdev = dspi->bitbang.master->dev.parent;
358934a6
SP
493
494 if (int_status & SPIFLG_TIMEOUT_MASK) {
21c015b7 495 dev_err(sdev, "SPI Time-out Error\n");
358934a6
SP
496 return -ETIMEDOUT;
497 }
498 if (int_status & SPIFLG_DESYNC_MASK) {
21c015b7 499 dev_err(sdev, "SPI Desynchronization Error\n");
358934a6
SP
500 return -EIO;
501 }
502 if (int_status & SPIFLG_BITERR_MASK) {
21c015b7 503 dev_err(sdev, "SPI Bit error\n");
358934a6
SP
504 return -EIO;
505 }
506
212d4b69 507 if (dspi->version == SPI_VERSION_2) {
358934a6 508 if (int_status & SPIFLG_DLEN_ERR_MASK) {
21c015b7 509 dev_err(sdev, "SPI Data Length Error\n");
358934a6
SP
510 return -EIO;
511 }
512 if (int_status & SPIFLG_PARERR_MASK) {
21c015b7 513 dev_err(sdev, "SPI Parity Error\n");
358934a6
SP
514 return -EIO;
515 }
516 if (int_status & SPIFLG_OVRRUN_MASK) {
21c015b7 517 dev_err(sdev, "SPI Data Overrun error\n");
358934a6
SP
518 return -EIO;
519 }
358934a6 520 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
21c015b7 521 dev_err(sdev, "SPI Buffer Init Active\n");
358934a6
SP
522 return -EBUSY;
523 }
524 }
525
526 return 0;
527}
528
e0d205e9
BN
529/**
530 * davinci_spi_process_events - check for and handle any SPI controller events
212d4b69 531 * @dspi: the controller data
e0d205e9
BN
532 *
533 * This function will check the SPIFLG register and handle any events that are
534 * detected there
535 */
212d4b69 536static int davinci_spi_process_events(struct davinci_spi *dspi)
e0d205e9 537{
212d4b69 538 u32 buf, status, errors = 0, spidat1;
e0d205e9 539
212d4b69 540 buf = ioread32(dspi->base + SPIBUF);
e0d205e9 541
212d4b69
SN
542 if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
543 dspi->get_rx(buf & 0xFFFF, dspi);
544 dspi->rcount--;
e0d205e9
BN
545 }
546
212d4b69 547 status = ioread32(dspi->base + SPIFLG);
e0d205e9
BN
548
549 if (unlikely(status & SPIFLG_ERROR_MASK)) {
550 errors = status & SPIFLG_ERROR_MASK;
551 goto out;
552 }
553
212d4b69
SN
554 if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
555 spidat1 = ioread32(dspi->base + SPIDAT1);
556 dspi->wcount--;
557 spidat1 &= ~0xFFFF;
558 spidat1 |= 0xFFFF & dspi->get_tx(dspi);
559 iowrite32(spidat1, dspi->base + SPIDAT1);
e0d205e9
BN
560 }
561
562out:
563 return errors;
564}
565
048177ce 566static void davinci_spi_dma_rx_callback(void *data)
87467bd9 567{
048177ce 568 struct davinci_spi *dspi = (struct davinci_spi *)data;
87467bd9 569
048177ce 570 dspi->rcount = 0;
87467bd9 571
048177ce
MP
572 if (!dspi->wcount && !dspi->rcount)
573 complete(&dspi->done);
574}
87467bd9 575
048177ce
MP
576static void davinci_spi_dma_tx_callback(void *data)
577{
578 struct davinci_spi *dspi = (struct davinci_spi *)data;
579
580 dspi->wcount = 0;
581
582 if (!dspi->wcount && !dspi->rcount)
212d4b69 583 complete(&dspi->done);
87467bd9
BN
584}
585
358934a6
SP
586/**
587 * davinci_spi_bufs - functions which will handle transfer data
588 * @spi: spi device on which data transfer to be done
589 * @t: spi transfer in which transfer info is filled
590 *
591 * This function will put data to be transferred into data register
592 * of SPI controller and then wait until the completion will be marked
593 * by the IRQ Handler.
594 */
87467bd9 595static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
358934a6 596{
212d4b69 597 struct davinci_spi *dspi;
048177ce 598 int data_type, ret = -ENOMEM;
212d4b69 599 u32 tx_data, spidat1;
839c996c 600 u32 errors = 0;
e0d205e9 601 struct davinci_spi_config *spicfg;
358934a6 602 struct davinci_spi_platform_data *pdata;
87467bd9 603 unsigned uninitialized_var(rx_buf_count);
358934a6 604
212d4b69 605 dspi = spi_master_get_devdata(spi->master);
aae7147d 606 pdata = &dspi->pdata;
e0d205e9
BN
607 spicfg = (struct davinci_spi_config *)spi->controller_data;
608 if (!spicfg)
609 spicfg = &davinci_spi_default_cfg;
87467bd9
BN
610
611 /* convert len to words based on bits_per_word */
212d4b69 612 data_type = dspi->bytes_per_word[spi->chip_select];
358934a6 613
212d4b69
SN
614 dspi->tx = t->tx_buf;
615 dspi->rx = t->rx_buf;
616 dspi->wcount = t->len / data_type;
617 dspi->rcount = dspi->wcount;
7978b8c3 618
212d4b69 619 spidat1 = ioread32(dspi->base + SPIDAT1);
839c996c 620
212d4b69
SN
621 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
622 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
358934a6 623
16735d02 624 reinit_completion(&dspi->done);
87467bd9 625
0718b764
FI
626 if (!davinci_spi_can_dma(spi->master, spi, t)) {
627 if (spicfg->io_type != SPI_IO_TYPE_POLL)
628 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
87467bd9 629 /* start the transfer */
212d4b69
SN
630 dspi->wcount--;
631 tx_data = dspi->get_tx(dspi);
632 spidat1 &= 0xFFFF0000;
633 spidat1 |= tx_data & 0xFFFF;
634 iowrite32(spidat1, dspi->base + SPIDAT1);
87467bd9 635 } else {
048177ce
MP
636 struct dma_slave_config dma_rx_conf = {
637 .direction = DMA_DEV_TO_MEM,
638 .src_addr = (unsigned long)dspi->pbase + SPIBUF,
639 .src_addr_width = data_type,
640 .src_maxburst = 1,
641 };
642 struct dma_slave_config dma_tx_conf = {
643 .direction = DMA_MEM_TO_DEV,
644 .dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
645 .dst_addr_width = data_type,
646 .dst_maxburst = 1,
647 };
648 struct dma_async_tx_descriptor *rxdesc;
649 struct dma_async_tx_descriptor *txdesc;
048177ce
MP
650
651 dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
652 dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
653
048177ce 654 rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
8aedbf58 655 t->rx_sg.sgl, t->rx_sg.nents, DMA_DEV_TO_MEM,
048177ce
MP
656 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
657 if (!rxdesc)
658 goto err_desc;
659
6b3a631e
FI
660 if (!t->tx_buf) {
661 /* use rx buffer as dummy tx buffer */
662 t->tx_sg.sgl = t->rx_sg.sgl;
663 t->tx_sg.nents = t->rx_sg.nents;
664 }
665
048177ce 666 txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
8aedbf58 667 t->tx_sg.sgl, t->tx_sg.nents, DMA_MEM_TO_DEV,
048177ce
MP
668 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
669 if (!txdesc)
670 goto err_desc;
671
672 rxdesc->callback = davinci_spi_dma_rx_callback;
673 rxdesc->callback_param = (void *)dspi;
674 txdesc->callback = davinci_spi_dma_tx_callback;
675 txdesc->callback_param = (void *)dspi;
87467bd9
BN
676
677 if (pdata->cshold_bug)
212d4b69 678 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
87467bd9 679
048177ce
MP
680 dmaengine_submit(rxdesc);
681 dmaengine_submit(txdesc);
682
683 dma_async_issue_pending(dspi->dma_rx);
684 dma_async_issue_pending(dspi->dma_tx);
685
212d4b69 686 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
87467bd9 687 }
358934a6 688
e0d205e9 689 /* Wait for the transfer to complete */
87467bd9 690 if (spicfg->io_type != SPI_IO_TYPE_POLL) {
7f3ac71a
SN
691 if (wait_for_completion_timeout(&dspi->done, HZ) == 0)
692 errors = SPIFLG_TIMEOUT_MASK;
e0d205e9 693 } else {
212d4b69
SN
694 while (dspi->rcount > 0 || dspi->wcount > 0) {
695 errors = davinci_spi_process_events(dspi);
e0d205e9
BN
696 if (errors)
697 break;
698 cpu_relax();
358934a6
SP
699 }
700 }
701
212d4b69 702 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
0718b764 703 if (davinci_spi_can_dma(spi->master, spi, t))
212d4b69 704 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
048177ce 705
212d4b69
SN
706 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
707 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
3f27b57c 708
358934a6
SP
709 /*
710 * Check for bit error, desync error,parity error,timeout error and
711 * receive overflow errors
712 */
839c996c 713 if (errors) {
212d4b69 714 ret = davinci_spi_check_error(dspi, errors);
839c996c
BN
715 WARN(!ret, "%s: error reported but no error found!\n",
716 dev_name(&spi->dev));
358934a6 717 return ret;
839c996c 718 }
358934a6 719
212d4b69 720 if (dspi->rcount != 0 || dspi->wcount != 0) {
048177ce 721 dev_err(&spi->dev, "SPI data transfer error\n");
87467bd9
BN
722 return -EIO;
723 }
724
358934a6 725 return t->len;
048177ce
MP
726
727err_desc:
048177ce 728 return ret;
358934a6
SP
729}
730
32310aaf
MK
731/**
732 * dummy_thread_fn - dummy thread function
733 * @irq: IRQ number for this SPI Master
734 * @context_data: structure for SPI Master controller davinci_spi
735 *
736 * This is to satisfy the request_threaded_irq() API so that the irq
737 * handler is called in interrupt context.
738 */
739static irqreturn_t dummy_thread_fn(s32 irq, void *data)
740{
741 return IRQ_HANDLED;
742}
743
e0d205e9
BN
744/**
745 * davinci_spi_irq - Interrupt handler for SPI Master Controller
746 * @irq: IRQ number for this SPI Master
747 * @context_data: structure for SPI Master controller davinci_spi
748 *
749 * ISR will determine that interrupt arrives either for READ or WRITE command.
750 * According to command it will do the appropriate action. It will check
751 * transfer length and if it is not zero then dispatch transfer command again.
752 * If transfer length is zero then it will indicate the COMPLETION so that
753 * davinci_spi_bufs function can go ahead.
754 */
212d4b69 755static irqreturn_t davinci_spi_irq(s32 irq, void *data)
e0d205e9 756{
212d4b69 757 struct davinci_spi *dspi = data;
e0d205e9
BN
758 int status;
759
212d4b69 760 status = davinci_spi_process_events(dspi);
e0d205e9 761 if (unlikely(status != 0))
212d4b69 762 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
e0d205e9 763
212d4b69
SN
764 if ((!dspi->rcount && !dspi->wcount) || status)
765 complete(&dspi->done);
e0d205e9
BN
766
767 return IRQ_HANDLED;
768}
769
212d4b69 770static int davinci_spi_request_dma(struct davinci_spi *dspi)
903ca25b 771{
048177ce 772 struct device *sdev = dspi->bitbang.master->dev.parent;
048177ce 773
fe5fd254
PU
774 dspi->dma_rx = dma_request_chan(sdev, "rx");
775 if (IS_ERR(dspi->dma_rx))
776 return PTR_ERR(dspi->dma_rx);
903ca25b 777
fe5fd254
PU
778 dspi->dma_tx = dma_request_chan(sdev, "tx");
779 if (IS_ERR(dspi->dma_tx)) {
780 dma_release_channel(dspi->dma_rx);
781 return PTR_ERR(dspi->dma_tx);
903ca25b
SN
782 }
783
784 return 0;
785}
786
aae7147d 787#if defined(CONFIG_OF)
fa466c91
FCJ
788
789/* OF SPI data structure */
790struct davinci_spi_of_data {
791 u8 version;
792 u8 prescaler_limit;
793};
794
795static const struct davinci_spi_of_data dm6441_spi_data = {
796 .version = SPI_VERSION_1,
797 .prescaler_limit = 2,
798};
799
800static const struct davinci_spi_of_data da830_spi_data = {
801 .version = SPI_VERSION_2,
802 .prescaler_limit = 2,
803};
804
805static const struct davinci_spi_of_data keystone_spi_data = {
806 .version = SPI_VERSION_1,
807 .prescaler_limit = 0,
808};
809
aae7147d
MK
810static const struct of_device_id davinci_spi_of_match[] = {
811 {
804413f2 812 .compatible = "ti,dm6441-spi",
fa466c91 813 .data = &dm6441_spi_data,
aae7147d
MK
814 },
815 {
804413f2 816 .compatible = "ti,da830-spi",
fa466c91
FCJ
817 .data = &da830_spi_data,
818 },
819 {
820 .compatible = "ti,keystone-spi",
821 .data = &keystone_spi_data,
aae7147d
MK
822 },
823 { },
824};
0d2d0cc5 825MODULE_DEVICE_TABLE(of, davinci_spi_of_match);
aae7147d
MK
826
827/**
828 * spi_davinci_get_pdata - Get platform data from DTS binding
829 * @pdev: ptr to platform data
830 * @dspi: ptr to driver data
831 *
832 * Parses and populates pdata in dspi from device tree bindings.
833 *
834 * NOTE: Not all platform data params are supported currently.
835 */
836static int spi_davinci_get_pdata(struct platform_device *pdev,
837 struct davinci_spi *dspi)
838{
839 struct device_node *node = pdev->dev.of_node;
fa466c91 840 struct davinci_spi_of_data *spi_data;
aae7147d
MK
841 struct davinci_spi_platform_data *pdata;
842 unsigned int num_cs, intr_line = 0;
843 const struct of_device_id *match;
844
845 pdata = &dspi->pdata;
846
b53b34f0 847 match = of_match_device(davinci_spi_of_match, &pdev->dev);
aae7147d
MK
848 if (!match)
849 return -ENODEV;
850
fa466c91 851 spi_data = (struct davinci_spi_of_data *)match->data;
aae7147d 852
fa466c91
FCJ
853 pdata->version = spi_data->version;
854 pdata->prescaler_limit = spi_data->prescaler_limit;
aae7147d
MK
855 /*
856 * default num_cs is 1 and all chipsel are internal to the chip
a88e34ea
MK
857 * indicated by chip_sel being NULL or cs_gpios being NULL or
858 * set to -ENOENT. num-cs includes internal as well as gpios.
aae7147d
MK
859 * indicated by chip_sel being NULL. GPIO based CS is not
860 * supported yet in DT bindings.
861 */
862 num_cs = 1;
863 of_property_read_u32(node, "num-cs", &num_cs);
864 pdata->num_chipselect = num_cs;
865 of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line);
866 pdata->intr_line = intr_line;
867 return 0;
868}
869#else
aae7147d
MK
870static struct davinci_spi_platform_data
871 *spi_davinci_get_pdata(struct platform_device *pdev,
872 struct davinci_spi *dspi)
873{
874 return -ENODEV;
875}
876#endif
877
358934a6
SP
878/**
879 * davinci_spi_probe - probe function for SPI Master Controller
880 * @pdev: platform_device structure which contains plateform specific data
035540f6
BN
881 *
882 * According to Linux Device Model this function will be invoked by Linux
883 * with platform_device struct which contains the device specific info.
884 * This function will map the SPI controller's memory, register IRQ,
885 * Reset SPI controller and setting its registers to default value.
886 * It will invoke spi_bitbang_start to create work queue so that client driver
887 * can register transfer method to work queue.
358934a6 888 */
fd4a319b 889static int davinci_spi_probe(struct platform_device *pdev)
358934a6
SP
890{
891 struct spi_master *master;
212d4b69 892 struct davinci_spi *dspi;
358934a6 893 struct davinci_spi_platform_data *pdata;
5b3bb596 894 struct resource *r;
c0600140 895 int ret = 0;
f34bd4cc 896 u32 spipc0;
358934a6 897
358934a6
SP
898 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
899 if (master == NULL) {
900 ret = -ENOMEM;
901 goto err;
902 }
903
24b5a82c 904 platform_set_drvdata(pdev, master);
358934a6 905
212d4b69 906 dspi = spi_master_get_devdata(master);
358934a6 907
8074cf06
JH
908 if (dev_get_platdata(&pdev->dev)) {
909 pdata = dev_get_platdata(&pdev->dev);
aae7147d
MK
910 dspi->pdata = *pdata;
911 } else {
912 /* update dspi pdata with that from the DT */
913 ret = spi_davinci_get_pdata(pdev, dspi);
914 if (ret < 0)
915 goto free_master;
916 }
917
918 /* pdata in dspi is now updated and point pdata to that */
919 pdata = &dspi->pdata;
920
7480e755
MK
921 dspi->bytes_per_word = devm_kzalloc(&pdev->dev,
922 sizeof(*dspi->bytes_per_word) *
923 pdata->num_chipselect, GFP_KERNEL);
924 if (dspi->bytes_per_word == NULL) {
925 ret = -ENOMEM;
926 goto free_master;
927 }
928
358934a6
SP
929 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
930 if (r == NULL) {
931 ret = -ENOENT;
932 goto free_master;
933 }
934
212d4b69 935 dspi->pbase = r->start;
358934a6 936
5b3bb596
JH
937 dspi->base = devm_ioremap_resource(&pdev->dev, r);
938 if (IS_ERR(dspi->base)) {
939 ret = PTR_ERR(dspi->base);
358934a6
SP
940 goto free_master;
941 }
942
8494cdea
AH
943 ret = platform_get_irq(pdev, 0);
944 if (ret == 0)
e0d205e9 945 ret = -EINVAL;
8494cdea 946 if (ret < 0)
5b3bb596 947 goto free_master;
8494cdea 948 dspi->irq = ret;
e0d205e9 949
5b3bb596
JH
950 ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq,
951 dummy_thread_fn, 0, dev_name(&pdev->dev), dspi);
e0d205e9 952 if (ret)
5b3bb596 953 goto free_master;
e0d205e9 954
94c69f76 955 dspi->bitbang.master = master;
358934a6 956
5b3bb596 957 dspi->clk = devm_clk_get(&pdev->dev, NULL);
212d4b69 958 if (IS_ERR(dspi->clk)) {
358934a6 959 ret = -ENODEV;
5b3bb596 960 goto free_master;
358934a6 961 }
aae7147d 962 clk_prepare_enable(dspi->clk);
358934a6 963
aae7147d 964 master->dev.of_node = pdev->dev.of_node;
358934a6
SP
965 master->bus_num = pdev->id;
966 master->num_chipselect = pdata->num_chipselect;
24778be2 967 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
6b3a631e 968 master->flags = SPI_MASTER_MUST_RX;
358934a6 969 master->setup = davinci_spi_setup;
365a7bb3 970 master->cleanup = davinci_spi_cleanup;
8aedbf58 971 master->can_dma = davinci_spi_can_dma;
358934a6 972
212d4b69
SN
973 dspi->bitbang.chipselect = davinci_spi_chipselect;
974 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
fa466c91 975 dspi->prescaler_limit = pdata->prescaler_limit;
212d4b69 976 dspi->version = pdata->version;
358934a6 977
212d4b69
SN
978 dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
979 if (dspi->version == SPI_VERSION_2)
980 dspi->bitbang.flags |= SPI_READY;
358934a6 981
8936decd
GS
982 if (pdev->dev.of_node) {
983 int i;
984
985 for (i = 0; i < pdata->num_chipselect; i++) {
986 int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
987 "cs-gpios", i);
988
989 if (cs_gpio == -EPROBE_DEFER) {
990 ret = cs_gpio;
991 goto free_clk;
992 }
993
994 if (gpio_is_valid(cs_gpio)) {
995 ret = devm_gpio_request(&pdev->dev, cs_gpio,
996 dev_name(&pdev->dev));
997 if (ret)
998 goto free_clk;
999 }
1000 }
1001 }
1002
212d4b69 1003 dspi->bitbang.txrx_bufs = davinci_spi_bufs;
fe5fd254
PU
1004
1005 ret = davinci_spi_request_dma(dspi);
1006 if (ret == -EPROBE_DEFER) {
1007 goto free_clk;
1008 } else if (ret) {
1009 dev_info(&pdev->dev, "DMA is not supported (%d)\n", ret);
1010 dspi->dma_rx = NULL;
1011 dspi->dma_tx = NULL;
358934a6
SP
1012 }
1013
212d4b69
SN
1014 dspi->get_rx = davinci_spi_rx_buf_u8;
1015 dspi->get_tx = davinci_spi_tx_buf_u8;
358934a6 1016
212d4b69 1017 init_completion(&dspi->done);
e0d205e9 1018
358934a6 1019 /* Reset In/OUT SPI module */
212d4b69 1020 iowrite32(0, dspi->base + SPIGCR0);
358934a6 1021 udelay(100);
212d4b69 1022 iowrite32(1, dspi->base + SPIGCR0);
358934a6 1023
be88471b 1024 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
f34bd4cc 1025 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
212d4b69 1026 iowrite32(spipc0, dspi->base + SPIPC0);
f34bd4cc 1027
e0d205e9 1028 if (pdata->intr_line)
212d4b69 1029 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
e0d205e9 1030 else
212d4b69 1031 iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
e0d205e9 1032
212d4b69 1033 iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
843a713b 1034
358934a6 1035 /* master mode default */
212d4b69
SN
1036 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
1037 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1038 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
358934a6 1039
212d4b69 1040 ret = spi_bitbang_start(&dspi->bitbang);
358934a6 1041 if (ret)
903ca25b 1042 goto free_dma;
358934a6 1043
212d4b69 1044 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
358934a6 1045
358934a6
SP
1046 return ret;
1047
903ca25b 1048free_dma:
fe5fd254
PU
1049 if (dspi->dma_rx) {
1050 dma_release_channel(dspi->dma_rx);
1051 dma_release_channel(dspi->dma_tx);
1052 }
358934a6 1053free_clk:
aae7147d 1054 clk_disable_unprepare(dspi->clk);
358934a6 1055free_master:
94c69f76 1056 spi_master_put(master);
358934a6
SP
1057err:
1058 return ret;
1059}
1060
1061/**
1062 * davinci_spi_remove - remove function for SPI Master Controller
1063 * @pdev: platform_device structure which contains plateform specific data
1064 *
1065 * This function will do the reverse action of davinci_spi_probe function
1066 * It will free the IRQ and SPI controller's memory region.
1067 * It will also call spi_bitbang_stop to destroy the work queue which was
1068 * created by spi_bitbang_start.
1069 */
fd4a319b 1070static int davinci_spi_remove(struct platform_device *pdev)
358934a6 1071{
212d4b69 1072 struct davinci_spi *dspi;
358934a6
SP
1073 struct spi_master *master;
1074
24b5a82c 1075 master = platform_get_drvdata(pdev);
212d4b69 1076 dspi = spi_master_get_devdata(master);
358934a6 1077
212d4b69 1078 spi_bitbang_stop(&dspi->bitbang);
358934a6 1079
aae7147d 1080 clk_disable_unprepare(dspi->clk);
94c69f76 1081 spi_master_put(master);
358934a6 1082
fe5fd254
PU
1083 if (dspi->dma_rx) {
1084 dma_release_channel(dspi->dma_rx);
1085 dma_release_channel(dspi->dma_tx);
1086 }
1087
358934a6
SP
1088 return 0;
1089}
1090
1091static struct platform_driver davinci_spi_driver = {
d8c174cd
BN
1092 .driver = {
1093 .name = "spi_davinci",
b53b34f0 1094 .of_match_table = of_match_ptr(davinci_spi_of_match),
d8c174cd 1095 },
940ab889 1096 .probe = davinci_spi_probe,
fd4a319b 1097 .remove = davinci_spi_remove,
358934a6 1098};
940ab889 1099module_platform_driver(davinci_spi_driver);
358934a6
SP
1100
1101MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1102MODULE_LICENSE("GPL");