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358934a6 SP |
1 | /* |
2 | * Copyright (C) 2009 Texas Instruments. | |
43abb11b | 3 | * Copyright (C) 2010 EF Johnson Technologies |
358934a6 SP |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
358934a6 SP |
14 | */ |
15 | ||
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/gpio.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/clk.h> | |
048177ce | 24 | #include <linux/dmaengine.h> |
358934a6 | 25 | #include <linux/dma-mapping.h> |
aae7147d MK |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
a88e34ea | 28 | #include <linux/of_gpio.h> |
358934a6 SP |
29 | #include <linux/spi/spi.h> |
30 | #include <linux/spi/spi_bitbang.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
358934a6 | 32 | |
ec2a0833 | 33 | #include <linux/platform_data/spi-davinci.h> |
358934a6 | 34 | |
358934a6 SP |
35 | #define CS_DEFAULT 0xFF |
36 | ||
358934a6 SP |
37 | #define SPIFMT_PHASE_MASK BIT(16) |
38 | #define SPIFMT_POLARITY_MASK BIT(17) | |
39 | #define SPIFMT_DISTIMER_MASK BIT(18) | |
40 | #define SPIFMT_SHIFTDIR_MASK BIT(20) | |
41 | #define SPIFMT_WAITENA_MASK BIT(21) | |
42 | #define SPIFMT_PARITYENA_MASK BIT(22) | |
43 | #define SPIFMT_ODD_PARITY_MASK BIT(23) | |
44 | #define SPIFMT_WDELAY_MASK 0x3f000000u | |
45 | #define SPIFMT_WDELAY_SHIFT 24 | |
7fe0092b | 46 | #define SPIFMT_PRESCALE_SHIFT 8 |
358934a6 | 47 | |
358934a6 SP |
48 | /* SPIPC0 */ |
49 | #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ | |
50 | #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ | |
51 | #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ | |
52 | #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ | |
358934a6 SP |
53 | |
54 | #define SPIINT_MASKALL 0x0101035F | |
e0d205e9 BN |
55 | #define SPIINT_MASKINT 0x0000015F |
56 | #define SPI_INTLVL_1 0x000001FF | |
57 | #define SPI_INTLVL_0 0x00000000 | |
358934a6 | 58 | |
cfbc5d1d BN |
59 | /* SPIDAT1 (upper 16 bit defines) */ |
60 | #define SPIDAT1_CSHOLD_MASK BIT(12) | |
365a7bb3 | 61 | #define SPIDAT1_WDEL BIT(10) |
cfbc5d1d BN |
62 | |
63 | /* SPIGCR1 */ | |
358934a6 SP |
64 | #define SPIGCR1_CLKMOD_MASK BIT(1) |
65 | #define SPIGCR1_MASTER_MASK BIT(0) | |
3f27b57c | 66 | #define SPIGCR1_POWERDOWN_MASK BIT(8) |
358934a6 | 67 | #define SPIGCR1_LOOPBACK_MASK BIT(16) |
8e206f1c | 68 | #define SPIGCR1_SPIENA_MASK BIT(24) |
358934a6 SP |
69 | |
70 | /* SPIBUF */ | |
71 | #define SPIBUF_TXFULL_MASK BIT(29) | |
72 | #define SPIBUF_RXEMPTY_MASK BIT(31) | |
73 | ||
7abbf23c BN |
74 | /* SPIDELAY */ |
75 | #define SPIDELAY_C2TDELAY_SHIFT 24 | |
76 | #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) | |
77 | #define SPIDELAY_T2CDELAY_SHIFT 16 | |
78 | #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) | |
79 | #define SPIDELAY_T2EDELAY_SHIFT 8 | |
80 | #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) | |
81 | #define SPIDELAY_C2EDELAY_SHIFT 0 | |
82 | #define SPIDELAY_C2EDELAY_MASK 0xFF | |
83 | ||
358934a6 SP |
84 | /* Error Masks */ |
85 | #define SPIFLG_DLEN_ERR_MASK BIT(0) | |
86 | #define SPIFLG_TIMEOUT_MASK BIT(1) | |
87 | #define SPIFLG_PARERR_MASK BIT(2) | |
88 | #define SPIFLG_DESYNC_MASK BIT(3) | |
89 | #define SPIFLG_BITERR_MASK BIT(4) | |
90 | #define SPIFLG_OVRRUN_MASK BIT(6) | |
358934a6 | 91 | #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) |
839c996c BN |
92 | #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ |
93 | | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ | |
94 | | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ | |
95 | | SPIFLG_OVRRUN_MASK) | |
8e206f1c | 96 | |
358934a6 | 97 | #define SPIINT_DMA_REQ_EN BIT(16) |
358934a6 | 98 | |
358934a6 SP |
99 | /* SPI Controller registers */ |
100 | #define SPIGCR0 0x00 | |
101 | #define SPIGCR1 0x04 | |
102 | #define SPIINT 0x08 | |
103 | #define SPILVL 0x0c | |
104 | #define SPIFLG 0x10 | |
105 | #define SPIPC0 0x14 | |
358934a6 SP |
106 | #define SPIDAT1 0x3c |
107 | #define SPIBUF 0x40 | |
358934a6 SP |
108 | #define SPIDELAY 0x48 |
109 | #define SPIDEF 0x4c | |
110 | #define SPIFMT0 0x50 | |
358934a6 | 111 | |
358934a6 SP |
112 | /* SPI Controller driver's private data. */ |
113 | struct davinci_spi { | |
114 | struct spi_bitbang bitbang; | |
115 | struct clk *clk; | |
116 | ||
117 | u8 version; | |
118 | resource_size_t pbase; | |
119 | void __iomem *base; | |
e0d205e9 BN |
120 | u32 irq; |
121 | struct completion done; | |
358934a6 SP |
122 | |
123 | const void *tx; | |
124 | void *rx; | |
e0d205e9 BN |
125 | int rcount; |
126 | int wcount; | |
048177ce MP |
127 | |
128 | struct dma_chan *dma_rx; | |
129 | struct dma_chan *dma_tx; | |
048177ce | 130 | |
aae7147d | 131 | struct davinci_spi_platform_data pdata; |
358934a6 SP |
132 | |
133 | void (*get_rx)(u32 rx_data, struct davinci_spi *); | |
134 | u32 (*get_tx)(struct davinci_spi *); | |
135 | ||
7480e755 | 136 | u8 *bytes_per_word; |
fa466c91 FCJ |
137 | |
138 | u8 prescaler_limit; | |
358934a6 SP |
139 | }; |
140 | ||
53a31b07 BN |
141 | static struct davinci_spi_config davinci_spi_default_cfg; |
142 | ||
212d4b69 | 143 | static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi) |
358934a6 | 144 | { |
212d4b69 SN |
145 | if (dspi->rx) { |
146 | u8 *rx = dspi->rx; | |
53d454a1 | 147 | *rx++ = (u8)data; |
212d4b69 | 148 | dspi->rx = rx; |
53d454a1 | 149 | } |
358934a6 SP |
150 | } |
151 | ||
212d4b69 | 152 | static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi) |
358934a6 | 153 | { |
212d4b69 SN |
154 | if (dspi->rx) { |
155 | u16 *rx = dspi->rx; | |
53d454a1 | 156 | *rx++ = (u16)data; |
212d4b69 | 157 | dspi->rx = rx; |
53d454a1 | 158 | } |
358934a6 SP |
159 | } |
160 | ||
212d4b69 | 161 | static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi) |
358934a6 | 162 | { |
53d454a1 | 163 | u32 data = 0; |
859c3377 | 164 | |
212d4b69 SN |
165 | if (dspi->tx) { |
166 | const u8 *tx = dspi->tx; | |
859c3377 | 167 | |
53d454a1 | 168 | data = *tx++; |
212d4b69 | 169 | dspi->tx = tx; |
53d454a1 | 170 | } |
358934a6 SP |
171 | return data; |
172 | } | |
173 | ||
212d4b69 | 174 | static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi) |
358934a6 | 175 | { |
53d454a1 | 176 | u32 data = 0; |
859c3377 | 177 | |
212d4b69 SN |
178 | if (dspi->tx) { |
179 | const u16 *tx = dspi->tx; | |
859c3377 | 180 | |
53d454a1 | 181 | data = *tx++; |
212d4b69 | 182 | dspi->tx = tx; |
53d454a1 | 183 | } |
358934a6 SP |
184 | return data; |
185 | } | |
186 | ||
187 | static inline void set_io_bits(void __iomem *addr, u32 bits) | |
188 | { | |
189 | u32 v = ioread32(addr); | |
190 | ||
191 | v |= bits; | |
192 | iowrite32(v, addr); | |
193 | } | |
194 | ||
195 | static inline void clear_io_bits(void __iomem *addr, u32 bits) | |
196 | { | |
197 | u32 v = ioread32(addr); | |
198 | ||
199 | v &= ~bits; | |
200 | iowrite32(v, addr); | |
201 | } | |
202 | ||
358934a6 SP |
203 | /* |
204 | * Interface to control the chip select signal | |
205 | */ | |
206 | static void davinci_spi_chipselect(struct spi_device *spi, int value) | |
207 | { | |
212d4b69 | 208 | struct davinci_spi *dspi; |
358934a6 | 209 | struct davinci_spi_platform_data *pdata; |
365a7bb3 | 210 | struct davinci_spi_config *spicfg = spi->controller_data; |
7978b8c3 | 211 | u8 chip_sel = spi->chip_select; |
212d4b69 | 212 | u16 spidat1 = CS_DEFAULT; |
358934a6 | 213 | |
212d4b69 | 214 | dspi = spi_master_get_devdata(spi->master); |
aae7147d | 215 | pdata = &dspi->pdata; |
358934a6 | 216 | |
365a7bb3 MK |
217 | /* program delay transfers if tx_delay is non zero */ |
218 | if (spicfg->wdelay) | |
219 | spidat1 |= SPIDAT1_WDEL; | |
220 | ||
358934a6 SP |
221 | /* |
222 | * Board specific chip select logic decides the polarity and cs | |
223 | * line for the controller | |
224 | */ | |
8cae0424 | 225 | if (spi->cs_gpio >= 0) { |
23853973 | 226 | if (value == BITBANG_CS_ACTIVE) |
8cae0424 | 227 | gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH); |
23853973 | 228 | else |
8cae0424 LB |
229 | gpio_set_value(spi->cs_gpio, |
230 | !(spi->mode & SPI_CS_HIGH)); | |
23853973 BN |
231 | } else { |
232 | if (value == BITBANG_CS_ACTIVE) { | |
212d4b69 SN |
233 | spidat1 |= SPIDAT1_CSHOLD_MASK; |
234 | spidat1 &= ~(0x1 << chip_sel); | |
23853973 | 235 | } |
23853973 | 236 | } |
365a7bb3 MK |
237 | |
238 | iowrite16(spidat1, dspi->base + SPIDAT1 + 2); | |
358934a6 SP |
239 | } |
240 | ||
7fe0092b BN |
241 | /** |
242 | * davinci_spi_get_prescale - Calculates the correct prescale value | |
243 | * @maxspeed_hz: the maximum rate the SPI clock can run at | |
244 | * | |
245 | * This function calculates the prescale value that generates a clock rate | |
246 | * less than or equal to the specified maximum. | |
247 | * | |
bba732d8 | 248 | * Returns: calculated prescale value for easy programming into SPI registers |
7fe0092b BN |
249 | * or negative error number if valid prescalar cannot be updated. |
250 | */ | |
212d4b69 | 251 | static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, |
7fe0092b BN |
252 | u32 max_speed_hz) |
253 | { | |
254 | int ret; | |
255 | ||
bba732d8 FCJ |
256 | /* Subtract 1 to match what will be programmed into SPI register. */ |
257 | ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1; | |
7fe0092b | 258 | |
fa466c91 | 259 | if (ret < dspi->prescaler_limit || ret > 255) |
7fe0092b BN |
260 | return -EINVAL; |
261 | ||
bba732d8 | 262 | return ret; |
7fe0092b BN |
263 | } |
264 | ||
358934a6 SP |
265 | /** |
266 | * davinci_spi_setup_transfer - This functions will determine transfer method | |
267 | * @spi: spi device on which data transfer to be done | |
268 | * @t: spi transfer in which transfer info is filled | |
269 | * | |
270 | * This function determines data transfer method (8/16/32 bit transfer). | |
271 | * It will also set the SPI Clock Control register according to | |
272 | * SPI slave device freq. | |
273 | */ | |
274 | static int davinci_spi_setup_transfer(struct spi_device *spi, | |
275 | struct spi_transfer *t) | |
276 | { | |
277 | ||
212d4b69 | 278 | struct davinci_spi *dspi; |
25f33512 | 279 | struct davinci_spi_config *spicfg; |
358934a6 | 280 | u8 bits_per_word = 0; |
32ea3944 SK |
281 | u32 hz = 0, spifmt = 0; |
282 | int prescale; | |
358934a6 | 283 | |
212d4b69 | 284 | dspi = spi_master_get_devdata(spi->master); |
365a7bb3 | 285 | spicfg = spi->controller_data; |
25f33512 BN |
286 | if (!spicfg) |
287 | spicfg = &davinci_spi_default_cfg; | |
358934a6 SP |
288 | |
289 | if (t) { | |
290 | bits_per_word = t->bits_per_word; | |
291 | hz = t->speed_hz; | |
292 | } | |
293 | ||
294 | /* if bits_per_word is not set then set it default */ | |
295 | if (!bits_per_word) | |
296 | bits_per_word = spi->bits_per_word; | |
297 | ||
298 | /* | |
299 | * Assign function pointer to appropriate transfer method | |
300 | * 8bit, 16bit or 32bit transfer | |
301 | */ | |
24778be2 | 302 | if (bits_per_word <= 8) { |
212d4b69 SN |
303 | dspi->get_rx = davinci_spi_rx_buf_u8; |
304 | dspi->get_tx = davinci_spi_tx_buf_u8; | |
305 | dspi->bytes_per_word[spi->chip_select] = 1; | |
24778be2 | 306 | } else { |
212d4b69 SN |
307 | dspi->get_rx = davinci_spi_rx_buf_u16; |
308 | dspi->get_tx = davinci_spi_tx_buf_u16; | |
309 | dspi->bytes_per_word[spi->chip_select] = 2; | |
24778be2 | 310 | } |
358934a6 SP |
311 | |
312 | if (!hz) | |
313 | hz = spi->max_speed_hz; | |
314 | ||
25f33512 BN |
315 | /* Set up SPIFMTn register, unique to this chipselect. */ |
316 | ||
212d4b69 | 317 | prescale = davinci_spi_get_prescale(dspi, hz); |
7fe0092b BN |
318 | if (prescale < 0) |
319 | return prescale; | |
320 | ||
25f33512 BN |
321 | spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); |
322 | ||
323 | if (spi->mode & SPI_LSB_FIRST) | |
324 | spifmt |= SPIFMT_SHIFTDIR_MASK; | |
325 | ||
326 | if (spi->mode & SPI_CPOL) | |
327 | spifmt |= SPIFMT_POLARITY_MASK; | |
328 | ||
329 | if (!(spi->mode & SPI_CPHA)) | |
330 | spifmt |= SPIFMT_PHASE_MASK; | |
331 | ||
365a7bb3 MK |
332 | /* |
333 | * Assume wdelay is used only on SPI peripherals that has this field | |
334 | * in SPIFMTn register and when it's configured from board file or DT. | |
335 | */ | |
336 | if (spicfg->wdelay) | |
337 | spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) | |
338 | & SPIFMT_WDELAY_MASK); | |
339 | ||
25f33512 BN |
340 | /* |
341 | * Version 1 hardware supports two basic SPI modes: | |
342 | * - Standard SPI mode uses 4 pins, with chipselect | |
343 | * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) | |
344 | * (distinct from SPI_3WIRE, with just one data wire; | |
345 | * or similar variants without MOSI or without MISO) | |
346 | * | |
347 | * Version 2 hardware supports an optional handshaking signal, | |
348 | * so it can support two more modes: | |
349 | * - 5 pin SPI variant is standard SPI plus SPI_READY | |
350 | * - 4 pin with enable is (SPI_READY | SPI_NO_CS) | |
351 | */ | |
352 | ||
212d4b69 | 353 | if (dspi->version == SPI_VERSION_2) { |
25f33512 | 354 | |
7abbf23c BN |
355 | u32 delay = 0; |
356 | ||
25f33512 BN |
357 | if (spicfg->odd_parity) |
358 | spifmt |= SPIFMT_ODD_PARITY_MASK; | |
359 | ||
360 | if (spicfg->parity_enable) | |
361 | spifmt |= SPIFMT_PARITYENA_MASK; | |
362 | ||
7abbf23c | 363 | if (spicfg->timer_disable) { |
25f33512 | 364 | spifmt |= SPIFMT_DISTIMER_MASK; |
7abbf23c BN |
365 | } else { |
366 | delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) | |
367 | & SPIDELAY_C2TDELAY_MASK; | |
368 | delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) | |
369 | & SPIDELAY_T2CDELAY_MASK; | |
370 | } | |
25f33512 | 371 | |
7abbf23c | 372 | if (spi->mode & SPI_READY) { |
25f33512 | 373 | spifmt |= SPIFMT_WAITENA_MASK; |
7abbf23c BN |
374 | delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) |
375 | & SPIDELAY_T2EDELAY_MASK; | |
376 | delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) | |
377 | & SPIDELAY_C2EDELAY_MASK; | |
378 | } | |
379 | ||
212d4b69 | 380 | iowrite32(delay, dspi->base + SPIDELAY); |
25f33512 BN |
381 | } |
382 | ||
212d4b69 | 383 | iowrite32(spifmt, dspi->base + SPIFMT0); |
358934a6 SP |
384 | |
385 | return 0; | |
386 | } | |
387 | ||
365a7bb3 MK |
388 | static int davinci_spi_of_setup(struct spi_device *spi) |
389 | { | |
390 | struct davinci_spi_config *spicfg = spi->controller_data; | |
391 | struct device_node *np = spi->dev.of_node; | |
3e2e1258 | 392 | struct davinci_spi *dspi = spi_master_get_devdata(spi->master); |
365a7bb3 MK |
393 | u32 prop; |
394 | ||
395 | if (spicfg == NULL && np) { | |
396 | spicfg = kzalloc(sizeof(*spicfg), GFP_KERNEL); | |
397 | if (!spicfg) | |
398 | return -ENOMEM; | |
399 | *spicfg = davinci_spi_default_cfg; | |
400 | /* override with dt configured values */ | |
401 | if (!of_property_read_u32(np, "ti,spi-wdelay", &prop)) | |
402 | spicfg->wdelay = (u8)prop; | |
403 | spi->controller_data = spicfg; | |
3e2e1258 FP |
404 | |
405 | if (dspi->dma_rx && dspi->dma_tx) | |
406 | spicfg->io_type = SPI_IO_TYPE_DMA; | |
365a7bb3 MK |
407 | } |
408 | ||
409 | return 0; | |
410 | } | |
411 | ||
358934a6 SP |
412 | /** |
413 | * davinci_spi_setup - This functions will set default transfer method | |
414 | * @spi: spi device on which data transfer to be done | |
415 | * | |
416 | * This functions sets the default transfer method. | |
417 | */ | |
358934a6 SP |
418 | static int davinci_spi_setup(struct spi_device *spi) |
419 | { | |
b23a5d46 | 420 | int retval = 0; |
212d4b69 | 421 | struct davinci_spi *dspi; |
be88471b | 422 | struct davinci_spi_platform_data *pdata; |
a88e34ea MK |
423 | struct spi_master *master = spi->master; |
424 | struct device_node *np = spi->dev.of_node; | |
425 | bool internal_cs = true; | |
358934a6 | 426 | |
212d4b69 | 427 | dspi = spi_master_get_devdata(spi->master); |
aae7147d | 428 | pdata = &dspi->pdata; |
358934a6 | 429 | |
be88471b | 430 | if (!(spi->mode & SPI_NO_CS)) { |
a88e34ea | 431 | if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) { |
8936decd GS |
432 | retval = gpio_direction_output( |
433 | spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); | |
a88e34ea MK |
434 | internal_cs = false; |
435 | } else if (pdata->chip_sel && | |
436 | spi->chip_select < pdata->num_chipselect && | |
437 | pdata->chip_sel[spi->chip_select] != SPI_INTERN_CS) { | |
c0600140 | 438 | spi->cs_gpio = pdata->chip_sel[spi->chip_select]; |
8936decd GS |
439 | retval = gpio_direction_output( |
440 | spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); | |
a88e34ea MK |
441 | internal_cs = false; |
442 | } | |
be88471b | 443 | |
3f2dad99 GS |
444 | if (retval) { |
445 | dev_err(&spi->dev, "GPIO %d setup failed (%d)\n", | |
446 | spi->cs_gpio, retval); | |
447 | return retval; | |
448 | } | |
c0600140 | 449 | |
3f2dad99 GS |
450 | if (internal_cs) |
451 | set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); | |
452 | } | |
a88e34ea | 453 | |
be88471b | 454 | if (spi->mode & SPI_READY) |
212d4b69 | 455 | set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); |
be88471b BN |
456 | |
457 | if (spi->mode & SPI_LOOP) | |
212d4b69 | 458 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); |
be88471b | 459 | else |
212d4b69 | 460 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); |
be88471b | 461 | |
365a7bb3 MK |
462 | return davinci_spi_of_setup(spi); |
463 | } | |
464 | ||
465 | static void davinci_spi_cleanup(struct spi_device *spi) | |
466 | { | |
467 | struct davinci_spi_config *spicfg = spi->controller_data; | |
468 | ||
469 | spi->controller_data = NULL; | |
470 | if (spi->dev.of_node) | |
471 | kfree(spicfg); | |
358934a6 SP |
472 | } |
473 | ||
8aedbf58 FP |
474 | static bool davinci_spi_can_dma(struct spi_master *master, |
475 | struct spi_device *spi, | |
476 | struct spi_transfer *xfer) | |
477 | { | |
478 | struct davinci_spi_config *spicfg = spi->controller_data; | |
479 | bool can_dma = false; | |
480 | ||
481 | if (spicfg) | |
482 | can_dma = spicfg->io_type == SPI_IO_TYPE_DMA; | |
483 | ||
484 | return can_dma; | |
485 | } | |
486 | ||
212d4b69 | 487 | static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) |
358934a6 | 488 | { |
212d4b69 | 489 | struct device *sdev = dspi->bitbang.master->dev.parent; |
358934a6 SP |
490 | |
491 | if (int_status & SPIFLG_TIMEOUT_MASK) { | |
21c015b7 | 492 | dev_err(sdev, "SPI Time-out Error\n"); |
358934a6 SP |
493 | return -ETIMEDOUT; |
494 | } | |
495 | if (int_status & SPIFLG_DESYNC_MASK) { | |
21c015b7 | 496 | dev_err(sdev, "SPI Desynchronization Error\n"); |
358934a6 SP |
497 | return -EIO; |
498 | } | |
499 | if (int_status & SPIFLG_BITERR_MASK) { | |
21c015b7 | 500 | dev_err(sdev, "SPI Bit error\n"); |
358934a6 SP |
501 | return -EIO; |
502 | } | |
503 | ||
212d4b69 | 504 | if (dspi->version == SPI_VERSION_2) { |
358934a6 | 505 | if (int_status & SPIFLG_DLEN_ERR_MASK) { |
21c015b7 | 506 | dev_err(sdev, "SPI Data Length Error\n"); |
358934a6 SP |
507 | return -EIO; |
508 | } | |
509 | if (int_status & SPIFLG_PARERR_MASK) { | |
21c015b7 | 510 | dev_err(sdev, "SPI Parity Error\n"); |
358934a6 SP |
511 | return -EIO; |
512 | } | |
513 | if (int_status & SPIFLG_OVRRUN_MASK) { | |
21c015b7 | 514 | dev_err(sdev, "SPI Data Overrun error\n"); |
358934a6 SP |
515 | return -EIO; |
516 | } | |
358934a6 | 517 | if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { |
21c015b7 | 518 | dev_err(sdev, "SPI Buffer Init Active\n"); |
358934a6 SP |
519 | return -EBUSY; |
520 | } | |
521 | } | |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
e0d205e9 BN |
526 | /** |
527 | * davinci_spi_process_events - check for and handle any SPI controller events | |
212d4b69 | 528 | * @dspi: the controller data |
e0d205e9 BN |
529 | * |
530 | * This function will check the SPIFLG register and handle any events that are | |
531 | * detected there | |
532 | */ | |
212d4b69 | 533 | static int davinci_spi_process_events(struct davinci_spi *dspi) |
e0d205e9 | 534 | { |
212d4b69 | 535 | u32 buf, status, errors = 0, spidat1; |
e0d205e9 | 536 | |
212d4b69 | 537 | buf = ioread32(dspi->base + SPIBUF); |
e0d205e9 | 538 | |
212d4b69 SN |
539 | if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { |
540 | dspi->get_rx(buf & 0xFFFF, dspi); | |
541 | dspi->rcount--; | |
e0d205e9 BN |
542 | } |
543 | ||
212d4b69 | 544 | status = ioread32(dspi->base + SPIFLG); |
e0d205e9 BN |
545 | |
546 | if (unlikely(status & SPIFLG_ERROR_MASK)) { | |
547 | errors = status & SPIFLG_ERROR_MASK; | |
548 | goto out; | |
549 | } | |
550 | ||
212d4b69 SN |
551 | if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { |
552 | spidat1 = ioread32(dspi->base + SPIDAT1); | |
553 | dspi->wcount--; | |
554 | spidat1 &= ~0xFFFF; | |
555 | spidat1 |= 0xFFFF & dspi->get_tx(dspi); | |
556 | iowrite32(spidat1, dspi->base + SPIDAT1); | |
e0d205e9 BN |
557 | } |
558 | ||
559 | out: | |
560 | return errors; | |
561 | } | |
562 | ||
048177ce | 563 | static void davinci_spi_dma_rx_callback(void *data) |
87467bd9 | 564 | { |
048177ce | 565 | struct davinci_spi *dspi = (struct davinci_spi *)data; |
87467bd9 | 566 | |
048177ce | 567 | dspi->rcount = 0; |
87467bd9 | 568 | |
048177ce MP |
569 | if (!dspi->wcount && !dspi->rcount) |
570 | complete(&dspi->done); | |
571 | } | |
87467bd9 | 572 | |
048177ce MP |
573 | static void davinci_spi_dma_tx_callback(void *data) |
574 | { | |
575 | struct davinci_spi *dspi = (struct davinci_spi *)data; | |
576 | ||
577 | dspi->wcount = 0; | |
578 | ||
579 | if (!dspi->wcount && !dspi->rcount) | |
212d4b69 | 580 | complete(&dspi->done); |
87467bd9 BN |
581 | } |
582 | ||
358934a6 SP |
583 | /** |
584 | * davinci_spi_bufs - functions which will handle transfer data | |
585 | * @spi: spi device on which data transfer to be done | |
586 | * @t: spi transfer in which transfer info is filled | |
587 | * | |
588 | * This function will put data to be transferred into data register | |
589 | * of SPI controller and then wait until the completion will be marked | |
590 | * by the IRQ Handler. | |
591 | */ | |
87467bd9 | 592 | static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) |
358934a6 | 593 | { |
212d4b69 | 594 | struct davinci_spi *dspi; |
048177ce | 595 | int data_type, ret = -ENOMEM; |
212d4b69 | 596 | u32 tx_data, spidat1; |
839c996c | 597 | u32 errors = 0; |
e0d205e9 | 598 | struct davinci_spi_config *spicfg; |
358934a6 | 599 | struct davinci_spi_platform_data *pdata; |
87467bd9 | 600 | unsigned uninitialized_var(rx_buf_count); |
358934a6 | 601 | |
212d4b69 | 602 | dspi = spi_master_get_devdata(spi->master); |
aae7147d | 603 | pdata = &dspi->pdata; |
e0d205e9 BN |
604 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
605 | if (!spicfg) | |
606 | spicfg = &davinci_spi_default_cfg; | |
87467bd9 BN |
607 | |
608 | /* convert len to words based on bits_per_word */ | |
212d4b69 | 609 | data_type = dspi->bytes_per_word[spi->chip_select]; |
358934a6 | 610 | |
212d4b69 SN |
611 | dspi->tx = t->tx_buf; |
612 | dspi->rx = t->rx_buf; | |
613 | dspi->wcount = t->len / data_type; | |
614 | dspi->rcount = dspi->wcount; | |
7978b8c3 | 615 | |
212d4b69 | 616 | spidat1 = ioread32(dspi->base + SPIDAT1); |
839c996c | 617 | |
212d4b69 SN |
618 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); |
619 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | |
358934a6 | 620 | |
16735d02 | 621 | reinit_completion(&dspi->done); |
87467bd9 BN |
622 | |
623 | if (spicfg->io_type == SPI_IO_TYPE_INTR) | |
212d4b69 | 624 | set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); |
cf90fe73 | 625 | |
87467bd9 BN |
626 | if (spicfg->io_type != SPI_IO_TYPE_DMA) { |
627 | /* start the transfer */ | |
212d4b69 SN |
628 | dspi->wcount--; |
629 | tx_data = dspi->get_tx(dspi); | |
630 | spidat1 &= 0xFFFF0000; | |
631 | spidat1 |= tx_data & 0xFFFF; | |
632 | iowrite32(spidat1, dspi->base + SPIDAT1); | |
87467bd9 | 633 | } else { |
048177ce MP |
634 | struct dma_slave_config dma_rx_conf = { |
635 | .direction = DMA_DEV_TO_MEM, | |
636 | .src_addr = (unsigned long)dspi->pbase + SPIBUF, | |
637 | .src_addr_width = data_type, | |
638 | .src_maxburst = 1, | |
639 | }; | |
640 | struct dma_slave_config dma_tx_conf = { | |
641 | .direction = DMA_MEM_TO_DEV, | |
642 | .dst_addr = (unsigned long)dspi->pbase + SPIDAT1, | |
643 | .dst_addr_width = data_type, | |
644 | .dst_maxburst = 1, | |
645 | }; | |
646 | struct dma_async_tx_descriptor *rxdesc; | |
647 | struct dma_async_tx_descriptor *txdesc; | |
048177ce MP |
648 | |
649 | dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf); | |
650 | dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf); | |
651 | ||
048177ce | 652 | rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx, |
8aedbf58 | 653 | t->rx_sg.sgl, t->rx_sg.nents, DMA_DEV_TO_MEM, |
048177ce MP |
654 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
655 | if (!rxdesc) | |
656 | goto err_desc; | |
657 | ||
658 | txdesc = dmaengine_prep_slave_sg(dspi->dma_tx, | |
8aedbf58 | 659 | t->tx_sg.sgl, t->tx_sg.nents, DMA_MEM_TO_DEV, |
048177ce MP |
660 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
661 | if (!txdesc) | |
662 | goto err_desc; | |
663 | ||
664 | rxdesc->callback = davinci_spi_dma_rx_callback; | |
665 | rxdesc->callback_param = (void *)dspi; | |
666 | txdesc->callback = davinci_spi_dma_tx_callback; | |
667 | txdesc->callback_param = (void *)dspi; | |
87467bd9 BN |
668 | |
669 | if (pdata->cshold_bug) | |
212d4b69 | 670 | iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2); |
87467bd9 | 671 | |
048177ce MP |
672 | dmaengine_submit(rxdesc); |
673 | dmaengine_submit(txdesc); | |
674 | ||
675 | dma_async_issue_pending(dspi->dma_rx); | |
676 | dma_async_issue_pending(dspi->dma_tx); | |
677 | ||
212d4b69 | 678 | set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); |
87467bd9 | 679 | } |
358934a6 | 680 | |
e0d205e9 | 681 | /* Wait for the transfer to complete */ |
87467bd9 | 682 | if (spicfg->io_type != SPI_IO_TYPE_POLL) { |
7f3ac71a SN |
683 | if (wait_for_completion_timeout(&dspi->done, HZ) == 0) |
684 | errors = SPIFLG_TIMEOUT_MASK; | |
e0d205e9 | 685 | } else { |
212d4b69 SN |
686 | while (dspi->rcount > 0 || dspi->wcount > 0) { |
687 | errors = davinci_spi_process_events(dspi); | |
e0d205e9 BN |
688 | if (errors) |
689 | break; | |
690 | cpu_relax(); | |
358934a6 SP |
691 | } |
692 | } | |
693 | ||
212d4b69 | 694 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); |
8aedbf58 | 695 | if (spicfg->io_type == SPI_IO_TYPE_DMA) |
212d4b69 | 696 | clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); |
048177ce | 697 | |
212d4b69 SN |
698 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); |
699 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); | |
3f27b57c | 700 | |
358934a6 SP |
701 | /* |
702 | * Check for bit error, desync error,parity error,timeout error and | |
703 | * receive overflow errors | |
704 | */ | |
839c996c | 705 | if (errors) { |
212d4b69 | 706 | ret = davinci_spi_check_error(dspi, errors); |
839c996c BN |
707 | WARN(!ret, "%s: error reported but no error found!\n", |
708 | dev_name(&spi->dev)); | |
358934a6 | 709 | return ret; |
839c996c | 710 | } |
358934a6 | 711 | |
212d4b69 | 712 | if (dspi->rcount != 0 || dspi->wcount != 0) { |
048177ce | 713 | dev_err(&spi->dev, "SPI data transfer error\n"); |
87467bd9 BN |
714 | return -EIO; |
715 | } | |
716 | ||
358934a6 | 717 | return t->len; |
048177ce MP |
718 | |
719 | err_desc: | |
048177ce | 720 | return ret; |
358934a6 SP |
721 | } |
722 | ||
32310aaf MK |
723 | /** |
724 | * dummy_thread_fn - dummy thread function | |
725 | * @irq: IRQ number for this SPI Master | |
726 | * @context_data: structure for SPI Master controller davinci_spi | |
727 | * | |
728 | * This is to satisfy the request_threaded_irq() API so that the irq | |
729 | * handler is called in interrupt context. | |
730 | */ | |
731 | static irqreturn_t dummy_thread_fn(s32 irq, void *data) | |
732 | { | |
733 | return IRQ_HANDLED; | |
734 | } | |
735 | ||
e0d205e9 BN |
736 | /** |
737 | * davinci_spi_irq - Interrupt handler for SPI Master Controller | |
738 | * @irq: IRQ number for this SPI Master | |
739 | * @context_data: structure for SPI Master controller davinci_spi | |
740 | * | |
741 | * ISR will determine that interrupt arrives either for READ or WRITE command. | |
742 | * According to command it will do the appropriate action. It will check | |
743 | * transfer length and if it is not zero then dispatch transfer command again. | |
744 | * If transfer length is zero then it will indicate the COMPLETION so that | |
745 | * davinci_spi_bufs function can go ahead. | |
746 | */ | |
212d4b69 | 747 | static irqreturn_t davinci_spi_irq(s32 irq, void *data) |
e0d205e9 | 748 | { |
212d4b69 | 749 | struct davinci_spi *dspi = data; |
e0d205e9 BN |
750 | int status; |
751 | ||
212d4b69 | 752 | status = davinci_spi_process_events(dspi); |
e0d205e9 | 753 | if (unlikely(status != 0)) |
212d4b69 | 754 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); |
e0d205e9 | 755 | |
212d4b69 SN |
756 | if ((!dspi->rcount && !dspi->wcount) || status) |
757 | complete(&dspi->done); | |
e0d205e9 BN |
758 | |
759 | return IRQ_HANDLED; | |
760 | } | |
761 | ||
212d4b69 | 762 | static int davinci_spi_request_dma(struct davinci_spi *dspi) |
903ca25b | 763 | { |
048177ce | 764 | struct device *sdev = dspi->bitbang.master->dev.parent; |
048177ce | 765 | |
fe5fd254 PU |
766 | dspi->dma_rx = dma_request_chan(sdev, "rx"); |
767 | if (IS_ERR(dspi->dma_rx)) | |
768 | return PTR_ERR(dspi->dma_rx); | |
903ca25b | 769 | |
fe5fd254 PU |
770 | dspi->dma_tx = dma_request_chan(sdev, "tx"); |
771 | if (IS_ERR(dspi->dma_tx)) { | |
772 | dma_release_channel(dspi->dma_rx); | |
773 | return PTR_ERR(dspi->dma_tx); | |
903ca25b SN |
774 | } |
775 | ||
776 | return 0; | |
777 | } | |
778 | ||
aae7147d | 779 | #if defined(CONFIG_OF) |
fa466c91 FCJ |
780 | |
781 | /* OF SPI data structure */ | |
782 | struct davinci_spi_of_data { | |
783 | u8 version; | |
784 | u8 prescaler_limit; | |
785 | }; | |
786 | ||
787 | static const struct davinci_spi_of_data dm6441_spi_data = { | |
788 | .version = SPI_VERSION_1, | |
789 | .prescaler_limit = 2, | |
790 | }; | |
791 | ||
792 | static const struct davinci_spi_of_data da830_spi_data = { | |
793 | .version = SPI_VERSION_2, | |
794 | .prescaler_limit = 2, | |
795 | }; | |
796 | ||
797 | static const struct davinci_spi_of_data keystone_spi_data = { | |
798 | .version = SPI_VERSION_1, | |
799 | .prescaler_limit = 0, | |
800 | }; | |
801 | ||
aae7147d MK |
802 | static const struct of_device_id davinci_spi_of_match[] = { |
803 | { | |
804413f2 | 804 | .compatible = "ti,dm6441-spi", |
fa466c91 | 805 | .data = &dm6441_spi_data, |
aae7147d MK |
806 | }, |
807 | { | |
804413f2 | 808 | .compatible = "ti,da830-spi", |
fa466c91 FCJ |
809 | .data = &da830_spi_data, |
810 | }, | |
811 | { | |
812 | .compatible = "ti,keystone-spi", | |
813 | .data = &keystone_spi_data, | |
aae7147d MK |
814 | }, |
815 | { }, | |
816 | }; | |
0d2d0cc5 | 817 | MODULE_DEVICE_TABLE(of, davinci_spi_of_match); |
aae7147d MK |
818 | |
819 | /** | |
820 | * spi_davinci_get_pdata - Get platform data from DTS binding | |
821 | * @pdev: ptr to platform data | |
822 | * @dspi: ptr to driver data | |
823 | * | |
824 | * Parses and populates pdata in dspi from device tree bindings. | |
825 | * | |
826 | * NOTE: Not all platform data params are supported currently. | |
827 | */ | |
828 | static int spi_davinci_get_pdata(struct platform_device *pdev, | |
829 | struct davinci_spi *dspi) | |
830 | { | |
831 | struct device_node *node = pdev->dev.of_node; | |
fa466c91 | 832 | struct davinci_spi_of_data *spi_data; |
aae7147d MK |
833 | struct davinci_spi_platform_data *pdata; |
834 | unsigned int num_cs, intr_line = 0; | |
835 | const struct of_device_id *match; | |
836 | ||
837 | pdata = &dspi->pdata; | |
838 | ||
b53b34f0 | 839 | match = of_match_device(davinci_spi_of_match, &pdev->dev); |
aae7147d MK |
840 | if (!match) |
841 | return -ENODEV; | |
842 | ||
fa466c91 | 843 | spi_data = (struct davinci_spi_of_data *)match->data; |
aae7147d | 844 | |
fa466c91 FCJ |
845 | pdata->version = spi_data->version; |
846 | pdata->prescaler_limit = spi_data->prescaler_limit; | |
aae7147d MK |
847 | /* |
848 | * default num_cs is 1 and all chipsel are internal to the chip | |
a88e34ea MK |
849 | * indicated by chip_sel being NULL or cs_gpios being NULL or |
850 | * set to -ENOENT. num-cs includes internal as well as gpios. | |
aae7147d MK |
851 | * indicated by chip_sel being NULL. GPIO based CS is not |
852 | * supported yet in DT bindings. | |
853 | */ | |
854 | num_cs = 1; | |
855 | of_property_read_u32(node, "num-cs", &num_cs); | |
856 | pdata->num_chipselect = num_cs; | |
857 | of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line); | |
858 | pdata->intr_line = intr_line; | |
859 | return 0; | |
860 | } | |
861 | #else | |
aae7147d MK |
862 | static struct davinci_spi_platform_data |
863 | *spi_davinci_get_pdata(struct platform_device *pdev, | |
864 | struct davinci_spi *dspi) | |
865 | { | |
866 | return -ENODEV; | |
867 | } | |
868 | #endif | |
869 | ||
358934a6 SP |
870 | /** |
871 | * davinci_spi_probe - probe function for SPI Master Controller | |
872 | * @pdev: platform_device structure which contains plateform specific data | |
035540f6 BN |
873 | * |
874 | * According to Linux Device Model this function will be invoked by Linux | |
875 | * with platform_device struct which contains the device specific info. | |
876 | * This function will map the SPI controller's memory, register IRQ, | |
877 | * Reset SPI controller and setting its registers to default value. | |
878 | * It will invoke spi_bitbang_start to create work queue so that client driver | |
879 | * can register transfer method to work queue. | |
358934a6 | 880 | */ |
fd4a319b | 881 | static int davinci_spi_probe(struct platform_device *pdev) |
358934a6 SP |
882 | { |
883 | struct spi_master *master; | |
212d4b69 | 884 | struct davinci_spi *dspi; |
358934a6 | 885 | struct davinci_spi_platform_data *pdata; |
5b3bb596 | 886 | struct resource *r; |
c0600140 | 887 | int ret = 0; |
f34bd4cc | 888 | u32 spipc0; |
358934a6 | 889 | |
358934a6 SP |
890 | master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); |
891 | if (master == NULL) { | |
892 | ret = -ENOMEM; | |
893 | goto err; | |
894 | } | |
895 | ||
24b5a82c | 896 | platform_set_drvdata(pdev, master); |
358934a6 | 897 | |
212d4b69 | 898 | dspi = spi_master_get_devdata(master); |
358934a6 | 899 | |
8074cf06 JH |
900 | if (dev_get_platdata(&pdev->dev)) { |
901 | pdata = dev_get_platdata(&pdev->dev); | |
aae7147d MK |
902 | dspi->pdata = *pdata; |
903 | } else { | |
904 | /* update dspi pdata with that from the DT */ | |
905 | ret = spi_davinci_get_pdata(pdev, dspi); | |
906 | if (ret < 0) | |
907 | goto free_master; | |
908 | } | |
909 | ||
910 | /* pdata in dspi is now updated and point pdata to that */ | |
911 | pdata = &dspi->pdata; | |
912 | ||
7480e755 MK |
913 | dspi->bytes_per_word = devm_kzalloc(&pdev->dev, |
914 | sizeof(*dspi->bytes_per_word) * | |
915 | pdata->num_chipselect, GFP_KERNEL); | |
916 | if (dspi->bytes_per_word == NULL) { | |
917 | ret = -ENOMEM; | |
918 | goto free_master; | |
919 | } | |
920 | ||
358934a6 SP |
921 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
922 | if (r == NULL) { | |
923 | ret = -ENOENT; | |
924 | goto free_master; | |
925 | } | |
926 | ||
212d4b69 | 927 | dspi->pbase = r->start; |
358934a6 | 928 | |
5b3bb596 JH |
929 | dspi->base = devm_ioremap_resource(&pdev->dev, r); |
930 | if (IS_ERR(dspi->base)) { | |
931 | ret = PTR_ERR(dspi->base); | |
358934a6 SP |
932 | goto free_master; |
933 | } | |
934 | ||
8494cdea AH |
935 | ret = platform_get_irq(pdev, 0); |
936 | if (ret == 0) | |
e0d205e9 | 937 | ret = -EINVAL; |
8494cdea | 938 | if (ret < 0) |
5b3bb596 | 939 | goto free_master; |
8494cdea | 940 | dspi->irq = ret; |
e0d205e9 | 941 | |
5b3bb596 JH |
942 | ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq, |
943 | dummy_thread_fn, 0, dev_name(&pdev->dev), dspi); | |
e0d205e9 | 944 | if (ret) |
5b3bb596 | 945 | goto free_master; |
e0d205e9 | 946 | |
94c69f76 | 947 | dspi->bitbang.master = master; |
358934a6 | 948 | |
5b3bb596 | 949 | dspi->clk = devm_clk_get(&pdev->dev, NULL); |
212d4b69 | 950 | if (IS_ERR(dspi->clk)) { |
358934a6 | 951 | ret = -ENODEV; |
5b3bb596 | 952 | goto free_master; |
358934a6 | 953 | } |
aae7147d | 954 | clk_prepare_enable(dspi->clk); |
358934a6 | 955 | |
aae7147d | 956 | master->dev.of_node = pdev->dev.of_node; |
358934a6 SP |
957 | master->bus_num = pdev->id; |
958 | master->num_chipselect = pdata->num_chipselect; | |
24778be2 | 959 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16); |
8aedbf58 | 960 | master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX); |
358934a6 | 961 | master->setup = davinci_spi_setup; |
365a7bb3 | 962 | master->cleanup = davinci_spi_cleanup; |
8aedbf58 | 963 | master->can_dma = davinci_spi_can_dma; |
358934a6 | 964 | |
212d4b69 SN |
965 | dspi->bitbang.chipselect = davinci_spi_chipselect; |
966 | dspi->bitbang.setup_transfer = davinci_spi_setup_transfer; | |
fa466c91 | 967 | dspi->prescaler_limit = pdata->prescaler_limit; |
212d4b69 | 968 | dspi->version = pdata->version; |
358934a6 | 969 | |
212d4b69 SN |
970 | dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; |
971 | if (dspi->version == SPI_VERSION_2) | |
972 | dspi->bitbang.flags |= SPI_READY; | |
358934a6 | 973 | |
8936decd GS |
974 | if (pdev->dev.of_node) { |
975 | int i; | |
976 | ||
977 | for (i = 0; i < pdata->num_chipselect; i++) { | |
978 | int cs_gpio = of_get_named_gpio(pdev->dev.of_node, | |
979 | "cs-gpios", i); | |
980 | ||
981 | if (cs_gpio == -EPROBE_DEFER) { | |
982 | ret = cs_gpio; | |
983 | goto free_clk; | |
984 | } | |
985 | ||
986 | if (gpio_is_valid(cs_gpio)) { | |
987 | ret = devm_gpio_request(&pdev->dev, cs_gpio, | |
988 | dev_name(&pdev->dev)); | |
989 | if (ret) | |
990 | goto free_clk; | |
991 | } | |
992 | } | |
993 | } | |
994 | ||
212d4b69 | 995 | dspi->bitbang.txrx_bufs = davinci_spi_bufs; |
fe5fd254 PU |
996 | |
997 | ret = davinci_spi_request_dma(dspi); | |
998 | if (ret == -EPROBE_DEFER) { | |
999 | goto free_clk; | |
1000 | } else if (ret) { | |
1001 | dev_info(&pdev->dev, "DMA is not supported (%d)\n", ret); | |
1002 | dspi->dma_rx = NULL; | |
1003 | dspi->dma_tx = NULL; | |
358934a6 SP |
1004 | } |
1005 | ||
212d4b69 SN |
1006 | dspi->get_rx = davinci_spi_rx_buf_u8; |
1007 | dspi->get_tx = davinci_spi_tx_buf_u8; | |
358934a6 | 1008 | |
212d4b69 | 1009 | init_completion(&dspi->done); |
e0d205e9 | 1010 | |
358934a6 | 1011 | /* Reset In/OUT SPI module */ |
212d4b69 | 1012 | iowrite32(0, dspi->base + SPIGCR0); |
358934a6 | 1013 | udelay(100); |
212d4b69 | 1014 | iowrite32(1, dspi->base + SPIGCR0); |
358934a6 | 1015 | |
be88471b | 1016 | /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ |
f34bd4cc | 1017 | spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; |
212d4b69 | 1018 | iowrite32(spipc0, dspi->base + SPIPC0); |
f34bd4cc | 1019 | |
e0d205e9 | 1020 | if (pdata->intr_line) |
212d4b69 | 1021 | iowrite32(SPI_INTLVL_1, dspi->base + SPILVL); |
e0d205e9 | 1022 | else |
212d4b69 | 1023 | iowrite32(SPI_INTLVL_0, dspi->base + SPILVL); |
e0d205e9 | 1024 | |
212d4b69 | 1025 | iowrite32(CS_DEFAULT, dspi->base + SPIDEF); |
843a713b | 1026 | |
358934a6 | 1027 | /* master mode default */ |
212d4b69 SN |
1028 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); |
1029 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); | |
1030 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); | |
358934a6 | 1031 | |
212d4b69 | 1032 | ret = spi_bitbang_start(&dspi->bitbang); |
358934a6 | 1033 | if (ret) |
903ca25b | 1034 | goto free_dma; |
358934a6 | 1035 | |
212d4b69 | 1036 | dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base); |
358934a6 | 1037 | |
358934a6 SP |
1038 | return ret; |
1039 | ||
903ca25b | 1040 | free_dma: |
fe5fd254 PU |
1041 | if (dspi->dma_rx) { |
1042 | dma_release_channel(dspi->dma_rx); | |
1043 | dma_release_channel(dspi->dma_tx); | |
1044 | } | |
358934a6 | 1045 | free_clk: |
aae7147d | 1046 | clk_disable_unprepare(dspi->clk); |
358934a6 | 1047 | free_master: |
94c69f76 | 1048 | spi_master_put(master); |
358934a6 SP |
1049 | err: |
1050 | return ret; | |
1051 | } | |
1052 | ||
1053 | /** | |
1054 | * davinci_spi_remove - remove function for SPI Master Controller | |
1055 | * @pdev: platform_device structure which contains plateform specific data | |
1056 | * | |
1057 | * This function will do the reverse action of davinci_spi_probe function | |
1058 | * It will free the IRQ and SPI controller's memory region. | |
1059 | * It will also call spi_bitbang_stop to destroy the work queue which was | |
1060 | * created by spi_bitbang_start. | |
1061 | */ | |
fd4a319b | 1062 | static int davinci_spi_remove(struct platform_device *pdev) |
358934a6 | 1063 | { |
212d4b69 | 1064 | struct davinci_spi *dspi; |
358934a6 SP |
1065 | struct spi_master *master; |
1066 | ||
24b5a82c | 1067 | master = platform_get_drvdata(pdev); |
212d4b69 | 1068 | dspi = spi_master_get_devdata(master); |
358934a6 | 1069 | |
212d4b69 | 1070 | spi_bitbang_stop(&dspi->bitbang); |
358934a6 | 1071 | |
aae7147d | 1072 | clk_disable_unprepare(dspi->clk); |
94c69f76 | 1073 | spi_master_put(master); |
358934a6 | 1074 | |
fe5fd254 PU |
1075 | if (dspi->dma_rx) { |
1076 | dma_release_channel(dspi->dma_rx); | |
1077 | dma_release_channel(dspi->dma_tx); | |
1078 | } | |
1079 | ||
358934a6 SP |
1080 | return 0; |
1081 | } | |
1082 | ||
1083 | static struct platform_driver davinci_spi_driver = { | |
d8c174cd BN |
1084 | .driver = { |
1085 | .name = "spi_davinci", | |
b53b34f0 | 1086 | .of_match_table = of_match_ptr(davinci_spi_of_match), |
d8c174cd | 1087 | }, |
940ab889 | 1088 | .probe = davinci_spi_probe, |
fd4a319b | 1089 | .remove = davinci_spi_remove, |
358934a6 | 1090 | }; |
940ab889 | 1091 | module_platform_driver(davinci_spi_driver); |
358934a6 SP |
1092 | |
1093 | MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); | |
1094 | MODULE_LICENSE("GPL"); |