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358934a6 SP |
1 | /* |
2 | * Copyright (C) 2009 Texas Instruments. | |
43abb11b | 3 | * Copyright (C) 2010 EF Johnson Technologies |
358934a6 SP |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/gpio.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/clk.h> | |
048177ce | 28 | #include <linux/dmaengine.h> |
358934a6 | 29 | #include <linux/dma-mapping.h> |
048177ce | 30 | #include <linux/edma.h> |
aae7147d MK |
31 | #include <linux/of.h> |
32 | #include <linux/of_device.h> | |
a88e34ea | 33 | #include <linux/of_gpio.h> |
358934a6 SP |
34 | #include <linux/spi/spi.h> |
35 | #include <linux/spi/spi_bitbang.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
358934a6 | 37 | |
ec2a0833 | 38 | #include <linux/platform_data/spi-davinci.h> |
358934a6 SP |
39 | |
40 | #define SPI_NO_RESOURCE ((resource_size_t)-1) | |
41 | ||
358934a6 SP |
42 | #define CS_DEFAULT 0xFF |
43 | ||
358934a6 SP |
44 | #define SPIFMT_PHASE_MASK BIT(16) |
45 | #define SPIFMT_POLARITY_MASK BIT(17) | |
46 | #define SPIFMT_DISTIMER_MASK BIT(18) | |
47 | #define SPIFMT_SHIFTDIR_MASK BIT(20) | |
48 | #define SPIFMT_WAITENA_MASK BIT(21) | |
49 | #define SPIFMT_PARITYENA_MASK BIT(22) | |
50 | #define SPIFMT_ODD_PARITY_MASK BIT(23) | |
51 | #define SPIFMT_WDELAY_MASK 0x3f000000u | |
52 | #define SPIFMT_WDELAY_SHIFT 24 | |
7fe0092b | 53 | #define SPIFMT_PRESCALE_SHIFT 8 |
358934a6 | 54 | |
358934a6 SP |
55 | /* SPIPC0 */ |
56 | #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ | |
57 | #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ | |
58 | #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ | |
59 | #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ | |
358934a6 SP |
60 | |
61 | #define SPIINT_MASKALL 0x0101035F | |
e0d205e9 BN |
62 | #define SPIINT_MASKINT 0x0000015F |
63 | #define SPI_INTLVL_1 0x000001FF | |
64 | #define SPI_INTLVL_0 0x00000000 | |
358934a6 | 65 | |
cfbc5d1d BN |
66 | /* SPIDAT1 (upper 16 bit defines) */ |
67 | #define SPIDAT1_CSHOLD_MASK BIT(12) | |
68 | ||
69 | /* SPIGCR1 */ | |
358934a6 SP |
70 | #define SPIGCR1_CLKMOD_MASK BIT(1) |
71 | #define SPIGCR1_MASTER_MASK BIT(0) | |
3f27b57c | 72 | #define SPIGCR1_POWERDOWN_MASK BIT(8) |
358934a6 | 73 | #define SPIGCR1_LOOPBACK_MASK BIT(16) |
8e206f1c | 74 | #define SPIGCR1_SPIENA_MASK BIT(24) |
358934a6 SP |
75 | |
76 | /* SPIBUF */ | |
77 | #define SPIBUF_TXFULL_MASK BIT(29) | |
78 | #define SPIBUF_RXEMPTY_MASK BIT(31) | |
79 | ||
7abbf23c BN |
80 | /* SPIDELAY */ |
81 | #define SPIDELAY_C2TDELAY_SHIFT 24 | |
82 | #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) | |
83 | #define SPIDELAY_T2CDELAY_SHIFT 16 | |
84 | #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) | |
85 | #define SPIDELAY_T2EDELAY_SHIFT 8 | |
86 | #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) | |
87 | #define SPIDELAY_C2EDELAY_SHIFT 0 | |
88 | #define SPIDELAY_C2EDELAY_MASK 0xFF | |
89 | ||
358934a6 SP |
90 | /* Error Masks */ |
91 | #define SPIFLG_DLEN_ERR_MASK BIT(0) | |
92 | #define SPIFLG_TIMEOUT_MASK BIT(1) | |
93 | #define SPIFLG_PARERR_MASK BIT(2) | |
94 | #define SPIFLG_DESYNC_MASK BIT(3) | |
95 | #define SPIFLG_BITERR_MASK BIT(4) | |
96 | #define SPIFLG_OVRRUN_MASK BIT(6) | |
358934a6 | 97 | #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) |
839c996c BN |
98 | #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ |
99 | | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ | |
100 | | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ | |
101 | | SPIFLG_OVRRUN_MASK) | |
8e206f1c | 102 | |
358934a6 | 103 | #define SPIINT_DMA_REQ_EN BIT(16) |
358934a6 | 104 | |
358934a6 SP |
105 | /* SPI Controller registers */ |
106 | #define SPIGCR0 0x00 | |
107 | #define SPIGCR1 0x04 | |
108 | #define SPIINT 0x08 | |
109 | #define SPILVL 0x0c | |
110 | #define SPIFLG 0x10 | |
111 | #define SPIPC0 0x14 | |
358934a6 SP |
112 | #define SPIDAT1 0x3c |
113 | #define SPIBUF 0x40 | |
358934a6 SP |
114 | #define SPIDELAY 0x48 |
115 | #define SPIDEF 0x4c | |
116 | #define SPIFMT0 0x50 | |
358934a6 | 117 | |
358934a6 SP |
118 | /* SPI Controller driver's private data. */ |
119 | struct davinci_spi { | |
120 | struct spi_bitbang bitbang; | |
121 | struct clk *clk; | |
122 | ||
123 | u8 version; | |
124 | resource_size_t pbase; | |
125 | void __iomem *base; | |
e0d205e9 BN |
126 | u32 irq; |
127 | struct completion done; | |
358934a6 SP |
128 | |
129 | const void *tx; | |
130 | void *rx; | |
e0d205e9 BN |
131 | int rcount; |
132 | int wcount; | |
048177ce MP |
133 | |
134 | struct dma_chan *dma_rx; | |
135 | struct dma_chan *dma_tx; | |
136 | int dma_rx_chnum; | |
137 | int dma_tx_chnum; | |
138 | ||
aae7147d | 139 | struct davinci_spi_platform_data pdata; |
358934a6 SP |
140 | |
141 | void (*get_rx)(u32 rx_data, struct davinci_spi *); | |
142 | u32 (*get_tx)(struct davinci_spi *); | |
143 | ||
7480e755 | 144 | u8 *bytes_per_word; |
358934a6 SP |
145 | }; |
146 | ||
53a31b07 BN |
147 | static struct davinci_spi_config davinci_spi_default_cfg; |
148 | ||
212d4b69 | 149 | static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi) |
358934a6 | 150 | { |
212d4b69 SN |
151 | if (dspi->rx) { |
152 | u8 *rx = dspi->rx; | |
53d454a1 | 153 | *rx++ = (u8)data; |
212d4b69 | 154 | dspi->rx = rx; |
53d454a1 | 155 | } |
358934a6 SP |
156 | } |
157 | ||
212d4b69 | 158 | static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi) |
358934a6 | 159 | { |
212d4b69 SN |
160 | if (dspi->rx) { |
161 | u16 *rx = dspi->rx; | |
53d454a1 | 162 | *rx++ = (u16)data; |
212d4b69 | 163 | dspi->rx = rx; |
53d454a1 | 164 | } |
358934a6 SP |
165 | } |
166 | ||
212d4b69 | 167 | static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi) |
358934a6 | 168 | { |
53d454a1 | 169 | u32 data = 0; |
212d4b69 SN |
170 | if (dspi->tx) { |
171 | const u8 *tx = dspi->tx; | |
53d454a1 | 172 | data = *tx++; |
212d4b69 | 173 | dspi->tx = tx; |
53d454a1 | 174 | } |
358934a6 SP |
175 | return data; |
176 | } | |
177 | ||
212d4b69 | 178 | static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi) |
358934a6 | 179 | { |
53d454a1 | 180 | u32 data = 0; |
212d4b69 SN |
181 | if (dspi->tx) { |
182 | const u16 *tx = dspi->tx; | |
53d454a1 | 183 | data = *tx++; |
212d4b69 | 184 | dspi->tx = tx; |
53d454a1 | 185 | } |
358934a6 SP |
186 | return data; |
187 | } | |
188 | ||
189 | static inline void set_io_bits(void __iomem *addr, u32 bits) | |
190 | { | |
191 | u32 v = ioread32(addr); | |
192 | ||
193 | v |= bits; | |
194 | iowrite32(v, addr); | |
195 | } | |
196 | ||
197 | static inline void clear_io_bits(void __iomem *addr, u32 bits) | |
198 | { | |
199 | u32 v = ioread32(addr); | |
200 | ||
201 | v &= ~bits; | |
202 | iowrite32(v, addr); | |
203 | } | |
204 | ||
358934a6 SP |
205 | /* |
206 | * Interface to control the chip select signal | |
207 | */ | |
208 | static void davinci_spi_chipselect(struct spi_device *spi, int value) | |
209 | { | |
212d4b69 | 210 | struct davinci_spi *dspi; |
a88e34ea | 211 | struct device_node *np = spi->dev.of_node; |
358934a6 | 212 | struct davinci_spi_platform_data *pdata; |
a88e34ea | 213 | struct spi_master *master = spi->master; |
7978b8c3 | 214 | u8 chip_sel = spi->chip_select; |
212d4b69 | 215 | u16 spidat1 = CS_DEFAULT; |
23853973 | 216 | bool gpio_chipsel = false; |
a88e34ea | 217 | int gpio; |
358934a6 | 218 | |
212d4b69 | 219 | dspi = spi_master_get_devdata(spi->master); |
aae7147d | 220 | pdata = &dspi->pdata; |
358934a6 | 221 | |
a88e34ea MK |
222 | if (np && master->cs_gpios != NULL && spi->cs_gpio >= 0) { |
223 | /* SPI core parse and update master->cs_gpio */ | |
23853973 | 224 | gpio_chipsel = true; |
a88e34ea MK |
225 | gpio = spi->cs_gpio; |
226 | } else if (pdata->chip_sel && | |
227 | chip_sel < pdata->num_chipselect && | |
228 | pdata->chip_sel[chip_sel] != SPI_INTERN_CS) { | |
229 | /* platform data defines chip_sel */ | |
230 | gpio_chipsel = true; | |
231 | gpio = pdata->chip_sel[chip_sel]; | |
232 | } | |
23853973 | 233 | |
358934a6 SP |
234 | /* |
235 | * Board specific chip select logic decides the polarity and cs | |
236 | * line for the controller | |
237 | */ | |
23853973 BN |
238 | if (gpio_chipsel) { |
239 | if (value == BITBANG_CS_ACTIVE) | |
a88e34ea | 240 | gpio_set_value(gpio, 0); |
23853973 | 241 | else |
a88e34ea | 242 | gpio_set_value(gpio, 1); |
23853973 BN |
243 | } else { |
244 | if (value == BITBANG_CS_ACTIVE) { | |
212d4b69 SN |
245 | spidat1 |= SPIDAT1_CSHOLD_MASK; |
246 | spidat1 &= ~(0x1 << chip_sel); | |
23853973 | 247 | } |
7978b8c3 | 248 | |
212d4b69 | 249 | iowrite16(spidat1, dspi->base + SPIDAT1 + 2); |
23853973 | 250 | } |
358934a6 SP |
251 | } |
252 | ||
7fe0092b BN |
253 | /** |
254 | * davinci_spi_get_prescale - Calculates the correct prescale value | |
255 | * @maxspeed_hz: the maximum rate the SPI clock can run at | |
256 | * | |
257 | * This function calculates the prescale value that generates a clock rate | |
258 | * less than or equal to the specified maximum. | |
259 | * | |
260 | * Returns: calculated prescale - 1 for easy programming into SPI registers | |
261 | * or negative error number if valid prescalar cannot be updated. | |
262 | */ | |
212d4b69 | 263 | static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, |
7fe0092b BN |
264 | u32 max_speed_hz) |
265 | { | |
266 | int ret; | |
267 | ||
212d4b69 | 268 | ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz); |
7fe0092b BN |
269 | |
270 | if (ret < 3 || ret > 256) | |
271 | return -EINVAL; | |
272 | ||
273 | return ret - 1; | |
274 | } | |
275 | ||
358934a6 SP |
276 | /** |
277 | * davinci_spi_setup_transfer - This functions will determine transfer method | |
278 | * @spi: spi device on which data transfer to be done | |
279 | * @t: spi transfer in which transfer info is filled | |
280 | * | |
281 | * This function determines data transfer method (8/16/32 bit transfer). | |
282 | * It will also set the SPI Clock Control register according to | |
283 | * SPI slave device freq. | |
284 | */ | |
285 | static int davinci_spi_setup_transfer(struct spi_device *spi, | |
286 | struct spi_transfer *t) | |
287 | { | |
288 | ||
212d4b69 | 289 | struct davinci_spi *dspi; |
25f33512 | 290 | struct davinci_spi_config *spicfg; |
358934a6 | 291 | u8 bits_per_word = 0; |
32ea3944 SK |
292 | u32 hz = 0, spifmt = 0; |
293 | int prescale; | |
358934a6 | 294 | |
212d4b69 | 295 | dspi = spi_master_get_devdata(spi->master); |
25f33512 BN |
296 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
297 | if (!spicfg) | |
298 | spicfg = &davinci_spi_default_cfg; | |
358934a6 SP |
299 | |
300 | if (t) { | |
301 | bits_per_word = t->bits_per_word; | |
302 | hz = t->speed_hz; | |
303 | } | |
304 | ||
305 | /* if bits_per_word is not set then set it default */ | |
306 | if (!bits_per_word) | |
307 | bits_per_word = spi->bits_per_word; | |
308 | ||
309 | /* | |
310 | * Assign function pointer to appropriate transfer method | |
311 | * 8bit, 16bit or 32bit transfer | |
312 | */ | |
24778be2 | 313 | if (bits_per_word <= 8) { |
212d4b69 SN |
314 | dspi->get_rx = davinci_spi_rx_buf_u8; |
315 | dspi->get_tx = davinci_spi_tx_buf_u8; | |
316 | dspi->bytes_per_word[spi->chip_select] = 1; | |
24778be2 | 317 | } else { |
212d4b69 SN |
318 | dspi->get_rx = davinci_spi_rx_buf_u16; |
319 | dspi->get_tx = davinci_spi_tx_buf_u16; | |
320 | dspi->bytes_per_word[spi->chip_select] = 2; | |
24778be2 | 321 | } |
358934a6 SP |
322 | |
323 | if (!hz) | |
324 | hz = spi->max_speed_hz; | |
325 | ||
25f33512 BN |
326 | /* Set up SPIFMTn register, unique to this chipselect. */ |
327 | ||
212d4b69 | 328 | prescale = davinci_spi_get_prescale(dspi, hz); |
7fe0092b BN |
329 | if (prescale < 0) |
330 | return prescale; | |
331 | ||
25f33512 BN |
332 | spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); |
333 | ||
334 | if (spi->mode & SPI_LSB_FIRST) | |
335 | spifmt |= SPIFMT_SHIFTDIR_MASK; | |
336 | ||
337 | if (spi->mode & SPI_CPOL) | |
338 | spifmt |= SPIFMT_POLARITY_MASK; | |
339 | ||
340 | if (!(spi->mode & SPI_CPHA)) | |
341 | spifmt |= SPIFMT_PHASE_MASK; | |
342 | ||
343 | /* | |
344 | * Version 1 hardware supports two basic SPI modes: | |
345 | * - Standard SPI mode uses 4 pins, with chipselect | |
346 | * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) | |
347 | * (distinct from SPI_3WIRE, with just one data wire; | |
348 | * or similar variants without MOSI or without MISO) | |
349 | * | |
350 | * Version 2 hardware supports an optional handshaking signal, | |
351 | * so it can support two more modes: | |
352 | * - 5 pin SPI variant is standard SPI plus SPI_READY | |
353 | * - 4 pin with enable is (SPI_READY | SPI_NO_CS) | |
354 | */ | |
355 | ||
212d4b69 | 356 | if (dspi->version == SPI_VERSION_2) { |
25f33512 | 357 | |
7abbf23c BN |
358 | u32 delay = 0; |
359 | ||
25f33512 BN |
360 | spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) |
361 | & SPIFMT_WDELAY_MASK); | |
358934a6 | 362 | |
25f33512 BN |
363 | if (spicfg->odd_parity) |
364 | spifmt |= SPIFMT_ODD_PARITY_MASK; | |
365 | ||
366 | if (spicfg->parity_enable) | |
367 | spifmt |= SPIFMT_PARITYENA_MASK; | |
368 | ||
7abbf23c | 369 | if (spicfg->timer_disable) { |
25f33512 | 370 | spifmt |= SPIFMT_DISTIMER_MASK; |
7abbf23c BN |
371 | } else { |
372 | delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) | |
373 | & SPIDELAY_C2TDELAY_MASK; | |
374 | delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) | |
375 | & SPIDELAY_T2CDELAY_MASK; | |
376 | } | |
25f33512 | 377 | |
7abbf23c | 378 | if (spi->mode & SPI_READY) { |
25f33512 | 379 | spifmt |= SPIFMT_WAITENA_MASK; |
7abbf23c BN |
380 | delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) |
381 | & SPIDELAY_T2EDELAY_MASK; | |
382 | delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) | |
383 | & SPIDELAY_C2EDELAY_MASK; | |
384 | } | |
385 | ||
212d4b69 | 386 | iowrite32(delay, dspi->base + SPIDELAY); |
25f33512 BN |
387 | } |
388 | ||
212d4b69 | 389 | iowrite32(spifmt, dspi->base + SPIFMT0); |
358934a6 SP |
390 | |
391 | return 0; | |
392 | } | |
393 | ||
358934a6 SP |
394 | /** |
395 | * davinci_spi_setup - This functions will set default transfer method | |
396 | * @spi: spi device on which data transfer to be done | |
397 | * | |
398 | * This functions sets the default transfer method. | |
399 | */ | |
358934a6 SP |
400 | static int davinci_spi_setup(struct spi_device *spi) |
401 | { | |
b23a5d46 | 402 | int retval = 0; |
212d4b69 | 403 | struct davinci_spi *dspi; |
be88471b | 404 | struct davinci_spi_platform_data *pdata; |
a88e34ea MK |
405 | struct spi_master *master = spi->master; |
406 | struct device_node *np = spi->dev.of_node; | |
407 | bool internal_cs = true; | |
358934a6 | 408 | |
212d4b69 | 409 | dspi = spi_master_get_devdata(spi->master); |
aae7147d | 410 | pdata = &dspi->pdata; |
358934a6 | 411 | |
be88471b | 412 | if (!(spi->mode & SPI_NO_CS)) { |
a88e34ea MK |
413 | if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) { |
414 | unsigned long flags; | |
415 | ||
416 | flags = GPIOF_DIR_OUT; | |
417 | if (spi->mode & SPI_CS_HIGH) | |
418 | flags |= GPIOF_INIT_LOW; | |
419 | else | |
420 | flags |= GPIOF_INIT_HIGH; | |
421 | retval = gpio_request_one(spi->cs_gpio, | |
422 | flags, dev_name(&spi->dev)); | |
423 | if (retval) { | |
424 | dev_err(&spi->dev, | |
425 | "GPIO %d request failed (%d)\n", | |
426 | spi->cs_gpio, retval); | |
427 | return retval; | |
428 | } | |
429 | internal_cs = false; | |
430 | } else if (pdata->chip_sel && | |
431 | spi->chip_select < pdata->num_chipselect && | |
432 | pdata->chip_sel[spi->chip_select] != SPI_INTERN_CS) { | |
433 | internal_cs = false; | |
434 | } | |
be88471b BN |
435 | } |
436 | ||
a88e34ea MK |
437 | if (internal_cs) |
438 | set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); | |
439 | ||
be88471b | 440 | if (spi->mode & SPI_READY) |
212d4b69 | 441 | set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); |
be88471b BN |
442 | |
443 | if (spi->mode & SPI_LOOP) | |
212d4b69 | 444 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); |
be88471b | 445 | else |
212d4b69 | 446 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); |
be88471b | 447 | |
358934a6 SP |
448 | return retval; |
449 | } | |
450 | ||
a88e34ea MK |
451 | static void davinci_spi_cleanup(struct spi_device *spi) |
452 | { | |
453 | struct spi_master *master = spi->master; | |
454 | struct device_node *np = spi->dev.of_node; | |
455 | ||
456 | if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) | |
457 | gpio_free(spi->cs_gpio); | |
458 | } | |
459 | ||
212d4b69 | 460 | static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) |
358934a6 | 461 | { |
212d4b69 | 462 | struct device *sdev = dspi->bitbang.master->dev.parent; |
358934a6 SP |
463 | |
464 | if (int_status & SPIFLG_TIMEOUT_MASK) { | |
465 | dev_dbg(sdev, "SPI Time-out Error\n"); | |
466 | return -ETIMEDOUT; | |
467 | } | |
468 | if (int_status & SPIFLG_DESYNC_MASK) { | |
469 | dev_dbg(sdev, "SPI Desynchronization Error\n"); | |
470 | return -EIO; | |
471 | } | |
472 | if (int_status & SPIFLG_BITERR_MASK) { | |
473 | dev_dbg(sdev, "SPI Bit error\n"); | |
474 | return -EIO; | |
475 | } | |
476 | ||
212d4b69 | 477 | if (dspi->version == SPI_VERSION_2) { |
358934a6 SP |
478 | if (int_status & SPIFLG_DLEN_ERR_MASK) { |
479 | dev_dbg(sdev, "SPI Data Length Error\n"); | |
480 | return -EIO; | |
481 | } | |
482 | if (int_status & SPIFLG_PARERR_MASK) { | |
483 | dev_dbg(sdev, "SPI Parity Error\n"); | |
484 | return -EIO; | |
485 | } | |
486 | if (int_status & SPIFLG_OVRRUN_MASK) { | |
487 | dev_dbg(sdev, "SPI Data Overrun error\n"); | |
488 | return -EIO; | |
489 | } | |
358934a6 SP |
490 | if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { |
491 | dev_dbg(sdev, "SPI Buffer Init Active\n"); | |
492 | return -EBUSY; | |
493 | } | |
494 | } | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
e0d205e9 BN |
499 | /** |
500 | * davinci_spi_process_events - check for and handle any SPI controller events | |
212d4b69 | 501 | * @dspi: the controller data |
e0d205e9 BN |
502 | * |
503 | * This function will check the SPIFLG register and handle any events that are | |
504 | * detected there | |
505 | */ | |
212d4b69 | 506 | static int davinci_spi_process_events(struct davinci_spi *dspi) |
e0d205e9 | 507 | { |
212d4b69 | 508 | u32 buf, status, errors = 0, spidat1; |
e0d205e9 | 509 | |
212d4b69 | 510 | buf = ioread32(dspi->base + SPIBUF); |
e0d205e9 | 511 | |
212d4b69 SN |
512 | if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { |
513 | dspi->get_rx(buf & 0xFFFF, dspi); | |
514 | dspi->rcount--; | |
e0d205e9 BN |
515 | } |
516 | ||
212d4b69 | 517 | status = ioread32(dspi->base + SPIFLG); |
e0d205e9 BN |
518 | |
519 | if (unlikely(status & SPIFLG_ERROR_MASK)) { | |
520 | errors = status & SPIFLG_ERROR_MASK; | |
521 | goto out; | |
522 | } | |
523 | ||
212d4b69 SN |
524 | if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { |
525 | spidat1 = ioread32(dspi->base + SPIDAT1); | |
526 | dspi->wcount--; | |
527 | spidat1 &= ~0xFFFF; | |
528 | spidat1 |= 0xFFFF & dspi->get_tx(dspi); | |
529 | iowrite32(spidat1, dspi->base + SPIDAT1); | |
e0d205e9 BN |
530 | } |
531 | ||
532 | out: | |
533 | return errors; | |
534 | } | |
535 | ||
048177ce | 536 | static void davinci_spi_dma_rx_callback(void *data) |
87467bd9 | 537 | { |
048177ce | 538 | struct davinci_spi *dspi = (struct davinci_spi *)data; |
87467bd9 | 539 | |
048177ce | 540 | dspi->rcount = 0; |
87467bd9 | 541 | |
048177ce MP |
542 | if (!dspi->wcount && !dspi->rcount) |
543 | complete(&dspi->done); | |
544 | } | |
87467bd9 | 545 | |
048177ce MP |
546 | static void davinci_spi_dma_tx_callback(void *data) |
547 | { | |
548 | struct davinci_spi *dspi = (struct davinci_spi *)data; | |
549 | ||
550 | dspi->wcount = 0; | |
551 | ||
552 | if (!dspi->wcount && !dspi->rcount) | |
212d4b69 | 553 | complete(&dspi->done); |
87467bd9 BN |
554 | } |
555 | ||
358934a6 SP |
556 | /** |
557 | * davinci_spi_bufs - functions which will handle transfer data | |
558 | * @spi: spi device on which data transfer to be done | |
559 | * @t: spi transfer in which transfer info is filled | |
560 | * | |
561 | * This function will put data to be transferred into data register | |
562 | * of SPI controller and then wait until the completion will be marked | |
563 | * by the IRQ Handler. | |
564 | */ | |
87467bd9 | 565 | static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) |
358934a6 | 566 | { |
212d4b69 | 567 | struct davinci_spi *dspi; |
048177ce | 568 | int data_type, ret = -ENOMEM; |
212d4b69 | 569 | u32 tx_data, spidat1; |
839c996c | 570 | u32 errors = 0; |
e0d205e9 | 571 | struct davinci_spi_config *spicfg; |
358934a6 | 572 | struct davinci_spi_platform_data *pdata; |
87467bd9 | 573 | unsigned uninitialized_var(rx_buf_count); |
048177ce MP |
574 | void *dummy_buf = NULL; |
575 | struct scatterlist sg_rx, sg_tx; | |
358934a6 | 576 | |
212d4b69 | 577 | dspi = spi_master_get_devdata(spi->master); |
aae7147d | 578 | pdata = &dspi->pdata; |
e0d205e9 BN |
579 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
580 | if (!spicfg) | |
581 | spicfg = &davinci_spi_default_cfg; | |
87467bd9 BN |
582 | |
583 | /* convert len to words based on bits_per_word */ | |
212d4b69 | 584 | data_type = dspi->bytes_per_word[spi->chip_select]; |
358934a6 | 585 | |
212d4b69 SN |
586 | dspi->tx = t->tx_buf; |
587 | dspi->rx = t->rx_buf; | |
588 | dspi->wcount = t->len / data_type; | |
589 | dspi->rcount = dspi->wcount; | |
7978b8c3 | 590 | |
212d4b69 | 591 | spidat1 = ioread32(dspi->base + SPIDAT1); |
839c996c | 592 | |
212d4b69 SN |
593 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); |
594 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | |
358934a6 | 595 | |
16735d02 | 596 | reinit_completion(&dspi->done); |
87467bd9 BN |
597 | |
598 | if (spicfg->io_type == SPI_IO_TYPE_INTR) | |
212d4b69 | 599 | set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); |
cf90fe73 | 600 | |
87467bd9 BN |
601 | if (spicfg->io_type != SPI_IO_TYPE_DMA) { |
602 | /* start the transfer */ | |
212d4b69 SN |
603 | dspi->wcount--; |
604 | tx_data = dspi->get_tx(dspi); | |
605 | spidat1 &= 0xFFFF0000; | |
606 | spidat1 |= tx_data & 0xFFFF; | |
607 | iowrite32(spidat1, dspi->base + SPIDAT1); | |
87467bd9 | 608 | } else { |
048177ce MP |
609 | struct dma_slave_config dma_rx_conf = { |
610 | .direction = DMA_DEV_TO_MEM, | |
611 | .src_addr = (unsigned long)dspi->pbase + SPIBUF, | |
612 | .src_addr_width = data_type, | |
613 | .src_maxburst = 1, | |
614 | }; | |
615 | struct dma_slave_config dma_tx_conf = { | |
616 | .direction = DMA_MEM_TO_DEV, | |
617 | .dst_addr = (unsigned long)dspi->pbase + SPIDAT1, | |
618 | .dst_addr_width = data_type, | |
619 | .dst_maxburst = 1, | |
620 | }; | |
621 | struct dma_async_tx_descriptor *rxdesc; | |
622 | struct dma_async_tx_descriptor *txdesc; | |
623 | void *buf; | |
624 | ||
625 | dummy_buf = kzalloc(t->len, GFP_KERNEL); | |
626 | if (!dummy_buf) | |
627 | goto err_alloc_dummy_buf; | |
628 | ||
629 | dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf); | |
630 | dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf); | |
631 | ||
632 | sg_init_table(&sg_rx, 1); | |
633 | if (!t->rx_buf) | |
634 | buf = dummy_buf; | |
b1178b21 | 635 | else |
048177ce MP |
636 | buf = t->rx_buf; |
637 | t->rx_dma = dma_map_single(&spi->dev, buf, | |
638 | t->len, DMA_FROM_DEVICE); | |
639 | if (!t->rx_dma) { | |
640 | ret = -EFAULT; | |
641 | goto err_rx_map; | |
87467bd9 | 642 | } |
048177ce MP |
643 | sg_dma_address(&sg_rx) = t->rx_dma; |
644 | sg_dma_len(&sg_rx) = t->len; | |
87467bd9 | 645 | |
048177ce MP |
646 | sg_init_table(&sg_tx, 1); |
647 | if (!t->tx_buf) | |
648 | buf = dummy_buf; | |
649 | else | |
650 | buf = (void *)t->tx_buf; | |
651 | t->tx_dma = dma_map_single(&spi->dev, buf, | |
89c66ee8 | 652 | t->len, DMA_TO_DEVICE); |
048177ce MP |
653 | if (!t->tx_dma) { |
654 | ret = -EFAULT; | |
655 | goto err_tx_map; | |
87467bd9 | 656 | } |
048177ce MP |
657 | sg_dma_address(&sg_tx) = t->tx_dma; |
658 | sg_dma_len(&sg_tx) = t->len; | |
659 | ||
660 | rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx, | |
661 | &sg_rx, 1, DMA_DEV_TO_MEM, | |
662 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
663 | if (!rxdesc) | |
664 | goto err_desc; | |
665 | ||
666 | txdesc = dmaengine_prep_slave_sg(dspi->dma_tx, | |
667 | &sg_tx, 1, DMA_MEM_TO_DEV, | |
668 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
669 | if (!txdesc) | |
670 | goto err_desc; | |
671 | ||
672 | rxdesc->callback = davinci_spi_dma_rx_callback; | |
673 | rxdesc->callback_param = (void *)dspi; | |
674 | txdesc->callback = davinci_spi_dma_tx_callback; | |
675 | txdesc->callback_param = (void *)dspi; | |
87467bd9 BN |
676 | |
677 | if (pdata->cshold_bug) | |
212d4b69 | 678 | iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2); |
87467bd9 | 679 | |
048177ce MP |
680 | dmaengine_submit(rxdesc); |
681 | dmaengine_submit(txdesc); | |
682 | ||
683 | dma_async_issue_pending(dspi->dma_rx); | |
684 | dma_async_issue_pending(dspi->dma_tx); | |
685 | ||
212d4b69 | 686 | set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); |
87467bd9 | 687 | } |
358934a6 | 688 | |
e0d205e9 | 689 | /* Wait for the transfer to complete */ |
87467bd9 | 690 | if (spicfg->io_type != SPI_IO_TYPE_POLL) { |
212d4b69 | 691 | wait_for_completion_interruptible(&(dspi->done)); |
e0d205e9 | 692 | } else { |
212d4b69 SN |
693 | while (dspi->rcount > 0 || dspi->wcount > 0) { |
694 | errors = davinci_spi_process_events(dspi); | |
e0d205e9 BN |
695 | if (errors) |
696 | break; | |
697 | cpu_relax(); | |
358934a6 SP |
698 | } |
699 | } | |
700 | ||
212d4b69 | 701 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); |
87467bd9 | 702 | if (spicfg->io_type == SPI_IO_TYPE_DMA) { |
212d4b69 | 703 | clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); |
048177ce MP |
704 | |
705 | dma_unmap_single(&spi->dev, t->rx_dma, | |
706 | t->len, DMA_FROM_DEVICE); | |
707 | dma_unmap_single(&spi->dev, t->tx_dma, | |
708 | t->len, DMA_TO_DEVICE); | |
709 | kfree(dummy_buf); | |
87467bd9 | 710 | } |
e0d205e9 | 711 | |
212d4b69 SN |
712 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); |
713 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); | |
3f27b57c | 714 | |
358934a6 SP |
715 | /* |
716 | * Check for bit error, desync error,parity error,timeout error and | |
717 | * receive overflow errors | |
718 | */ | |
839c996c | 719 | if (errors) { |
212d4b69 | 720 | ret = davinci_spi_check_error(dspi, errors); |
839c996c BN |
721 | WARN(!ret, "%s: error reported but no error found!\n", |
722 | dev_name(&spi->dev)); | |
358934a6 | 723 | return ret; |
839c996c | 724 | } |
358934a6 | 725 | |
212d4b69 | 726 | if (dspi->rcount != 0 || dspi->wcount != 0) { |
048177ce | 727 | dev_err(&spi->dev, "SPI data transfer error\n"); |
87467bd9 BN |
728 | return -EIO; |
729 | } | |
730 | ||
358934a6 | 731 | return t->len; |
048177ce MP |
732 | |
733 | err_desc: | |
734 | dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE); | |
735 | err_tx_map: | |
736 | dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE); | |
737 | err_rx_map: | |
738 | kfree(dummy_buf); | |
739 | err_alloc_dummy_buf: | |
740 | return ret; | |
358934a6 SP |
741 | } |
742 | ||
32310aaf MK |
743 | /** |
744 | * dummy_thread_fn - dummy thread function | |
745 | * @irq: IRQ number for this SPI Master | |
746 | * @context_data: structure for SPI Master controller davinci_spi | |
747 | * | |
748 | * This is to satisfy the request_threaded_irq() API so that the irq | |
749 | * handler is called in interrupt context. | |
750 | */ | |
751 | static irqreturn_t dummy_thread_fn(s32 irq, void *data) | |
752 | { | |
753 | return IRQ_HANDLED; | |
754 | } | |
755 | ||
e0d205e9 BN |
756 | /** |
757 | * davinci_spi_irq - Interrupt handler for SPI Master Controller | |
758 | * @irq: IRQ number for this SPI Master | |
759 | * @context_data: structure for SPI Master controller davinci_spi | |
760 | * | |
761 | * ISR will determine that interrupt arrives either for READ or WRITE command. | |
762 | * According to command it will do the appropriate action. It will check | |
763 | * transfer length and if it is not zero then dispatch transfer command again. | |
764 | * If transfer length is zero then it will indicate the COMPLETION so that | |
765 | * davinci_spi_bufs function can go ahead. | |
766 | */ | |
212d4b69 | 767 | static irqreturn_t davinci_spi_irq(s32 irq, void *data) |
e0d205e9 | 768 | { |
212d4b69 | 769 | struct davinci_spi *dspi = data; |
e0d205e9 BN |
770 | int status; |
771 | ||
212d4b69 | 772 | status = davinci_spi_process_events(dspi); |
e0d205e9 | 773 | if (unlikely(status != 0)) |
212d4b69 | 774 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); |
e0d205e9 | 775 | |
212d4b69 SN |
776 | if ((!dspi->rcount && !dspi->wcount) || status) |
777 | complete(&dspi->done); | |
e0d205e9 BN |
778 | |
779 | return IRQ_HANDLED; | |
780 | } | |
781 | ||
212d4b69 | 782 | static int davinci_spi_request_dma(struct davinci_spi *dspi) |
903ca25b | 783 | { |
048177ce MP |
784 | dma_cap_mask_t mask; |
785 | struct device *sdev = dspi->bitbang.master->dev.parent; | |
903ca25b SN |
786 | int r; |
787 | ||
048177ce MP |
788 | dma_cap_zero(mask); |
789 | dma_cap_set(DMA_SLAVE, mask); | |
790 | ||
791 | dspi->dma_rx = dma_request_channel(mask, edma_filter_fn, | |
792 | &dspi->dma_rx_chnum); | |
793 | if (!dspi->dma_rx) { | |
794 | dev_err(sdev, "request RX DMA channel failed\n"); | |
795 | r = -ENODEV; | |
523c37e7 | 796 | goto rx_dma_failed; |
903ca25b SN |
797 | } |
798 | ||
048177ce MP |
799 | dspi->dma_tx = dma_request_channel(mask, edma_filter_fn, |
800 | &dspi->dma_tx_chnum); | |
801 | if (!dspi->dma_tx) { | |
802 | dev_err(sdev, "request TX DMA channel failed\n"); | |
803 | r = -ENODEV; | |
523c37e7 | 804 | goto tx_dma_failed; |
903ca25b SN |
805 | } |
806 | ||
807 | return 0; | |
048177ce | 808 | |
523c37e7 | 809 | tx_dma_failed: |
048177ce | 810 | dma_release_channel(dspi->dma_rx); |
523c37e7 BN |
811 | rx_dma_failed: |
812 | return r; | |
903ca25b SN |
813 | } |
814 | ||
aae7147d MK |
815 | #if defined(CONFIG_OF) |
816 | static const struct of_device_id davinci_spi_of_match[] = { | |
817 | { | |
804413f2 | 818 | .compatible = "ti,dm6441-spi", |
aae7147d MK |
819 | }, |
820 | { | |
804413f2 | 821 | .compatible = "ti,da830-spi", |
aae7147d MK |
822 | .data = (void *)SPI_VERSION_2, |
823 | }, | |
824 | { }, | |
825 | }; | |
0d2d0cc5 | 826 | MODULE_DEVICE_TABLE(of, davinci_spi_of_match); |
aae7147d MK |
827 | |
828 | /** | |
829 | * spi_davinci_get_pdata - Get platform data from DTS binding | |
830 | * @pdev: ptr to platform data | |
831 | * @dspi: ptr to driver data | |
832 | * | |
833 | * Parses and populates pdata in dspi from device tree bindings. | |
834 | * | |
835 | * NOTE: Not all platform data params are supported currently. | |
836 | */ | |
837 | static int spi_davinci_get_pdata(struct platform_device *pdev, | |
838 | struct davinci_spi *dspi) | |
839 | { | |
840 | struct device_node *node = pdev->dev.of_node; | |
841 | struct davinci_spi_platform_data *pdata; | |
842 | unsigned int num_cs, intr_line = 0; | |
843 | const struct of_device_id *match; | |
844 | ||
845 | pdata = &dspi->pdata; | |
846 | ||
847 | pdata->version = SPI_VERSION_1; | |
b53b34f0 | 848 | match = of_match_device(davinci_spi_of_match, &pdev->dev); |
aae7147d MK |
849 | if (!match) |
850 | return -ENODEV; | |
851 | ||
852 | /* match data has the SPI version number for SPI_VERSION_2 */ | |
853 | if (match->data == (void *)SPI_VERSION_2) | |
854 | pdata->version = SPI_VERSION_2; | |
855 | ||
856 | /* | |
857 | * default num_cs is 1 and all chipsel are internal to the chip | |
a88e34ea MK |
858 | * indicated by chip_sel being NULL or cs_gpios being NULL or |
859 | * set to -ENOENT. num-cs includes internal as well as gpios. | |
aae7147d MK |
860 | * indicated by chip_sel being NULL. GPIO based CS is not |
861 | * supported yet in DT bindings. | |
862 | */ | |
863 | num_cs = 1; | |
864 | of_property_read_u32(node, "num-cs", &num_cs); | |
865 | pdata->num_chipselect = num_cs; | |
866 | of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line); | |
867 | pdata->intr_line = intr_line; | |
868 | return 0; | |
869 | } | |
870 | #else | |
aae7147d MK |
871 | static struct davinci_spi_platform_data |
872 | *spi_davinci_get_pdata(struct platform_device *pdev, | |
873 | struct davinci_spi *dspi) | |
874 | { | |
875 | return -ENODEV; | |
876 | } | |
877 | #endif | |
878 | ||
358934a6 SP |
879 | /** |
880 | * davinci_spi_probe - probe function for SPI Master Controller | |
881 | * @pdev: platform_device structure which contains plateform specific data | |
035540f6 BN |
882 | * |
883 | * According to Linux Device Model this function will be invoked by Linux | |
884 | * with platform_device struct which contains the device specific info. | |
885 | * This function will map the SPI controller's memory, register IRQ, | |
886 | * Reset SPI controller and setting its registers to default value. | |
887 | * It will invoke spi_bitbang_start to create work queue so that client driver | |
888 | * can register transfer method to work queue. | |
358934a6 | 889 | */ |
fd4a319b | 890 | static int davinci_spi_probe(struct platform_device *pdev) |
358934a6 SP |
891 | { |
892 | struct spi_master *master; | |
212d4b69 | 893 | struct davinci_spi *dspi; |
358934a6 | 894 | struct davinci_spi_platform_data *pdata; |
5b3bb596 | 895 | struct resource *r; |
358934a6 SP |
896 | resource_size_t dma_rx_chan = SPI_NO_RESOURCE; |
897 | resource_size_t dma_tx_chan = SPI_NO_RESOURCE; | |
358934a6 | 898 | int i = 0, ret = 0; |
f34bd4cc | 899 | u32 spipc0; |
358934a6 | 900 | |
358934a6 SP |
901 | master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); |
902 | if (master == NULL) { | |
903 | ret = -ENOMEM; | |
904 | goto err; | |
905 | } | |
906 | ||
24b5a82c | 907 | platform_set_drvdata(pdev, master); |
358934a6 | 908 | |
212d4b69 | 909 | dspi = spi_master_get_devdata(master); |
358934a6 | 910 | |
8074cf06 JH |
911 | if (dev_get_platdata(&pdev->dev)) { |
912 | pdata = dev_get_platdata(&pdev->dev); | |
aae7147d MK |
913 | dspi->pdata = *pdata; |
914 | } else { | |
915 | /* update dspi pdata with that from the DT */ | |
916 | ret = spi_davinci_get_pdata(pdev, dspi); | |
917 | if (ret < 0) | |
918 | goto free_master; | |
919 | } | |
920 | ||
921 | /* pdata in dspi is now updated and point pdata to that */ | |
922 | pdata = &dspi->pdata; | |
923 | ||
7480e755 MK |
924 | dspi->bytes_per_word = devm_kzalloc(&pdev->dev, |
925 | sizeof(*dspi->bytes_per_word) * | |
926 | pdata->num_chipselect, GFP_KERNEL); | |
927 | if (dspi->bytes_per_word == NULL) { | |
928 | ret = -ENOMEM; | |
929 | goto free_master; | |
930 | } | |
931 | ||
358934a6 SP |
932 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
933 | if (r == NULL) { | |
934 | ret = -ENOENT; | |
935 | goto free_master; | |
936 | } | |
937 | ||
212d4b69 | 938 | dspi->pbase = r->start; |
358934a6 | 939 | |
5b3bb596 JH |
940 | dspi->base = devm_ioremap_resource(&pdev->dev, r); |
941 | if (IS_ERR(dspi->base)) { | |
942 | ret = PTR_ERR(dspi->base); | |
358934a6 SP |
943 | goto free_master; |
944 | } | |
945 | ||
212d4b69 SN |
946 | dspi->irq = platform_get_irq(pdev, 0); |
947 | if (dspi->irq <= 0) { | |
e0d205e9 | 948 | ret = -EINVAL; |
5b3bb596 | 949 | goto free_master; |
e0d205e9 BN |
950 | } |
951 | ||
5b3bb596 JH |
952 | ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq, |
953 | dummy_thread_fn, 0, dev_name(&pdev->dev), dspi); | |
e0d205e9 | 954 | if (ret) |
5b3bb596 | 955 | goto free_master; |
e0d205e9 | 956 | |
94c69f76 | 957 | dspi->bitbang.master = master; |
358934a6 | 958 | |
5b3bb596 | 959 | dspi->clk = devm_clk_get(&pdev->dev, NULL); |
212d4b69 | 960 | if (IS_ERR(dspi->clk)) { |
358934a6 | 961 | ret = -ENODEV; |
5b3bb596 | 962 | goto free_master; |
358934a6 | 963 | } |
aae7147d | 964 | clk_prepare_enable(dspi->clk); |
358934a6 | 965 | |
aae7147d | 966 | master->dev.of_node = pdev->dev.of_node; |
358934a6 SP |
967 | master->bus_num = pdev->id; |
968 | master->num_chipselect = pdata->num_chipselect; | |
24778be2 | 969 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16); |
358934a6 | 970 | master->setup = davinci_spi_setup; |
a88e34ea | 971 | master->cleanup = davinci_spi_cleanup; |
358934a6 | 972 | |
212d4b69 SN |
973 | dspi->bitbang.chipselect = davinci_spi_chipselect; |
974 | dspi->bitbang.setup_transfer = davinci_spi_setup_transfer; | |
358934a6 | 975 | |
212d4b69 | 976 | dspi->version = pdata->version; |
358934a6 | 977 | |
212d4b69 SN |
978 | dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; |
979 | if (dspi->version == SPI_VERSION_2) | |
980 | dspi->bitbang.flags |= SPI_READY; | |
358934a6 | 981 | |
903ca25b SN |
982 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
983 | if (r) | |
984 | dma_rx_chan = r->start; | |
985 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
986 | if (r) | |
987 | dma_tx_chan = r->start; | |
903ca25b | 988 | |
212d4b69 | 989 | dspi->bitbang.txrx_bufs = davinci_spi_bufs; |
903ca25b | 990 | if (dma_rx_chan != SPI_NO_RESOURCE && |
2e3e2a5e | 991 | dma_tx_chan != SPI_NO_RESOURCE) { |
048177ce MP |
992 | dspi->dma_rx_chnum = dma_rx_chan; |
993 | dspi->dma_tx_chnum = dma_tx_chan; | |
96fd881f | 994 | |
212d4b69 | 995 | ret = davinci_spi_request_dma(dspi); |
903ca25b SN |
996 | if (ret) |
997 | goto free_clk; | |
998 | ||
87467bd9 | 999 | dev_info(&pdev->dev, "DMA: supported\n"); |
a4ee96e4 SS |
1000 | dev_info(&pdev->dev, "DMA: RX channel: %pa, TX channel: %pa, " |
1001 | "event queue: %d\n", &dma_rx_chan, &dma_tx_chan, | |
2e3e2a5e | 1002 | pdata->dma_event_q); |
358934a6 SP |
1003 | } |
1004 | ||
212d4b69 SN |
1005 | dspi->get_rx = davinci_spi_rx_buf_u8; |
1006 | dspi->get_tx = davinci_spi_tx_buf_u8; | |
358934a6 | 1007 | |
212d4b69 | 1008 | init_completion(&dspi->done); |
e0d205e9 | 1009 | |
358934a6 | 1010 | /* Reset In/OUT SPI module */ |
212d4b69 | 1011 | iowrite32(0, dspi->base + SPIGCR0); |
358934a6 | 1012 | udelay(100); |
212d4b69 | 1013 | iowrite32(1, dspi->base + SPIGCR0); |
358934a6 | 1014 | |
be88471b | 1015 | /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ |
f34bd4cc | 1016 | spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; |
212d4b69 | 1017 | iowrite32(spipc0, dspi->base + SPIPC0); |
f34bd4cc | 1018 | |
23853973 BN |
1019 | /* initialize chip selects */ |
1020 | if (pdata->chip_sel) { | |
1021 | for (i = 0; i < pdata->num_chipselect; i++) { | |
1022 | if (pdata->chip_sel[i] != SPI_INTERN_CS) | |
1023 | gpio_direction_output(pdata->chip_sel[i], 1); | |
1024 | } | |
1025 | } | |
1026 | ||
e0d205e9 | 1027 | if (pdata->intr_line) |
212d4b69 | 1028 | iowrite32(SPI_INTLVL_1, dspi->base + SPILVL); |
e0d205e9 | 1029 | else |
212d4b69 | 1030 | iowrite32(SPI_INTLVL_0, dspi->base + SPILVL); |
e0d205e9 | 1031 | |
212d4b69 | 1032 | iowrite32(CS_DEFAULT, dspi->base + SPIDEF); |
843a713b | 1033 | |
358934a6 | 1034 | /* master mode default */ |
212d4b69 SN |
1035 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); |
1036 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); | |
1037 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); | |
358934a6 | 1038 | |
212d4b69 | 1039 | ret = spi_bitbang_start(&dspi->bitbang); |
358934a6 | 1040 | if (ret) |
903ca25b | 1041 | goto free_dma; |
358934a6 | 1042 | |
212d4b69 | 1043 | dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base); |
358934a6 | 1044 | |
358934a6 SP |
1045 | return ret; |
1046 | ||
903ca25b | 1047 | free_dma: |
048177ce MP |
1048 | dma_release_channel(dspi->dma_rx); |
1049 | dma_release_channel(dspi->dma_tx); | |
358934a6 | 1050 | free_clk: |
aae7147d | 1051 | clk_disable_unprepare(dspi->clk); |
358934a6 | 1052 | free_master: |
94c69f76 | 1053 | spi_master_put(master); |
358934a6 SP |
1054 | err: |
1055 | return ret; | |
1056 | } | |
1057 | ||
1058 | /** | |
1059 | * davinci_spi_remove - remove function for SPI Master Controller | |
1060 | * @pdev: platform_device structure which contains plateform specific data | |
1061 | * | |
1062 | * This function will do the reverse action of davinci_spi_probe function | |
1063 | * It will free the IRQ and SPI controller's memory region. | |
1064 | * It will also call spi_bitbang_stop to destroy the work queue which was | |
1065 | * created by spi_bitbang_start. | |
1066 | */ | |
fd4a319b | 1067 | static int davinci_spi_remove(struct platform_device *pdev) |
358934a6 | 1068 | { |
212d4b69 | 1069 | struct davinci_spi *dspi; |
358934a6 SP |
1070 | struct spi_master *master; |
1071 | ||
24b5a82c | 1072 | master = platform_get_drvdata(pdev); |
212d4b69 | 1073 | dspi = spi_master_get_devdata(master); |
358934a6 | 1074 | |
212d4b69 | 1075 | spi_bitbang_stop(&dspi->bitbang); |
358934a6 | 1076 | |
aae7147d | 1077 | clk_disable_unprepare(dspi->clk); |
94c69f76 | 1078 | spi_master_put(master); |
358934a6 SP |
1079 | |
1080 | return 0; | |
1081 | } | |
1082 | ||
1083 | static struct platform_driver davinci_spi_driver = { | |
d8c174cd BN |
1084 | .driver = { |
1085 | .name = "spi_davinci", | |
1086 | .owner = THIS_MODULE, | |
b53b34f0 | 1087 | .of_match_table = of_match_ptr(davinci_spi_of_match), |
d8c174cd | 1088 | }, |
940ab889 | 1089 | .probe = davinci_spi_probe, |
fd4a319b | 1090 | .remove = davinci_spi_remove, |
358934a6 | 1091 | }; |
940ab889 | 1092 | module_platform_driver(davinci_spi_driver); |
358934a6 SP |
1093 | |
1094 | MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); | |
1095 | MODULE_LICENSE("GPL"); |