[mirror_ubuntu-bionic-kernel.git] / drivers / spi / spi-dw-mid.c

/*
 * Special handling for DW core on Intel MID platform
 *
 * Copyright (c) 2009, 2014 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/types.h>

#include "spi-dw.h"

#ifdef CONFIG_SPI_DW_MID_DMA
#include <linux/pci.h>
#include <linux/platform_data/dma-dw.h>

#define RX_BUSY		0
#define TX_BUSY		1

static struct dw_dma_slave mid_dma_tx = { .dst_id = 1 };
static struct dw_dma_slave mid_dma_rx = { .src_id = 0 };

static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
{
	struct dw_dma_slave *s = param;

	if (s->dma_dev != chan->device->dev)
		return false;

	chan->private = s;
	return true;
}

static int mid_spi_dma_init(struct dw_spi *dws)
{
	struct pci_dev *dma_dev;
	struct dw_dma_slave *tx = dws->dma_tx;
	struct dw_dma_slave *rx = dws->dma_rx;
	dma_cap_mask_t mask;

	/*
	 * Get pci device for DMA controller, currently it could only
	 * be the DMA controller of Medfield
	 */
	dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
	if (!dma_dev)
		return -ENODEV;

	dma_cap_zero(mask);
	dma_cap_set(DMA_SLAVE, mask);

	/* 1. Init rx channel */
	rx->dma_dev = &dma_dev->dev;
	dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, rx);
	if (!dws->rxchan)
		goto err_exit;
	dws->master->dma_rx = dws->rxchan;

	/* 2. Init tx channel */
	tx->dma_dev = &dma_dev->dev;
	dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, tx);
	if (!dws->txchan)
		goto free_rxchan;
	dws->master->dma_tx = dws->txchan;

	dws->dma_inited = 1;
	return 0;

free_rxchan:
	dma_release_channel(dws->rxchan);
err_exit:
	return -EBUSY;
}

static void mid_spi_dma_exit(struct dw_spi *dws)
{
	if (!dws->dma_inited)
		return;

	dmaengine_terminate_sync(dws->txchan);
	dma_release_channel(dws->txchan);

	dmaengine_terminate_sync(dws->rxchan);
	dma_release_channel(dws->rxchan);
}

static irqreturn_t dma_transfer(struct dw_spi *dws)
{
	u16 irq_status = dw_readl(dws, DW_SPI_ISR);

	if (!irq_status)
		return IRQ_NONE;

	dw_readl(dws, DW_SPI_ICR);
	spi_reset_chip(dws);

	dev_err(&dws->master->dev, "%s: FIFO overrun/underrun\n", __func__);
	dws->master->cur_msg->status = -EIO;
	spi_finalize_current_transfer(dws->master);
	return IRQ_HANDLED;
}

static bool mid_spi_can_dma(struct spi_master *master, struct spi_device *spi,
		struct spi_transfer *xfer)
{
	struct dw_spi *dws = spi_master_get_devdata(master);

	if (!dws->dma_inited)
		return false;

	return xfer->len > dws->fifo_len;
}

static enum dma_slave_buswidth convert_dma_width(u32 dma_width) {
	if (dma_width == 1)
		return DMA_SLAVE_BUSWIDTH_1_BYTE;
	else if (dma_width == 2)
		return DMA_SLAVE_BUSWIDTH_2_BYTES;

	return DMA_SLAVE_BUSWIDTH_UNDEFINED;
}

/*
 * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
 * channel will clear a corresponding bit.
 */
static void dw_spi_dma_tx_done(void *arg)
{
	struct dw_spi *dws = arg;

	clear_bit(TX_BUSY, &dws->dma_chan_busy);
	if (test_bit(RX_BUSY, &dws->dma_chan_busy))
		return;
	spi_finalize_current_transfer(dws->master);
}

static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
		struct spi_transfer *xfer)
{
	struct dma_slave_config txconf;
	struct dma_async_tx_descriptor *txdesc;

	if (!xfer->tx_buf)
		return NULL;

	txconf.direction = DMA_MEM_TO_DEV;
	txconf.dst_addr = dws->dma_addr;
	txconf.dst_maxburst = 16;
	txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	txconf.dst_addr_width = convert_dma_width(dws->dma_width);
	txconf.device_fc = false;

	dmaengine_slave_config(dws->txchan, &txconf);

	txdesc = dmaengine_prep_slave_sg(dws->txchan,
				xfer->tx_sg.sgl,
				xfer->tx_sg.nents,
				DMA_MEM_TO_DEV,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	if (!txdesc)
		return NULL;

	txdesc->callback = dw_spi_dma_tx_done;
	txdesc->callback_param = dws;

	return txdesc;
}

/*
 * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
 * channel will clear a corresponding bit.
 */
static void dw_spi_dma_rx_done(void *arg)
{
	struct dw_spi *dws = arg;

	clear_bit(RX_BUSY, &dws->dma_chan_busy);
	if (test_bit(TX_BUSY, &dws->dma_chan_busy))
		return;
	spi_finalize_current_transfer(dws->master);
}

static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
		struct spi_transfer *xfer)
{
	struct dma_slave_config rxconf;
	struct dma_async_tx_descriptor *rxdesc;

	if (!xfer->rx_buf)
		return NULL;

	rxconf.direction = DMA_DEV_TO_MEM;
	rxconf.src_addr = dws->dma_addr;
	rxconf.src_maxburst = 16;
	rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	rxconf.src_addr_width = convert_dma_width(dws->dma_width);
	rxconf.device_fc = false;

	dmaengine_slave_config(dws->rxchan, &rxconf);

	rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
				xfer->rx_sg.sgl,
				xfer->rx_sg.nents,
				DMA_DEV_TO_MEM,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	if (!rxdesc)
		return NULL;

	rxdesc->callback = dw_spi_dma_rx_done;
	rxdesc->callback_param = dws;

	return rxdesc;
}

static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
{
	u16 dma_ctrl = 0;

	dw_writel(dws, DW_SPI_DMARDLR, 0xf);
	dw_writel(dws, DW_SPI_DMATDLR, 0x10);

	if (xfer->tx_buf)
		dma_ctrl |= SPI_DMA_TDMAE;
	if (xfer->rx_buf)
		dma_ctrl |= SPI_DMA_RDMAE;
	dw_writel(dws, DW_SPI_DMACR, dma_ctrl);

	/* Set the interrupt mask */
	spi_umask_intr(dws, SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI);

	dws->transfer_handler = dma_transfer;

	return 0;
}

static int mid_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
{
	struct dma_async_tx_descriptor *txdesc, *rxdesc;

	/* Prepare the TX dma transfer */
	txdesc = dw_spi_dma_prepare_tx(dws, xfer);

	/* Prepare the RX dma transfer */
	rxdesc = dw_spi_dma_prepare_rx(dws, xfer);

	/* rx must be started before tx due to spi instinct */
	if (rxdesc) {
		set_bit(RX_BUSY, &dws->dma_chan_busy);
		dmaengine_submit(rxdesc);
		dma_async_issue_pending(dws->rxchan);
	}

	if (txdesc) {
		set_bit(TX_BUSY, &dws->dma_chan_busy);
		dmaengine_submit(txdesc);
		dma_async_issue_pending(dws->txchan);
	}

	return 0;
}

static void mid_spi_dma_stop(struct dw_spi *dws)
{
	if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {
		dmaengine_terminate_sync(dws->txchan);
		clear_bit(TX_BUSY, &dws->dma_chan_busy);
	}
	if (test_bit(RX_BUSY, &dws->dma_chan_busy)) {
		dmaengine_terminate_sync(dws->rxchan);
		clear_bit(RX_BUSY, &dws->dma_chan_busy);
	}
}

static const struct dw_spi_dma_ops mid_dma_ops = {
	.dma_init	= mid_spi_dma_init,
	.dma_exit	= mid_spi_dma_exit,
	.dma_setup	= mid_spi_dma_setup,
	.can_dma	= mid_spi_can_dma,
	.dma_transfer	= mid_spi_dma_transfer,
	.dma_stop	= mid_spi_dma_stop,
};
#endif

/* Some specific info for SPI0 controller on Intel MID */

/* HW info for MRST Clk Control Unit, 32b reg per controller */
#define MRST_SPI_CLK_BASE	100000000	/* 100m */
#define MRST_CLK_SPI_REG	0xff11d86c
#define CLK_SPI_BDIV_OFFSET	0
#define CLK_SPI_BDIV_MASK	0x00000007
#define CLK_SPI_CDIV_OFFSET	9
#define CLK_SPI_CDIV_MASK	0x00000e00
#define CLK_SPI_DISABLE_OFFSET	8

int dw_spi_mid_init(struct dw_spi *dws)
{
	void __iomem *clk_reg;
	u32 clk_cdiv;

	clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
	if (!clk_reg)
		return -ENOMEM;

	/* Get SPI controller operating freq info */
	clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
	clk_cdiv &= CLK_SPI_CDIV_MASK;
	clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
	dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);

	iounmap(clk_reg);

#ifdef CONFIG_SPI_DW_MID_DMA
	dws->dma_tx = &mid_dma_tx;
	dws->dma_rx = &mid_dma_rx;
	dws->dma_ops = &mid_dma_ops;
#endif
	return 0;
}
Commit	Line	Data
7063c0d9	1	/*
ca632f55	2	* Special handling for DW core on Intel MID platform
7063c0d9	3	*
197e96b4	4	* Copyright (c) 2009, 2014 Intel Corporation.
7063c0d9 FT	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
7063c0d9 FT	14	*/
	15
	16	#include <linux/dma-mapping.h>
	17	#include <linux/dmaengine.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/slab.h>
	20	#include <linux/spi/spi.h>
258aea76	21	#include <linux/types.h>
568a60ed	22
ca632f55	23	#include "spi-dw.h"
7063c0d9 FT	24
7063c0d9 FT	25	#ifdef CONFIG_SPI_DW_MID_DMA
7063c0d9	26	#include <linux/pci.h>
d744f826	27	#include <linux/platform_data/dma-dw.h>
7063c0d9	28
30c8eb52 AS	29	#define RX_BUSY 0
	30	#define TX_BUSY 1
	31
d744f826 AS	32	static struct dw_dma_slave mid_dma_tx = { .dst_id = 1 };
d744f826 AS	33	static struct dw_dma_slave mid_dma_rx = { .src_id = 0 };
7063c0d9 FT	34
	35	static bool mid_spi_dma_chan_filter(struct dma_chan chan, void param)
	36	{
d744f826 AS	37	struct dw_dma_slave *s = param;
	38
	39	if (s->dma_dev != chan->device->dev)
	40	return false;
7063c0d9	41
d744f826 AS	42	chan->private = s;
d744f826 AS	43	return true;
7063c0d9 FT	44	}
	45
	46	static int mid_spi_dma_init(struct dw_spi *dws)
	47	{
b89e9c87	48	struct pci_dev *dma_dev;
d744f826 AS	49	struct dw_dma_slave *tx = dws->dma_tx;
d744f826 AS	50	struct dw_dma_slave *rx = dws->dma_rx;
7063c0d9 FT	51	dma_cap_mask_t mask;
	52
	53	/*
	54	* Get pci device for DMA controller, currently it could only
ea092455	55	* be the DMA controller of Medfield
7063c0d9	56	*/
b89e9c87 AS	57	dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
	58	if (!dma_dev)
	59	return -ENODEV;
	60
7063c0d9 FT	61	dma_cap_zero(mask);
	62	dma_cap_set(DMA_SLAVE, mask);
	63
	64	/* 1. Init rx channel */
d744f826 AS	65	rx->dma_dev = &dma_dev->dev;
d744f826 AS	66	dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, rx);
7063c0d9 FT	67	if (!dws->rxchan)
7063c0d9 FT	68	goto err_exit;
f89a6d8f	69	dws->master->dma_rx = dws->rxchan;
7063c0d9 FT	70
7063c0d9 FT	71	/* 2. Init tx channel */
d744f826 AS	72	tx->dma_dev = &dma_dev->dev;
d744f826 AS	73	dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, tx);
7063c0d9 FT	74	if (!dws->txchan)
7063c0d9 FT	75	goto free_rxchan;
f89a6d8f	76	dws->master->dma_tx = dws->txchan;
7063c0d9 FT	77
	78	dws->dma_inited = 1;
	79	return 0;
	80
	81	free_rxchan:
	82	dma_release_channel(dws->rxchan);
	83	err_exit:
b89e9c87	84	return -EBUSY;
7063c0d9 FT	85	}
	86
	87	static void mid_spi_dma_exit(struct dw_spi *dws)
	88	{
fb57862e AS	89	if (!dws->dma_inited)
fb57862e AS	90	return;
8e45ef68	91
a3ff9582	92	dmaengine_terminate_sync(dws->txchan);
7063c0d9	93	dma_release_channel(dws->txchan);
8e45ef68	94
a3ff9582	95	dmaengine_terminate_sync(dws->rxchan);
7063c0d9 FT	96	dma_release_channel(dws->rxchan);
	97	}
	98
f051fc8f AS	99	static irqreturn_t dma_transfer(struct dw_spi *dws)
f051fc8f AS	100	{
dd114443	101	u16 irq_status = dw_readl(dws, DW_SPI_ISR);
f051fc8f AS	102
	103	if (!irq_status)
	104	return IRQ_NONE;
	105
dd114443	106	dw_readl(dws, DW_SPI_ICR);
f051fc8f AS	107	spi_reset_chip(dws);
	108
	109	dev_err(&dws->master->dev, "%s: FIFO overrun/underrun\n", __func__);
	110	dws->master->cur_msg->status = -EIO;
	111	spi_finalize_current_transfer(dws->master);
	112	return IRQ_HANDLED;
	113	}
	114
f89a6d8f AS	115	static bool mid_spi_can_dma(struct spi_master master, struct spi_device spi,
	116	struct spi_transfer *xfer)
	117	{
	118	struct dw_spi *dws = spi_master_get_devdata(master);
	119
	120	if (!dws->dma_inited)
	121	return false;
	122
	123	return xfer->len > dws->fifo_len;
	124	}
	125
e31abce7 AS	126	static enum dma_slave_buswidth convert_dma_width(u32 dma_width) {
	127	if (dma_width == 1)
	128	return DMA_SLAVE_BUSWIDTH_1_BYTE;
	129	else if (dma_width == 2)
	130	return DMA_SLAVE_BUSWIDTH_2_BYTES;
	131
	132	return DMA_SLAVE_BUSWIDTH_UNDEFINED;
	133	}
	134
7063c0d9	135	/*
30c8eb52 AS	136	* dws->dma_chan_busy is set before the dma transfer starts, callback for tx
30c8eb52 AS	137	* channel will clear a corresponding bit.
7063c0d9	138	*/
30c8eb52	139	static void dw_spi_dma_tx_done(void *arg)
7063c0d9 FT	140	{
	141	struct dw_spi *dws = arg;
	142
854d2f24 AS	143	clear_bit(TX_BUSY, &dws->dma_chan_busy);
854d2f24 AS	144	if (test_bit(RX_BUSY, &dws->dma_chan_busy))
7063c0d9	145	return;
c22c62db	146	spi_finalize_current_transfer(dws->master);
7063c0d9 FT	147	}
7063c0d9 FT	148
f89a6d8f AS	149	static struct dma_async_tx_descriptor dw_spi_dma_prepare_tx(struct dw_spi dws,
f89a6d8f AS	150	struct spi_transfer *xfer)
7063c0d9	151	{
a5c2db96 AS	152	struct dma_slave_config txconf;
a5c2db96 AS	153	struct dma_async_tx_descriptor *txdesc;
7063c0d9	154
f89a6d8f	155	if (!xfer->tx_buf)
30c8eb52 AS	156	return NULL;
30c8eb52 AS	157
a485df4b	158	txconf.direction = DMA_MEM_TO_DEV;
7063c0d9	159	txconf.dst_addr = dws->dma_addr;
d744f826	160	txconf.dst_maxburst = 16;
7063c0d9	161	txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
e31abce7	162	txconf.dst_addr_width = convert_dma_width(dws->dma_width);
258aea76	163	txconf.device_fc = false;
7063c0d9	164
2a285299	165	dmaengine_slave_config(dws->txchan, &txconf);
7063c0d9	166
2a285299	167	txdesc = dmaengine_prep_slave_sg(dws->txchan,
f89a6d8f AS	168	xfer->tx_sg.sgl,
f89a6d8f AS	169	xfer->tx_sg.nents,
a485df4b	170	DMA_MEM_TO_DEV,
f7477c2b	171	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
c9dafb27 AS	172	if (!txdesc)
	173	return NULL;
	174
30c8eb52	175	txdesc->callback = dw_spi_dma_tx_done;
7063c0d9 FT	176	txdesc->callback_param = dws;
7063c0d9 FT	177
a5c2db96 AS	178	return txdesc;
	179	}
	180
30c8eb52 AS	181	/*
	182	* dws->dma_chan_busy is set before the dma transfer starts, callback for rx
	183	* channel will clear a corresponding bit.
	184	*/
	185	static void dw_spi_dma_rx_done(void *arg)
	186	{
	187	struct dw_spi *dws = arg;
	188
854d2f24 AS	189	clear_bit(RX_BUSY, &dws->dma_chan_busy);
854d2f24 AS	190	if (test_bit(TX_BUSY, &dws->dma_chan_busy))
30c8eb52	191	return;
c22c62db	192	spi_finalize_current_transfer(dws->master);
30c8eb52 AS	193	}
30c8eb52 AS	194
f89a6d8f AS	195	static struct dma_async_tx_descriptor dw_spi_dma_prepare_rx(struct dw_spi dws,
f89a6d8f AS	196	struct spi_transfer *xfer)
a5c2db96 AS	197	{
	198	struct dma_slave_config rxconf;
	199	struct dma_async_tx_descriptor *rxdesc;
	200
f89a6d8f	201	if (!xfer->rx_buf)
30c8eb52 AS	202	return NULL;
30c8eb52 AS	203
a485df4b	204	rxconf.direction = DMA_DEV_TO_MEM;
7063c0d9	205	rxconf.src_addr = dws->dma_addr;
d744f826	206	rxconf.src_maxburst = 16;
7063c0d9	207	rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
e31abce7	208	rxconf.src_addr_width = convert_dma_width(dws->dma_width);
258aea76	209	rxconf.device_fc = false;
7063c0d9	210
2a285299	211	dmaengine_slave_config(dws->rxchan, &rxconf);
7063c0d9	212
2a285299	213	rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
f89a6d8f AS	214	xfer->rx_sg.sgl,
f89a6d8f AS	215	xfer->rx_sg.nents,
a485df4b	216	DMA_DEV_TO_MEM,
f7477c2b	217	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
c9dafb27 AS	218	if (!rxdesc)
	219	return NULL;
	220
30c8eb52	221	rxdesc->callback = dw_spi_dma_rx_done;
7063c0d9 FT	222	rxdesc->callback_param = dws;
7063c0d9 FT	223
a5c2db96 AS	224	return rxdesc;
	225	}
	226
f89a6d8f	227	static int mid_spi_dma_setup(struct dw_spi dws, struct spi_transfer xfer)
a5c2db96 AS	228	{
	229	u16 dma_ctrl = 0;
	230
dd114443 TT	231	dw_writel(dws, DW_SPI_DMARDLR, 0xf);
dd114443 TT	232	dw_writel(dws, DW_SPI_DMATDLR, 0x10);
a5c2db96	233
f89a6d8f	234	if (xfer->tx_buf)
a5c2db96	235	dma_ctrl \|= SPI_DMA_TDMAE;
f89a6d8f	236	if (xfer->rx_buf)
a5c2db96	237	dma_ctrl \|= SPI_DMA_RDMAE;
dd114443	238	dw_writel(dws, DW_SPI_DMACR, dma_ctrl);
a5c2db96	239
f051fc8f AS	240	/* Set the interrupt mask */
	241	spi_umask_intr(dws, SPI_INT_TXOI \| SPI_INT_RXUI \| SPI_INT_RXOI);
	242
	243	dws->transfer_handler = dma_transfer;
	244
9f14538e	245	return 0;
a5c2db96 AS	246	}
a5c2db96 AS	247
f89a6d8f	248	static int mid_spi_dma_transfer(struct dw_spi dws, struct spi_transfer xfer)
a5c2db96 AS	249	{
	250	struct dma_async_tx_descriptor txdesc, rxdesc;
	251
9f14538e	252	/* Prepare the TX dma transfer */
f89a6d8f	253	txdesc = dw_spi_dma_prepare_tx(dws, xfer);
a5c2db96	254
9f14538e	255	/* Prepare the RX dma transfer */
f89a6d8f	256	rxdesc = dw_spi_dma_prepare_rx(dws, xfer);
a5c2db96	257
7063c0d9	258	/* rx must be started before tx due to spi instinct */
30c8eb52 AS	259	if (rxdesc) {
	260	set_bit(RX_BUSY, &dws->dma_chan_busy);
	261	dmaengine_submit(rxdesc);
	262	dma_async_issue_pending(dws->rxchan);
	263	}
	264
	265	if (txdesc) {
	266	set_bit(TX_BUSY, &dws->dma_chan_busy);
	267	dmaengine_submit(txdesc);
	268	dma_async_issue_pending(dws->txchan);
	269	}
f7477c2b	270
7063c0d9 FT	271	return 0;
	272	}
	273
4d5ac1ed AS	274	static void mid_spi_dma_stop(struct dw_spi *dws)
	275	{
	276	if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {
cf1716e9	277	dmaengine_terminate_sync(dws->txchan);
4d5ac1ed AS	278	clear_bit(TX_BUSY, &dws->dma_chan_busy);
	279	}
	280	if (test_bit(RX_BUSY, &dws->dma_chan_busy)) {
cf1716e9	281	dmaengine_terminate_sync(dws->rxchan);
4d5ac1ed AS	282	clear_bit(RX_BUSY, &dws->dma_chan_busy);
	283	}
	284	}
	285
4fe338c9	286	static const struct dw_spi_dma_ops mid_dma_ops = {
7063c0d9 FT	287	.dma_init = mid_spi_dma_init,
7063c0d9 FT	288	.dma_exit = mid_spi_dma_exit,
9f14538e	289	.dma_setup = mid_spi_dma_setup,
f89a6d8f	290	.can_dma = mid_spi_can_dma,
7063c0d9	291	.dma_transfer = mid_spi_dma_transfer,
4d5ac1ed	292	.dma_stop = mid_spi_dma_stop,
7063c0d9 FT	293	};
	294	#endif
	295
ea092455	296	/* Some specific info for SPI0 controller on Intel MID */
7063c0d9	297
d9c14743	298	/* HW info for MRST Clk Control Unit, 32b reg per controller */
7063c0d9	299	#define MRST_SPI_CLK_BASE 100000000 /* 100m */
d9c14743	300	#define MRST_CLK_SPI_REG 0xff11d86c
7063c0d9 FT	301	#define CLK_SPI_BDIV_OFFSET 0
	302	#define CLK_SPI_BDIV_MASK 0x00000007
	303	#define CLK_SPI_CDIV_OFFSET 9
	304	#define CLK_SPI_CDIV_MASK 0x00000e00
	305	#define CLK_SPI_DISABLE_OFFSET 8
	306
	307	int dw_spi_mid_init(struct dw_spi *dws)
	308	{
7eb187b3 HS	309	void __iomem *clk_reg;
7eb187b3 HS	310	u32 clk_cdiv;
7063c0d9	311
d9c14743	312	clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
7063c0d9 FT	313	if (!clk_reg)
	314	return -ENOMEM;
	315
d9c14743 AS	316	/* Get SPI controller operating freq info */
	317	clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
	318	clk_cdiv &= CLK_SPI_CDIV_MASK;
	319	clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
7063c0d9	320	dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
d9c14743	321
7063c0d9 FT	322	iounmap(clk_reg);
7063c0d9 FT	323
7063c0d9	324	#ifdef CONFIG_SPI_DW_MID_DMA
d744f826 AS	325	dws->dma_tx = &mid_dma_tx;
d744f826 AS	326	dws->dma_rx = &mid_dma_rx;
7063c0d9 FT	327	dws->dma_ops = &mid_dma_ops;
	328	#endif
	329	return 0;
	330	}