[mirror_ubuntu-bionic-kernel.git] / drivers / spi / spi-dw-mid.c

/*
 * Special handling for DW core on Intel MID platform
 *
 * Copyright (c) 2009, 2014 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/types.h>

#include "spi-dw.h"

#ifdef CONFIG_SPI_DW_MID_DMA
#include <linux/intel_mid_dma.h>
#include <linux/pci.h>

#define RX_BUSY		0
#define TX_BUSY		1

struct mid_dma {
	struct intel_mid_dma_slave	dmas_tx;
	struct intel_mid_dma_slave	dmas_rx;
};

static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
{
	struct dw_spi *dws = param;

	return dws->dma_dev == chan->device->dev;
}

static int mid_spi_dma_init(struct dw_spi *dws)
{
	struct mid_dma *dw_dma = dws->dma_priv;
	struct pci_dev *dma_dev;
	struct intel_mid_dma_slave *rxs, *txs;
	dma_cap_mask_t mask;

	/*
	 * Get pci device for DMA controller, currently it could only
	 * be the DMA controller of Medfield
	 */
	dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
	if (!dma_dev)
		return -ENODEV;

	dws->dma_dev = &dma_dev->dev;

	dma_cap_zero(mask);
	dma_cap_set(DMA_SLAVE, mask);

	/* 1. Init rx channel */
	dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	if (!dws->rxchan)
		goto err_exit;
	rxs = &dw_dma->dmas_rx;
	rxs->hs_mode = LNW_DMA_HW_HS;
	rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
	dws->rxchan->private = rxs;

	/* 2. Init tx channel */
	dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	if (!dws->txchan)
		goto free_rxchan;
	txs = &dw_dma->dmas_tx;
	txs->hs_mode = LNW_DMA_HW_HS;
	txs->cfg_mode = LNW_DMA_MEM_TO_PER;
	dws->txchan->private = txs;

	dws->dma_inited = 1;
	return 0;

free_rxchan:
	dma_release_channel(dws->rxchan);
err_exit:
	return -EBUSY;
}

static void mid_spi_dma_exit(struct dw_spi *dws)
{
	if (!dws->dma_inited)
		return;

	dmaengine_terminate_all(dws->txchan);
	dma_release_channel(dws->txchan);

	dmaengine_terminate_all(dws->rxchan);
	dma_release_channel(dws->rxchan);
}

/*
 * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
 * channel will clear a corresponding bit.
 */
static void dw_spi_dma_tx_done(void *arg)
{
	struct dw_spi *dws = arg;

	if (test_and_clear_bit(TX_BUSY, &dws->dma_chan_busy) & BIT(RX_BUSY))
		return;
	dw_spi_xfer_done(dws);
}

static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws)
{
	struct dma_slave_config txconf;
	struct dma_async_tx_descriptor *txdesc;

	if (!dws->tx_dma)
		return NULL;

	txconf.direction = DMA_MEM_TO_DEV;
	txconf.dst_addr = dws->dma_addr;
	txconf.dst_maxburst = LNW_DMA_MSIZE_16;
	txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	txconf.dst_addr_width = dws->dma_width;
	txconf.device_fc = false;

	dmaengine_slave_config(dws->txchan, &txconf);

	memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
	dws->tx_sgl.dma_address = dws->tx_dma;
	dws->tx_sgl.length = dws->len;

	txdesc = dmaengine_prep_slave_sg(dws->txchan,
				&dws->tx_sgl,
				1,
				DMA_MEM_TO_DEV,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	txdesc->callback = dw_spi_dma_tx_done;
	txdesc->callback_param = dws;

	return txdesc;
}

/*
 * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
 * channel will clear a corresponding bit.
 */
static void dw_spi_dma_rx_done(void *arg)
{
	struct dw_spi *dws = arg;

	if (test_and_clear_bit(RX_BUSY, &dws->dma_chan_busy) & BIT(TX_BUSY))
		return;
	dw_spi_xfer_done(dws);
}

static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
{
	struct dma_slave_config rxconf;
	struct dma_async_tx_descriptor *rxdesc;

	if (!dws->rx_dma)
		return NULL;

	rxconf.direction = DMA_DEV_TO_MEM;
	rxconf.src_addr = dws->dma_addr;
	rxconf.src_maxburst = LNW_DMA_MSIZE_16;
	rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	rxconf.src_addr_width = dws->dma_width;
	rxconf.device_fc = false;

	dmaengine_slave_config(dws->rxchan, &rxconf);

	memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
	dws->rx_sgl.dma_address = dws->rx_dma;
	dws->rx_sgl.length = dws->len;

	rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
				&dws->rx_sgl,
				1,
				DMA_DEV_TO_MEM,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	rxdesc->callback = dw_spi_dma_rx_done;
	rxdesc->callback_param = dws;

	return rxdesc;
}

static void dw_spi_dma_setup(struct dw_spi *dws)
{
	u16 dma_ctrl = 0;

	spi_enable_chip(dws, 0);

	dw_writew(dws, DW_SPI_DMARDLR, 0xf);
	dw_writew(dws, DW_SPI_DMATDLR, 0x10);

	if (dws->tx_dma)
		dma_ctrl |= SPI_DMA_TDMAE;
	if (dws->rx_dma)
		dma_ctrl |= SPI_DMA_RDMAE;
	dw_writew(dws, DW_SPI_DMACR, dma_ctrl);

	spi_enable_chip(dws, 1);
}

static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
{
	struct dma_async_tx_descriptor *txdesc, *rxdesc;

	/* 1. setup DMA related registers */
	if (cs_change)
		dw_spi_dma_setup(dws);

	/* 2. Prepare the TX dma transfer */
	txdesc = dw_spi_dma_prepare_tx(dws);

	/* 3. Prepare the RX dma transfer */
	rxdesc = dw_spi_dma_prepare_rx(dws);

	/* rx must be started before tx due to spi instinct */
	if (rxdesc) {
		set_bit(RX_BUSY, &dws->dma_chan_busy);
		dmaengine_submit(rxdesc);
		dma_async_issue_pending(dws->rxchan);
	}

	if (txdesc) {
		set_bit(TX_BUSY, &dws->dma_chan_busy);
		dmaengine_submit(txdesc);
		dma_async_issue_pending(dws->txchan);
	}

	return 0;
}

static struct dw_spi_dma_ops mid_dma_ops = {
	.dma_init	= mid_spi_dma_init,
	.dma_exit	= mid_spi_dma_exit,
	.dma_transfer	= mid_spi_dma_transfer,
};
#endif

/* Some specific info for SPI0 controller on Intel MID */

/* HW info for MRST Clk Control Unit, 32b reg per controller */
#define MRST_SPI_CLK_BASE	100000000	/* 100m */
#define MRST_CLK_SPI_REG	0xff11d86c
#define CLK_SPI_BDIV_OFFSET	0
#define CLK_SPI_BDIV_MASK	0x00000007
#define CLK_SPI_CDIV_OFFSET	9
#define CLK_SPI_CDIV_MASK	0x00000e00
#define CLK_SPI_DISABLE_OFFSET	8

int dw_spi_mid_init(struct dw_spi *dws)
{
	void __iomem *clk_reg;
	u32 clk_cdiv;

	clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
	if (!clk_reg)
		return -ENOMEM;

	/* Get SPI controller operating freq info */
	clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
	clk_cdiv &= CLK_SPI_CDIV_MASK;
	clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
	dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);

	iounmap(clk_reg);

#ifdef CONFIG_SPI_DW_MID_DMA
	dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
	if (!dws->dma_priv)
		return -ENOMEM;
	dws->dma_ops = &mid_dma_ops;
#endif
	return 0;
}
Commit	Line	Data
7063c0d9	1	/*
ca632f55	2	* Special handling for DW core on Intel MID platform
7063c0d9	3	*
197e96b4	4	* Copyright (c) 2009, 2014 Intel Corporation.
7063c0d9 FT	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
7063c0d9 FT	14	*/
	15
	16	#include <linux/dma-mapping.h>
	17	#include <linux/dmaengine.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/slab.h>
	20	#include <linux/spi/spi.h>
258aea76	21	#include <linux/types.h>
568a60ed	22
ca632f55	23	#include "spi-dw.h"
7063c0d9 FT	24
	25	#ifdef CONFIG_SPI_DW_MID_DMA
	26	#include <linux/intel_mid_dma.h>
	27	#include <linux/pci.h>
	28
30c8eb52 AS	29	#define RX_BUSY 0
	30	#define TX_BUSY 1
	31
7063c0d9 FT	32	struct mid_dma {
	33	struct intel_mid_dma_slave dmas_tx;
	34	struct intel_mid_dma_slave dmas_rx;
	35	};
	36
	37	static bool mid_spi_dma_chan_filter(struct dma_chan chan, void param)
	38	{
	39	struct dw_spi *dws = param;
	40
b89e9c87	41	return dws->dma_dev == chan->device->dev;
7063c0d9 FT	42	}
	43
	44	static int mid_spi_dma_init(struct dw_spi *dws)
	45	{
	46	struct mid_dma *dw_dma = dws->dma_priv;
b89e9c87	47	struct pci_dev *dma_dev;
7063c0d9 FT	48	struct intel_mid_dma_slave rxs, txs;
	49	dma_cap_mask_t mask;
	50
	51	/*
	52	* Get pci device for DMA controller, currently it could only
ea092455	53	* be the DMA controller of Medfield
7063c0d9	54	*/
b89e9c87 AS	55	dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
	56	if (!dma_dev)
	57	return -ENODEV;
	58
	59	dws->dma_dev = &dma_dev->dev;
7063c0d9 FT	60
	61	dma_cap_zero(mask);
	62	dma_cap_set(DMA_SLAVE, mask);
	63
	64	/* 1. Init rx channel */
	65	dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	66	if (!dws->rxchan)
	67	goto err_exit;
	68	rxs = &dw_dma->dmas_rx;
	69	rxs->hs_mode = LNW_DMA_HW_HS;
	70	rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
	71	dws->rxchan->private = rxs;
	72
	73	/* 2. Init tx channel */
	74	dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	75	if (!dws->txchan)
	76	goto free_rxchan;
	77	txs = &dw_dma->dmas_tx;
	78	txs->hs_mode = LNW_DMA_HW_HS;
	79	txs->cfg_mode = LNW_DMA_MEM_TO_PER;
	80	dws->txchan->private = txs;
	81
	82	dws->dma_inited = 1;
	83	return 0;
	84
	85	free_rxchan:
	86	dma_release_channel(dws->rxchan);
	87	err_exit:
b89e9c87	88	return -EBUSY;
7063c0d9 FT	89	}
	90
	91	static void mid_spi_dma_exit(struct dw_spi *dws)
	92	{
fb57862e AS	93	if (!dws->dma_inited)
fb57862e AS	94	return;
8e45ef68 AS	95
8e45ef68 AS	96	dmaengine_terminate_all(dws->txchan);
7063c0d9	97	dma_release_channel(dws->txchan);
8e45ef68 AS	98
8e45ef68 AS	99	dmaengine_terminate_all(dws->rxchan);
7063c0d9 FT	100	dma_release_channel(dws->rxchan);
	101	}
	102
	103	/*
30c8eb52 AS	104	* dws->dma_chan_busy is set before the dma transfer starts, callback for tx
30c8eb52 AS	105	* channel will clear a corresponding bit.
7063c0d9	106	*/
30c8eb52	107	static void dw_spi_dma_tx_done(void *arg)
7063c0d9 FT	108	{
	109	struct dw_spi *dws = arg;
	110
30c8eb52	111	if (test_and_clear_bit(TX_BUSY, &dws->dma_chan_busy) & BIT(RX_BUSY))
7063c0d9 FT	112	return;
	113	dw_spi_xfer_done(dws);
	114	}
	115
a5c2db96	116	static struct dma_async_tx_descriptor dw_spi_dma_prepare_tx(struct dw_spi dws)
7063c0d9	117	{
a5c2db96 AS	118	struct dma_slave_config txconf;
a5c2db96 AS	119	struct dma_async_tx_descriptor *txdesc;
7063c0d9	120
30c8eb52 AS	121	if (!dws->tx_dma)
	122	return NULL;
	123
a485df4b	124	txconf.direction = DMA_MEM_TO_DEV;
7063c0d9 FT	125	txconf.dst_addr = dws->dma_addr;
	126	txconf.dst_maxburst = LNW_DMA_MSIZE_16;
	127	txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
b41583e7	128	txconf.dst_addr_width = dws->dma_width;
258aea76	129	txconf.device_fc = false;
7063c0d9	130
2a285299	131	dmaengine_slave_config(dws->txchan, &txconf);
7063c0d9 FT	132
	133	memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
	134	dws->tx_sgl.dma_address = dws->tx_dma;
	135	dws->tx_sgl.length = dws->len;
	136
2a285299	137	txdesc = dmaengine_prep_slave_sg(dws->txchan,
7063c0d9 FT	138	&dws->tx_sgl,
7063c0d9 FT	139	1,
a485df4b	140	DMA_MEM_TO_DEV,
f7477c2b	141	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
30c8eb52	142	txdesc->callback = dw_spi_dma_tx_done;
7063c0d9 FT	143	txdesc->callback_param = dws;
7063c0d9 FT	144
a5c2db96 AS	145	return txdesc;
	146	}
	147
30c8eb52 AS	148	/*
	149	* dws->dma_chan_busy is set before the dma transfer starts, callback for rx
	150	* channel will clear a corresponding bit.
	151	*/
	152	static void dw_spi_dma_rx_done(void *arg)
	153	{
	154	struct dw_spi *dws = arg;
	155
	156	if (test_and_clear_bit(RX_BUSY, &dws->dma_chan_busy) & BIT(TX_BUSY))
	157	return;
	158	dw_spi_xfer_done(dws);
	159	}
	160
a5c2db96 AS	161	static struct dma_async_tx_descriptor dw_spi_dma_prepare_rx(struct dw_spi dws)
	162	{
	163	struct dma_slave_config rxconf;
	164	struct dma_async_tx_descriptor *rxdesc;
	165
30c8eb52 AS	166	if (!dws->rx_dma)
	167	return NULL;
	168
a485df4b	169	rxconf.direction = DMA_DEV_TO_MEM;
7063c0d9 FT	170	rxconf.src_addr = dws->dma_addr;
	171	rxconf.src_maxburst = LNW_DMA_MSIZE_16;
	172	rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
b41583e7	173	rxconf.src_addr_width = dws->dma_width;
258aea76	174	rxconf.device_fc = false;
7063c0d9	175
2a285299	176	dmaengine_slave_config(dws->rxchan, &rxconf);
7063c0d9 FT	177
	178	memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
	179	dws->rx_sgl.dma_address = dws->rx_dma;
	180	dws->rx_sgl.length = dws->len;
	181
2a285299	182	rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
7063c0d9 FT	183	&dws->rx_sgl,
7063c0d9 FT	184	1,
a485df4b	185	DMA_DEV_TO_MEM,
f7477c2b	186	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
30c8eb52	187	rxdesc->callback = dw_spi_dma_rx_done;
7063c0d9 FT	188	rxdesc->callback_param = dws;
7063c0d9 FT	189
a5c2db96 AS	190	return rxdesc;
	191	}
	192
	193	static void dw_spi_dma_setup(struct dw_spi *dws)
	194	{
	195	u16 dma_ctrl = 0;
	196
	197	spi_enable_chip(dws, 0);
	198
	199	dw_writew(dws, DW_SPI_DMARDLR, 0xf);
	200	dw_writew(dws, DW_SPI_DMATDLR, 0x10);
	201
	202	if (dws->tx_dma)
	203	dma_ctrl \|= SPI_DMA_TDMAE;
	204	if (dws->rx_dma)
	205	dma_ctrl \|= SPI_DMA_RDMAE;
	206	dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
	207
	208	spi_enable_chip(dws, 1);
	209	}
	210
	211	static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
	212	{
	213	struct dma_async_tx_descriptor txdesc, rxdesc;
	214
	215	/* 1. setup DMA related registers */
	216	if (cs_change)
	217	dw_spi_dma_setup(dws);
	218
a5c2db96 AS	219	/* 2. Prepare the TX dma transfer */
	220	txdesc = dw_spi_dma_prepare_tx(dws);
	221
	222	/* 3. Prepare the RX dma transfer */
	223	rxdesc = dw_spi_dma_prepare_rx(dws);
	224
7063c0d9	225	/* rx must be started before tx due to spi instinct */
30c8eb52 AS	226	if (rxdesc) {
	227	set_bit(RX_BUSY, &dws->dma_chan_busy);
	228	dmaengine_submit(rxdesc);
	229	dma_async_issue_pending(dws->rxchan);
	230	}
	231
	232	if (txdesc) {
	233	set_bit(TX_BUSY, &dws->dma_chan_busy);
	234	dmaengine_submit(txdesc);
	235	dma_async_issue_pending(dws->txchan);
	236	}
f7477c2b	237
7063c0d9 FT	238	return 0;
	239	}
	240
	241	static struct dw_spi_dma_ops mid_dma_ops = {
	242	.dma_init = mid_spi_dma_init,
	243	.dma_exit = mid_spi_dma_exit,
	244	.dma_transfer = mid_spi_dma_transfer,
	245	};
	246	#endif
	247
ea092455	248	/* Some specific info for SPI0 controller on Intel MID */
7063c0d9	249
d9c14743	250	/* HW info for MRST Clk Control Unit, 32b reg per controller */
7063c0d9	251	#define MRST_SPI_CLK_BASE 100000000 /* 100m */
d9c14743	252	#define MRST_CLK_SPI_REG 0xff11d86c
7063c0d9 FT	253	#define CLK_SPI_BDIV_OFFSET 0
	254	#define CLK_SPI_BDIV_MASK 0x00000007
	255	#define CLK_SPI_CDIV_OFFSET 9
	256	#define CLK_SPI_CDIV_MASK 0x00000e00
	257	#define CLK_SPI_DISABLE_OFFSET 8
	258
	259	int dw_spi_mid_init(struct dw_spi *dws)
	260	{
7eb187b3 HS	261	void __iomem *clk_reg;
7eb187b3 HS	262	u32 clk_cdiv;
7063c0d9	263
d9c14743	264	clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
7063c0d9 FT	265	if (!clk_reg)
	266	return -ENOMEM;
	267
d9c14743 AS	268	/* Get SPI controller operating freq info */
	269	clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
	270	clk_cdiv &= CLK_SPI_CDIV_MASK;
	271	clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
7063c0d9	272	dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
d9c14743	273
7063c0d9 FT	274	iounmap(clk_reg);
7063c0d9 FT	275
7063c0d9 FT	276	#ifdef CONFIG_SPI_DW_MID_DMA
	277	dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
	278	if (!dws->dma_priv)
	279	return -ENOMEM;
	280	dws->dma_ops = &mid_dma_ops;
	281	#endif
	282	return 0;
	283	}