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Commit | Line | Data |
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e24c7452 | 1 | /* |
ca632f55 | 2 | * Designware SPI core controller driver (refer pxa2xx_spi.c) |
e24c7452 FT |
3 | * |
4 | * Copyright (c) 2009, Intel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
e24c7452 FT |
14 | */ |
15 | ||
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/interrupt.h> | |
d7614de4 | 18 | #include <linux/module.h> |
e24c7452 FT |
19 | #include <linux/highmem.h> |
20 | #include <linux/delay.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
e24c7452 | 22 | #include <linux/spi/spi.h> |
d9c73bb8 | 23 | #include <linux/gpio.h> |
e24c7452 | 24 | |
ca632f55 | 25 | #include "spi-dw.h" |
568a60ed | 26 | |
e24c7452 FT |
27 | #ifdef CONFIG_DEBUG_FS |
28 | #include <linux/debugfs.h> | |
29 | #endif | |
30 | ||
e24c7452 FT |
31 | /* Slave spi_dev related */ |
32 | struct chip_data { | |
e24c7452 | 33 | u8 cs; /* chip select pin */ |
e24c7452 FT |
34 | u8 tmode; /* TR/TO/RO/EEPROM */ |
35 | u8 type; /* SPI/SSP/MicroWire */ | |
36 | ||
37 | u8 poll_mode; /* 1 means use poll mode */ | |
38 | ||
e24c7452 | 39 | u8 enable_dma; |
e24c7452 FT |
40 | u16 clk_div; /* baud rate divider */ |
41 | u32 speed_hz; /* baud rate */ | |
e24c7452 FT |
42 | void (*cs_control)(u32 command); |
43 | }; | |
44 | ||
45 | #ifdef CONFIG_DEBUG_FS | |
e24c7452 | 46 | #define SPI_REGS_BUFSIZE 1024 |
53288fe9 AS |
47 | static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf, |
48 | size_t count, loff_t *ppos) | |
e24c7452 | 49 | { |
53288fe9 | 50 | struct dw_spi *dws = file->private_data; |
e24c7452 FT |
51 | char *buf; |
52 | u32 len = 0; | |
53 | ssize_t ret; | |
54 | ||
e24c7452 FT |
55 | buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL); |
56 | if (!buf) | |
57 | return 0; | |
58 | ||
59 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
53288fe9 | 60 | "%s registers:\n", dev_name(&dws->master->dev)); |
e24c7452 FT |
61 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
62 | "=================================\n"); | |
63 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
7eb187b3 | 64 | "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0)); |
e24c7452 | 65 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 66 | "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1)); |
e24c7452 | 67 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 68 | "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR)); |
e24c7452 | 69 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 70 | "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER)); |
e24c7452 | 71 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 72 | "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR)); |
e24c7452 | 73 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 74 | "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR)); |
e24c7452 | 75 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 76 | "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR)); |
e24c7452 | 77 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 78 | "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR)); |
e24c7452 | 79 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 80 | "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR)); |
e24c7452 | 81 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 82 | "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR)); |
e24c7452 | 83 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 84 | "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR)); |
e24c7452 | 85 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 86 | "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR)); |
e24c7452 | 87 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 88 | "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR)); |
e24c7452 | 89 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 90 | "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR)); |
e24c7452 | 91 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 92 | "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR)); |
e24c7452 FT |
93 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
94 | "=================================\n"); | |
95 | ||
53288fe9 | 96 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); |
e24c7452 FT |
97 | kfree(buf); |
98 | return ret; | |
99 | } | |
100 | ||
53288fe9 | 101 | static const struct file_operations dw_spi_regs_ops = { |
e24c7452 | 102 | .owner = THIS_MODULE, |
234e3405 | 103 | .open = simple_open, |
53288fe9 | 104 | .read = dw_spi_show_regs, |
6038f373 | 105 | .llseek = default_llseek, |
e24c7452 FT |
106 | }; |
107 | ||
53288fe9 | 108 | static int dw_spi_debugfs_init(struct dw_spi *dws) |
e24c7452 | 109 | { |
13288bdf PR |
110 | char name[128]; |
111 | ||
112 | snprintf(name, 128, "dw_spi-%s", dev_name(&dws->master->dev)); | |
113 | dws->debugfs = debugfs_create_dir(name, NULL); | |
e24c7452 FT |
114 | if (!dws->debugfs) |
115 | return -ENOMEM; | |
116 | ||
117 | debugfs_create_file("registers", S_IFREG | S_IRUGO, | |
53288fe9 | 118 | dws->debugfs, (void *)dws, &dw_spi_regs_ops); |
e24c7452 FT |
119 | return 0; |
120 | } | |
121 | ||
53288fe9 | 122 | static void dw_spi_debugfs_remove(struct dw_spi *dws) |
e24c7452 | 123 | { |
fadcace7 | 124 | debugfs_remove_recursive(dws->debugfs); |
e24c7452 FT |
125 | } |
126 | ||
127 | #else | |
53288fe9 | 128 | static inline int dw_spi_debugfs_init(struct dw_spi *dws) |
e24c7452 | 129 | { |
20a588fc | 130 | return 0; |
e24c7452 FT |
131 | } |
132 | ||
53288fe9 | 133 | static inline void dw_spi_debugfs_remove(struct dw_spi *dws) |
e24c7452 FT |
134 | { |
135 | } | |
136 | #endif /* CONFIG_DEBUG_FS */ | |
137 | ||
c22c62db AS |
138 | static void dw_spi_set_cs(struct spi_device *spi, bool enable) |
139 | { | |
140 | struct dw_spi *dws = spi_master_get_devdata(spi->master); | |
141 | struct chip_data *chip = spi_get_ctldata(spi); | |
142 | ||
143 | /* Chip select logic is inverted from spi_set_cs() */ | |
207cda93 | 144 | if (chip && chip->cs_control) |
c22c62db AS |
145 | chip->cs_control(!enable); |
146 | ||
147 | if (!enable) | |
148 | dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); | |
149 | } | |
150 | ||
2ff271bf AD |
151 | /* Return the max entries we can fill into tx fifo */ |
152 | static inline u32 tx_max(struct dw_spi *dws) | |
153 | { | |
154 | u32 tx_left, tx_room, rxtx_gap; | |
155 | ||
156 | tx_left = (dws->tx_end - dws->tx) / dws->n_bytes; | |
dd114443 | 157 | tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR); |
2ff271bf AD |
158 | |
159 | /* | |
160 | * Another concern is about the tx/rx mismatch, we | |
161 | * though to use (dws->fifo_len - rxflr - txflr) as | |
162 | * one maximum value for tx, but it doesn't cover the | |
163 | * data which is out of tx/rx fifo and inside the | |
164 | * shift registers. So a control from sw point of | |
165 | * view is taken. | |
166 | */ | |
167 | rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx)) | |
168 | / dws->n_bytes; | |
169 | ||
170 | return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap)); | |
171 | } | |
172 | ||
173 | /* Return the max entries we should read out of rx fifo */ | |
174 | static inline u32 rx_max(struct dw_spi *dws) | |
175 | { | |
176 | u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes; | |
177 | ||
dd114443 | 178 | return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR)); |
2ff271bf AD |
179 | } |
180 | ||
3b8a4dd3 | 181 | static void dw_writer(struct dw_spi *dws) |
e24c7452 | 182 | { |
2ff271bf | 183 | u32 max = tx_max(dws); |
de6efe0a | 184 | u16 txw = 0; |
e24c7452 | 185 | |
2ff271bf AD |
186 | while (max--) { |
187 | /* Set the tx word if the transfer's original "tx" is not null */ | |
188 | if (dws->tx_end - dws->len) { | |
189 | if (dws->n_bytes == 1) | |
190 | txw = *(u8 *)(dws->tx); | |
191 | else | |
192 | txw = *(u16 *)(dws->tx); | |
193 | } | |
c4fe57f7 | 194 | dw_write_io_reg(dws, DW_SPI_DR, txw); |
2ff271bf | 195 | dws->tx += dws->n_bytes; |
e24c7452 | 196 | } |
e24c7452 FT |
197 | } |
198 | ||
3b8a4dd3 | 199 | static void dw_reader(struct dw_spi *dws) |
e24c7452 | 200 | { |
2ff271bf | 201 | u32 max = rx_max(dws); |
de6efe0a | 202 | u16 rxw; |
e24c7452 | 203 | |
2ff271bf | 204 | while (max--) { |
c4fe57f7 | 205 | rxw = dw_read_io_reg(dws, DW_SPI_DR); |
de6efe0a FT |
206 | /* Care rx only if the transfer's original "rx" is not null */ |
207 | if (dws->rx_end - dws->len) { | |
208 | if (dws->n_bytes == 1) | |
209 | *(u8 *)(dws->rx) = rxw; | |
210 | else | |
211 | *(u16 *)(dws->rx) = rxw; | |
212 | } | |
213 | dws->rx += dws->n_bytes; | |
e24c7452 | 214 | } |
e24c7452 FT |
215 | } |
216 | ||
e24c7452 FT |
217 | static void int_error_stop(struct dw_spi *dws, const char *msg) |
218 | { | |
45746e82 | 219 | spi_reset_chip(dws); |
e24c7452 FT |
220 | |
221 | dev_err(&dws->master->dev, "%s\n", msg); | |
c22c62db AS |
222 | dws->master->cur_msg->status = -EIO; |
223 | spi_finalize_current_transfer(dws->master); | |
e24c7452 FT |
224 | } |
225 | ||
e24c7452 FT |
226 | static irqreturn_t interrupt_transfer(struct dw_spi *dws) |
227 | { | |
dd114443 | 228 | u16 irq_status = dw_readl(dws, DW_SPI_ISR); |
e24c7452 | 229 | |
e24c7452 FT |
230 | /* Error handling */ |
231 | if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) { | |
dd114443 | 232 | dw_readl(dws, DW_SPI_ICR); |
3b8a4dd3 | 233 | int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun"); |
e24c7452 FT |
234 | return IRQ_HANDLED; |
235 | } | |
236 | ||
3b8a4dd3 AD |
237 | dw_reader(dws); |
238 | if (dws->rx_end == dws->rx) { | |
239 | spi_mask_intr(dws, SPI_INT_TXEI); | |
c22c62db | 240 | spi_finalize_current_transfer(dws->master); |
3b8a4dd3 AD |
241 | return IRQ_HANDLED; |
242 | } | |
552e4509 FT |
243 | if (irq_status & SPI_INT_TXEI) { |
244 | spi_mask_intr(dws, SPI_INT_TXEI); | |
3b8a4dd3 AD |
245 | dw_writer(dws); |
246 | /* Enable TX irq always, it will be disabled when RX finished */ | |
247 | spi_umask_intr(dws, SPI_INT_TXEI); | |
e24c7452 FT |
248 | } |
249 | ||
e24c7452 FT |
250 | return IRQ_HANDLED; |
251 | } | |
252 | ||
253 | static irqreturn_t dw_spi_irq(int irq, void *dev_id) | |
254 | { | |
c22c62db AS |
255 | struct spi_master *master = dev_id; |
256 | struct dw_spi *dws = spi_master_get_devdata(master); | |
dd114443 | 257 | u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f; |
cbcc062a | 258 | |
cbcc062a YW |
259 | if (!irq_status) |
260 | return IRQ_NONE; | |
e24c7452 | 261 | |
c22c62db | 262 | if (!master->cur_msg) { |
e24c7452 | 263 | spi_mask_intr(dws, SPI_INT_TXEI); |
e24c7452 FT |
264 | return IRQ_HANDLED; |
265 | } | |
266 | ||
267 | return dws->transfer_handler(dws); | |
268 | } | |
269 | ||
270 | /* Must be called inside pump_transfers() */ | |
c22c62db | 271 | static int poll_transfer(struct dw_spi *dws) |
e24c7452 | 272 | { |
2ff271bf AD |
273 | do { |
274 | dw_writer(dws); | |
de6efe0a | 275 | dw_reader(dws); |
2ff271bf AD |
276 | cpu_relax(); |
277 | } while (dws->rx_end > dws->rx); | |
e24c7452 | 278 | |
c22c62db | 279 | return 0; |
e24c7452 FT |
280 | } |
281 | ||
c22c62db AS |
282 | static int dw_spi_transfer_one(struct spi_master *master, |
283 | struct spi_device *spi, struct spi_transfer *transfer) | |
e24c7452 | 284 | { |
c22c62db AS |
285 | struct dw_spi *dws = spi_master_get_devdata(master); |
286 | struct chip_data *chip = spi_get_ctldata(spi); | |
e24c7452 | 287 | u8 imask = 0; |
ea11370f | 288 | u16 txlevel = 0; |
4adb1f8f | 289 | u32 cr0; |
9f14538e | 290 | int ret; |
e24c7452 | 291 | |
f89a6d8f | 292 | dws->dma_mapped = 0; |
e24c7452 | 293 | |
e24c7452 FT |
294 | dws->tx = (void *)transfer->tx_buf; |
295 | dws->tx_end = dws->tx + transfer->len; | |
296 | dws->rx = transfer->rx_buf; | |
297 | dws->rx_end = dws->rx + transfer->len; | |
c22c62db | 298 | dws->len = transfer->len; |
e24c7452 | 299 | |
0b2e8915 AS |
300 | spi_enable_chip(dws, 0); |
301 | ||
e24c7452 | 302 | /* Handle per transfer options for bpw and speed */ |
13b10301 MS |
303 | if (transfer->speed_hz != dws->current_freq) { |
304 | if (transfer->speed_hz != chip->speed_hz) { | |
305 | /* clk_div doesn't support odd number */ | |
3aef4632 | 306 | chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe; |
13b10301 MS |
307 | chip->speed_hz = transfer->speed_hz; |
308 | } | |
309 | dws->current_freq = transfer->speed_hz; | |
0ed36990 | 310 | spi_set_clk(dws, chip->clk_div); |
e24c7452 | 311 | } |
0ed36990 JN |
312 | if (transfer->bits_per_word == 8) { |
313 | dws->n_bytes = 1; | |
314 | dws->dma_width = 1; | |
315 | } else if (transfer->bits_per_word == 16) { | |
316 | dws->n_bytes = 2; | |
317 | dws->dma_width = 2; | |
863cb2f7 AS |
318 | } else { |
319 | return -EINVAL; | |
e24c7452 | 320 | } |
4adb1f8f | 321 | /* Default SPI mode is SCPOL = 0, SCPH = 0 */ |
0ed36990 JN |
322 | cr0 = (transfer->bits_per_word - 1) |
323 | | (chip->type << SPI_FRF_OFFSET) | |
324 | | (spi->mode << SPI_MODE_OFFSET) | |
325 | | (chip->tmode << SPI_TMOD_OFFSET); | |
e24c7452 | 326 | |
052dc7c4 GS |
327 | /* |
328 | * Adjust transfer mode if necessary. Requires platform dependent | |
329 | * chipselect mechanism. | |
330 | */ | |
c22c62db | 331 | if (chip->cs_control) { |
052dc7c4 | 332 | if (dws->rx && dws->tx) |
e3e55ff5 | 333 | chip->tmode = SPI_TMOD_TR; |
052dc7c4 | 334 | else if (dws->rx) |
e3e55ff5 | 335 | chip->tmode = SPI_TMOD_RO; |
052dc7c4 | 336 | else |
e3e55ff5 | 337 | chip->tmode = SPI_TMOD_TO; |
052dc7c4 | 338 | |
e3e55ff5 | 339 | cr0 &= ~SPI_TMOD_MASK; |
052dc7c4 GS |
340 | cr0 |= (chip->tmode << SPI_TMOD_OFFSET); |
341 | } | |
342 | ||
dd114443 | 343 | dw_writel(dws, DW_SPI_CTRL0, cr0); |
0b2e8915 | 344 | |
e24c7452 | 345 | /* Check if current transfer is a DMA transaction */ |
f89a6d8f AS |
346 | if (master->can_dma && master->can_dma(master, spi, transfer)) |
347 | dws->dma_mapped = master->cur_msg_mapped; | |
e24c7452 | 348 | |
0b2e8915 AS |
349 | /* For poll mode just disable all interrupts */ |
350 | spi_mask_intr(dws, 0xff); | |
351 | ||
552e4509 FT |
352 | /* |
353 | * Interrupt mode | |
354 | * we only need set the TXEI IRQ, as TX/RX always happen syncronizely | |
355 | */ | |
9f14538e | 356 | if (dws->dma_mapped) { |
f89a6d8f | 357 | ret = dws->dma_ops->dma_setup(dws, transfer); |
9f14538e AS |
358 | if (ret < 0) { |
359 | spi_enable_chip(dws, 1); | |
360 | return ret; | |
361 | } | |
362 | } else if (!chip->poll_mode) { | |
ea11370f | 363 | txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes); |
dd114443 | 364 | dw_writel(dws, DW_SPI_TXFLTR, txlevel); |
552e4509 | 365 | |
0b2e8915 | 366 | /* Set the interrupt mask */ |
fadcace7 JH |
367 | imask |= SPI_INT_TXEI | SPI_INT_TXOI | |
368 | SPI_INT_RXUI | SPI_INT_RXOI; | |
0b2e8915 AS |
369 | spi_umask_intr(dws, imask); |
370 | ||
e24c7452 FT |
371 | dws->transfer_handler = interrupt_transfer; |
372 | } | |
373 | ||
0b2e8915 | 374 | spi_enable_chip(dws, 1); |
e24c7452 | 375 | |
9f14538e | 376 | if (dws->dma_mapped) { |
f89a6d8f | 377 | ret = dws->dma_ops->dma_transfer(dws, transfer); |
9f14538e AS |
378 | if (ret < 0) |
379 | return ret; | |
380 | } | |
e24c7452 FT |
381 | |
382 | if (chip->poll_mode) | |
c22c62db | 383 | return poll_transfer(dws); |
e24c7452 | 384 | |
c22c62db | 385 | return 1; |
e24c7452 FT |
386 | } |
387 | ||
c22c62db | 388 | static void dw_spi_handle_err(struct spi_master *master, |
ec37e8e1 | 389 | struct spi_message *msg) |
e24c7452 | 390 | { |
ec37e8e1 | 391 | struct dw_spi *dws = spi_master_get_devdata(master); |
e24c7452 | 392 | |
4d5ac1ed AS |
393 | if (dws->dma_mapped) |
394 | dws->dma_ops->dma_stop(dws); | |
395 | ||
c22c62db | 396 | spi_reset_chip(dws); |
e24c7452 FT |
397 | } |
398 | ||
399 | /* This may be called twice for each spi dev */ | |
400 | static int dw_spi_setup(struct spi_device *spi) | |
401 | { | |
402 | struct dw_spi_chip *chip_info = NULL; | |
403 | struct chip_data *chip; | |
d9c73bb8 | 404 | int ret; |
e24c7452 | 405 | |
e24c7452 FT |
406 | /* Only alloc on first setup */ |
407 | chip = spi_get_ctldata(spi); | |
408 | if (!chip) { | |
a97c883a | 409 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
e24c7452 FT |
410 | if (!chip) |
411 | return -ENOMEM; | |
43f627ac | 412 | spi_set_ctldata(spi, chip); |
e24c7452 FT |
413 | } |
414 | ||
415 | /* | |
416 | * Protocol drivers may change the chip settings, so... | |
417 | * if chip_info exists, use it | |
418 | */ | |
419 | chip_info = spi->controller_data; | |
420 | ||
421 | /* chip_info doesn't always exist */ | |
422 | if (chip_info) { | |
423 | if (chip_info->cs_control) | |
424 | chip->cs_control = chip_info->cs_control; | |
425 | ||
426 | chip->poll_mode = chip_info->poll_mode; | |
427 | chip->type = chip_info->type; | |
e24c7452 FT |
428 | } |
429 | ||
6096828e | 430 | chip->tmode = SPI_TMOD_TR; |
c3ce15bf | 431 | |
d9c73bb8 BS |
432 | if (gpio_is_valid(spi->cs_gpio)) { |
433 | ret = gpio_direction_output(spi->cs_gpio, | |
434 | !(spi->mode & SPI_CS_HIGH)); | |
435 | if (ret) | |
436 | return ret; | |
437 | } | |
438 | ||
e24c7452 FT |
439 | return 0; |
440 | } | |
441 | ||
a97c883a AL |
442 | static void dw_spi_cleanup(struct spi_device *spi) |
443 | { | |
444 | struct chip_data *chip = spi_get_ctldata(spi); | |
445 | ||
446 | kfree(chip); | |
447 | spi_set_ctldata(spi, NULL); | |
448 | } | |
449 | ||
e24c7452 | 450 | /* Restart the controller, disable all interrupts, clean rx fifo */ |
30b4b703 | 451 | static void spi_hw_init(struct device *dev, struct dw_spi *dws) |
e24c7452 | 452 | { |
45746e82 | 453 | spi_reset_chip(dws); |
c587b6fa FT |
454 | |
455 | /* | |
456 | * Try to detect the FIFO depth if not set by interface driver, | |
457 | * the depth could be from 2 to 256 from HW spec | |
458 | */ | |
459 | if (!dws->fifo_len) { | |
460 | u32 fifo; | |
fadcace7 | 461 | |
9d239d35 | 462 | for (fifo = 1; fifo < 256; fifo++) { |
dd114443 TT |
463 | dw_writel(dws, DW_SPI_TXFLTR, fifo); |
464 | if (fifo != dw_readl(dws, DW_SPI_TXFLTR)) | |
c587b6fa FT |
465 | break; |
466 | } | |
dd114443 | 467 | dw_writel(dws, DW_SPI_TXFLTR, 0); |
c587b6fa | 468 | |
9d239d35 | 469 | dws->fifo_len = (fifo == 1) ? 0 : fifo; |
30b4b703 | 470 | dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); |
c587b6fa | 471 | } |
e24c7452 FT |
472 | } |
473 | ||
04f421e7 | 474 | int dw_spi_add_host(struct device *dev, struct dw_spi *dws) |
e24c7452 FT |
475 | { |
476 | struct spi_master *master; | |
477 | int ret; | |
478 | ||
479 | BUG_ON(dws == NULL); | |
480 | ||
04f421e7 BS |
481 | master = spi_alloc_master(dev, 0); |
482 | if (!master) | |
483 | return -ENOMEM; | |
e24c7452 FT |
484 | |
485 | dws->master = master; | |
486 | dws->type = SSI_MOTO_SPI; | |
e24c7452 | 487 | dws->dma_inited = 0; |
d7ef54ca | 488 | dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR); |
c3c6e231 | 489 | snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num); |
e24c7452 | 490 | |
02f20387 | 491 | ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dws->name, master); |
e24c7452 | 492 | if (ret < 0) { |
5f0966e6 | 493 | dev_err(dev, "can not get IRQ\n"); |
e24c7452 FT |
494 | goto err_free_master; |
495 | } | |
496 | ||
c3ce15bf | 497 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; |
24778be2 | 498 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); |
e24c7452 FT |
499 | master->bus_num = dws->bus_num; |
500 | master->num_chipselect = dws->num_cs; | |
e24c7452 | 501 | master->setup = dw_spi_setup; |
a97c883a | 502 | master->cleanup = dw_spi_cleanup; |
c22c62db AS |
503 | master->set_cs = dw_spi_set_cs; |
504 | master->transfer_one = dw_spi_transfer_one; | |
505 | master->handle_err = dw_spi_handle_err; | |
765ee709 | 506 | master->max_speed_hz = dws->max_freq; |
9c6de47d | 507 | master->dev.of_node = dev->of_node; |
80b444e5 | 508 | master->flags = SPI_MASTER_GPIO_SS; |
e24c7452 | 509 | |
e24c7452 | 510 | /* Basic HW init */ |
30b4b703 | 511 | spi_hw_init(dev, dws); |
e24c7452 | 512 | |
7063c0d9 FT |
513 | if (dws->dma_ops && dws->dma_ops->dma_init) { |
514 | ret = dws->dma_ops->dma_init(dws); | |
515 | if (ret) { | |
3dbb3b98 | 516 | dev_warn(dev, "DMA init failed\n"); |
7063c0d9 | 517 | dws->dma_inited = 0; |
f89a6d8f AS |
518 | } else { |
519 | master->can_dma = dws->dma_ops->can_dma; | |
7063c0d9 FT |
520 | } |
521 | } | |
522 | ||
e24c7452 | 523 | spi_master_set_devdata(master, dws); |
04f421e7 | 524 | ret = devm_spi_register_master(dev, master); |
e24c7452 FT |
525 | if (ret) { |
526 | dev_err(&master->dev, "problem registering spi master\n"); | |
ec37e8e1 | 527 | goto err_dma_exit; |
e24c7452 FT |
528 | } |
529 | ||
53288fe9 | 530 | dw_spi_debugfs_init(dws); |
e24c7452 FT |
531 | return 0; |
532 | ||
ec37e8e1 | 533 | err_dma_exit: |
7063c0d9 FT |
534 | if (dws->dma_ops && dws->dma_ops->dma_exit) |
535 | dws->dma_ops->dma_exit(dws); | |
e24c7452 | 536 | spi_enable_chip(dws, 0); |
02f20387 | 537 | free_irq(dws->irq, master); |
e24c7452 FT |
538 | err_free_master: |
539 | spi_master_put(master); | |
e24c7452 FT |
540 | return ret; |
541 | } | |
79290a2a | 542 | EXPORT_SYMBOL_GPL(dw_spi_add_host); |
e24c7452 | 543 | |
fd4a319b | 544 | void dw_spi_remove_host(struct dw_spi *dws) |
e24c7452 | 545 | { |
53288fe9 | 546 | dw_spi_debugfs_remove(dws); |
e24c7452 | 547 | |
7063c0d9 FT |
548 | if (dws->dma_ops && dws->dma_ops->dma_exit) |
549 | dws->dma_ops->dma_exit(dws); | |
1cc3f141 AS |
550 | |
551 | spi_shutdown_chip(dws); | |
02f20387 AS |
552 | |
553 | free_irq(dws->irq, dws->master); | |
e24c7452 | 554 | } |
79290a2a | 555 | EXPORT_SYMBOL_GPL(dw_spi_remove_host); |
e24c7452 FT |
556 | |
557 | int dw_spi_suspend_host(struct dw_spi *dws) | |
558 | { | |
1cc3f141 | 559 | int ret; |
e24c7452 | 560 | |
ec37e8e1 | 561 | ret = spi_master_suspend(dws->master); |
e24c7452 FT |
562 | if (ret) |
563 | return ret; | |
1cc3f141 AS |
564 | |
565 | spi_shutdown_chip(dws); | |
566 | return 0; | |
e24c7452 | 567 | } |
79290a2a | 568 | EXPORT_SYMBOL_GPL(dw_spi_suspend_host); |
e24c7452 FT |
569 | |
570 | int dw_spi_resume_host(struct dw_spi *dws) | |
571 | { | |
572 | int ret; | |
573 | ||
30b4b703 | 574 | spi_hw_init(&dws->master->dev, dws); |
ec37e8e1 | 575 | ret = spi_master_resume(dws->master); |
e24c7452 FT |
576 | if (ret) |
577 | dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret); | |
578 | return ret; | |
579 | } | |
79290a2a | 580 | EXPORT_SYMBOL_GPL(dw_spi_resume_host); |
e24c7452 FT |
581 | |
582 | MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>"); | |
583 | MODULE_DESCRIPTION("Driver for DesignWare SPI controller core"); | |
584 | MODULE_LICENSE("GPL v2"); |