[mirror_ubuntu-focal-kernel.git] / drivers / spi / spi-dw.c

/*
 * Designware SPI core controller driver (refer pxa2xx_spi.c)
 *
 * Copyright (c) 2009, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/highmem.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/gpio.h>

#include "spi-dw.h"

#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
#endif

/* Slave spi_dev related */
struct chip_data {
	u8 tmode;		/* TR/TO/RO/EEPROM */
	u8 type;		/* SPI/SSP/MicroWire */

	u8 poll_mode;		/* 1 means use poll mode */

	u16 clk_div;		/* baud rate divider */
	u32 speed_hz;		/* baud rate */
	void (*cs_control)(u32 command);
};

#ifdef CONFIG_DEBUG_FS
#define SPI_REGS_BUFSIZE	1024
static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
		size_t count, loff_t *ppos)
{
	struct dw_spi *dws = file->private_data;
	char *buf;
	u32 len = 0;
	ssize_t ret;

	buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
	if (!buf)
		return 0;

	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
			"%s registers:\n", dev_name(&dws->master->dev));
	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
			"=================================\n");
	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
			"CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
			"CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
			"SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
			"SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
			"BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
			"TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
			"RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
			"TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
			"RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
			"SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
			"IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
			"ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
			"DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
			"DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
			"DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
			"=================================\n");

	ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
	kfree(buf);
	return ret;
}

static const struct file_operations dw_spi_regs_ops = {
	.owner		= THIS_MODULE,
	.open		= simple_open,
	.read		= dw_spi_show_regs,
	.llseek		= default_llseek,
};

static int dw_spi_debugfs_init(struct dw_spi *dws)
{
	char name[32];

	snprintf(name, 32, "dw_spi%d", dws->master->bus_num);
	dws->debugfs = debugfs_create_dir(name, NULL);
	if (!dws->debugfs)
		return -ENOMEM;

	debugfs_create_file("registers", S_IFREG | S_IRUGO,
		dws->debugfs, (void *)dws, &dw_spi_regs_ops);
	return 0;
}

static void dw_spi_debugfs_remove(struct dw_spi *dws)
{
	debugfs_remove_recursive(dws->debugfs);
}

#else
static inline int dw_spi_debugfs_init(struct dw_spi *dws)
{
	return 0;
}

static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
{
}
#endif /* CONFIG_DEBUG_FS */

void dw_spi_set_cs(struct spi_device *spi, bool enable)
{
	struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
	struct chip_data *chip = spi_get_ctldata(spi);

	/* Chip select logic is inverted from spi_set_cs() */
	if (chip && chip->cs_control)
		chip->cs_control(!enable);

	if (!enable)
		dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
	else if (dws->cs_override)
		dw_writel(dws, DW_SPI_SER, 0);
}
EXPORT_SYMBOL_GPL(dw_spi_set_cs);

/* Return the max entries we can fill into tx fifo */
static inline u32 tx_max(struct dw_spi *dws)
{
	u32 tx_left, tx_room, rxtx_gap;

	tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
	tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);

	/*
	 * Another concern is about the tx/rx mismatch, we
	 * though to use (dws->fifo_len - rxflr - txflr) as
	 * one maximum value for tx, but it doesn't cover the
	 * data which is out of tx/rx fifo and inside the
	 * shift registers. So a control from sw point of
	 * view is taken.
	 */
	rxtx_gap =  ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
			/ dws->n_bytes;

	return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
}

/* Return the max entries we should read out of rx fifo */
static inline u32 rx_max(struct dw_spi *dws)
{
	u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;

	return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
}

static void dw_writer(struct dw_spi *dws)
{
	u32 max = tx_max(dws);
	u16 txw = 0;

	while (max--) {
		/* Set the tx word if the transfer's original "tx" is not null */
		if (dws->tx_end - dws->len) {
			if (dws->n_bytes == 1)
				txw = *(u8 *)(dws->tx);
			else
				txw = *(u16 *)(dws->tx);
		}
		dw_write_io_reg(dws, DW_SPI_DR, txw);
		dws->tx += dws->n_bytes;
	}
}

static void dw_reader(struct dw_spi *dws)
{
	u32 max = rx_max(dws);
	u16 rxw;

	while (max--) {
		rxw = dw_read_io_reg(dws, DW_SPI_DR);
		/* Care rx only if the transfer's original "rx" is not null */
		if (dws->rx_end - dws->len) {
			if (dws->n_bytes == 1)
				*(u8 *)(dws->rx) = rxw;
			else
				*(u16 *)(dws->rx) = rxw;
		}
		dws->rx += dws->n_bytes;
	}
}

static void int_error_stop(struct dw_spi *dws, const char *msg)
{
	spi_reset_chip(dws);

	dev_err(&dws->master->dev, "%s\n", msg);
	dws->master->cur_msg->status = -EIO;
	spi_finalize_current_transfer(dws->master);
}

static irqreturn_t interrupt_transfer(struct dw_spi *dws)
{
	u16 irq_status = dw_readl(dws, DW_SPI_ISR);

	/* Error handling */
	if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
		dw_readl(dws, DW_SPI_ICR);
		int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
		return IRQ_HANDLED;
	}

	dw_reader(dws);
	if (dws->rx_end == dws->rx) {
		spi_mask_intr(dws, SPI_INT_TXEI);
		spi_finalize_current_transfer(dws->master);
		return IRQ_HANDLED;
	}
	if (irq_status & SPI_INT_TXEI) {
		spi_mask_intr(dws, SPI_INT_TXEI);
		dw_writer(dws);
		/* Enable TX irq always, it will be disabled when RX finished */
		spi_umask_intr(dws, SPI_INT_TXEI);
	}

	return IRQ_HANDLED;
}

static irqreturn_t dw_spi_irq(int irq, void *dev_id)
{
	struct spi_controller *master = dev_id;
	struct dw_spi *dws = spi_controller_get_devdata(master);
	u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;

	if (!irq_status)
		return IRQ_NONE;

	if (!master->cur_msg) {
		spi_mask_intr(dws, SPI_INT_TXEI);
		return IRQ_HANDLED;
	}

	return dws->transfer_handler(dws);
}

/* Must be called inside pump_transfers() */
static int poll_transfer(struct dw_spi *dws)
{
	do {
		dw_writer(dws);
		dw_reader(dws);
		cpu_relax();
	} while (dws->rx_end > dws->rx);

	return 0;
}

static int dw_spi_transfer_one(struct spi_controller *master,
		struct spi_device *spi, struct spi_transfer *transfer)
{
	struct dw_spi *dws = spi_controller_get_devdata(master);
	struct chip_data *chip = spi_get_ctldata(spi);
	u8 imask = 0;
	u16 txlevel = 0;
	u32 cr0;
	int ret;

	dws->dma_mapped = 0;

	dws->tx = (void *)transfer->tx_buf;
	dws->tx_end = dws->tx + transfer->len;
	dws->rx = transfer->rx_buf;
	dws->rx_end = dws->rx + transfer->len;
	dws->len = transfer->len;

	spi_enable_chip(dws, 0);

	/* Handle per transfer options for bpw and speed */
	if (transfer->speed_hz != dws->current_freq) {
		if (transfer->speed_hz != chip->speed_hz) {
			/* clk_div doesn't support odd number */
			chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe;
			chip->speed_hz = transfer->speed_hz;
		}
		dws->current_freq = transfer->speed_hz;
		spi_set_clk(dws, chip->clk_div);
	}

	dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
	dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);

	/* Default SPI mode is SCPOL = 0, SCPH = 0 */
	cr0 = (transfer->bits_per_word - 1)
		| (chip->type << SPI_FRF_OFFSET)
		| (spi->mode << SPI_MODE_OFFSET)
		| (chip->tmode << SPI_TMOD_OFFSET);

	/*
	 * Adjust transfer mode if necessary. Requires platform dependent
	 * chipselect mechanism.
	 */
	if (chip->cs_control) {
		if (dws->rx && dws->tx)
			chip->tmode = SPI_TMOD_TR;
		else if (dws->rx)
			chip->tmode = SPI_TMOD_RO;
		else
			chip->tmode = SPI_TMOD_TO;

		cr0 &= ~SPI_TMOD_MASK;
		cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
	}

	dw_writel(dws, DW_SPI_CTRL0, cr0);

	/* Check if current transfer is a DMA transaction */
	if (master->can_dma && master->can_dma(master, spi, transfer))
		dws->dma_mapped = master->cur_msg_mapped;

	/* For poll mode just disable all interrupts */
	spi_mask_intr(dws, 0xff);

	/*
	 * Interrupt mode
	 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
	 */
	if (dws->dma_mapped) {
		ret = dws->dma_ops->dma_setup(dws, transfer);
		if (ret < 0) {
			spi_enable_chip(dws, 1);
			return ret;
		}
	} else if (!chip->poll_mode) {
		txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
		dw_writel(dws, DW_SPI_TXFLTR, txlevel);

		/* Set the interrupt mask */
		imask |= SPI_INT_TXEI | SPI_INT_TXOI |
			 SPI_INT_RXUI | SPI_INT_RXOI;
		spi_umask_intr(dws, imask);

		dws->transfer_handler = interrupt_transfer;
	}

	spi_enable_chip(dws, 1);

	if (dws->dma_mapped) {
		ret = dws->dma_ops->dma_transfer(dws, transfer);
		if (ret < 0)
			return ret;
	}

	if (chip->poll_mode)
		return poll_transfer(dws);

	return 1;
}

static void dw_spi_handle_err(struct spi_controller *master,
		struct spi_message *msg)
{
	struct dw_spi *dws = spi_controller_get_devdata(master);

	if (dws->dma_mapped)
		dws->dma_ops->dma_stop(dws);

	spi_reset_chip(dws);
}

/* This may be called twice for each spi dev */
static int dw_spi_setup(struct spi_device *spi)
{
	struct dw_spi_chip *chip_info = NULL;
	struct chip_data *chip;
	int ret;

	/* Only alloc on first setup */
	chip = spi_get_ctldata(spi);
	if (!chip) {
		chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
		if (!chip)
			return -ENOMEM;
		spi_set_ctldata(spi, chip);
	}

	/*
	 * Protocol drivers may change the chip settings, so...
	 * if chip_info exists, use it
	 */
	chip_info = spi->controller_data;

	/* chip_info doesn't always exist */
	if (chip_info) {
		if (chip_info->cs_control)
			chip->cs_control = chip_info->cs_control;

		chip->poll_mode = chip_info->poll_mode;
		chip->type = chip_info->type;
	}

	chip->tmode = SPI_TMOD_TR;

	if (gpio_is_valid(spi->cs_gpio)) {
		ret = gpio_direction_output(spi->cs_gpio,
				!(spi->mode & SPI_CS_HIGH));
		if (ret)
			return ret;
	}

	return 0;
}

static void dw_spi_cleanup(struct spi_device *spi)
{
	struct chip_data *chip = spi_get_ctldata(spi);

	kfree(chip);
	spi_set_ctldata(spi, NULL);
}

/* Restart the controller, disable all interrupts, clean rx fifo */
static void spi_hw_init(struct device *dev, struct dw_spi *dws)
{
	spi_reset_chip(dws);

	/*
	 * Try to detect the FIFO depth if not set by interface driver,
	 * the depth could be from 2 to 256 from HW spec
	 */
	if (!dws->fifo_len) {
		u32 fifo;

		for (fifo = 1; fifo < 256; fifo++) {
			dw_writel(dws, DW_SPI_TXFLTR, fifo);
			if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
				break;
		}
		dw_writel(dws, DW_SPI_TXFLTR, 0);

		dws->fifo_len = (fifo == 1) ? 0 : fifo;
		dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
	}

	/* enable HW fixup for explicit CS deselect for Amazon's alpine chip */
	if (dws->cs_override)
		dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF);
}

int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
{
	struct spi_controller *master;
	int ret;

	BUG_ON(dws == NULL);

	master = spi_alloc_master(dev, 0);
	if (!master)
		return -ENOMEM;

	dws->master = master;
	dws->type = SSI_MOTO_SPI;
	dws->dma_inited = 0;
	dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);

	spi_controller_set_devdata(master, dws);

	ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
			  master);
	if (ret < 0) {
		dev_err(dev, "can not get IRQ\n");
		goto err_free_master;
	}

	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
	master->bits_per_word_mask =  SPI_BPW_RANGE_MASK(4, 16);
	master->bus_num = dws->bus_num;
	master->num_chipselect = dws->num_cs;
	master->setup = dw_spi_setup;
	master->cleanup = dw_spi_cleanup;
	master->set_cs = dw_spi_set_cs;
	master->transfer_one = dw_spi_transfer_one;
	master->handle_err = dw_spi_handle_err;
	master->max_speed_hz = dws->max_freq;
	master->dev.of_node = dev->of_node;
	master->flags = SPI_MASTER_GPIO_SS;

	if (dws->set_cs)
		master->set_cs = dws->set_cs;

	/* Basic HW init */
	spi_hw_init(dev, dws);

	if (dws->dma_ops && dws->dma_ops->dma_init) {
		ret = dws->dma_ops->dma_init(dws);
		if (ret) {
			dev_warn(dev, "DMA init failed\n");
			dws->dma_inited = 0;
		} else {
			master->can_dma = dws->dma_ops->can_dma;
		}
	}

	ret = devm_spi_register_controller(dev, master);
	if (ret) {
		dev_err(&master->dev, "problem registering spi master\n");
		goto err_dma_exit;
	}

	dw_spi_debugfs_init(dws);
	return 0;

err_dma_exit:
	if (dws->dma_ops && dws->dma_ops->dma_exit)
		dws->dma_ops->dma_exit(dws);
	spi_enable_chip(dws, 0);
	free_irq(dws->irq, master);
err_free_master:
	spi_controller_put(master);
	return ret;
}
EXPORT_SYMBOL_GPL(dw_spi_add_host);

void dw_spi_remove_host(struct dw_spi *dws)
{
	dw_spi_debugfs_remove(dws);

	if (dws->dma_ops && dws->dma_ops->dma_exit)
		dws->dma_ops->dma_exit(dws);

	spi_shutdown_chip(dws);

	free_irq(dws->irq, dws->master);
}
EXPORT_SYMBOL_GPL(dw_spi_remove_host);

int dw_spi_suspend_host(struct dw_spi *dws)
{
	int ret;

	ret = spi_controller_suspend(dws->master);
	if (ret)
		return ret;

	spi_shutdown_chip(dws);
	return 0;
}
EXPORT_SYMBOL_GPL(dw_spi_suspend_host);

int dw_spi_resume_host(struct dw_spi *dws)
{
	spi_hw_init(&dws->master->dev, dws);
	return spi_controller_resume(dws->master);
}
EXPORT_SYMBOL_GPL(dw_spi_resume_host);

MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
e24c7452	1	/*
ca632f55	2	* Designware SPI core controller driver (refer pxa2xx_spi.c)
e24c7452 FT	3	*
	4	* Copyright (c) 2009, Intel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
e24c7452 FT	14	*/
	15
	16	#include <linux/dma-mapping.h>
	17	#include <linux/interrupt.h>
d7614de4	18	#include <linux/module.h>
e24c7452 FT	19	#include <linux/highmem.h>
e24c7452 FT	20	#include <linux/delay.h>
5a0e3ad6	21	#include <linux/slab.h>
e24c7452	22	#include <linux/spi/spi.h>
d9c73bb8	23	#include <linux/gpio.h>
e24c7452	24
ca632f55	25	#include "spi-dw.h"
568a60ed	26
e24c7452 FT	27	#ifdef CONFIG_DEBUG_FS
	28	#include <linux/debugfs.h>
	29	#endif
	30
e24c7452 FT	31	/* Slave spi_dev related */
e24c7452 FT	32	struct chip_data {
e24c7452 FT	33	u8 tmode; /* TR/TO/RO/EEPROM */
	34	u8 type; /* SPI/SSP/MicroWire */
	35
	36	u8 poll_mode; /* 1 means use poll mode */
	37
e24c7452 FT	38	u16 clk_div; /* baud rate divider */
e24c7452 FT	39	u32 speed_hz; /* baud rate */
e24c7452 FT	40	void (*cs_control)(u32 command);
	41	};
	42
	43	#ifdef CONFIG_DEBUG_FS
e24c7452	44	#define SPI_REGS_BUFSIZE 1024
53288fe9 AS	45	static ssize_t dw_spi_show_regs(struct file file, char __user user_buf,
53288fe9 AS	46	size_t count, loff_t *ppos)
e24c7452	47	{
53288fe9	48	struct dw_spi *dws = file->private_data;
e24c7452 FT	49	char *buf;
	50	u32 len = 0;
	51	ssize_t ret;
	52
e24c7452 FT	53	buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
	54	if (!buf)
	55	return 0;
	56
	57	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
53288fe9	58	"%s registers:\n", dev_name(&dws->master->dev));
e24c7452 FT	59	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
	60	"=================================\n");
	61	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3	62	"CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
e24c7452	63	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3	64	"CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
e24c7452	65	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3	66	"SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
e24c7452	67	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3	68	"SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
e24c7452	69	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3	70	"BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
e24c7452	71	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3	72	"TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
e24c7452	73	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3	74	"RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
e24c7452	75	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3	76	"TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
e24c7452	77	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3	78	"RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
e24c7452	79	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3	80	"SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
e24c7452	81	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3	82	"IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
e24c7452	83	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3	84	"ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
e24c7452	85	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3	86	"DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
e24c7452	87	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3	88	"DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
e24c7452	89	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3	90	"DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
e24c7452 FT	91	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
	92	"=================================\n");
	93
53288fe9	94	ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
e24c7452 FT	95	kfree(buf);
	96	return ret;
	97	}
	98
53288fe9	99	static const struct file_operations dw_spi_regs_ops = {
e24c7452	100	.owner = THIS_MODULE,
234e3405	101	.open = simple_open,
53288fe9	102	.read = dw_spi_show_regs,
6038f373	103	.llseek = default_llseek,
e24c7452 FT	104	};
e24c7452 FT	105
53288fe9	106	static int dw_spi_debugfs_init(struct dw_spi *dws)
e24c7452	107	{
e70002c8	108	char name[32];
13288bdf	109
e70002c8	110	snprintf(name, 32, "dw_spi%d", dws->master->bus_num);
13288bdf	111	dws->debugfs = debugfs_create_dir(name, NULL);
e24c7452 FT	112	if (!dws->debugfs)
	113	return -ENOMEM;
	114
	115	debugfs_create_file("registers", S_IFREG \| S_IRUGO,
53288fe9	116	dws->debugfs, (void *)dws, &dw_spi_regs_ops);
e24c7452 FT	117	return 0;
	118	}
	119
53288fe9	120	static void dw_spi_debugfs_remove(struct dw_spi *dws)
e24c7452	121	{
fadcace7	122	debugfs_remove_recursive(dws->debugfs);
e24c7452 FT	123	}
	124
	125	#else
53288fe9	126	static inline int dw_spi_debugfs_init(struct dw_spi *dws)
e24c7452	127	{
20a588fc	128	return 0;
e24c7452 FT	129	}
e24c7452 FT	130
53288fe9	131	static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
e24c7452 FT	132	{
	133	}
	134	#endif /* CONFIG_DEBUG_FS */
	135
c79bdbb4	136	void dw_spi_set_cs(struct spi_device *spi, bool enable)
c22c62db	137	{
721483e2	138	struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
c22c62db AS	139	struct chip_data *chip = spi_get_ctldata(spi);
	140
	141	/* Chip select logic is inverted from spi_set_cs() */
207cda93	142	if (chip && chip->cs_control)
c22c62db AS	143	chip->cs_control(!enable);
	144
	145	if (!enable)
	146	dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
f2d70479 TS	147	else if (dws->cs_override)
f2d70479 TS	148	dw_writel(dws, DW_SPI_SER, 0);
c22c62db	149	}
c79bdbb4	150	EXPORT_SYMBOL_GPL(dw_spi_set_cs);
c22c62db	151
2ff271bf AD	152	/* Return the max entries we can fill into tx fifo */
	153	static inline u32 tx_max(struct dw_spi *dws)
	154	{
	155	u32 tx_left, tx_room, rxtx_gap;
	156
	157	tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
dd114443	158	tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
2ff271bf AD	159
	160	/*
	161	* Another concern is about the tx/rx mismatch, we
	162	* though to use (dws->fifo_len - rxflr - txflr) as
	163	* one maximum value for tx, but it doesn't cover the
	164	* data which is out of tx/rx fifo and inside the
	165	* shift registers. So a control from sw point of
	166	* view is taken.
	167	*/
	168	rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
	169	/ dws->n_bytes;
	170
	171	return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
	172	}
	173
	174	/* Return the max entries we should read out of rx fifo */
	175	static inline u32 rx_max(struct dw_spi *dws)
	176	{
	177	u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
	178
dd114443	179	return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
2ff271bf AD	180	}
2ff271bf AD	181
3b8a4dd3	182	static void dw_writer(struct dw_spi *dws)
e24c7452	183	{
2ff271bf	184	u32 max = tx_max(dws);
de6efe0a	185	u16 txw = 0;
e24c7452	186
2ff271bf AD	187	while (max--) {
	188	/* Set the tx word if the transfer's original "tx" is not null */
	189	if (dws->tx_end - dws->len) {
	190	if (dws->n_bytes == 1)
	191	txw = (u8 )(dws->tx);
	192	else
	193	txw = (u16 )(dws->tx);
	194	}
c4fe57f7	195	dw_write_io_reg(dws, DW_SPI_DR, txw);
2ff271bf	196	dws->tx += dws->n_bytes;
e24c7452	197	}
e24c7452 FT	198	}
e24c7452 FT	199
3b8a4dd3	200	static void dw_reader(struct dw_spi *dws)
e24c7452	201	{
2ff271bf	202	u32 max = rx_max(dws);
de6efe0a	203	u16 rxw;
e24c7452	204
2ff271bf	205	while (max--) {
c4fe57f7	206	rxw = dw_read_io_reg(dws, DW_SPI_DR);
de6efe0a FT	207	/* Care rx only if the transfer's original "rx" is not null */
	208	if (dws->rx_end - dws->len) {
	209	if (dws->n_bytes == 1)
	210	(u8 )(dws->rx) = rxw;
	211	else
	212	(u16 )(dws->rx) = rxw;
	213	}
	214	dws->rx += dws->n_bytes;
e24c7452	215	}
e24c7452 FT	216	}
e24c7452 FT	217
e24c7452 FT	218	static void int_error_stop(struct dw_spi dws, const char msg)
e24c7452 FT	219	{
45746e82	220	spi_reset_chip(dws);
e24c7452 FT	221
e24c7452 FT	222	dev_err(&dws->master->dev, "%s\n", msg);
c22c62db AS	223	dws->master->cur_msg->status = -EIO;
c22c62db AS	224	spi_finalize_current_transfer(dws->master);
e24c7452 FT	225	}
e24c7452 FT	226
e24c7452 FT	227	static irqreturn_t interrupt_transfer(struct dw_spi *dws)
e24c7452 FT	228	{
dd114443	229	u16 irq_status = dw_readl(dws, DW_SPI_ISR);
e24c7452	230
e24c7452 FT	231	/* Error handling */
e24c7452 FT	232	if (irq_status & (SPI_INT_TXOI \| SPI_INT_RXOI \| SPI_INT_RXUI)) {
dd114443	233	dw_readl(dws, DW_SPI_ICR);
3b8a4dd3	234	int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
e24c7452 FT	235	return IRQ_HANDLED;
	236	}
	237
3b8a4dd3 AD	238	dw_reader(dws);
	239	if (dws->rx_end == dws->rx) {
	240	spi_mask_intr(dws, SPI_INT_TXEI);
c22c62db	241	spi_finalize_current_transfer(dws->master);
3b8a4dd3 AD	242	return IRQ_HANDLED;
3b8a4dd3 AD	243	}
552e4509 FT	244	if (irq_status & SPI_INT_TXEI) {
552e4509 FT	245	spi_mask_intr(dws, SPI_INT_TXEI);
3b8a4dd3 AD	246	dw_writer(dws);
	247	/* Enable TX irq always, it will be disabled when RX finished */
	248	spi_umask_intr(dws, SPI_INT_TXEI);
e24c7452 FT	249	}
e24c7452 FT	250
e24c7452 FT	251	return IRQ_HANDLED;
	252	}
	253
	254	static irqreturn_t dw_spi_irq(int irq, void *dev_id)
	255	{
721483e2 JN	256	struct spi_controller *master = dev_id;
721483e2 JN	257	struct dw_spi *dws = spi_controller_get_devdata(master);
dd114443	258	u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
cbcc062a	259
cbcc062a YW	260	if (!irq_status)
cbcc062a YW	261	return IRQ_NONE;
e24c7452	262
c22c62db	263	if (!master->cur_msg) {
e24c7452	264	spi_mask_intr(dws, SPI_INT_TXEI);
e24c7452 FT	265	return IRQ_HANDLED;
	266	}
	267
	268	return dws->transfer_handler(dws);
	269	}
	270
	271	/* Must be called inside pump_transfers() */
c22c62db	272	static int poll_transfer(struct dw_spi *dws)
e24c7452	273	{
2ff271bf AD	274	do {
2ff271bf AD	275	dw_writer(dws);
de6efe0a	276	dw_reader(dws);
2ff271bf AD	277	cpu_relax();
2ff271bf AD	278	} while (dws->rx_end > dws->rx);
e24c7452	279
c22c62db	280	return 0;
e24c7452 FT	281	}
e24c7452 FT	282
721483e2	283	static int dw_spi_transfer_one(struct spi_controller *master,
c22c62db	284	struct spi_device spi, struct spi_transfer transfer)
e24c7452	285	{
721483e2	286	struct dw_spi *dws = spi_controller_get_devdata(master);
c22c62db	287	struct chip_data *chip = spi_get_ctldata(spi);
e24c7452	288	u8 imask = 0;
ea11370f	289	u16 txlevel = 0;
4adb1f8f	290	u32 cr0;
9f14538e	291	int ret;
e24c7452	292
f89a6d8f	293	dws->dma_mapped = 0;
e24c7452	294
e24c7452 FT	295	dws->tx = (void *)transfer->tx_buf;
	296	dws->tx_end = dws->tx + transfer->len;
	297	dws->rx = transfer->rx_buf;
	298	dws->rx_end = dws->rx + transfer->len;
c22c62db	299	dws->len = transfer->len;
e24c7452	300
0b2e8915 AS	301	spi_enable_chip(dws, 0);
0b2e8915 AS	302
e24c7452	303	/* Handle per transfer options for bpw and speed */
13b10301 MS	304	if (transfer->speed_hz != dws->current_freq) {
	305	if (transfer->speed_hz != chip->speed_hz) {
	306	/* clk_div doesn't support odd number */
3aef4632	307	chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe;
13b10301 MS	308	chip->speed_hz = transfer->speed_hz;
	309	}
	310	dws->current_freq = transfer->speed_hz;
0ed36990	311	spi_set_clk(dws, chip->clk_div);
e24c7452	312	}
af060b3f SG	313
	314	dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
	315	dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
	316
4adb1f8f	317	/* Default SPI mode is SCPOL = 0, SCPH = 0 */
0ed36990 JN	318	cr0 = (transfer->bits_per_word - 1)
	319	\| (chip->type << SPI_FRF_OFFSET)
	320	\| (spi->mode << SPI_MODE_OFFSET)
	321	\| (chip->tmode << SPI_TMOD_OFFSET);
e24c7452	322
052dc7c4 GS	323	/*
	324	* Adjust transfer mode if necessary. Requires platform dependent
	325	* chipselect mechanism.
	326	*/
c22c62db	327	if (chip->cs_control) {
052dc7c4	328	if (dws->rx && dws->tx)
e3e55ff5	329	chip->tmode = SPI_TMOD_TR;
052dc7c4	330	else if (dws->rx)
e3e55ff5	331	chip->tmode = SPI_TMOD_RO;
052dc7c4	332	else
e3e55ff5	333	chip->tmode = SPI_TMOD_TO;
052dc7c4	334
e3e55ff5	335	cr0 &= ~SPI_TMOD_MASK;
052dc7c4 GS	336	cr0 \|= (chip->tmode << SPI_TMOD_OFFSET);
	337	}
	338
dd114443	339	dw_writel(dws, DW_SPI_CTRL0, cr0);
0b2e8915	340
e24c7452	341	/* Check if current transfer is a DMA transaction */
f89a6d8f AS	342	if (master->can_dma && master->can_dma(master, spi, transfer))
f89a6d8f AS	343	dws->dma_mapped = master->cur_msg_mapped;
e24c7452	344
0b2e8915 AS	345	/* For poll mode just disable all interrupts */
	346	spi_mask_intr(dws, 0xff);
	347
552e4509 FT	348	/*
	349	* Interrupt mode
	350	* we only need set the TXEI IRQ, as TX/RX always happen syncronizely
	351	*/
9f14538e	352	if (dws->dma_mapped) {
f89a6d8f	353	ret = dws->dma_ops->dma_setup(dws, transfer);
9f14538e AS	354	if (ret < 0) {
	355	spi_enable_chip(dws, 1);
	356	return ret;
	357	}
	358	} else if (!chip->poll_mode) {
ea11370f	359	txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
dd114443	360	dw_writel(dws, DW_SPI_TXFLTR, txlevel);
552e4509	361
0b2e8915	362	/* Set the interrupt mask */
fadcace7 JH	363	imask \|= SPI_INT_TXEI \| SPI_INT_TXOI \|
fadcace7 JH	364	SPI_INT_RXUI \| SPI_INT_RXOI;
0b2e8915 AS	365	spi_umask_intr(dws, imask);
0b2e8915 AS	366
e24c7452 FT	367	dws->transfer_handler = interrupt_transfer;
	368	}
	369
0b2e8915	370	spi_enable_chip(dws, 1);
e24c7452	371
9f14538e	372	if (dws->dma_mapped) {
f89a6d8f	373	ret = dws->dma_ops->dma_transfer(dws, transfer);
9f14538e AS	374	if (ret < 0)
	375	return ret;
	376	}
e24c7452 FT	377
e24c7452 FT	378	if (chip->poll_mode)
c22c62db	379	return poll_transfer(dws);
e24c7452	380
c22c62db	381	return 1;
e24c7452 FT	382	}
e24c7452 FT	383
721483e2	384	static void dw_spi_handle_err(struct spi_controller *master,
ec37e8e1	385	struct spi_message *msg)
e24c7452	386	{
721483e2	387	struct dw_spi *dws = spi_controller_get_devdata(master);
e24c7452	388
4d5ac1ed AS	389	if (dws->dma_mapped)
	390	dws->dma_ops->dma_stop(dws);
	391
c22c62db	392	spi_reset_chip(dws);
e24c7452 FT	393	}
	394
	395	/* This may be called twice for each spi dev */
	396	static int dw_spi_setup(struct spi_device *spi)
	397	{
	398	struct dw_spi_chip *chip_info = NULL;
	399	struct chip_data *chip;
d9c73bb8	400	int ret;
e24c7452	401
e24c7452 FT	402	/* Only alloc on first setup */
	403	chip = spi_get_ctldata(spi);
	404	if (!chip) {
a97c883a	405	chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
e24c7452 FT	406	if (!chip)
e24c7452 FT	407	return -ENOMEM;
43f627ac	408	spi_set_ctldata(spi, chip);
e24c7452 FT	409	}
	410
	411	/*
	412	* Protocol drivers may change the chip settings, so...
	413	* if chip_info exists, use it
	414	*/
	415	chip_info = spi->controller_data;
	416
	417	/* chip_info doesn't always exist */
	418	if (chip_info) {
	419	if (chip_info->cs_control)
	420	chip->cs_control = chip_info->cs_control;
	421
	422	chip->poll_mode = chip_info->poll_mode;
	423	chip->type = chip_info->type;
e24c7452 FT	424	}
e24c7452 FT	425
6096828e	426	chip->tmode = SPI_TMOD_TR;
c3ce15bf	427
d9c73bb8 BS	428	if (gpio_is_valid(spi->cs_gpio)) {
	429	ret = gpio_direction_output(spi->cs_gpio,
	430	!(spi->mode & SPI_CS_HIGH));
	431	if (ret)
	432	return ret;
	433	}
	434
e24c7452 FT	435	return 0;
	436	}
	437
a97c883a AL	438	static void dw_spi_cleanup(struct spi_device *spi)
	439	{
	440	struct chip_data *chip = spi_get_ctldata(spi);
	441
	442	kfree(chip);
	443	spi_set_ctldata(spi, NULL);
	444	}
	445
e24c7452	446	/* Restart the controller, disable all interrupts, clean rx fifo */
30b4b703	447	static void spi_hw_init(struct device dev, struct dw_spi dws)
e24c7452	448	{
45746e82	449	spi_reset_chip(dws);
c587b6fa FT	450
	451	/*
	452	* Try to detect the FIFO depth if not set by interface driver,
	453	* the depth could be from 2 to 256 from HW spec
	454	*/
	455	if (!dws->fifo_len) {
	456	u32 fifo;
fadcace7	457
9d239d35	458	for (fifo = 1; fifo < 256; fifo++) {
dd114443 TT	459	dw_writel(dws, DW_SPI_TXFLTR, fifo);
dd114443 TT	460	if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
c587b6fa FT	461	break;
c587b6fa FT	462	}
dd114443	463	dw_writel(dws, DW_SPI_TXFLTR, 0);
c587b6fa	464
9d239d35	465	dws->fifo_len = (fifo == 1) ? 0 : fifo;
30b4b703	466	dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
c587b6fa	467	}
f2d70479 TS	468
	469	/* enable HW fixup for explicit CS deselect for Amazon's alpine chip */
	470	if (dws->cs_override)
	471	dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF);
e24c7452 FT	472	}
e24c7452 FT	473
04f421e7	474	int dw_spi_add_host(struct device dev, struct dw_spi dws)
e24c7452	475	{
721483e2	476	struct spi_controller *master;
e24c7452 FT	477	int ret;
	478
	479	BUG_ON(dws == NULL);
	480
04f421e7 BS	481	master = spi_alloc_master(dev, 0);
	482	if (!master)
	483	return -ENOMEM;
e24c7452 FT	484
	485	dws->master = master;
	486	dws->type = SSI_MOTO_SPI;
e24c7452	487	dws->dma_inited = 0;
d7ef54ca	488	dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
e24c7452	489
66b19d76 AB	490	spi_controller_set_devdata(master, dws);
66b19d76 AB	491
e70002c8 PR	492	ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
e70002c8 PR	493	master);
e24c7452	494	if (ret < 0) {
5f0966e6	495	dev_err(dev, "can not get IRQ\n");
e24c7452 FT	496	goto err_free_master;
	497	}
	498
c3ce15bf	499	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_LOOP;
af060b3f	500	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
e24c7452 FT	501	master->bus_num = dws->bus_num;
e24c7452 FT	502	master->num_chipselect = dws->num_cs;
e24c7452	503	master->setup = dw_spi_setup;
a97c883a	504	master->cleanup = dw_spi_cleanup;
c22c62db AS	505	master->set_cs = dw_spi_set_cs;
	506	master->transfer_one = dw_spi_transfer_one;
	507	master->handle_err = dw_spi_handle_err;
765ee709	508	master->max_speed_hz = dws->max_freq;
9c6de47d	509	master->dev.of_node = dev->of_node;
80b444e5	510	master->flags = SPI_MASTER_GPIO_SS;
e24c7452	511
62dbbae4 AB	512	if (dws->set_cs)
	513	master->set_cs = dws->set_cs;
	514
e24c7452	515	/* Basic HW init */
30b4b703	516	spi_hw_init(dev, dws);
e24c7452	517
7063c0d9 FT	518	if (dws->dma_ops && dws->dma_ops->dma_init) {
	519	ret = dws->dma_ops->dma_init(dws);
	520	if (ret) {
3dbb3b98	521	dev_warn(dev, "DMA init failed\n");
7063c0d9	522	dws->dma_inited = 0;
f89a6d8f AS	523	} else {
f89a6d8f AS	524	master->can_dma = dws->dma_ops->can_dma;
7063c0d9 FT	525	}
	526	}
	527
721483e2	528	ret = devm_spi_register_controller(dev, master);
e24c7452 FT	529	if (ret) {
e24c7452 FT	530	dev_err(&master->dev, "problem registering spi master\n");
ec37e8e1	531	goto err_dma_exit;
e24c7452 FT	532	}
e24c7452 FT	533
53288fe9	534	dw_spi_debugfs_init(dws);
e24c7452 FT	535	return 0;
e24c7452 FT	536
ec37e8e1	537	err_dma_exit:
7063c0d9 FT	538	if (dws->dma_ops && dws->dma_ops->dma_exit)
7063c0d9 FT	539	dws->dma_ops->dma_exit(dws);
e24c7452	540	spi_enable_chip(dws, 0);
02f20387	541	free_irq(dws->irq, master);
e24c7452	542	err_free_master:
721483e2	543	spi_controller_put(master);
e24c7452 FT	544	return ret;
e24c7452 FT	545	}
79290a2a	546	EXPORT_SYMBOL_GPL(dw_spi_add_host);
e24c7452	547
fd4a319b	548	void dw_spi_remove_host(struct dw_spi *dws)
e24c7452	549	{
53288fe9	550	dw_spi_debugfs_remove(dws);
e24c7452	551
7063c0d9 FT	552	if (dws->dma_ops && dws->dma_ops->dma_exit)
7063c0d9 FT	553	dws->dma_ops->dma_exit(dws);
1cc3f141 AS	554
1cc3f141 AS	555	spi_shutdown_chip(dws);
02f20387 AS	556
02f20387 AS	557	free_irq(dws->irq, dws->master);
e24c7452	558	}
79290a2a	559	EXPORT_SYMBOL_GPL(dw_spi_remove_host);
e24c7452 FT	560
	561	int dw_spi_suspend_host(struct dw_spi *dws)
	562	{
1cc3f141	563	int ret;
e24c7452	564
721483e2	565	ret = spi_controller_suspend(dws->master);
e24c7452 FT	566	if (ret)
e24c7452 FT	567	return ret;
1cc3f141 AS	568
	569	spi_shutdown_chip(dws);
	570	return 0;
e24c7452	571	}
79290a2a	572	EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
e24c7452 FT	573
	574	int dw_spi_resume_host(struct dw_spi *dws)
	575	{
30b4b703	576	spi_hw_init(&dws->master->dev, dws);
7c5d8a24	577	return spi_controller_resume(dws->master);
e24c7452	578	}
79290a2a	579	EXPORT_SYMBOL_GPL(dw_spi_resume_host);
e24c7452 FT	580
	581	MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
	582	MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
	583	MODULE_LICENSE("GPL v2");