[mirror_ubuntu-artful-kernel.git] / drivers / spi / spi-dw.h

#ifndef DW_SPI_HEADER_H
#define DW_SPI_HEADER_H

#include <linux/io.h>
#include <linux/scatterlist.h>
#include <linux/gpio.h>

/* Register offsets */
#define DW_SPI_CTRL0			0x00
#define DW_SPI_CTRL1			0x04
#define DW_SPI_SSIENR			0x08
#define DW_SPI_MWCR			0x0c
#define DW_SPI_SER			0x10
#define DW_SPI_BAUDR			0x14
#define DW_SPI_TXFLTR			0x18
#define DW_SPI_RXFLTR			0x1c
#define DW_SPI_TXFLR			0x20
#define DW_SPI_RXFLR			0x24
#define DW_SPI_SR			0x28
#define DW_SPI_IMR			0x2c
#define DW_SPI_ISR			0x30
#define DW_SPI_RISR			0x34
#define DW_SPI_TXOICR			0x38
#define DW_SPI_RXOICR			0x3c
#define DW_SPI_RXUICR			0x40
#define DW_SPI_MSTICR			0x44
#define DW_SPI_ICR			0x48
#define DW_SPI_DMACR			0x4c
#define DW_SPI_DMATDLR			0x50
#define DW_SPI_DMARDLR			0x54
#define DW_SPI_IDR			0x58
#define DW_SPI_VERSION			0x5c
#define DW_SPI_DR			0x60

/* Bit fields in CTRLR0 */
#define SPI_DFS_OFFSET			0

#define SPI_FRF_OFFSET			4
#define SPI_FRF_SPI			0x0
#define SPI_FRF_SSP			0x1
#define SPI_FRF_MICROWIRE		0x2
#define SPI_FRF_RESV			0x3

#define SPI_MODE_OFFSET			6
#define SPI_SCPH_OFFSET			6
#define SPI_SCOL_OFFSET			7

#define SPI_TMOD_OFFSET			8
#define SPI_TMOD_MASK			(0x3 << SPI_TMOD_OFFSET)
#define	SPI_TMOD_TR			0x0		/* xmit & recv */
#define SPI_TMOD_TO			0x1		/* xmit only */
#define SPI_TMOD_RO			0x2		/* recv only */
#define SPI_TMOD_EPROMREAD		0x3		/* eeprom read mode */

#define SPI_SLVOE_OFFSET		10
#define SPI_SRL_OFFSET			11
#define SPI_CFS_OFFSET			12

/* Bit fields in SR, 7 bits */
#define SR_MASK				0x7f		/* cover 7 bits */
#define SR_BUSY				(1 << 0)
#define SR_TF_NOT_FULL			(1 << 1)
#define SR_TF_EMPT			(1 << 2)
#define SR_RF_NOT_EMPT			(1 << 3)
#define SR_RF_FULL			(1 << 4)
#define SR_TX_ERR			(1 << 5)
#define SR_DCOL				(1 << 6)

/* Bit fields in ISR, IMR, RISR, 7 bits */
#define SPI_INT_TXEI			(1 << 0)
#define SPI_INT_TXOI			(1 << 1)
#define SPI_INT_RXUI			(1 << 2)
#define SPI_INT_RXOI			(1 << 3)
#define SPI_INT_RXFI			(1 << 4)
#define SPI_INT_MSTI			(1 << 5)

/* Bit fields in DMACR */
#define SPI_DMA_RDMAE			(1 << 0)
#define SPI_DMA_TDMAE			(1 << 1)

/* TX RX interrupt level threshold, max can be 256 */
#define SPI_INT_THRESHOLD		32

enum dw_ssi_type {
	SSI_MOTO_SPI = 0,
	SSI_TI_SSP,
	SSI_NS_MICROWIRE,
};

struct dw_spi;
struct dw_spi_dma_ops {
	int (*dma_init)(struct dw_spi *dws);
	void (*dma_exit)(struct dw_spi *dws);
	int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
	bool (*can_dma)(struct spi_master *master, struct spi_device *spi,
			struct spi_transfer *xfer);
	int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
	void (*dma_stop)(struct dw_spi *dws);
};

struct dw_spi {
	struct spi_master	*master;
	enum dw_ssi_type	type;

	void __iomem		*regs;
	unsigned long		paddr;
	int			irq;
	u32			fifo_len;	/* depth of the FIFO buffer */
	u32			max_freq;	/* max bus freq supported */

	u32			reg_io_width;	/* DR I/O width in bytes */
	u16			bus_num;
	u16			num_cs;		/* supported slave numbers */

	/* Current message transfer state info */
	size_t			len;
	void			*tx;
	void			*tx_end;
	void			*rx;
	void			*rx_end;
	int			dma_mapped;
	u8			n_bytes;	/* current is a 1/2 bytes op */
	u32			dma_width;
	irqreturn_t		(*transfer_handler)(struct dw_spi *dws);
	u32			current_freq;	/* frequency in hz */

	/* DMA info */
	int			dma_inited;
	struct dma_chan		*txchan;
	struct dma_chan		*rxchan;
	unsigned long		dma_chan_busy;
	dma_addr_t		dma_addr; /* phy address of the Data register */
	const struct dw_spi_dma_ops *dma_ops;
	void			*dma_tx;
	void			*dma_rx;

	/* Bus interface info */
	void			*priv;
#ifdef CONFIG_DEBUG_FS
	struct dentry *debugfs;
#endif
};

static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
{
	return __raw_readl(dws->regs + offset);
}

static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
{
	return __raw_readw(dws->regs + offset);
}

static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
{
	__raw_writel(val, dws->regs + offset);
}

static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
{
	__raw_writew(val, dws->regs + offset);
}

static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
{
	switch (dws->reg_io_width) {
	case 2:
		return dw_readw(dws, offset);
	case 4:
	default:
		return dw_readl(dws, offset);
	}
}

static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
{
	switch (dws->reg_io_width) {
	case 2:
		dw_writew(dws, offset, val);
		break;
	case 4:
	default:
		dw_writel(dws, offset, val);
		break;
	}
}

static inline void spi_enable_chip(struct dw_spi *dws, int enable)
{
	dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
}

static inline void spi_set_clk(struct dw_spi *dws, u16 div)
{
	dw_writel(dws, DW_SPI_BAUDR, div);
}

/* Disable IRQ bits */
static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
{
	u32 new_mask;

	new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
	dw_writel(dws, DW_SPI_IMR, new_mask);
}

/* Enable IRQ bits */
static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
{
	u32 new_mask;

	new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
	dw_writel(dws, DW_SPI_IMR, new_mask);
}

/*
 * This does disable the SPI controller, interrupts, and re-enable the
 * controller back. Transmit and receive FIFO buffers are cleared when the
 * device is disabled.
 */
static inline void spi_reset_chip(struct dw_spi *dws)
{
	spi_enable_chip(dws, 0);
	spi_mask_intr(dws, 0xff);
	spi_enable_chip(dws, 1);
}

static inline void spi_shutdown_chip(struct dw_spi *dws)
{
	spi_enable_chip(dws, 0);
	spi_set_clk(dws, 0);
}

/*
 * Each SPI slave device to work with dw_api controller should
 * has such a structure claiming its working mode (poll or PIO/DMA),
 * which can be save in the "controller_data" member of the
 * struct spi_device.
 */
struct dw_spi_chip {
	u8 poll_mode;	/* 1 for controller polling mode */
	u8 type;	/* SPI/SSP/MicroWire */
	void (*cs_control)(u32 command);
};

extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
extern void dw_spi_remove_host(struct dw_spi *dws);
extern int dw_spi_suspend_host(struct dw_spi *dws);
extern int dw_spi_resume_host(struct dw_spi *dws);

/* platform related setup */
extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
#endif /* DW_SPI_HEADER_H */
Commit	Line	Data
e24c7452 FT	1	#ifndef DW_SPI_HEADER_H
e24c7452 FT	2	#define DW_SPI_HEADER_H
7063c0d9	3
e24c7452	4	#include <linux/io.h>
46165a3d	5	#include <linux/scatterlist.h>
d9c73bb8	6	#include <linux/gpio.h>
e24c7452	7
7eb187b3 HS	8	/* Register offsets */
	9	#define DW_SPI_CTRL0 0x00
	10	#define DW_SPI_CTRL1 0x04
	11	#define DW_SPI_SSIENR 0x08
	12	#define DW_SPI_MWCR 0x0c
	13	#define DW_SPI_SER 0x10
	14	#define DW_SPI_BAUDR 0x14
	15	#define DW_SPI_TXFLTR 0x18
	16	#define DW_SPI_RXFLTR 0x1c
	17	#define DW_SPI_TXFLR 0x20
	18	#define DW_SPI_RXFLR 0x24
	19	#define DW_SPI_SR 0x28
	20	#define DW_SPI_IMR 0x2c
	21	#define DW_SPI_ISR 0x30
	22	#define DW_SPI_RISR 0x34
	23	#define DW_SPI_TXOICR 0x38
	24	#define DW_SPI_RXOICR 0x3c
	25	#define DW_SPI_RXUICR 0x40
	26	#define DW_SPI_MSTICR 0x44
	27	#define DW_SPI_ICR 0x48
	28	#define DW_SPI_DMACR 0x4c
	29	#define DW_SPI_DMATDLR 0x50
	30	#define DW_SPI_DMARDLR 0x54
	31	#define DW_SPI_IDR 0x58
	32	#define DW_SPI_VERSION 0x5c
	33	#define DW_SPI_DR 0x60
	34
e24c7452 FT	35	/* Bit fields in CTRLR0 */
	36	#define SPI_DFS_OFFSET 0
	37
	38	#define SPI_FRF_OFFSET 4
	39	#define SPI_FRF_SPI 0x0
	40	#define SPI_FRF_SSP 0x1
	41	#define SPI_FRF_MICROWIRE 0x2
	42	#define SPI_FRF_RESV 0x3
	43
	44	#define SPI_MODE_OFFSET 6
	45	#define SPI_SCPH_OFFSET 6
	46	#define SPI_SCOL_OFFSET 7
e3e55ff5	47
e24c7452	48	#define SPI_TMOD_OFFSET 8
e3e55ff5	49	#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
e24c7452 FT	50	#define SPI_TMOD_TR 0x0 /* xmit & recv */
	51	#define SPI_TMOD_TO 0x1 /* xmit only */
	52	#define SPI_TMOD_RO 0x2 /* recv only */
	53	#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
	54
	55	#define SPI_SLVOE_OFFSET 10
	56	#define SPI_SRL_OFFSET 11
	57	#define SPI_CFS_OFFSET 12
	58
	59	/* Bit fields in SR, 7 bits */
	60	#define SR_MASK 0x7f /* cover 7 bits */
	61	#define SR_BUSY (1 << 0)
	62	#define SR_TF_NOT_FULL (1 << 1)
	63	#define SR_TF_EMPT (1 << 2)
	64	#define SR_RF_NOT_EMPT (1 << 3)
	65	#define SR_RF_FULL (1 << 4)
	66	#define SR_TX_ERR (1 << 5)
	67	#define SR_DCOL (1 << 6)
	68
	69	/* Bit fields in ISR, IMR, RISR, 7 bits */
	70	#define SPI_INT_TXEI (1 << 0)
	71	#define SPI_INT_TXOI (1 << 1)
	72	#define SPI_INT_RXUI (1 << 2)
	73	#define SPI_INT_RXOI (1 << 3)
	74	#define SPI_INT_RXFI (1 << 4)
	75	#define SPI_INT_MSTI (1 << 5)
	76
15ee3be7 AS	77	/* Bit fields in DMACR */
	78	#define SPI_DMA_RDMAE (1 << 0)
	79	#define SPI_DMA_TDMAE (1 << 1)
	80
25985edc	81	/* TX RX interrupt level threshold, max can be 256 */
e24c7452 FT	82	#define SPI_INT_THRESHOLD 32
	83
	84	enum dw_ssi_type {
	85	SSI_MOTO_SPI = 0,
	86	SSI_TI_SSP,
	87	SSI_NS_MICROWIRE,
	88	};
	89
7063c0d9 FT	90	struct dw_spi;
	91	struct dw_spi_dma_ops {
	92	int (dma_init)(struct dw_spi dws);
	93	void (dma_exit)(struct dw_spi dws);
f89a6d8f AS	94	int (dma_setup)(struct dw_spi dws, struct spi_transfer *xfer);
	95	bool (can_dma)(struct spi_master master, struct spi_device *spi,
	96	struct spi_transfer *xfer);
	97	int (dma_transfer)(struct dw_spi dws, struct spi_transfer *xfer);
4d5ac1ed	98	void (dma_stop)(struct dw_spi dws);
7063c0d9 FT	99	};
7063c0d9 FT	100
e24c7452 FT	101	struct dw_spi {
e24c7452 FT	102	struct spi_master *master;
e24c7452 FT	103	enum dw_ssi_type type;
	104
	105	void __iomem *regs;
	106	unsigned long paddr;
e24c7452	107	int irq;
552e4509	108	u32 fifo_len; /* depth of the FIFO buffer */
e24c7452 FT	109	u32 max_freq; /* max bus freq supported */
e24c7452 FT	110
c4fe57f7	111	u32 reg_io_width; /* DR I/O width in bytes */
e24c7452 FT	112	u16 bus_num;
	113	u16 num_cs; /* supported slave numbers */
	114
e24c7452	115	/* Current message transfer state info */
e24c7452 FT	116	size_t len;
	117	void *tx;
	118	void *tx_end;
	119	void *rx;
	120	void *rx_end;
	121	int dma_mapped;
e24c7452	122	u8 n_bytes; /* current is a 1/2 bytes op */
e24c7452	123	u32 dma_width;
e24c7452	124	irqreturn_t (transfer_handler)(struct dw_spi dws);
13b10301	125	u32 current_freq; /* frequency in hz */
e24c7452	126
f89a6d8f	127	/* DMA info */
e24c7452 FT	128	int dma_inited;
	129	struct dma_chan *txchan;
	130	struct dma_chan *rxchan;
30c8eb52	131	unsigned long dma_chan_busy;
7063c0d9	132	dma_addr_t dma_addr; /* phy address of the Data register */
4fe338c9	133	const struct dw_spi_dma_ops *dma_ops;
d744f826 AS	134	void *dma_tx;
d744f826 AS	135	void *dma_rx;
e24c7452 FT	136
	137	/* Bus interface info */
	138	void *priv;
	139	#ifdef CONFIG_DEBUG_FS
	140	struct dentry *debugfs;
	141	#endif
	142	};
	143
7eb187b3 HS	144	static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
	145	{
	146	return __raw_readl(dws->regs + offset);
	147	}
	148
c4fe57f7 MW	149	static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
	150	{
	151	return __raw_readw(dws->regs + offset);
	152	}
	153
7eb187b3 HS	154	static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
	155	{
	156	__raw_writel(val, dws->regs + offset);
	157	}
	158
c4fe57f7 MW	159	static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
	160	{
	161	__raw_writew(val, dws->regs + offset);
	162	}
	163
	164	static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
	165	{
	166	switch (dws->reg_io_width) {
	167	case 2:
	168	return dw_readw(dws, offset);
	169	case 4:
	170	default:
	171	return dw_readl(dws, offset);
	172	}
	173	}
	174
	175	static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
	176	{
	177	switch (dws->reg_io_width) {
	178	case 2:
	179	dw_writew(dws, offset, val);
	180	break;
	181	case 4:
	182	default:
	183	dw_writel(dws, offset, val);
	184	break;
	185	}
	186	}
	187
e24c7452 FT	188	static inline void spi_enable_chip(struct dw_spi *dws, int enable)
e24c7452 FT	189	{
7eb187b3	190	dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
e24c7452 FT	191	}
	192
	193	static inline void spi_set_clk(struct dw_spi *dws, u16 div)
	194	{
7eb187b3	195	dw_writel(dws, DW_SPI_BAUDR, div);
e24c7452 FT	196	}
e24c7452 FT	197
e24c7452 FT	198	/* Disable IRQ bits */
	199	static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
	200	{
	201	u32 new_mask;
	202
7eb187b3 HS	203	new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
7eb187b3 HS	204	dw_writel(dws, DW_SPI_IMR, new_mask);
e24c7452 FT	205	}
	206
	207	/* Enable IRQ bits */
	208	static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
	209	{
	210	u32 new_mask;
	211
7eb187b3 HS	212	new_mask = dw_readl(dws, DW_SPI_IMR) \| mask;
7eb187b3 HS	213	dw_writel(dws, DW_SPI_IMR, new_mask);
e24c7452 FT	214	}
e24c7452 FT	215
45746e82 AS	216	/*
	217	* This does disable the SPI controller, interrupts, and re-enable the
	218	* controller back. Transmit and receive FIFO buffers are cleared when the
	219	* device is disabled.
	220	*/
	221	static inline void spi_reset_chip(struct dw_spi *dws)
	222	{
	223	spi_enable_chip(dws, 0);
	224	spi_mask_intr(dws, 0xff);
	225	spi_enable_chip(dws, 1);
	226	}
	227
1cc3f141 AS	228	static inline void spi_shutdown_chip(struct dw_spi *dws)
	229	{
	230	spi_enable_chip(dws, 0);
	231	spi_set_clk(dws, 0);
	232	}
	233
e24c7452 FT	234	/*
e24c7452 FT	235	* Each SPI slave device to work with dw_api controller should
f89a6d8f	236	* has such a structure claiming its working mode (poll or PIO/DMA),
e24c7452	237	* which can be save in the "controller_data" member of the
05ed2aee	238	* struct spi_device.
e24c7452 FT	239	*/
e24c7452 FT	240	struct dw_spi_chip {
05ed2aee AS	241	u8 poll_mode; /* 1 for controller polling mode */
05ed2aee AS	242	u8 type; /* SPI/SSP/MicroWire */
e24c7452 FT	243	void (*cs_control)(u32 command);
	244	};
	245
04f421e7	246	extern int dw_spi_add_host(struct device dev, struct dw_spi dws);
e24c7452 FT	247	extern void dw_spi_remove_host(struct dw_spi *dws);
	248	extern int dw_spi_suspend_host(struct dw_spi *dws);
	249	extern int dw_spi_resume_host(struct dw_spi *dws);
7063c0d9 FT	250
	251	/* platform related setup */
	252	extern int dw_spi_mid_init(struct dw_spi dws); / Intel MID platforms */
e24c7452	253	#endif /* DW_SPI_HEADER_H */