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Commit | Line | Data |
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e24c7452 FT |
1 | #ifndef DW_SPI_HEADER_H |
2 | #define DW_SPI_HEADER_H | |
7063c0d9 | 3 | |
e24c7452 | 4 | #include <linux/io.h> |
46165a3d | 5 | #include <linux/scatterlist.h> |
d9c73bb8 | 6 | #include <linux/gpio.h> |
e24c7452 | 7 | |
7eb187b3 HS |
8 | /* Register offsets */ |
9 | #define DW_SPI_CTRL0 0x00 | |
10 | #define DW_SPI_CTRL1 0x04 | |
11 | #define DW_SPI_SSIENR 0x08 | |
12 | #define DW_SPI_MWCR 0x0c | |
13 | #define DW_SPI_SER 0x10 | |
14 | #define DW_SPI_BAUDR 0x14 | |
15 | #define DW_SPI_TXFLTR 0x18 | |
16 | #define DW_SPI_RXFLTR 0x1c | |
17 | #define DW_SPI_TXFLR 0x20 | |
18 | #define DW_SPI_RXFLR 0x24 | |
19 | #define DW_SPI_SR 0x28 | |
20 | #define DW_SPI_IMR 0x2c | |
21 | #define DW_SPI_ISR 0x30 | |
22 | #define DW_SPI_RISR 0x34 | |
23 | #define DW_SPI_TXOICR 0x38 | |
24 | #define DW_SPI_RXOICR 0x3c | |
25 | #define DW_SPI_RXUICR 0x40 | |
26 | #define DW_SPI_MSTICR 0x44 | |
27 | #define DW_SPI_ICR 0x48 | |
28 | #define DW_SPI_DMACR 0x4c | |
29 | #define DW_SPI_DMATDLR 0x50 | |
30 | #define DW_SPI_DMARDLR 0x54 | |
31 | #define DW_SPI_IDR 0x58 | |
32 | #define DW_SPI_VERSION 0x5c | |
33 | #define DW_SPI_DR 0x60 | |
34 | ||
e24c7452 FT |
35 | /* Bit fields in CTRLR0 */ |
36 | #define SPI_DFS_OFFSET 0 | |
37 | ||
38 | #define SPI_FRF_OFFSET 4 | |
39 | #define SPI_FRF_SPI 0x0 | |
40 | #define SPI_FRF_SSP 0x1 | |
41 | #define SPI_FRF_MICROWIRE 0x2 | |
42 | #define SPI_FRF_RESV 0x3 | |
43 | ||
44 | #define SPI_MODE_OFFSET 6 | |
45 | #define SPI_SCPH_OFFSET 6 | |
46 | #define SPI_SCOL_OFFSET 7 | |
e3e55ff5 | 47 | |
e24c7452 | 48 | #define SPI_TMOD_OFFSET 8 |
e3e55ff5 | 49 | #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET) |
e24c7452 FT |
50 | #define SPI_TMOD_TR 0x0 /* xmit & recv */ |
51 | #define SPI_TMOD_TO 0x1 /* xmit only */ | |
52 | #define SPI_TMOD_RO 0x2 /* recv only */ | |
53 | #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ | |
54 | ||
55 | #define SPI_SLVOE_OFFSET 10 | |
56 | #define SPI_SRL_OFFSET 11 | |
57 | #define SPI_CFS_OFFSET 12 | |
58 | ||
59 | /* Bit fields in SR, 7 bits */ | |
60 | #define SR_MASK 0x7f /* cover 7 bits */ | |
61 | #define SR_BUSY (1 << 0) | |
62 | #define SR_TF_NOT_FULL (1 << 1) | |
63 | #define SR_TF_EMPT (1 << 2) | |
64 | #define SR_RF_NOT_EMPT (1 << 3) | |
65 | #define SR_RF_FULL (1 << 4) | |
66 | #define SR_TX_ERR (1 << 5) | |
67 | #define SR_DCOL (1 << 6) | |
68 | ||
69 | /* Bit fields in ISR, IMR, RISR, 7 bits */ | |
70 | #define SPI_INT_TXEI (1 << 0) | |
71 | #define SPI_INT_TXOI (1 << 1) | |
72 | #define SPI_INT_RXUI (1 << 2) | |
73 | #define SPI_INT_RXOI (1 << 3) | |
74 | #define SPI_INT_RXFI (1 << 4) | |
75 | #define SPI_INT_MSTI (1 << 5) | |
76 | ||
15ee3be7 AS |
77 | /* Bit fields in DMACR */ |
78 | #define SPI_DMA_RDMAE (1 << 0) | |
79 | #define SPI_DMA_TDMAE (1 << 1) | |
80 | ||
25985edc | 81 | /* TX RX interrupt level threshold, max can be 256 */ |
e24c7452 FT |
82 | #define SPI_INT_THRESHOLD 32 |
83 | ||
84 | enum dw_ssi_type { | |
85 | SSI_MOTO_SPI = 0, | |
86 | SSI_TI_SSP, | |
87 | SSI_NS_MICROWIRE, | |
88 | }; | |
89 | ||
7063c0d9 FT |
90 | struct dw_spi; |
91 | struct dw_spi_dma_ops { | |
92 | int (*dma_init)(struct dw_spi *dws); | |
93 | void (*dma_exit)(struct dw_spi *dws); | |
f89a6d8f AS |
94 | int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer); |
95 | bool (*can_dma)(struct spi_master *master, struct spi_device *spi, | |
96 | struct spi_transfer *xfer); | |
97 | int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer); | |
4d5ac1ed | 98 | void (*dma_stop)(struct dw_spi *dws); |
7063c0d9 FT |
99 | }; |
100 | ||
e24c7452 FT |
101 | struct dw_spi { |
102 | struct spi_master *master; | |
e24c7452 | 103 | enum dw_ssi_type type; |
40bfff85 | 104 | char name[16]; |
e24c7452 FT |
105 | |
106 | void __iomem *regs; | |
107 | unsigned long paddr; | |
e24c7452 | 108 | int irq; |
552e4509 | 109 | u32 fifo_len; /* depth of the FIFO buffer */ |
e24c7452 FT |
110 | u32 max_freq; /* max bus freq supported */ |
111 | ||
112 | u16 bus_num; | |
113 | u16 num_cs; /* supported slave numbers */ | |
114 | ||
e24c7452 | 115 | /* Current message transfer state info */ |
e24c7452 FT |
116 | size_t len; |
117 | void *tx; | |
118 | void *tx_end; | |
119 | void *rx; | |
120 | void *rx_end; | |
121 | int dma_mapped; | |
e24c7452 | 122 | u8 n_bytes; /* current is a 1/2 bytes op */ |
e24c7452 | 123 | u32 dma_width; |
e24c7452 | 124 | irqreturn_t (*transfer_handler)(struct dw_spi *dws); |
e24c7452 | 125 | |
f89a6d8f | 126 | /* DMA info */ |
e24c7452 FT |
127 | int dma_inited; |
128 | struct dma_chan *txchan; | |
129 | struct dma_chan *rxchan; | |
30c8eb52 | 130 | unsigned long dma_chan_busy; |
7063c0d9 FT |
131 | dma_addr_t dma_addr; /* phy address of the Data register */ |
132 | struct dw_spi_dma_ops *dma_ops; | |
d744f826 AS |
133 | void *dma_tx; |
134 | void *dma_rx; | |
e24c7452 FT |
135 | |
136 | /* Bus interface info */ | |
137 | void *priv; | |
138 | #ifdef CONFIG_DEBUG_FS | |
139 | struct dentry *debugfs; | |
140 | #endif | |
141 | }; | |
142 | ||
7eb187b3 HS |
143 | static inline u32 dw_readl(struct dw_spi *dws, u32 offset) |
144 | { | |
145 | return __raw_readl(dws->regs + offset); | |
146 | } | |
147 | ||
148 | static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) | |
149 | { | |
150 | __raw_writel(val, dws->regs + offset); | |
151 | } | |
152 | ||
e24c7452 FT |
153 | static inline void spi_enable_chip(struct dw_spi *dws, int enable) |
154 | { | |
7eb187b3 | 155 | dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); |
e24c7452 FT |
156 | } |
157 | ||
158 | static inline void spi_set_clk(struct dw_spi *dws, u16 div) | |
159 | { | |
7eb187b3 | 160 | dw_writel(dws, DW_SPI_BAUDR, div); |
e24c7452 FT |
161 | } |
162 | ||
e24c7452 FT |
163 | /* Disable IRQ bits */ |
164 | static inline void spi_mask_intr(struct dw_spi *dws, u32 mask) | |
165 | { | |
166 | u32 new_mask; | |
167 | ||
7eb187b3 HS |
168 | new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask; |
169 | dw_writel(dws, DW_SPI_IMR, new_mask); | |
e24c7452 FT |
170 | } |
171 | ||
172 | /* Enable IRQ bits */ | |
173 | static inline void spi_umask_intr(struct dw_spi *dws, u32 mask) | |
174 | { | |
175 | u32 new_mask; | |
176 | ||
7eb187b3 HS |
177 | new_mask = dw_readl(dws, DW_SPI_IMR) | mask; |
178 | dw_writel(dws, DW_SPI_IMR, new_mask); | |
e24c7452 FT |
179 | } |
180 | ||
45746e82 AS |
181 | /* |
182 | * This does disable the SPI controller, interrupts, and re-enable the | |
183 | * controller back. Transmit and receive FIFO buffers are cleared when the | |
184 | * device is disabled. | |
185 | */ | |
186 | static inline void spi_reset_chip(struct dw_spi *dws) | |
187 | { | |
188 | spi_enable_chip(dws, 0); | |
189 | spi_mask_intr(dws, 0xff); | |
190 | spi_enable_chip(dws, 1); | |
191 | } | |
192 | ||
e24c7452 FT |
193 | /* |
194 | * Each SPI slave device to work with dw_api controller should | |
f89a6d8f | 195 | * has such a structure claiming its working mode (poll or PIO/DMA), |
e24c7452 | 196 | * which can be save in the "controller_data" member of the |
05ed2aee | 197 | * struct spi_device. |
e24c7452 FT |
198 | */ |
199 | struct dw_spi_chip { | |
05ed2aee AS |
200 | u8 poll_mode; /* 1 for controller polling mode */ |
201 | u8 type; /* SPI/SSP/MicroWire */ | |
e24c7452 FT |
202 | void (*cs_control)(u32 command); |
203 | }; | |
204 | ||
04f421e7 | 205 | extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws); |
e24c7452 FT |
206 | extern void dw_spi_remove_host(struct dw_spi *dws); |
207 | extern int dw_spi_suspend_host(struct dw_spi *dws); | |
208 | extern int dw_spi_resume_host(struct dw_spi *dws); | |
7063c0d9 FT |
209 | |
210 | /* platform related setup */ | |
211 | extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */ | |
e24c7452 | 212 | #endif /* DW_SPI_HEADER_H */ |