[mirror_ubuntu-hirsute-kernel.git] / drivers / spi / spi-efm32.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2012-2013 Uwe Kleine-Koenig for Pengutronix
 */
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/platform_data/efm32-spi.h>

#define DRIVER_NAME "efm32-spi"

#define MASK_VAL(mask, val)		((val << __ffs(mask)) & mask)

#define REG_CTRL		0x00
#define REG_CTRL_SYNC			0x0001
#define REG_CTRL_CLKPOL			0x0100
#define REG_CTRL_CLKPHA			0x0200
#define REG_CTRL_MSBF			0x0400
#define REG_CTRL_TXBIL			0x1000

#define REG_FRAME		0x04
#define REG_FRAME_DATABITS__MASK	0x000f
#define REG_FRAME_DATABITS(n)		((n) - 3)

#define REG_CMD			0x0c
#define REG_CMD_RXEN			0x0001
#define REG_CMD_RXDIS			0x0002
#define REG_CMD_TXEN			0x0004
#define REG_CMD_TXDIS			0x0008
#define REG_CMD_MASTEREN		0x0010

#define REG_STATUS		0x10
#define REG_STATUS_TXENS		0x0002
#define REG_STATUS_TXC			0x0020
#define REG_STATUS_TXBL			0x0040
#define REG_STATUS_RXDATAV		0x0080

#define REG_CLKDIV		0x14

#define REG_RXDATAX		0x18
#define REG_RXDATAX_RXDATA__MASK	0x01ff
#define REG_RXDATAX_PERR		0x4000
#define REG_RXDATAX_FERR		0x8000

#define REG_TXDATA		0x34

#define REG_IF		0x40
#define REG_IF_TXBL			0x0002
#define REG_IF_RXDATAV			0x0004

#define REG_IFS		0x44
#define REG_IFC		0x48
#define REG_IEN		0x4c

#define REG_ROUTE		0x54
#define REG_ROUTE_RXPEN			0x0001
#define REG_ROUTE_TXPEN			0x0002
#define REG_ROUTE_CLKPEN		0x0008
#define REG_ROUTE_LOCATION__MASK	0x0700
#define REG_ROUTE_LOCATION(n)		MASK_VAL(REG_ROUTE_LOCATION__MASK, (n))

struct efm32_spi_ddata {
	struct spi_bitbang bitbang;

	spinlock_t lock;

	struct clk *clk;
	void __iomem *base;
	unsigned int rxirq, txirq;
	struct efm32_spi_pdata pdata;

	/* irq data */
	struct completion done;
	const u8 *tx_buf;
	u8 *rx_buf;
	unsigned tx_len, rx_len;

	/* chip selects */
	unsigned csgpio[];
};

#define ddata_to_dev(ddata)	(&(ddata->bitbang.master->dev))
#define efm32_spi_vdbg(ddata, format, arg...)	\
	dev_vdbg(ddata_to_dev(ddata), format, ##arg)

static void efm32_spi_write32(struct efm32_spi_ddata *ddata,
		u32 value, unsigned offset)
{
	writel_relaxed(value, ddata->base + offset);
}

static u32 efm32_spi_read32(struct efm32_spi_ddata *ddata, unsigned offset)
{
	return readl_relaxed(ddata->base + offset);
}

static void efm32_spi_chipselect(struct spi_device *spi, int is_on)
{
	struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master);
	int value = !(spi->mode & SPI_CS_HIGH) == !(is_on == BITBANG_CS_ACTIVE);

	gpio_set_value(ddata->csgpio[spi->chip_select], value);
}

static int efm32_spi_setup_transfer(struct spi_device *spi,
		struct spi_transfer *t)
{
	struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master);

	unsigned bpw = t->bits_per_word ?: spi->bits_per_word;
	unsigned speed = t->speed_hz ?: spi->max_speed_hz;
	unsigned long clkfreq = clk_get_rate(ddata->clk);
	u32 clkdiv;

	efm32_spi_write32(ddata, REG_CTRL_SYNC | REG_CTRL_MSBF |
			(spi->mode & SPI_CPHA ? REG_CTRL_CLKPHA : 0) |
			(spi->mode & SPI_CPOL ? REG_CTRL_CLKPOL : 0), REG_CTRL);

	efm32_spi_write32(ddata,
			REG_FRAME_DATABITS(bpw), REG_FRAME);

	if (2 * speed >= clkfreq)
		clkdiv = 0;
	else
		clkdiv = 64 * (DIV_ROUND_UP(2 * clkfreq, speed) - 4);

	if (clkdiv > (1U << 21))
		return -EINVAL;

	efm32_spi_write32(ddata, clkdiv, REG_CLKDIV);
	efm32_spi_write32(ddata, REG_CMD_MASTEREN, REG_CMD);
	efm32_spi_write32(ddata, REG_CMD_RXEN | REG_CMD_TXEN, REG_CMD);

	return 0;
}

static void efm32_spi_tx_u8(struct efm32_spi_ddata *ddata)
{
	u8 val = 0;

	if (ddata->tx_buf) {
		val = *ddata->tx_buf;
		ddata->tx_buf++;
	}

	ddata->tx_len--;
	efm32_spi_write32(ddata, val, REG_TXDATA);
	efm32_spi_vdbg(ddata, "%s: tx 0x%x\n", __func__, val);
}

static void efm32_spi_rx_u8(struct efm32_spi_ddata *ddata)
{
	u32 rxdata = efm32_spi_read32(ddata, REG_RXDATAX);
	efm32_spi_vdbg(ddata, "%s: rx 0x%x\n", __func__, rxdata);

	if (ddata->rx_buf) {
		*ddata->rx_buf = rxdata;
		ddata->rx_buf++;
	}

	ddata->rx_len--;
}

static void efm32_spi_filltx(struct efm32_spi_ddata *ddata)
{
	while (ddata->tx_len &&
			ddata->tx_len + 2 > ddata->rx_len &&
			efm32_spi_read32(ddata, REG_STATUS) & REG_STATUS_TXBL) {
		efm32_spi_tx_u8(ddata);
	}
}

static int efm32_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master);
	int ret = -EBUSY;

	spin_lock_irq(&ddata->lock);

	if (ddata->tx_buf || ddata->rx_buf)
		goto out_unlock;

	ddata->tx_buf = t->tx_buf;
	ddata->rx_buf = t->rx_buf;
	ddata->tx_len = ddata->rx_len =
		t->len * DIV_ROUND_UP(t->bits_per_word, 8);

	efm32_spi_filltx(ddata);

	reinit_completion(&ddata->done);

	efm32_spi_write32(ddata, REG_IF_TXBL | REG_IF_RXDATAV, REG_IEN);

	spin_unlock_irq(&ddata->lock);

	wait_for_completion(&ddata->done);

	spin_lock_irq(&ddata->lock);

	ret = t->len - max(ddata->tx_len, ddata->rx_len);

	efm32_spi_write32(ddata, 0, REG_IEN);
	ddata->tx_buf = ddata->rx_buf = NULL;

out_unlock:
	spin_unlock_irq(&ddata->lock);

	return ret;
}

static irqreturn_t efm32_spi_rxirq(int irq, void *data)
{
	struct efm32_spi_ddata *ddata = data;
	irqreturn_t ret = IRQ_NONE;

	spin_lock(&ddata->lock);

	while (ddata->rx_len > 0 &&
			efm32_spi_read32(ddata, REG_STATUS) &
			REG_STATUS_RXDATAV) {
		efm32_spi_rx_u8(ddata);

		ret = IRQ_HANDLED;
	}

	if (!ddata->rx_len) {
		u32 ien = efm32_spi_read32(ddata, REG_IEN);

		ien &= ~REG_IF_RXDATAV;

		efm32_spi_write32(ddata, ien, REG_IEN);

		complete(&ddata->done);
	}

	spin_unlock(&ddata->lock);

	return ret;
}

static irqreturn_t efm32_spi_txirq(int irq, void *data)
{
	struct efm32_spi_ddata *ddata = data;

	efm32_spi_vdbg(ddata,
			"%s: txlen = %u, rxlen = %u, if=0x%08x, stat=0x%08x\n",
			__func__, ddata->tx_len, ddata->rx_len,
			efm32_spi_read32(ddata, REG_IF),
			efm32_spi_read32(ddata, REG_STATUS));

	spin_lock(&ddata->lock);

	efm32_spi_filltx(ddata);

	efm32_spi_vdbg(ddata, "%s: txlen = %u, rxlen = %u\n",
			__func__, ddata->tx_len, ddata->rx_len);

	if (!ddata->tx_len) {
		u32 ien = efm32_spi_read32(ddata, REG_IEN);

		ien &= ~REG_IF_TXBL;

		efm32_spi_write32(ddata, ien, REG_IEN);
		efm32_spi_vdbg(ddata, "disable TXBL\n");
	}

	spin_unlock(&ddata->lock);

	return IRQ_HANDLED;
}

static u32 efm32_spi_get_configured_location(struct efm32_spi_ddata *ddata)
{
	u32 reg = efm32_spi_read32(ddata, REG_ROUTE);

	return (reg & REG_ROUTE_LOCATION__MASK) >> __ffs(REG_ROUTE_LOCATION__MASK);
}

static void efm32_spi_probe_dt(struct platform_device *pdev,
		struct spi_master *master, struct efm32_spi_ddata *ddata)
{
	struct device_node *np = pdev->dev.of_node;
	u32 location;
	int ret;

	ret = of_property_read_u32(np, "energymicro,location", &location);

	if (ret)
		/* fall back to wrongly namespaced property */
		ret = of_property_read_u32(np, "efm32,location", &location);

	if (ret)
		/* fall back to old and (wrongly) generic property "location" */
		ret = of_property_read_u32(np, "location", &location);

	if (!ret) {
		dev_dbg(&pdev->dev, "using location %u\n", location);
	} else {
		/* default to location configured in hardware */
		location = efm32_spi_get_configured_location(ddata);

		dev_info(&pdev->dev, "fall back to location %u\n", location);
	}

	ddata->pdata.location = location;
}

static int efm32_spi_probe(struct platform_device *pdev)
{
	struct efm32_spi_ddata *ddata;
	struct resource *res;
	int ret;
	struct spi_master *master;
	struct device_node *np = pdev->dev.of_node;
	int num_cs, i;

	if (!np)
		return -EINVAL;

	num_cs = of_gpio_named_count(np, "cs-gpios");
	if (num_cs < 0)
		return num_cs;

	master = spi_alloc_master(&pdev->dev,
			sizeof(*ddata) + num_cs * sizeof(unsigned));
	if (!master) {
		dev_dbg(&pdev->dev,
				"failed to allocate spi master controller\n");
		return -ENOMEM;
	}
	platform_set_drvdata(pdev, master);

	master->dev.of_node = pdev->dev.of_node;

	master->num_chipselect = num_cs;
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);

	ddata = spi_master_get_devdata(master);

	ddata->bitbang.master = master;
	ddata->bitbang.chipselect = efm32_spi_chipselect;
	ddata->bitbang.setup_transfer = efm32_spi_setup_transfer;
	ddata->bitbang.txrx_bufs = efm32_spi_txrx_bufs;

	spin_lock_init(&ddata->lock);
	init_completion(&ddata->done);

	ddata->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(ddata->clk)) {
		ret = PTR_ERR(ddata->clk);
		dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
		goto err;
	}

	for (i = 0; i < num_cs; ++i) {
		ret = of_get_named_gpio(np, "cs-gpios", i);
		if (ret < 0) {
			dev_err(&pdev->dev, "failed to get csgpio#%u (%d)\n",
					i, ret);
			goto err;
		}
		ddata->csgpio[i] = ret;
		dev_dbg(&pdev->dev, "csgpio#%u = %u\n", i, ddata->csgpio[i]);
		ret = devm_gpio_request_one(&pdev->dev, ddata->csgpio[i],
				GPIOF_OUT_INIT_LOW, DRIVER_NAME);
		if (ret < 0) {
			dev_err(&pdev->dev,
					"failed to configure csgpio#%u (%d)\n",
					i, ret);
			goto err;
		}
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		ret = -ENODEV;
		dev_err(&pdev->dev, "failed to determine base address\n");
		goto err;
	}

	if (resource_size(res) < 0x60) {
		ret = -EINVAL;
		dev_err(&pdev->dev, "memory resource too small\n");
		goto err;
	}

	ddata->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(ddata->base)) {
		ret = PTR_ERR(ddata->base);
		goto err;
	}

	ret = platform_get_irq(pdev, 0);
	if (ret <= 0) {
		dev_err(&pdev->dev, "failed to get rx irq (%d)\n", ret);
		goto err;
	}

	ddata->rxirq = ret;

	ret = platform_get_irq(pdev, 1);
	if (ret <= 0)
		ret = ddata->rxirq + 1;

	ddata->txirq = ret;

	ret = clk_prepare_enable(ddata->clk);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret);
		goto err;
	}

	efm32_spi_probe_dt(pdev, master, ddata);

	efm32_spi_write32(ddata, 0, REG_IEN);
	efm32_spi_write32(ddata, REG_ROUTE_TXPEN | REG_ROUTE_RXPEN |
			REG_ROUTE_CLKPEN |
			REG_ROUTE_LOCATION(ddata->pdata.location), REG_ROUTE);

	ret = request_irq(ddata->rxirq, efm32_spi_rxirq,
			0, DRIVER_NAME " rx", ddata);
	if (ret) {
		dev_err(&pdev->dev, "failed to register rxirq (%d)\n", ret);
		goto err_disable_clk;
	}

	ret = request_irq(ddata->txirq, efm32_spi_txirq,
			0, DRIVER_NAME " tx", ddata);
	if (ret) {
		dev_err(&pdev->dev, "failed to register txirq (%d)\n", ret);
		goto err_free_rx_irq;
	}

	ret = spi_bitbang_start(&ddata->bitbang);
	if (ret) {
		dev_err(&pdev->dev, "spi_bitbang_start failed (%d)\n", ret);

		free_irq(ddata->txirq, ddata);
err_free_rx_irq:
		free_irq(ddata->rxirq, ddata);
err_disable_clk:
		clk_disable_unprepare(ddata->clk);
err:
		spi_master_put(master);
	}

	return ret;
}

static int efm32_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct efm32_spi_ddata *ddata = spi_master_get_devdata(master);

	spi_bitbang_stop(&ddata->bitbang);

	efm32_spi_write32(ddata, 0, REG_IEN);

	free_irq(ddata->txirq, ddata);
	free_irq(ddata->rxirq, ddata);
	clk_disable_unprepare(ddata->clk);
	spi_master_put(master);

	return 0;
}

static const struct of_device_id efm32_spi_dt_ids[] = {
	{
		.compatible = "energymicro,efm32-spi",
	}, {
		/* doesn't follow the "vendor,device" scheme, don't use */
		.compatible = "efm32,spi",
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(of, efm32_spi_dt_ids);

static struct platform_driver efm32_spi_driver = {
	.probe = efm32_spi_probe,
	.remove = efm32_spi_remove,

	.driver = {
		.name = DRIVER_NAME,
		.of_match_table = efm32_spi_dt_ids,
	},
};
module_platform_driver(efm32_spi_driver);

MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
MODULE_DESCRIPTION("EFM32 SPI driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
86f8973c UKK	2	/*
86f8973c UKK	3	* Copyright (C) 2012-2013 Uwe Kleine-Koenig for Pengutronix
86f8973c UKK	4	*/
	5	#include <linux/kernel.h>
	6	#include <linux/io.h>
	7	#include <linux/spi/spi.h>
	8	#include <linux/spi/spi_bitbang.h>
	9	#include <linux/gpio.h>
	10	#include <linux/interrupt.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/clk.h>
	13	#include <linux/err.h>
	14	#include <linux/module.h>
	15	#include <linux/of_gpio.h>
	16	#include <linux/platform_data/efm32-spi.h>
	17
	18	#define DRIVER_NAME "efm32-spi"
	19
	20	#define MASK_VAL(mask, val) ((val << __ffs(mask)) & mask)
	21
	22	#define REG_CTRL 0x00
	23	#define REG_CTRL_SYNC 0x0001
	24	#define REG_CTRL_CLKPOL 0x0100
	25	#define REG_CTRL_CLKPHA 0x0200
	26	#define REG_CTRL_MSBF 0x0400
	27	#define REG_CTRL_TXBIL 0x1000
	28
	29	#define REG_FRAME 0x04
	30	#define REG_FRAME_DATABITS__MASK 0x000f
	31	#define REG_FRAME_DATABITS(n) ((n) - 3)
	32
	33	#define REG_CMD 0x0c
	34	#define REG_CMD_RXEN 0x0001
	35	#define REG_CMD_RXDIS 0x0002
	36	#define REG_CMD_TXEN 0x0004
	37	#define REG_CMD_TXDIS 0x0008
	38	#define REG_CMD_MASTEREN 0x0010
	39
	40	#define REG_STATUS 0x10
	41	#define REG_STATUS_TXENS 0x0002
	42	#define REG_STATUS_TXC 0x0020
	43	#define REG_STATUS_TXBL 0x0040
	44	#define REG_STATUS_RXDATAV 0x0080
	45
	46	#define REG_CLKDIV 0x14
	47
	48	#define REG_RXDATAX 0x18
	49	#define REG_RXDATAX_RXDATA__MASK 0x01ff
	50	#define REG_RXDATAX_PERR 0x4000
	51	#define REG_RXDATAX_FERR 0x8000
	52
	53	#define REG_TXDATA 0x34
	54
	55	#define REG_IF 0x40
	56	#define REG_IF_TXBL 0x0002
	57	#define REG_IF_RXDATAV 0x0004
	58
	59	#define REG_IFS 0x44
	60	#define REG_IFC 0x48
	61	#define REG_IEN 0x4c
	62
	63	#define REG_ROUTE 0x54
	64	#define REG_ROUTE_RXPEN 0x0001
	65	#define REG_ROUTE_TXPEN 0x0002
	66	#define REG_ROUTE_CLKPEN 0x0008
	67	#define REG_ROUTE_LOCATION__MASK 0x0700
68	#define REG_ROUTE_LOCATION(n) MASK_VAL(REG_ROUTE_LOCATION__MASK, (n))
69
70	struct efm32_spi_ddata {
71	struct spi_bitbang bitbang;
72
73	spinlock_t lock;
74
75	struct clk *clk;
76	void __iomem *base;
77	unsigned int rxirq, txirq;
78	struct efm32_spi_pdata pdata;
79
80	/* irq data */
81	struct completion done;
82	const u8 *tx_buf;
83	u8 *rx_buf;
84	unsigned tx_len, rx_len;
85
86	/* chip selects */
87	unsigned csgpio[];
88	};
89
90	#define ddata_to_dev(ddata) (&(ddata->bitbang.master->dev))
91	#define efm32_spi_vdbg(ddata, format, arg...) \
92	dev_vdbg(ddata_to_dev(ddata), format, ##arg)
93
94	static void efm32_spi_write32(struct efm32_spi_ddata *ddata,
95	u32 value, unsigned offset)
96	{
97	writel_relaxed(value, ddata->base + offset);
98	}
99
100	static u32 efm32_spi_read32(struct efm32_spi_ddata *ddata, unsigned offset)
101	{
102	return readl_relaxed(ddata->base + offset);
103	}
104
105	static void efm32_spi_chipselect(struct spi_device *spi, int is_on)
106	{
107	struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master);
108	int value = !(spi->mode & SPI_CS_HIGH) == !(is_on == BITBANG_CS_ACTIVE);
109
110	gpio_set_value(ddata->csgpio[spi->chip_select], value);
111	}
112
113	static int efm32_spi_setup_transfer(struct spi_device *spi,
114	struct spi_transfer *t)
115	{
116	struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master);
117
118	unsigned bpw = t->bits_per_word ?: spi->bits_per_word;
119	unsigned speed = t->speed_hz ?: spi->max_speed_hz;
120	unsigned long clkfreq = clk_get_rate(ddata->clk);
121	u32 clkdiv;
122
123	efm32_spi_write32(ddata, REG_CTRL_SYNC \| REG_CTRL_MSBF \|
124	(spi->mode & SPI_CPHA ? REG_CTRL_CLKPHA : 0) \|
125	(spi->mode & SPI_CPOL ? REG_CTRL_CLKPOL : 0), REG_CTRL);
126
127	efm32_spi_write32(ddata,
128	REG_FRAME_DATABITS(bpw), REG_FRAME);
129
130	if (2 * speed >= clkfreq)
131	clkdiv = 0;
132	else
133	clkdiv = 64 * (DIV_ROUND_UP(2 * clkfreq, speed) - 4);
134
135	if (clkdiv > (1U << 21))
136	return -EINVAL;
137
138	efm32_spi_write32(ddata, clkdiv, REG_CLKDIV);
139	efm32_spi_write32(ddata, REG_CMD_MASTEREN, REG_CMD);
140	efm32_spi_write32(ddata, REG_CMD_RXEN \| REG_CMD_TXEN, REG_CMD);
141
142	return 0;
143	}
144
145	static void efm32_spi_tx_u8(struct efm32_spi_ddata *ddata)
146	{
147	u8 val = 0;
148
149	if (ddata->tx_buf) {
150	val = *ddata->tx_buf;
151	ddata->tx_buf++;
152	}
153
154	ddata->tx_len--;
155	efm32_spi_write32(ddata, val, REG_TXDATA);
156	efm32_spi_vdbg(ddata, "%s: tx 0x%x\n", __func__, val);
157	}
158
159	static void efm32_spi_rx_u8(struct efm32_spi_ddata *ddata)
160	{
161	u32 rxdata = efm32_spi_read32(ddata, REG_RXDATAX);
162	efm32_spi_vdbg(ddata, "%s: rx 0x%x\n", __func__, rxdata);
163
164	if (ddata->rx_buf) {
165	*ddata->rx_buf = rxdata;
166	ddata->rx_buf++;
167	}
168
169	ddata->rx_len--;
170	}
171
172	static void efm32_spi_filltx(struct efm32_spi_ddata *ddata)
173	{
174	while (ddata->tx_len &&
175	ddata->tx_len + 2 > ddata->rx_len &&
176	efm32_spi_read32(ddata, REG_STATUS) & REG_STATUS_TXBL) {
177	efm32_spi_tx_u8(ddata);
178	}
179	}
180
181	static int efm32_spi_txrx_bufs(struct spi_device spi, struct spi_transfer t)
182	{
183	struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master);
184	int ret = -EBUSY;
185
186	spin_lock_irq(&ddata->lock);
187
188	if (ddata->tx_buf \|\| ddata->rx_buf)
189	goto out_unlock;
190
191	ddata->tx_buf = t->tx_buf;
192	ddata->rx_buf = t->rx_buf;
193	ddata->tx_len = ddata->rx_len =
194	t->len * DIV_ROUND_UP(t->bits_per_word, 8);
195
196	efm32_spi_filltx(ddata);
197
aa0fe826	198	reinit_completion(&ddata->done);
86f8973c UKK	199
	200	efm32_spi_write32(ddata, REG_IF_TXBL \| REG_IF_RXDATAV, REG_IEN);
	201
	202	spin_unlock_irq(&ddata->lock);
	203
	204	wait_for_completion(&ddata->done);
	205
	206	spin_lock_irq(&ddata->lock);
	207
	208	ret = t->len - max(ddata->tx_len, ddata->rx_len);
	209
	210	efm32_spi_write32(ddata, 0, REG_IEN);
	211	ddata->tx_buf = ddata->rx_buf = NULL;
	212
	213	out_unlock:
	214	spin_unlock_irq(&ddata->lock);
	215
	216	return ret;
	217	}
	218
	219	static irqreturn_t efm32_spi_rxirq(int irq, void *data)
	220	{
	221	struct efm32_spi_ddata *ddata = data;
	222	irqreturn_t ret = IRQ_NONE;
	223
	224	spin_lock(&ddata->lock);
	225
	226	while (ddata->rx_len > 0 &&
	227	efm32_spi_read32(ddata, REG_STATUS) &
	228	REG_STATUS_RXDATAV) {
	229	efm32_spi_rx_u8(ddata);
	230
	231	ret = IRQ_HANDLED;
	232	}
	233
	234	if (!ddata->rx_len) {
	235	u32 ien = efm32_spi_read32(ddata, REG_IEN);
	236
	237	ien &= ~REG_IF_RXDATAV;
	238
	239	efm32_spi_write32(ddata, ien, REG_IEN);
	240
	241	complete(&ddata->done);
	242	}
	243
	244	spin_unlock(&ddata->lock);
	245
	246	return ret;
	247	}
	248
	249	static irqreturn_t efm32_spi_txirq(int irq, void *data)
	250	{
	251	struct efm32_spi_ddata *ddata = data;
	252
	253	efm32_spi_vdbg(ddata,
	254	"%s: txlen = %u, rxlen = %u, if=0x%08x, stat=0x%08x\n",
	255	__func__, ddata->tx_len, ddata->rx_len,
	256	efm32_spi_read32(ddata, REG_IF),
	257	efm32_spi_read32(ddata, REG_STATUS));
	258
	259	spin_lock(&ddata->lock);
	260
	261	efm32_spi_filltx(ddata);
	262
263	efm32_spi_vdbg(ddata, "%s: txlen = %u, rxlen = %u\n",
264	__func__, ddata->tx_len, ddata->rx_len);
265
266	if (!ddata->tx_len) {
267	u32 ien = efm32_spi_read32(ddata, REG_IEN);
268
269	ien &= ~REG_IF_TXBL;
270
271	efm32_spi_write32(ddata, ien, REG_IEN);
272	efm32_spi_vdbg(ddata, "disable TXBL\n");
273	}
274
275	spin_unlock(&ddata->lock);
276
277	return IRQ_HANDLED;
278	}
279
86f8973c UKK	280	static u32 efm32_spi_get_configured_location(struct efm32_spi_ddata *ddata)
	281	{
	282	u32 reg = efm32_spi_read32(ddata, REG_ROUTE);
	283
	284	return (reg & REG_ROUTE_LOCATION__MASK) >> __ffs(REG_ROUTE_LOCATION__MASK);
	285	}
	286
f9f4cbde	287	static void efm32_spi_probe_dt(struct platform_device *pdev,
86f8973c UKK	288	struct spi_master master, struct efm32_spi_ddata ddata)
	289	{
	290	struct device_node *np = pdev->dev.of_node;
	291	u32 location;
	292	int ret;
	293
10ed7e98 UKK	294	ret = of_property_read_u32(np, "energymicro,location", &location);
	295
	296	if (ret)
	297	/* fall back to wrongly namespaced property */
	298	ret = of_property_read_u32(np, "efm32,location", &location);
	299
f2bb3105 UKK	300	if (ret)
	301	/* fall back to old and (wrongly) generic property "location" */
	302	ret = of_property_read_u32(np, "location", &location);
10ed7e98	303
86f8973c UKK	304	if (!ret) {
	305	dev_dbg(&pdev->dev, "using location %u\n", location);
	306	} else {
	307	/* default to location configured in hardware */
	308	location = efm32_spi_get_configured_location(ddata);
	309
	310	dev_info(&pdev->dev, "fall back to location %u\n", location);
	311	}
	312
	313	ddata->pdata.location = location;
86f8973c UKK	314	}
	315
	316	static int efm32_spi_probe(struct platform_device *pdev)
	317	{
	318	struct efm32_spi_ddata *ddata;
	319	struct resource *res;
	320	int ret;
	321	struct spi_master *master;
	322	struct device_node *np = pdev->dev.of_node;
f9f4cbde AL	323	int num_cs, i;
	324
	325	if (!np)
	326	return -EINVAL;
86f8973c UKK	327
86f8973c UKK	328	num_cs = of_gpio_named_count(np, "cs-gpios");
f9f4cbde AL	329	if (num_cs < 0)
f9f4cbde AL	330	return num_cs;
86f8973c UKK	331
	332	master = spi_alloc_master(&pdev->dev,
	333	sizeof(ddata) + num_cs sizeof(unsigned));
	334	if (!master) {
	335	dev_dbg(&pdev->dev,
	336	"failed to allocate spi master controller\n");
	337	return -ENOMEM;
	338	}
	339	platform_set_drvdata(pdev, master);
	340
	341	master->dev.of_node = pdev->dev.of_node;
	342
	343	master->num_chipselect = num_cs;
	344	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH;
	345	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
	346
	347	ddata = spi_master_get_devdata(master);
	348
702a4879	349	ddata->bitbang.master = master;
86f8973c UKK	350	ddata->bitbang.chipselect = efm32_spi_chipselect;
	351	ddata->bitbang.setup_transfer = efm32_spi_setup_transfer;
	352	ddata->bitbang.txrx_bufs = efm32_spi_txrx_bufs;
	353
	354	spin_lock_init(&ddata->lock);
aa0fe826	355	init_completion(&ddata->done);
86f8973c UKK	356
	357	ddata->clk = devm_clk_get(&pdev->dev, NULL);
	358	if (IS_ERR(ddata->clk)) {
	359	ret = PTR_ERR(ddata->clk);
	360	dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
	361	goto err;
	362	}
	363
	364	for (i = 0; i < num_cs; ++i) {
	365	ret = of_get_named_gpio(np, "cs-gpios", i);
	366	if (ret < 0) {
	367	dev_err(&pdev->dev, "failed to get csgpio#%u (%d)\n",
	368	i, ret);
	369	goto err;
	370	}
	371	ddata->csgpio[i] = ret;
	372	dev_dbg(&pdev->dev, "csgpio#%u = %u\n", i, ddata->csgpio[i]);
	373	ret = devm_gpio_request_one(&pdev->dev, ddata->csgpio[i],
	374	GPIOF_OUT_INIT_LOW, DRIVER_NAME);
	375	if (ret < 0) {
	376	dev_err(&pdev->dev,
	377	"failed to configure csgpio#%u (%d)\n",
	378	i, ret);
	379	goto err;
	380	}
	381	}
	382
	383	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	384	if (!res) {
	385	ret = -ENODEV;
	386	dev_err(&pdev->dev, "failed to determine base address\n");
	387	goto err;
	388	}
	389
6a009e8d	390	if (resource_size(res) < 0x60) {
86f8973c UKK	391	ret = -EINVAL;
	392	dev_err(&pdev->dev, "memory resource too small\n");
	393	goto err;
	394	}
	395
	396	ddata->base = devm_ioremap_resource(&pdev->dev, res);
	397	if (IS_ERR(ddata->base)) {
	398	ret = PTR_ERR(ddata->base);
86f8973c UKK	399	goto err;
	400	}
	401
	402	ret = platform_get_irq(pdev, 0);
	403	if (ret <= 0) {
	404	dev_err(&pdev->dev, "failed to get rx irq (%d)\n", ret);
	405	goto err;
	406	}
	407
	408	ddata->rxirq = ret;
	409
	410	ret = platform_get_irq(pdev, 1);
	411	if (ret <= 0)
	412	ret = ddata->rxirq + 1;
	413
	414	ddata->txirq = ret;
	415
	416	ret = clk_prepare_enable(ddata->clk);
	417	if (ret < 0) {
	418	dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret);
	419	goto err;
	420	}
	421
f9f4cbde	422	efm32_spi_probe_dt(pdev, master, ddata);
86f8973c UKK	423
	424	efm32_spi_write32(ddata, 0, REG_IEN);
	425	efm32_spi_write32(ddata, REG_ROUTE_TXPEN \| REG_ROUTE_RXPEN \|
	426	REG_ROUTE_CLKPEN \|
	427	REG_ROUTE_LOCATION(ddata->pdata.location), REG_ROUTE);
	428
	429	ret = request_irq(ddata->rxirq, efm32_spi_rxirq,
	430	0, DRIVER_NAME " rx", ddata);
	431	if (ret) {
	432	dev_err(&pdev->dev, "failed to register rxirq (%d)\n", ret);
	433	goto err_disable_clk;
	434	}
	435
	436	ret = request_irq(ddata->txirq, efm32_spi_txirq,
	437	0, DRIVER_NAME " tx", ddata);
	438	if (ret) {
	439	dev_err(&pdev->dev, "failed to register txirq (%d)\n", ret);
	440	goto err_free_rx_irq;
	441	}
	442
	443	ret = spi_bitbang_start(&ddata->bitbang);
	444	if (ret) {
	445	dev_err(&pdev->dev, "spi_bitbang_start failed (%d)\n", ret);
	446
	447	free_irq(ddata->txirq, ddata);
	448	err_free_rx_irq:
	449	free_irq(ddata->rxirq, ddata);
	450	err_disable_clk:
	451	clk_disable_unprepare(ddata->clk);
	452	err:
	453	spi_master_put(master);
86f8973c UKK	454	}
	455
	456	return ret;
	457	}
	458
	459	static int efm32_spi_remove(struct platform_device *pdev)
	460	{
	461	struct spi_master *master = platform_get_drvdata(pdev);
	462	struct efm32_spi_ddata *ddata = spi_master_get_devdata(master);
	463
e6f7563b UKK	464	spi_bitbang_stop(&ddata->bitbang);
e6f7563b UKK	465
86f8973c UKK	466	efm32_spi_write32(ddata, 0, REG_IEN);
	467
	468	free_irq(ddata->txirq, ddata);
	469	free_irq(ddata->rxirq, ddata);
	470	clk_disable_unprepare(ddata->clk);
	471	spi_master_put(master);
86f8973c UKK	472
	473	return 0;
	474	}
	475
	476	static const struct of_device_id efm32_spi_dt_ids[] = {
	477	{
12f6dd86 UKK	478	.compatible = "energymicro,efm32-spi",
	479	}, {
	480	/* doesn't follow the "vendor,device" scheme, don't use */
86f8973c UKK	481	.compatible = "efm32,spi",
	482	}, {
	483	/* sentinel */
	484	}
	485	};
d8851a0d	486	MODULE_DEVICE_TABLE(of, efm32_spi_dt_ids);
86f8973c UKK	487
	488	static struct platform_driver efm32_spi_driver = {
	489	.probe = efm32_spi_probe,
	490	.remove = efm32_spi_remove,
	491
	492	.driver = {
	493	.name = DRIVER_NAME,
86f8973c UKK	494	.of_match_table = efm32_spi_dt_ids,
	495	},
	496	};
	497	module_platform_driver(efm32_spi_driver);
	498
	499	MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
	500	MODULE_DESCRIPTION("EFM32 SPI driver");
	501	MODULE_LICENSE("GPL v2");
	502	MODULE_ALIAS("platform:" DRIVER_NAME);