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011f23a3 MW |
1 | /* |
2 | * Driver for Cirrus Logic EP93xx SPI controller. | |
3 | * | |
626a96db | 4 | * Copyright (C) 2010-2011 Mika Westerberg |
011f23a3 MW |
5 | * |
6 | * Explicit FIFO handling code was inspired by amba-pl022 driver. | |
7 | * | |
8 | * Chip select support using other than built-in GPIOs by H. Hartley Sweeten. | |
9 | * | |
10 | * For more information about the SPI controller see documentation on Cirrus | |
11 | * Logic web site: | |
12 | * http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | */ | |
18 | ||
19 | #include <linux/io.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/device.h> | |
626a96db | 24 | #include <linux/dmaengine.h> |
011f23a3 MW |
25 | #include <linux/bitops.h> |
26 | #include <linux/interrupt.h> | |
5bdb7613 | 27 | #include <linux/module.h> |
011f23a3 | 28 | #include <linux/platform_device.h> |
011f23a3 | 29 | #include <linux/sched.h> |
626a96db | 30 | #include <linux/scatterlist.h> |
55f0cd3f | 31 | #include <linux/gpio.h> |
011f23a3 MW |
32 | #include <linux/spi/spi.h> |
33 | ||
a3b29245 AB |
34 | #include <linux/platform_data/dma-ep93xx.h> |
35 | #include <linux/platform_data/spi-ep93xx.h> | |
011f23a3 MW |
36 | |
37 | #define SSPCR0 0x0000 | |
38 | #define SSPCR0_MODE_SHIFT 6 | |
39 | #define SSPCR0_SCR_SHIFT 8 | |
40 | ||
41 | #define SSPCR1 0x0004 | |
42 | #define SSPCR1_RIE BIT(0) | |
43 | #define SSPCR1_TIE BIT(1) | |
44 | #define SSPCR1_RORIE BIT(2) | |
45 | #define SSPCR1_LBM BIT(3) | |
46 | #define SSPCR1_SSE BIT(4) | |
47 | #define SSPCR1_MS BIT(5) | |
48 | #define SSPCR1_SOD BIT(6) | |
49 | ||
50 | #define SSPDR 0x0008 | |
51 | ||
52 | #define SSPSR 0x000c | |
53 | #define SSPSR_TFE BIT(0) | |
54 | #define SSPSR_TNF BIT(1) | |
55 | #define SSPSR_RNE BIT(2) | |
56 | #define SSPSR_RFF BIT(3) | |
57 | #define SSPSR_BSY BIT(4) | |
58 | #define SSPCPSR 0x0010 | |
59 | ||
60 | #define SSPIIR 0x0014 | |
61 | #define SSPIIR_RIS BIT(0) | |
62 | #define SSPIIR_TIS BIT(1) | |
63 | #define SSPIIR_RORIS BIT(2) | |
64 | #define SSPICR SSPIIR | |
65 | ||
66 | /* timeout in milliseconds */ | |
67 | #define SPI_TIMEOUT 5 | |
68 | /* maximum depth of RX/TX FIFO */ | |
69 | #define SPI_FIFO_SIZE 8 | |
70 | ||
71 | /** | |
72 | * struct ep93xx_spi - EP93xx SPI controller structure | |
011f23a3 MW |
73 | * @pdev: pointer to platform device |
74 | * @clk: clock for the controller | |
1232978a | 75 | * @mmio: pointer to ioremap()'d registers |
626a96db | 76 | * @sspdr_phys: physical address of the SSPDR register |
011f23a3 | 77 | * @wait: wait here until given transfer is completed |
011f23a3 MW |
78 | * @current_msg: message that is currently processed (or %NULL if none) |
79 | * @tx: current byte in transfer to transmit | |
80 | * @rx: current byte in transfer to receive | |
81 | * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one | |
82 | * frame decreases this level and sending one frame increases it. | |
626a96db MW |
83 | * @dma_rx: RX DMA channel |
84 | * @dma_tx: TX DMA channel | |
85 | * @dma_rx_data: RX parameters passed to the DMA engine | |
86 | * @dma_tx_data: TX parameters passed to the DMA engine | |
87 | * @rx_sgt: sg table for RX transfers | |
88 | * @tx_sgt: sg table for TX transfers | |
89 | * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by | |
90 | * the client | |
011f23a3 MW |
91 | */ |
92 | struct ep93xx_spi { | |
011f23a3 MW |
93 | const struct platform_device *pdev; |
94 | struct clk *clk; | |
1232978a | 95 | void __iomem *mmio; |
626a96db | 96 | unsigned long sspdr_phys; |
011f23a3 | 97 | struct completion wait; |
011f23a3 MW |
98 | struct spi_message *current_msg; |
99 | size_t tx; | |
100 | size_t rx; | |
101 | size_t fifo_level; | |
626a96db MW |
102 | struct dma_chan *dma_rx; |
103 | struct dma_chan *dma_tx; | |
104 | struct ep93xx_dma_data dma_rx_data; | |
105 | struct ep93xx_dma_data dma_tx_data; | |
106 | struct sg_table rx_sgt; | |
107 | struct sg_table tx_sgt; | |
108 | void *zeropage; | |
011f23a3 MW |
109 | }; |
110 | ||
011f23a3 MW |
111 | /* converts bits per word to CR0.DSS value */ |
112 | #define bits_per_word_to_dss(bpw) ((bpw) - 1) | |
113 | ||
011f23a3 MW |
114 | static int ep93xx_spi_enable(const struct ep93xx_spi *espi) |
115 | { | |
8447e478 | 116 | u32 val; |
011f23a3 MW |
117 | int err; |
118 | ||
119 | err = clk_enable(espi->clk); | |
120 | if (err) | |
121 | return err; | |
122 | ||
8447e478 HS |
123 | val = readl(espi->mmio + SSPCR1); |
124 | val |= SSPCR1_SSE; | |
125 | writel(val, espi->mmio + SSPCR1); | |
011f23a3 MW |
126 | |
127 | return 0; | |
128 | } | |
129 | ||
130 | static void ep93xx_spi_disable(const struct ep93xx_spi *espi) | |
131 | { | |
8447e478 | 132 | u32 val; |
011f23a3 | 133 | |
8447e478 HS |
134 | val = readl(espi->mmio + SSPCR1); |
135 | val &= ~SSPCR1_SSE; | |
136 | writel(val, espi->mmio + SSPCR1); | |
011f23a3 MW |
137 | |
138 | clk_disable(espi->clk); | |
139 | } | |
140 | ||
141 | static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi) | |
142 | { | |
8447e478 | 143 | u32 val; |
011f23a3 | 144 | |
8447e478 HS |
145 | val = readl(espi->mmio + SSPCR1); |
146 | val |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); | |
147 | writel(val, espi->mmio + SSPCR1); | |
011f23a3 MW |
148 | } |
149 | ||
150 | static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi) | |
151 | { | |
8447e478 | 152 | u32 val; |
011f23a3 | 153 | |
8447e478 HS |
154 | val = readl(espi->mmio + SSPCR1); |
155 | val &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); | |
156 | writel(val, espi->mmio + SSPCR1); | |
011f23a3 MW |
157 | } |
158 | ||
159 | /** | |
160 | * ep93xx_spi_calc_divisors() - calculates SPI clock divisors | |
161 | * @espi: ep93xx SPI controller struct | |
011f23a3 | 162 | * @rate: desired SPI output clock rate |
f7ef1da9 HS |
163 | * @div_cpsr: pointer to return the cpsr (pre-scaler) divider |
164 | * @div_scr: pointer to return the scr divider | |
011f23a3 MW |
165 | */ |
166 | static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi, | |
56fc0b42 | 167 | u32 rate, u8 *div_cpsr, u8 *div_scr) |
011f23a3 | 168 | { |
56fc0b42 | 169 | struct spi_master *master = platform_get_drvdata(espi->pdev); |
011f23a3 MW |
170 | unsigned long spi_clk_rate = clk_get_rate(espi->clk); |
171 | int cpsr, scr; | |
172 | ||
173 | /* | |
174 | * Make sure that max value is between values supported by the | |
175 | * controller. Note that minimum value is already checked in | |
84ddb3c1 | 176 | * ep93xx_spi_transfer_one_message(). |
011f23a3 | 177 | */ |
56fc0b42 | 178 | rate = clamp(rate, master->min_speed_hz, master->max_speed_hz); |
011f23a3 MW |
179 | |
180 | /* | |
181 | * Calculate divisors so that we can get speed according the | |
182 | * following formula: | |
183 | * rate = spi_clock_rate / (cpsr * (1 + scr)) | |
184 | * | |
185 | * cpsr must be even number and starts from 2, scr can be any number | |
186 | * between 0 and 255. | |
187 | */ | |
188 | for (cpsr = 2; cpsr <= 254; cpsr += 2) { | |
189 | for (scr = 0; scr <= 255; scr++) { | |
190 | if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) { | |
f7ef1da9 HS |
191 | *div_scr = (u8)scr; |
192 | *div_cpsr = (u8)cpsr; | |
011f23a3 MW |
193 | return 0; |
194 | } | |
195 | } | |
196 | } | |
197 | ||
198 | return -EINVAL; | |
199 | } | |
200 | ||
55f0cd3f | 201 | static void ep93xx_spi_cs_control(struct spi_device *spi, bool enable) |
011f23a3 | 202 | { |
55f0cd3f HS |
203 | if (spi->mode & SPI_CS_HIGH) |
204 | enable = !enable; | |
011f23a3 | 205 | |
55f0cd3f HS |
206 | if (gpio_is_valid(spi->cs_gpio)) |
207 | gpio_set_value(spi->cs_gpio, !enable); | |
011f23a3 MW |
208 | } |
209 | ||
f7ef1da9 | 210 | static int ep93xx_spi_chip_setup(const struct ep93xx_spi *espi, |
55f0cd3f HS |
211 | struct spi_device *spi, |
212 | struct spi_transfer *xfer) | |
011f23a3 | 213 | { |
55f0cd3f | 214 | u8 dss = bits_per_word_to_dss(xfer->bits_per_word); |
f7ef1da9 HS |
215 | u8 div_cpsr = 0; |
216 | u8 div_scr = 0; | |
011f23a3 | 217 | u16 cr0; |
f7ef1da9 HS |
218 | int err; |
219 | ||
55f0cd3f HS |
220 | err = ep93xx_spi_calc_divisors(espi, xfer->speed_hz, |
221 | &div_cpsr, &div_scr); | |
f7ef1da9 HS |
222 | if (err) |
223 | return err; | |
011f23a3 | 224 | |
f7ef1da9 | 225 | cr0 = div_scr << SSPCR0_SCR_SHIFT; |
55f0cd3f | 226 | cr0 |= (spi->mode & (SPI_CPHA | SPI_CPOL)) << SSPCR0_MODE_SHIFT; |
d9b65dfd | 227 | cr0 |= dss; |
011f23a3 MW |
228 | |
229 | dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n", | |
55f0cd3f | 230 | spi->mode, div_cpsr, div_scr, dss); |
a1829d2b | 231 | dev_dbg(&espi->pdev->dev, "setup: cr0 %#x\n", cr0); |
011f23a3 | 232 | |
8447e478 HS |
233 | writel(div_cpsr, espi->mmio + SSPCPSR); |
234 | writel(cr0, espi->mmio + SSPCR0); | |
f7ef1da9 HS |
235 | |
236 | return 0; | |
011f23a3 MW |
237 | } |
238 | ||
011f23a3 MW |
239 | static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t) |
240 | { | |
8447e478 | 241 | u32 val = 0; |
011f23a3 | 242 | |
8447e478 | 243 | if (t->bits_per_word > 8) { |
011f23a3 | 244 | if (t->tx_buf) |
8447e478 HS |
245 | val = ((u16 *)t->tx_buf)[espi->tx]; |
246 | espi->tx += 2; | |
011f23a3 | 247 | } else { |
011f23a3 | 248 | if (t->tx_buf) |
8447e478 HS |
249 | val = ((u8 *)t->tx_buf)[espi->tx]; |
250 | espi->tx += 1; | |
011f23a3 | 251 | } |
8447e478 | 252 | writel(val, espi->mmio + SSPDR); |
011f23a3 MW |
253 | } |
254 | ||
255 | static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t) | |
256 | { | |
8447e478 | 257 | u32 val; |
011f23a3 | 258 | |
8447e478 HS |
259 | val = readl(espi->mmio + SSPDR); |
260 | if (t->bits_per_word > 8) { | |
011f23a3 | 261 | if (t->rx_buf) |
8447e478 HS |
262 | ((u16 *)t->rx_buf)[espi->rx] = val; |
263 | espi->rx += 2; | |
011f23a3 | 264 | } else { |
011f23a3 | 265 | if (t->rx_buf) |
8447e478 HS |
266 | ((u8 *)t->rx_buf)[espi->rx] = val; |
267 | espi->rx += 1; | |
011f23a3 MW |
268 | } |
269 | } | |
270 | ||
271 | /** | |
272 | * ep93xx_spi_read_write() - perform next RX/TX transfer | |
273 | * @espi: ep93xx SPI controller struct | |
274 | * | |
275 | * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If | |
276 | * called several times, the whole transfer will be completed. Returns | |
277 | * %-EINPROGRESS when current transfer was not yet completed otherwise %0. | |
278 | * | |
279 | * When this function is finished, RX FIFO should be empty and TX FIFO should be | |
280 | * full. | |
281 | */ | |
282 | static int ep93xx_spi_read_write(struct ep93xx_spi *espi) | |
283 | { | |
284 | struct spi_message *msg = espi->current_msg; | |
285 | struct spi_transfer *t = msg->state; | |
286 | ||
287 | /* read as long as RX FIFO has frames in it */ | |
8447e478 | 288 | while ((readl(espi->mmio + SSPSR) & SSPSR_RNE)) { |
011f23a3 MW |
289 | ep93xx_do_read(espi, t); |
290 | espi->fifo_level--; | |
291 | } | |
292 | ||
293 | /* write as long as TX FIFO has room */ | |
294 | while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < t->len) { | |
295 | ep93xx_do_write(espi, t); | |
296 | espi->fifo_level++; | |
297 | } | |
298 | ||
626a96db | 299 | if (espi->rx == t->len) |
011f23a3 | 300 | return 0; |
011f23a3 MW |
301 | |
302 | return -EINPROGRESS; | |
303 | } | |
304 | ||
626a96db MW |
305 | static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi) |
306 | { | |
307 | /* | |
308 | * Now everything is set up for the current transfer. We prime the TX | |
309 | * FIFO, enable interrupts, and wait for the transfer to complete. | |
310 | */ | |
311 | if (ep93xx_spi_read_write(espi)) { | |
312 | ep93xx_spi_enable_interrupts(espi); | |
313 | wait_for_completion(&espi->wait); | |
314 | } | |
315 | } | |
316 | ||
317 | /** | |
318 | * ep93xx_spi_dma_prepare() - prepares a DMA transfer | |
319 | * @espi: ep93xx SPI controller struct | |
320 | * @dir: DMA transfer direction | |
321 | * | |
322 | * Function configures the DMA, maps the buffer and prepares the DMA | |
323 | * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR | |
324 | * in case of failure. | |
325 | */ | |
326 | static struct dma_async_tx_descriptor * | |
d4b9b578 | 327 | ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir) |
626a96db MW |
328 | { |
329 | struct spi_transfer *t = espi->current_msg->state; | |
330 | struct dma_async_tx_descriptor *txd; | |
331 | enum dma_slave_buswidth buswidth; | |
332 | struct dma_slave_config conf; | |
333 | struct scatterlist *sg; | |
334 | struct sg_table *sgt; | |
335 | struct dma_chan *chan; | |
336 | const void *buf, *pbuf; | |
337 | size_t len = t->len; | |
338 | int i, ret, nents; | |
339 | ||
701c3587 | 340 | if (t->bits_per_word > 8) |
626a96db MW |
341 | buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; |
342 | else | |
343 | buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
344 | ||
345 | memset(&conf, 0, sizeof(conf)); | |
346 | conf.direction = dir; | |
347 | ||
d4b9b578 | 348 | if (dir == DMA_DEV_TO_MEM) { |
626a96db MW |
349 | chan = espi->dma_rx; |
350 | buf = t->rx_buf; | |
351 | sgt = &espi->rx_sgt; | |
352 | ||
353 | conf.src_addr = espi->sspdr_phys; | |
354 | conf.src_addr_width = buswidth; | |
355 | } else { | |
356 | chan = espi->dma_tx; | |
357 | buf = t->tx_buf; | |
358 | sgt = &espi->tx_sgt; | |
359 | ||
360 | conf.dst_addr = espi->sspdr_phys; | |
361 | conf.dst_addr_width = buswidth; | |
362 | } | |
363 | ||
364 | ret = dmaengine_slave_config(chan, &conf); | |
365 | if (ret) | |
366 | return ERR_PTR(ret); | |
367 | ||
368 | /* | |
369 | * We need to split the transfer into PAGE_SIZE'd chunks. This is | |
370 | * because we are using @espi->zeropage to provide a zero RX buffer | |
371 | * for the TX transfers and we have only allocated one page for that. | |
372 | * | |
373 | * For performance reasons we allocate a new sg_table only when | |
374 | * needed. Otherwise we will re-use the current one. Eventually the | |
375 | * last sg_table is released in ep93xx_spi_release_dma(). | |
376 | */ | |
377 | ||
378 | nents = DIV_ROUND_UP(len, PAGE_SIZE); | |
379 | if (nents != sgt->nents) { | |
380 | sg_free_table(sgt); | |
381 | ||
382 | ret = sg_alloc_table(sgt, nents, GFP_KERNEL); | |
383 | if (ret) | |
384 | return ERR_PTR(ret); | |
385 | } | |
386 | ||
387 | pbuf = buf; | |
388 | for_each_sg(sgt->sgl, sg, sgt->nents, i) { | |
389 | size_t bytes = min_t(size_t, len, PAGE_SIZE); | |
390 | ||
391 | if (buf) { | |
392 | sg_set_page(sg, virt_to_page(pbuf), bytes, | |
393 | offset_in_page(pbuf)); | |
394 | } else { | |
395 | sg_set_page(sg, virt_to_page(espi->zeropage), | |
396 | bytes, 0); | |
397 | } | |
398 | ||
399 | pbuf += bytes; | |
400 | len -= bytes; | |
401 | } | |
402 | ||
403 | if (WARN_ON(len)) { | |
a1829d2b | 404 | dev_warn(&espi->pdev->dev, "len = %zu expected 0!\n", len); |
626a96db MW |
405 | return ERR_PTR(-EINVAL); |
406 | } | |
407 | ||
408 | nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); | |
409 | if (!nents) | |
410 | return ERR_PTR(-ENOMEM); | |
411 | ||
d4b9b578 | 412 | txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, DMA_CTRL_ACK); |
626a96db MW |
413 | if (!txd) { |
414 | dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); | |
415 | return ERR_PTR(-ENOMEM); | |
416 | } | |
417 | return txd; | |
418 | } | |
419 | ||
420 | /** | |
421 | * ep93xx_spi_dma_finish() - finishes with a DMA transfer | |
422 | * @espi: ep93xx SPI controller struct | |
423 | * @dir: DMA transfer direction | |
424 | * | |
425 | * Function finishes with the DMA transfer. After this, the DMA buffer is | |
426 | * unmapped. | |
427 | */ | |
428 | static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi, | |
d4b9b578 | 429 | enum dma_transfer_direction dir) |
626a96db MW |
430 | { |
431 | struct dma_chan *chan; | |
432 | struct sg_table *sgt; | |
433 | ||
d4b9b578 | 434 | if (dir == DMA_DEV_TO_MEM) { |
626a96db MW |
435 | chan = espi->dma_rx; |
436 | sgt = &espi->rx_sgt; | |
437 | } else { | |
438 | chan = espi->dma_tx; | |
439 | sgt = &espi->tx_sgt; | |
440 | } | |
441 | ||
442 | dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); | |
443 | } | |
444 | ||
445 | static void ep93xx_spi_dma_callback(void *callback_param) | |
446 | { | |
447 | complete(callback_param); | |
448 | } | |
449 | ||
450 | static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi) | |
451 | { | |
452 | struct spi_message *msg = espi->current_msg; | |
453 | struct dma_async_tx_descriptor *rxd, *txd; | |
454 | ||
d4b9b578 | 455 | rxd = ep93xx_spi_dma_prepare(espi, DMA_DEV_TO_MEM); |
626a96db MW |
456 | if (IS_ERR(rxd)) { |
457 | dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd)); | |
458 | msg->status = PTR_ERR(rxd); | |
459 | return; | |
460 | } | |
461 | ||
d4b9b578 | 462 | txd = ep93xx_spi_dma_prepare(espi, DMA_MEM_TO_DEV); |
626a96db | 463 | if (IS_ERR(txd)) { |
d4b9b578 | 464 | ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); |
f7aa23cb | 465 | dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(txd)); |
626a96db MW |
466 | msg->status = PTR_ERR(txd); |
467 | return; | |
468 | } | |
469 | ||
470 | /* We are ready when RX is done */ | |
471 | rxd->callback = ep93xx_spi_dma_callback; | |
472 | rxd->callback_param = &espi->wait; | |
473 | ||
474 | /* Now submit both descriptors and wait while they finish */ | |
475 | dmaengine_submit(rxd); | |
476 | dmaengine_submit(txd); | |
477 | ||
478 | dma_async_issue_pending(espi->dma_rx); | |
479 | dma_async_issue_pending(espi->dma_tx); | |
480 | ||
481 | wait_for_completion(&espi->wait); | |
482 | ||
d4b9b578 HS |
483 | ep93xx_spi_dma_finish(espi, DMA_MEM_TO_DEV); |
484 | ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); | |
626a96db MW |
485 | } |
486 | ||
011f23a3 MW |
487 | /** |
488 | * ep93xx_spi_process_transfer() - processes one SPI transfer | |
489 | * @espi: ep93xx SPI controller struct | |
490 | * @msg: current message | |
491 | * @t: transfer to process | |
492 | * | |
493 | * This function processes one SPI transfer given in @t. Function waits until | |
494 | * transfer is complete (may sleep) and updates @msg->status based on whether | |
25985edc | 495 | * transfer was successfully processed or not. |
011f23a3 MW |
496 | */ |
497 | static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi, | |
498 | struct spi_message *msg, | |
499 | struct spi_transfer *t) | |
500 | { | |
4870c217 | 501 | int err; |
011f23a3 MW |
502 | |
503 | msg->state = t; | |
504 | ||
55f0cd3f | 505 | err = ep93xx_spi_chip_setup(espi, msg->spi, t); |
4870c217 | 506 | if (err) { |
f7ef1da9 HS |
507 | dev_err(&espi->pdev->dev, |
508 | "failed to setup chip for transfer\n"); | |
4870c217 HS |
509 | msg->status = err; |
510 | return; | |
511 | } | |
011f23a3 | 512 | |
011f23a3 MW |
513 | espi->rx = 0; |
514 | espi->tx = 0; | |
515 | ||
516 | /* | |
626a96db MW |
517 | * There is no point of setting up DMA for the transfers which will |
518 | * fit into the FIFO and can be transferred with a single interrupt. | |
519 | * So in these cases we will be using PIO and don't bother for DMA. | |
011f23a3 | 520 | */ |
626a96db MW |
521 | if (espi->dma_rx && t->len > SPI_FIFO_SIZE) |
522 | ep93xx_spi_dma_transfer(espi); | |
523 | else | |
524 | ep93xx_spi_pio_transfer(espi); | |
011f23a3 MW |
525 | |
526 | /* | |
527 | * In case of error during transmit, we bail out from processing | |
528 | * the message. | |
529 | */ | |
530 | if (msg->status) | |
531 | return; | |
532 | ||
626a96db MW |
533 | msg->actual_length += t->len; |
534 | ||
011f23a3 MW |
535 | /* |
536 | * After this transfer is finished, perform any possible | |
537 | * post-transfer actions requested by the protocol driver. | |
538 | */ | |
539 | if (t->delay_usecs) { | |
540 | set_current_state(TASK_UNINTERRUPTIBLE); | |
541 | schedule_timeout(usecs_to_jiffies(t->delay_usecs)); | |
542 | } | |
543 | if (t->cs_change) { | |
544 | if (!list_is_last(&t->transfer_list, &msg->transfers)) { | |
545 | /* | |
546 | * In case protocol driver is asking us to drop the | |
547 | * chipselect briefly, we let the scheduler to handle | |
548 | * any "delay" here. | |
549 | */ | |
550 | ep93xx_spi_cs_control(msg->spi, false); | |
551 | cond_resched(); | |
552 | ep93xx_spi_cs_control(msg->spi, true); | |
553 | } | |
554 | } | |
011f23a3 MW |
555 | } |
556 | ||
557 | /* | |
558 | * ep93xx_spi_process_message() - process one SPI message | |
559 | * @espi: ep93xx SPI controller struct | |
560 | * @msg: message to process | |
561 | * | |
562 | * This function processes a single SPI message. We go through all transfers in | |
563 | * the message and pass them to ep93xx_spi_process_transfer(). Chipselect is | |
564 | * asserted during the whole message (unless per transfer cs_change is set). | |
565 | * | |
566 | * @msg->status contains %0 in case of success or negative error code in case of | |
567 | * failure. | |
568 | */ | |
569 | static void ep93xx_spi_process_message(struct ep93xx_spi *espi, | |
570 | struct spi_message *msg) | |
571 | { | |
572 | unsigned long timeout; | |
573 | struct spi_transfer *t; | |
574 | int err; | |
575 | ||
576 | /* | |
577 | * Enable the SPI controller and its clock. | |
578 | */ | |
579 | err = ep93xx_spi_enable(espi); | |
580 | if (err) { | |
581 | dev_err(&espi->pdev->dev, "failed to enable SPI controller\n"); | |
582 | msg->status = err; | |
583 | return; | |
584 | } | |
585 | ||
586 | /* | |
587 | * Just to be sure: flush any data from RX FIFO. | |
588 | */ | |
589 | timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT); | |
8447e478 | 590 | while (readl(espi->mmio + SSPSR) & SSPSR_RNE) { |
011f23a3 MW |
591 | if (time_after(jiffies, timeout)) { |
592 | dev_warn(&espi->pdev->dev, | |
593 | "timeout while flushing RX FIFO\n"); | |
594 | msg->status = -ETIMEDOUT; | |
595 | return; | |
596 | } | |
8447e478 | 597 | readl(espi->mmio + SSPDR); |
011f23a3 MW |
598 | } |
599 | ||
600 | /* | |
601 | * We explicitly handle FIFO level. This way we don't have to check TX | |
602 | * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns. | |
603 | */ | |
604 | espi->fifo_level = 0; | |
605 | ||
606 | /* | |
4870c217 | 607 | * Assert the chipselect. |
011f23a3 | 608 | */ |
011f23a3 MW |
609 | ep93xx_spi_cs_control(msg->spi, true); |
610 | ||
611 | list_for_each_entry(t, &msg->transfers, transfer_list) { | |
612 | ep93xx_spi_process_transfer(espi, msg, t); | |
613 | if (msg->status) | |
614 | break; | |
615 | } | |
616 | ||
617 | /* | |
618 | * Now the whole message is transferred (or failed for some reason). We | |
619 | * deselect the device and disable the SPI controller. | |
620 | */ | |
621 | ep93xx_spi_cs_control(msg->spi, false); | |
622 | ep93xx_spi_disable(espi); | |
623 | } | |
624 | ||
84ddb3c1 HS |
625 | static int ep93xx_spi_transfer_one_message(struct spi_master *master, |
626 | struct spi_message *msg) | |
011f23a3 | 627 | { |
84ddb3c1 | 628 | struct ep93xx_spi *espi = spi_master_get_devdata(master); |
011f23a3 | 629 | |
84ddb3c1 HS |
630 | msg->state = NULL; |
631 | msg->status = 0; | |
632 | msg->actual_length = 0; | |
011f23a3 | 633 | |
84ddb3c1 HS |
634 | espi->current_msg = msg; |
635 | ep93xx_spi_process_message(espi, msg); | |
011f23a3 | 636 | espi->current_msg = NULL; |
011f23a3 | 637 | |
84ddb3c1 HS |
638 | spi_finalize_current_message(master); |
639 | ||
640 | return 0; | |
011f23a3 MW |
641 | } |
642 | ||
643 | static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id) | |
644 | { | |
645 | struct ep93xx_spi *espi = dev_id; | |
011f23a3 MW |
646 | |
647 | /* | |
648 | * If we got ROR (receive overrun) interrupt we know that something is | |
649 | * wrong. Just abort the message. | |
650 | */ | |
8447e478 | 651 | if (readl(espi->mmio + SSPIIR) & SSPIIR_RORIS) { |
011f23a3 | 652 | /* clear the overrun interrupt */ |
8447e478 | 653 | writel(0, espi->mmio + SSPICR); |
011f23a3 MW |
654 | dev_warn(&espi->pdev->dev, |
655 | "receive overrun, aborting the message\n"); | |
656 | espi->current_msg->status = -EIO; | |
657 | } else { | |
658 | /* | |
659 | * Interrupt is either RX (RIS) or TX (TIS). For both cases we | |
660 | * simply execute next data transfer. | |
661 | */ | |
662 | if (ep93xx_spi_read_write(espi)) { | |
663 | /* | |
664 | * In normal case, there still is some processing left | |
665 | * for current transfer. Let's wait for the next | |
666 | * interrupt then. | |
667 | */ | |
668 | return IRQ_HANDLED; | |
669 | } | |
670 | } | |
671 | ||
672 | /* | |
673 | * Current transfer is finished, either with error or with success. In | |
674 | * any case we disable interrupts and notify the worker to handle | |
675 | * any post-processing of the message. | |
676 | */ | |
677 | ep93xx_spi_disable_interrupts(espi); | |
678 | complete(&espi->wait); | |
679 | return IRQ_HANDLED; | |
680 | } | |
681 | ||
626a96db MW |
682 | static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param) |
683 | { | |
684 | if (ep93xx_dma_chan_is_m2p(chan)) | |
685 | return false; | |
686 | ||
687 | chan->private = filter_param; | |
688 | return true; | |
689 | } | |
690 | ||
691 | static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi) | |
692 | { | |
693 | dma_cap_mask_t mask; | |
694 | int ret; | |
695 | ||
696 | espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL); | |
697 | if (!espi->zeropage) | |
698 | return -ENOMEM; | |
699 | ||
700 | dma_cap_zero(mask); | |
701 | dma_cap_set(DMA_SLAVE, mask); | |
702 | ||
703 | espi->dma_rx_data.port = EP93XX_DMA_SSP; | |
a485df4b | 704 | espi->dma_rx_data.direction = DMA_DEV_TO_MEM; |
626a96db MW |
705 | espi->dma_rx_data.name = "ep93xx-spi-rx"; |
706 | ||
707 | espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter, | |
708 | &espi->dma_rx_data); | |
709 | if (!espi->dma_rx) { | |
710 | ret = -ENODEV; | |
711 | goto fail_free_page; | |
712 | } | |
713 | ||
714 | espi->dma_tx_data.port = EP93XX_DMA_SSP; | |
a485df4b | 715 | espi->dma_tx_data.direction = DMA_MEM_TO_DEV; |
626a96db MW |
716 | espi->dma_tx_data.name = "ep93xx-spi-tx"; |
717 | ||
718 | espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter, | |
719 | &espi->dma_tx_data); | |
720 | if (!espi->dma_tx) { | |
721 | ret = -ENODEV; | |
722 | goto fail_release_rx; | |
723 | } | |
724 | ||
725 | return 0; | |
726 | ||
727 | fail_release_rx: | |
728 | dma_release_channel(espi->dma_rx); | |
729 | espi->dma_rx = NULL; | |
730 | fail_free_page: | |
731 | free_page((unsigned long)espi->zeropage); | |
732 | ||
733 | return ret; | |
734 | } | |
735 | ||
736 | static void ep93xx_spi_release_dma(struct ep93xx_spi *espi) | |
737 | { | |
738 | if (espi->dma_rx) { | |
739 | dma_release_channel(espi->dma_rx); | |
740 | sg_free_table(&espi->rx_sgt); | |
741 | } | |
742 | if (espi->dma_tx) { | |
743 | dma_release_channel(espi->dma_tx); | |
744 | sg_free_table(&espi->tx_sgt); | |
745 | } | |
746 | ||
747 | if (espi->zeropage) | |
748 | free_page((unsigned long)espi->zeropage); | |
749 | } | |
750 | ||
fd4a319b | 751 | static int ep93xx_spi_probe(struct platform_device *pdev) |
011f23a3 MW |
752 | { |
753 | struct spi_master *master; | |
754 | struct ep93xx_spi_info *info; | |
755 | struct ep93xx_spi *espi; | |
756 | struct resource *res; | |
6d6467ee | 757 | int irq; |
011f23a3 | 758 | int error; |
55f0cd3f | 759 | int i; |
011f23a3 | 760 | |
8074cf06 | 761 | info = dev_get_platdata(&pdev->dev); |
55f0cd3f HS |
762 | if (!info) { |
763 | dev_err(&pdev->dev, "missing platform data\n"); | |
764 | return -EINVAL; | |
765 | } | |
011f23a3 | 766 | |
48a7776e HS |
767 | irq = platform_get_irq(pdev, 0); |
768 | if (irq < 0) { | |
769 | dev_err(&pdev->dev, "failed to get irq resources\n"); | |
770 | return -EBUSY; | |
771 | } | |
772 | ||
773 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
774 | if (!res) { | |
775 | dev_err(&pdev->dev, "unable to get iomem resource\n"); | |
776 | return -ENODEV; | |
777 | } | |
778 | ||
011f23a3 | 779 | master = spi_alloc_master(&pdev->dev, sizeof(*espi)); |
b2d185ed | 780 | if (!master) |
011f23a3 | 781 | return -ENOMEM; |
011f23a3 | 782 | |
84ddb3c1 | 783 | master->transfer_one_message = ep93xx_spi_transfer_one_message; |
011f23a3 | 784 | master->bus_num = pdev->id; |
011f23a3 | 785 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
24778be2 | 786 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
011f23a3 | 787 | |
55f0cd3f HS |
788 | master->num_chipselect = info->num_chipselect; |
789 | master->cs_gpios = devm_kzalloc(&master->dev, | |
790 | sizeof(int) * master->num_chipselect, | |
791 | GFP_KERNEL); | |
792 | if (!master->cs_gpios) { | |
793 | error = -ENOMEM; | |
794 | goto fail_release_master; | |
795 | } | |
796 | ||
797 | for (i = 0; i < master->num_chipselect; i++) { | |
798 | master->cs_gpios[i] = info->chipselect[i]; | |
799 | ||
800 | if (!gpio_is_valid(master->cs_gpios[i])) | |
801 | continue; | |
802 | ||
803 | error = devm_gpio_request_one(&pdev->dev, master->cs_gpios[i], | |
804 | GPIOF_OUT_INIT_HIGH, | |
805 | "ep93xx-spi"); | |
806 | if (error) { | |
807 | dev_err(&pdev->dev, "could not request cs gpio %d\n", | |
808 | master->cs_gpios[i]); | |
809 | goto fail_release_master; | |
810 | } | |
811 | } | |
812 | ||
011f23a3 MW |
813 | platform_set_drvdata(pdev, master); |
814 | ||
815 | espi = spi_master_get_devdata(master); | |
816 | ||
e6eb8d9b | 817 | espi->clk = devm_clk_get(&pdev->dev, NULL); |
011f23a3 MW |
818 | if (IS_ERR(espi->clk)) { |
819 | dev_err(&pdev->dev, "unable to get spi clock\n"); | |
820 | error = PTR_ERR(espi->clk); | |
821 | goto fail_release_master; | |
822 | } | |
823 | ||
011f23a3 MW |
824 | init_completion(&espi->wait); |
825 | ||
826 | /* | |
827 | * Calculate maximum and minimum supported clock rates | |
828 | * for the controller. | |
829 | */ | |
56fc0b42 AL |
830 | master->max_speed_hz = clk_get_rate(espi->clk) / 2; |
831 | master->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256); | |
011f23a3 MW |
832 | espi->pdev = pdev; |
833 | ||
626a96db | 834 | espi->sspdr_phys = res->start + SSPDR; |
6d6467ee | 835 | |
1232978a HS |
836 | espi->mmio = devm_ioremap_resource(&pdev->dev, res); |
837 | if (IS_ERR(espi->mmio)) { | |
838 | error = PTR_ERR(espi->mmio); | |
e6eb8d9b | 839 | goto fail_release_master; |
011f23a3 MW |
840 | } |
841 | ||
6d6467ee HH |
842 | error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt, |
843 | 0, "ep93xx-spi", espi); | |
011f23a3 MW |
844 | if (error) { |
845 | dev_err(&pdev->dev, "failed to request irq\n"); | |
e6eb8d9b | 846 | goto fail_release_master; |
011f23a3 MW |
847 | } |
848 | ||
626a96db MW |
849 | if (info->use_dma && ep93xx_spi_setup_dma(espi)) |
850 | dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n"); | |
851 | ||
011f23a3 | 852 | /* make sure that the hardware is disabled */ |
8447e478 | 853 | writel(0, espi->mmio + SSPCR1); |
011f23a3 | 854 | |
434eaf3b | 855 | error = devm_spi_register_master(&pdev->dev, master); |
011f23a3 MW |
856 | if (error) { |
857 | dev_err(&pdev->dev, "failed to register SPI master\n"); | |
84ddb3c1 | 858 | goto fail_free_dma; |
011f23a3 MW |
859 | } |
860 | ||
861 | dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n", | |
6d6467ee | 862 | (unsigned long)res->start, irq); |
011f23a3 MW |
863 | |
864 | return 0; | |
865 | ||
626a96db MW |
866 | fail_free_dma: |
867 | ep93xx_spi_release_dma(espi); | |
011f23a3 MW |
868 | fail_release_master: |
869 | spi_master_put(master); | |
011f23a3 MW |
870 | |
871 | return error; | |
872 | } | |
873 | ||
fd4a319b | 874 | static int ep93xx_spi_remove(struct platform_device *pdev) |
011f23a3 MW |
875 | { |
876 | struct spi_master *master = platform_get_drvdata(pdev); | |
877 | struct ep93xx_spi *espi = spi_master_get_devdata(master); | |
011f23a3 | 878 | |
626a96db | 879 | ep93xx_spi_release_dma(espi); |
011f23a3 | 880 | |
011f23a3 MW |
881 | return 0; |
882 | } | |
883 | ||
884 | static struct platform_driver ep93xx_spi_driver = { | |
885 | .driver = { | |
886 | .name = "ep93xx-spi", | |
011f23a3 | 887 | }, |
940ab889 | 888 | .probe = ep93xx_spi_probe, |
fd4a319b | 889 | .remove = ep93xx_spi_remove, |
011f23a3 | 890 | }; |
940ab889 | 891 | module_platform_driver(ep93xx_spi_driver); |
011f23a3 MW |
892 | |
893 | MODULE_DESCRIPTION("EP93xx SPI Controller driver"); | |
894 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>"); | |
895 | MODULE_LICENSE("GPL"); | |
896 | MODULE_ALIAS("platform:ep93xx-spi"); |