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011f23a3 MW |
1 | /* |
2 | * Driver for Cirrus Logic EP93xx SPI controller. | |
3 | * | |
626a96db | 4 | * Copyright (C) 2010-2011 Mika Westerberg |
011f23a3 MW |
5 | * |
6 | * Explicit FIFO handling code was inspired by amba-pl022 driver. | |
7 | * | |
8 | * Chip select support using other than built-in GPIOs by H. Hartley Sweeten. | |
9 | * | |
10 | * For more information about the SPI controller see documentation on Cirrus | |
11 | * Logic web site: | |
12 | * http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | */ | |
18 | ||
19 | #include <linux/io.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/device.h> | |
626a96db | 24 | #include <linux/dmaengine.h> |
011f23a3 MW |
25 | #include <linux/bitops.h> |
26 | #include <linux/interrupt.h> | |
5bdb7613 | 27 | #include <linux/module.h> |
011f23a3 MW |
28 | #include <linux/platform_device.h> |
29 | #include <linux/workqueue.h> | |
30 | #include <linux/sched.h> | |
626a96db | 31 | #include <linux/scatterlist.h> |
011f23a3 MW |
32 | #include <linux/spi/spi.h> |
33 | ||
a3b29245 AB |
34 | #include <linux/platform_data/dma-ep93xx.h> |
35 | #include <linux/platform_data/spi-ep93xx.h> | |
011f23a3 MW |
36 | |
37 | #define SSPCR0 0x0000 | |
38 | #define SSPCR0_MODE_SHIFT 6 | |
39 | #define SSPCR0_SCR_SHIFT 8 | |
40 | ||
41 | #define SSPCR1 0x0004 | |
42 | #define SSPCR1_RIE BIT(0) | |
43 | #define SSPCR1_TIE BIT(1) | |
44 | #define SSPCR1_RORIE BIT(2) | |
45 | #define SSPCR1_LBM BIT(3) | |
46 | #define SSPCR1_SSE BIT(4) | |
47 | #define SSPCR1_MS BIT(5) | |
48 | #define SSPCR1_SOD BIT(6) | |
49 | ||
50 | #define SSPDR 0x0008 | |
51 | ||
52 | #define SSPSR 0x000c | |
53 | #define SSPSR_TFE BIT(0) | |
54 | #define SSPSR_TNF BIT(1) | |
55 | #define SSPSR_RNE BIT(2) | |
56 | #define SSPSR_RFF BIT(3) | |
57 | #define SSPSR_BSY BIT(4) | |
58 | #define SSPCPSR 0x0010 | |
59 | ||
60 | #define SSPIIR 0x0014 | |
61 | #define SSPIIR_RIS BIT(0) | |
62 | #define SSPIIR_TIS BIT(1) | |
63 | #define SSPIIR_RORIS BIT(2) | |
64 | #define SSPICR SSPIIR | |
65 | ||
66 | /* timeout in milliseconds */ | |
67 | #define SPI_TIMEOUT 5 | |
68 | /* maximum depth of RX/TX FIFO */ | |
69 | #define SPI_FIFO_SIZE 8 | |
70 | ||
71 | /** | |
72 | * struct ep93xx_spi - EP93xx SPI controller structure | |
73 | * @lock: spinlock that protects concurrent accesses to fields @running, | |
74 | * @current_msg and @msg_queue | |
75 | * @pdev: pointer to platform device | |
76 | * @clk: clock for the controller | |
77 | * @regs_base: pointer to ioremap()'d registers | |
626a96db | 78 | * @sspdr_phys: physical address of the SSPDR register |
011f23a3 MW |
79 | * @min_rate: minimum clock rate (in Hz) supported by the controller |
80 | * @max_rate: maximum clock rate (in Hz) supported by the controller | |
81 | * @running: is the queue running | |
82 | * @wq: workqueue used by the driver | |
83 | * @msg_work: work that is queued for the driver | |
84 | * @wait: wait here until given transfer is completed | |
85 | * @msg_queue: queue for the messages | |
86 | * @current_msg: message that is currently processed (or %NULL if none) | |
87 | * @tx: current byte in transfer to transmit | |
88 | * @rx: current byte in transfer to receive | |
89 | * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one | |
90 | * frame decreases this level and sending one frame increases it. | |
626a96db MW |
91 | * @dma_rx: RX DMA channel |
92 | * @dma_tx: TX DMA channel | |
93 | * @dma_rx_data: RX parameters passed to the DMA engine | |
94 | * @dma_tx_data: TX parameters passed to the DMA engine | |
95 | * @rx_sgt: sg table for RX transfers | |
96 | * @tx_sgt: sg table for TX transfers | |
97 | * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by | |
98 | * the client | |
011f23a3 MW |
99 | * |
100 | * This structure holds EP93xx SPI controller specific information. When | |
101 | * @running is %true, driver accepts transfer requests from protocol drivers. | |
102 | * @current_msg is used to hold pointer to the message that is currently | |
103 | * processed. If @current_msg is %NULL, it means that no processing is going | |
104 | * on. | |
105 | * | |
106 | * Most of the fields are only written once and they can be accessed without | |
107 | * taking the @lock. Fields that are accessed concurrently are: @current_msg, | |
108 | * @running, and @msg_queue. | |
109 | */ | |
110 | struct ep93xx_spi { | |
111 | spinlock_t lock; | |
112 | const struct platform_device *pdev; | |
113 | struct clk *clk; | |
114 | void __iomem *regs_base; | |
626a96db | 115 | unsigned long sspdr_phys; |
011f23a3 MW |
116 | unsigned long min_rate; |
117 | unsigned long max_rate; | |
118 | bool running; | |
119 | struct workqueue_struct *wq; | |
120 | struct work_struct msg_work; | |
121 | struct completion wait; | |
122 | struct list_head msg_queue; | |
123 | struct spi_message *current_msg; | |
124 | size_t tx; | |
125 | size_t rx; | |
126 | size_t fifo_level; | |
626a96db MW |
127 | struct dma_chan *dma_rx; |
128 | struct dma_chan *dma_tx; | |
129 | struct ep93xx_dma_data dma_rx_data; | |
130 | struct ep93xx_dma_data dma_tx_data; | |
131 | struct sg_table rx_sgt; | |
132 | struct sg_table tx_sgt; | |
133 | void *zeropage; | |
011f23a3 MW |
134 | }; |
135 | ||
136 | /** | |
137 | * struct ep93xx_spi_chip - SPI device hardware settings | |
138 | * @spi: back pointer to the SPI device | |
139 | * @rate: max rate in hz this chip supports | |
140 | * @div_cpsr: cpsr (pre-scaler) divider | |
141 | * @div_scr: scr divider | |
142 | * @dss: bits per word (4 - 16 bits) | |
143 | * @ops: private chip operations | |
144 | * | |
145 | * This structure is used to store hardware register specific settings for each | |
146 | * SPI device. Settings are written to hardware by function | |
147 | * ep93xx_spi_chip_setup(). | |
148 | */ | |
149 | struct ep93xx_spi_chip { | |
150 | const struct spi_device *spi; | |
151 | unsigned long rate; | |
152 | u8 div_cpsr; | |
153 | u8 div_scr; | |
154 | u8 dss; | |
155 | struct ep93xx_spi_chip_ops *ops; | |
156 | }; | |
157 | ||
158 | /* converts bits per word to CR0.DSS value */ | |
159 | #define bits_per_word_to_dss(bpw) ((bpw) - 1) | |
160 | ||
8d7586bd HS |
161 | static void ep93xx_spi_write_u8(const struct ep93xx_spi *espi, |
162 | u16 reg, u8 value) | |
011f23a3 | 163 | { |
8d7586bd | 164 | writeb(value, espi->regs_base + reg); |
011f23a3 MW |
165 | } |
166 | ||
8d7586bd | 167 | static u8 ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg) |
011f23a3 | 168 | { |
8d7586bd | 169 | return readb(spi->regs_base + reg); |
011f23a3 MW |
170 | } |
171 | ||
8d7586bd HS |
172 | static void ep93xx_spi_write_u16(const struct ep93xx_spi *espi, |
173 | u16 reg, u16 value) | |
011f23a3 | 174 | { |
8d7586bd | 175 | writew(value, espi->regs_base + reg); |
011f23a3 MW |
176 | } |
177 | ||
8d7586bd | 178 | static u16 ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg) |
011f23a3 | 179 | { |
8d7586bd | 180 | return readw(spi->regs_base + reg); |
011f23a3 MW |
181 | } |
182 | ||
183 | static int ep93xx_spi_enable(const struct ep93xx_spi *espi) | |
184 | { | |
185 | u8 regval; | |
186 | int err; | |
187 | ||
188 | err = clk_enable(espi->clk); | |
189 | if (err) | |
190 | return err; | |
191 | ||
192 | regval = ep93xx_spi_read_u8(espi, SSPCR1); | |
193 | regval |= SSPCR1_SSE; | |
194 | ep93xx_spi_write_u8(espi, SSPCR1, regval); | |
195 | ||
196 | return 0; | |
197 | } | |
198 | ||
199 | static void ep93xx_spi_disable(const struct ep93xx_spi *espi) | |
200 | { | |
201 | u8 regval; | |
202 | ||
203 | regval = ep93xx_spi_read_u8(espi, SSPCR1); | |
204 | regval &= ~SSPCR1_SSE; | |
205 | ep93xx_spi_write_u8(espi, SSPCR1, regval); | |
206 | ||
207 | clk_disable(espi->clk); | |
208 | } | |
209 | ||
210 | static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi) | |
211 | { | |
212 | u8 regval; | |
213 | ||
214 | regval = ep93xx_spi_read_u8(espi, SSPCR1); | |
215 | regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); | |
216 | ep93xx_spi_write_u8(espi, SSPCR1, regval); | |
217 | } | |
218 | ||
219 | static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi) | |
220 | { | |
221 | u8 regval; | |
222 | ||
223 | regval = ep93xx_spi_read_u8(espi, SSPCR1); | |
224 | regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); | |
225 | ep93xx_spi_write_u8(espi, SSPCR1, regval); | |
226 | } | |
227 | ||
228 | /** | |
229 | * ep93xx_spi_calc_divisors() - calculates SPI clock divisors | |
230 | * @espi: ep93xx SPI controller struct | |
231 | * @chip: divisors are calculated for this chip | |
232 | * @rate: desired SPI output clock rate | |
233 | * | |
234 | * Function calculates cpsr (clock pre-scaler) and scr divisors based on | |
235 | * given @rate and places them to @chip->div_cpsr and @chip->div_scr. If, | |
236 | * for some reason, divisors cannot be calculated nothing is stored and | |
237 | * %-EINVAL is returned. | |
238 | */ | |
239 | static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi, | |
240 | struct ep93xx_spi_chip *chip, | |
241 | unsigned long rate) | |
242 | { | |
243 | unsigned long spi_clk_rate = clk_get_rate(espi->clk); | |
244 | int cpsr, scr; | |
245 | ||
246 | /* | |
247 | * Make sure that max value is between values supported by the | |
248 | * controller. Note that minimum value is already checked in | |
249 | * ep93xx_spi_transfer(). | |
250 | */ | |
251 | rate = clamp(rate, espi->min_rate, espi->max_rate); | |
252 | ||
253 | /* | |
254 | * Calculate divisors so that we can get speed according the | |
255 | * following formula: | |
256 | * rate = spi_clock_rate / (cpsr * (1 + scr)) | |
257 | * | |
258 | * cpsr must be even number and starts from 2, scr can be any number | |
259 | * between 0 and 255. | |
260 | */ | |
261 | for (cpsr = 2; cpsr <= 254; cpsr += 2) { | |
262 | for (scr = 0; scr <= 255; scr++) { | |
263 | if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) { | |
264 | chip->div_scr = (u8)scr; | |
265 | chip->div_cpsr = (u8)cpsr; | |
266 | return 0; | |
267 | } | |
268 | } | |
269 | } | |
270 | ||
271 | return -EINVAL; | |
272 | } | |
273 | ||
274 | static void ep93xx_spi_cs_control(struct spi_device *spi, bool control) | |
275 | { | |
276 | struct ep93xx_spi_chip *chip = spi_get_ctldata(spi); | |
277 | int value = (spi->mode & SPI_CS_HIGH) ? control : !control; | |
278 | ||
279 | if (chip->ops && chip->ops->cs_control) | |
280 | chip->ops->cs_control(spi, value); | |
281 | } | |
282 | ||
283 | /** | |
284 | * ep93xx_spi_setup() - setup an SPI device | |
285 | * @spi: SPI device to setup | |
286 | * | |
287 | * This function sets up SPI device mode, speed etc. Can be called multiple | |
288 | * times for a single device. Returns %0 in case of success, negative error in | |
289 | * case of failure. When this function returns success, the device is | |
290 | * deselected. | |
291 | */ | |
292 | static int ep93xx_spi_setup(struct spi_device *spi) | |
293 | { | |
294 | struct ep93xx_spi *espi = spi_master_get_devdata(spi->master); | |
295 | struct ep93xx_spi_chip *chip; | |
296 | ||
011f23a3 MW |
297 | chip = spi_get_ctldata(spi); |
298 | if (!chip) { | |
299 | dev_dbg(&espi->pdev->dev, "initial setup for %s\n", | |
300 | spi->modalias); | |
301 | ||
302 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); | |
303 | if (!chip) | |
304 | return -ENOMEM; | |
305 | ||
306 | chip->spi = spi; | |
307 | chip->ops = spi->controller_data; | |
308 | ||
309 | if (chip->ops && chip->ops->setup) { | |
310 | int ret = chip->ops->setup(spi); | |
311 | if (ret) { | |
312 | kfree(chip); | |
313 | return ret; | |
314 | } | |
315 | } | |
316 | ||
317 | spi_set_ctldata(spi, chip); | |
318 | } | |
319 | ||
320 | if (spi->max_speed_hz != chip->rate) { | |
321 | int err; | |
322 | ||
323 | err = ep93xx_spi_calc_divisors(espi, chip, spi->max_speed_hz); | |
324 | if (err != 0) { | |
325 | spi_set_ctldata(spi, NULL); | |
326 | kfree(chip); | |
327 | return err; | |
328 | } | |
329 | chip->rate = spi->max_speed_hz; | |
330 | } | |
331 | ||
332 | chip->dss = bits_per_word_to_dss(spi->bits_per_word); | |
333 | ||
334 | ep93xx_spi_cs_control(spi, false); | |
335 | return 0; | |
336 | } | |
337 | ||
338 | /** | |
339 | * ep93xx_spi_transfer() - queue message to be transferred | |
340 | * @spi: target SPI device | |
341 | * @msg: message to be transferred | |
342 | * | |
343 | * This function is called by SPI device drivers when they are going to transfer | |
344 | * a new message. It simply puts the message in the queue and schedules | |
345 | * workqueue to perform the actual transfer later on. | |
346 | * | |
347 | * Returns %0 on success and negative error in case of failure. | |
348 | */ | |
349 | static int ep93xx_spi_transfer(struct spi_device *spi, struct spi_message *msg) | |
350 | { | |
351 | struct ep93xx_spi *espi = spi_master_get_devdata(spi->master); | |
352 | struct spi_transfer *t; | |
353 | unsigned long flags; | |
354 | ||
355 | if (!msg || !msg->complete) | |
356 | return -EINVAL; | |
357 | ||
358 | /* first validate each transfer */ | |
359 | list_for_each_entry(t, &msg->transfers, transfer_list) { | |
011f23a3 MW |
360 | if (t->speed_hz && t->speed_hz < espi->min_rate) |
361 | return -EINVAL; | |
362 | } | |
363 | ||
364 | /* | |
365 | * Now that we own the message, let's initialize it so that it is | |
366 | * suitable for us. We use @msg->status to signal whether there was | |
367 | * error in transfer and @msg->state is used to hold pointer to the | |
368 | * current transfer (or %NULL if no active current transfer). | |
369 | */ | |
370 | msg->state = NULL; | |
371 | msg->status = 0; | |
372 | msg->actual_length = 0; | |
373 | ||
374 | spin_lock_irqsave(&espi->lock, flags); | |
375 | if (!espi->running) { | |
376 | spin_unlock_irqrestore(&espi->lock, flags); | |
377 | return -ESHUTDOWN; | |
378 | } | |
379 | list_add_tail(&msg->queue, &espi->msg_queue); | |
380 | queue_work(espi->wq, &espi->msg_work); | |
381 | spin_unlock_irqrestore(&espi->lock, flags); | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
386 | /** | |
387 | * ep93xx_spi_cleanup() - cleans up master controller specific state | |
388 | * @spi: SPI device to cleanup | |
389 | * | |
390 | * This function releases master controller specific state for given @spi | |
391 | * device. | |
392 | */ | |
393 | static void ep93xx_spi_cleanup(struct spi_device *spi) | |
394 | { | |
395 | struct ep93xx_spi_chip *chip; | |
396 | ||
397 | chip = spi_get_ctldata(spi); | |
398 | if (chip) { | |
399 | if (chip->ops && chip->ops->cleanup) | |
400 | chip->ops->cleanup(spi); | |
401 | spi_set_ctldata(spi, NULL); | |
402 | kfree(chip); | |
403 | } | |
404 | } | |
405 | ||
406 | /** | |
407 | * ep93xx_spi_chip_setup() - configures hardware according to given @chip | |
408 | * @espi: ep93xx SPI controller struct | |
409 | * @chip: chip specific settings | |
410 | * | |
411 | * This function sets up the actual hardware registers with settings given in | |
412 | * @chip. Note that no validation is done so make sure that callers validate | |
413 | * settings before calling this. | |
414 | */ | |
415 | static void ep93xx_spi_chip_setup(const struct ep93xx_spi *espi, | |
416 | const struct ep93xx_spi_chip *chip) | |
417 | { | |
418 | u16 cr0; | |
419 | ||
420 | cr0 = chip->div_scr << SSPCR0_SCR_SHIFT; | |
421 | cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT; | |
422 | cr0 |= chip->dss; | |
423 | ||
424 | dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n", | |
425 | chip->spi->mode, chip->div_cpsr, chip->div_scr, chip->dss); | |
426 | dev_dbg(&espi->pdev->dev, "setup: cr0 %#x", cr0); | |
427 | ||
428 | ep93xx_spi_write_u8(espi, SSPCPSR, chip->div_cpsr); | |
429 | ep93xx_spi_write_u16(espi, SSPCR0, cr0); | |
430 | } | |
431 | ||
432 | static inline int bits_per_word(const struct ep93xx_spi *espi) | |
433 | { | |
434 | struct spi_message *msg = espi->current_msg; | |
435 | struct spi_transfer *t = msg->state; | |
436 | ||
766ed704 | 437 | return t->bits_per_word; |
011f23a3 MW |
438 | } |
439 | ||
440 | static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t) | |
441 | { | |
442 | if (bits_per_word(espi) > 8) { | |
443 | u16 tx_val = 0; | |
444 | ||
445 | if (t->tx_buf) | |
446 | tx_val = ((u16 *)t->tx_buf)[espi->tx]; | |
447 | ep93xx_spi_write_u16(espi, SSPDR, tx_val); | |
448 | espi->tx += sizeof(tx_val); | |
449 | } else { | |
450 | u8 tx_val = 0; | |
451 | ||
452 | if (t->tx_buf) | |
453 | tx_val = ((u8 *)t->tx_buf)[espi->tx]; | |
454 | ep93xx_spi_write_u8(espi, SSPDR, tx_val); | |
455 | espi->tx += sizeof(tx_val); | |
456 | } | |
457 | } | |
458 | ||
459 | static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t) | |
460 | { | |
461 | if (bits_per_word(espi) > 8) { | |
462 | u16 rx_val; | |
463 | ||
464 | rx_val = ep93xx_spi_read_u16(espi, SSPDR); | |
465 | if (t->rx_buf) | |
466 | ((u16 *)t->rx_buf)[espi->rx] = rx_val; | |
467 | espi->rx += sizeof(rx_val); | |
468 | } else { | |
469 | u8 rx_val; | |
470 | ||
471 | rx_val = ep93xx_spi_read_u8(espi, SSPDR); | |
472 | if (t->rx_buf) | |
473 | ((u8 *)t->rx_buf)[espi->rx] = rx_val; | |
474 | espi->rx += sizeof(rx_val); | |
475 | } | |
476 | } | |
477 | ||
478 | /** | |
479 | * ep93xx_spi_read_write() - perform next RX/TX transfer | |
480 | * @espi: ep93xx SPI controller struct | |
481 | * | |
482 | * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If | |
483 | * called several times, the whole transfer will be completed. Returns | |
484 | * %-EINPROGRESS when current transfer was not yet completed otherwise %0. | |
485 | * | |
486 | * When this function is finished, RX FIFO should be empty and TX FIFO should be | |
487 | * full. | |
488 | */ | |
489 | static int ep93xx_spi_read_write(struct ep93xx_spi *espi) | |
490 | { | |
491 | struct spi_message *msg = espi->current_msg; | |
492 | struct spi_transfer *t = msg->state; | |
493 | ||
494 | /* read as long as RX FIFO has frames in it */ | |
495 | while ((ep93xx_spi_read_u8(espi, SSPSR) & SSPSR_RNE)) { | |
496 | ep93xx_do_read(espi, t); | |
497 | espi->fifo_level--; | |
498 | } | |
499 | ||
500 | /* write as long as TX FIFO has room */ | |
501 | while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < t->len) { | |
502 | ep93xx_do_write(espi, t); | |
503 | espi->fifo_level++; | |
504 | } | |
505 | ||
626a96db | 506 | if (espi->rx == t->len) |
011f23a3 | 507 | return 0; |
011f23a3 MW |
508 | |
509 | return -EINPROGRESS; | |
510 | } | |
511 | ||
626a96db MW |
512 | static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi) |
513 | { | |
514 | /* | |
515 | * Now everything is set up for the current transfer. We prime the TX | |
516 | * FIFO, enable interrupts, and wait for the transfer to complete. | |
517 | */ | |
518 | if (ep93xx_spi_read_write(espi)) { | |
519 | ep93xx_spi_enable_interrupts(espi); | |
520 | wait_for_completion(&espi->wait); | |
521 | } | |
522 | } | |
523 | ||
524 | /** | |
525 | * ep93xx_spi_dma_prepare() - prepares a DMA transfer | |
526 | * @espi: ep93xx SPI controller struct | |
527 | * @dir: DMA transfer direction | |
528 | * | |
529 | * Function configures the DMA, maps the buffer and prepares the DMA | |
530 | * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR | |
531 | * in case of failure. | |
532 | */ | |
533 | static struct dma_async_tx_descriptor * | |
d4b9b578 | 534 | ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir) |
626a96db MW |
535 | { |
536 | struct spi_transfer *t = espi->current_msg->state; | |
537 | struct dma_async_tx_descriptor *txd; | |
538 | enum dma_slave_buswidth buswidth; | |
539 | struct dma_slave_config conf; | |
540 | struct scatterlist *sg; | |
541 | struct sg_table *sgt; | |
542 | struct dma_chan *chan; | |
543 | const void *buf, *pbuf; | |
544 | size_t len = t->len; | |
545 | int i, ret, nents; | |
546 | ||
547 | if (bits_per_word(espi) > 8) | |
548 | buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
549 | else | |
550 | buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
551 | ||
552 | memset(&conf, 0, sizeof(conf)); | |
553 | conf.direction = dir; | |
554 | ||
d4b9b578 | 555 | if (dir == DMA_DEV_TO_MEM) { |
626a96db MW |
556 | chan = espi->dma_rx; |
557 | buf = t->rx_buf; | |
558 | sgt = &espi->rx_sgt; | |
559 | ||
560 | conf.src_addr = espi->sspdr_phys; | |
561 | conf.src_addr_width = buswidth; | |
562 | } else { | |
563 | chan = espi->dma_tx; | |
564 | buf = t->tx_buf; | |
565 | sgt = &espi->tx_sgt; | |
566 | ||
567 | conf.dst_addr = espi->sspdr_phys; | |
568 | conf.dst_addr_width = buswidth; | |
569 | } | |
570 | ||
571 | ret = dmaengine_slave_config(chan, &conf); | |
572 | if (ret) | |
573 | return ERR_PTR(ret); | |
574 | ||
575 | /* | |
576 | * We need to split the transfer into PAGE_SIZE'd chunks. This is | |
577 | * because we are using @espi->zeropage to provide a zero RX buffer | |
578 | * for the TX transfers and we have only allocated one page for that. | |
579 | * | |
580 | * For performance reasons we allocate a new sg_table only when | |
581 | * needed. Otherwise we will re-use the current one. Eventually the | |
582 | * last sg_table is released in ep93xx_spi_release_dma(). | |
583 | */ | |
584 | ||
585 | nents = DIV_ROUND_UP(len, PAGE_SIZE); | |
586 | if (nents != sgt->nents) { | |
587 | sg_free_table(sgt); | |
588 | ||
589 | ret = sg_alloc_table(sgt, nents, GFP_KERNEL); | |
590 | if (ret) | |
591 | return ERR_PTR(ret); | |
592 | } | |
593 | ||
594 | pbuf = buf; | |
595 | for_each_sg(sgt->sgl, sg, sgt->nents, i) { | |
596 | size_t bytes = min_t(size_t, len, PAGE_SIZE); | |
597 | ||
598 | if (buf) { | |
599 | sg_set_page(sg, virt_to_page(pbuf), bytes, | |
600 | offset_in_page(pbuf)); | |
601 | } else { | |
602 | sg_set_page(sg, virt_to_page(espi->zeropage), | |
603 | bytes, 0); | |
604 | } | |
605 | ||
606 | pbuf += bytes; | |
607 | len -= bytes; | |
608 | } | |
609 | ||
610 | if (WARN_ON(len)) { | |
611 | dev_warn(&espi->pdev->dev, "len = %d expected 0!", len); | |
612 | return ERR_PTR(-EINVAL); | |
613 | } | |
614 | ||
615 | nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); | |
616 | if (!nents) | |
617 | return ERR_PTR(-ENOMEM); | |
618 | ||
d4b9b578 | 619 | txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, DMA_CTRL_ACK); |
626a96db MW |
620 | if (!txd) { |
621 | dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); | |
622 | return ERR_PTR(-ENOMEM); | |
623 | } | |
624 | return txd; | |
625 | } | |
626 | ||
627 | /** | |
628 | * ep93xx_spi_dma_finish() - finishes with a DMA transfer | |
629 | * @espi: ep93xx SPI controller struct | |
630 | * @dir: DMA transfer direction | |
631 | * | |
632 | * Function finishes with the DMA transfer. After this, the DMA buffer is | |
633 | * unmapped. | |
634 | */ | |
635 | static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi, | |
d4b9b578 | 636 | enum dma_transfer_direction dir) |
626a96db MW |
637 | { |
638 | struct dma_chan *chan; | |
639 | struct sg_table *sgt; | |
640 | ||
d4b9b578 | 641 | if (dir == DMA_DEV_TO_MEM) { |
626a96db MW |
642 | chan = espi->dma_rx; |
643 | sgt = &espi->rx_sgt; | |
644 | } else { | |
645 | chan = espi->dma_tx; | |
646 | sgt = &espi->tx_sgt; | |
647 | } | |
648 | ||
649 | dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); | |
650 | } | |
651 | ||
652 | static void ep93xx_spi_dma_callback(void *callback_param) | |
653 | { | |
654 | complete(callback_param); | |
655 | } | |
656 | ||
657 | static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi) | |
658 | { | |
659 | struct spi_message *msg = espi->current_msg; | |
660 | struct dma_async_tx_descriptor *rxd, *txd; | |
661 | ||
d4b9b578 | 662 | rxd = ep93xx_spi_dma_prepare(espi, DMA_DEV_TO_MEM); |
626a96db MW |
663 | if (IS_ERR(rxd)) { |
664 | dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd)); | |
665 | msg->status = PTR_ERR(rxd); | |
666 | return; | |
667 | } | |
668 | ||
d4b9b578 | 669 | txd = ep93xx_spi_dma_prepare(espi, DMA_MEM_TO_DEV); |
626a96db | 670 | if (IS_ERR(txd)) { |
d4b9b578 | 671 | ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); |
626a96db MW |
672 | dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(rxd)); |
673 | msg->status = PTR_ERR(txd); | |
674 | return; | |
675 | } | |
676 | ||
677 | /* We are ready when RX is done */ | |
678 | rxd->callback = ep93xx_spi_dma_callback; | |
679 | rxd->callback_param = &espi->wait; | |
680 | ||
681 | /* Now submit both descriptors and wait while they finish */ | |
682 | dmaengine_submit(rxd); | |
683 | dmaengine_submit(txd); | |
684 | ||
685 | dma_async_issue_pending(espi->dma_rx); | |
686 | dma_async_issue_pending(espi->dma_tx); | |
687 | ||
688 | wait_for_completion(&espi->wait); | |
689 | ||
d4b9b578 HS |
690 | ep93xx_spi_dma_finish(espi, DMA_MEM_TO_DEV); |
691 | ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); | |
626a96db MW |
692 | } |
693 | ||
011f23a3 MW |
694 | /** |
695 | * ep93xx_spi_process_transfer() - processes one SPI transfer | |
696 | * @espi: ep93xx SPI controller struct | |
697 | * @msg: current message | |
698 | * @t: transfer to process | |
699 | * | |
700 | * This function processes one SPI transfer given in @t. Function waits until | |
701 | * transfer is complete (may sleep) and updates @msg->status based on whether | |
25985edc | 702 | * transfer was successfully processed or not. |
011f23a3 MW |
703 | */ |
704 | static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi, | |
705 | struct spi_message *msg, | |
706 | struct spi_transfer *t) | |
707 | { | |
708 | struct ep93xx_spi_chip *chip = spi_get_ctldata(msg->spi); | |
4870c217 | 709 | int err; |
011f23a3 MW |
710 | |
711 | msg->state = t; | |
712 | ||
4870c217 HS |
713 | err = ep93xx_spi_calc_divisors(espi, chip, t->speed_hz); |
714 | if (err) { | |
715 | dev_err(&espi->pdev->dev, "failed to adjust speed\n"); | |
716 | msg->status = err; | |
717 | return; | |
718 | } | |
011f23a3 | 719 | |
4870c217 | 720 | chip->dss = bits_per_word_to_dss(t->bits_per_word); |
011f23a3 | 721 | |
4870c217 | 722 | ep93xx_spi_chip_setup(espi, chip); |
011f23a3 MW |
723 | |
724 | espi->rx = 0; | |
725 | espi->tx = 0; | |
726 | ||
727 | /* | |
626a96db MW |
728 | * There is no point of setting up DMA for the transfers which will |
729 | * fit into the FIFO and can be transferred with a single interrupt. | |
730 | * So in these cases we will be using PIO and don't bother for DMA. | |
011f23a3 | 731 | */ |
626a96db MW |
732 | if (espi->dma_rx && t->len > SPI_FIFO_SIZE) |
733 | ep93xx_spi_dma_transfer(espi); | |
734 | else | |
735 | ep93xx_spi_pio_transfer(espi); | |
011f23a3 MW |
736 | |
737 | /* | |
738 | * In case of error during transmit, we bail out from processing | |
739 | * the message. | |
740 | */ | |
741 | if (msg->status) | |
742 | return; | |
743 | ||
626a96db MW |
744 | msg->actual_length += t->len; |
745 | ||
011f23a3 MW |
746 | /* |
747 | * After this transfer is finished, perform any possible | |
748 | * post-transfer actions requested by the protocol driver. | |
749 | */ | |
750 | if (t->delay_usecs) { | |
751 | set_current_state(TASK_UNINTERRUPTIBLE); | |
752 | schedule_timeout(usecs_to_jiffies(t->delay_usecs)); | |
753 | } | |
754 | if (t->cs_change) { | |
755 | if (!list_is_last(&t->transfer_list, &msg->transfers)) { | |
756 | /* | |
757 | * In case protocol driver is asking us to drop the | |
758 | * chipselect briefly, we let the scheduler to handle | |
759 | * any "delay" here. | |
760 | */ | |
761 | ep93xx_spi_cs_control(msg->spi, false); | |
762 | cond_resched(); | |
763 | ep93xx_spi_cs_control(msg->spi, true); | |
764 | } | |
765 | } | |
011f23a3 MW |
766 | } |
767 | ||
768 | /* | |
769 | * ep93xx_spi_process_message() - process one SPI message | |
770 | * @espi: ep93xx SPI controller struct | |
771 | * @msg: message to process | |
772 | * | |
773 | * This function processes a single SPI message. We go through all transfers in | |
774 | * the message and pass them to ep93xx_spi_process_transfer(). Chipselect is | |
775 | * asserted during the whole message (unless per transfer cs_change is set). | |
776 | * | |
777 | * @msg->status contains %0 in case of success or negative error code in case of | |
778 | * failure. | |
779 | */ | |
780 | static void ep93xx_spi_process_message(struct ep93xx_spi *espi, | |
781 | struct spi_message *msg) | |
782 | { | |
783 | unsigned long timeout; | |
784 | struct spi_transfer *t; | |
785 | int err; | |
786 | ||
787 | /* | |
788 | * Enable the SPI controller and its clock. | |
789 | */ | |
790 | err = ep93xx_spi_enable(espi); | |
791 | if (err) { | |
792 | dev_err(&espi->pdev->dev, "failed to enable SPI controller\n"); | |
793 | msg->status = err; | |
794 | return; | |
795 | } | |
796 | ||
797 | /* | |
798 | * Just to be sure: flush any data from RX FIFO. | |
799 | */ | |
800 | timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT); | |
801 | while (ep93xx_spi_read_u16(espi, SSPSR) & SSPSR_RNE) { | |
802 | if (time_after(jiffies, timeout)) { | |
803 | dev_warn(&espi->pdev->dev, | |
804 | "timeout while flushing RX FIFO\n"); | |
805 | msg->status = -ETIMEDOUT; | |
806 | return; | |
807 | } | |
808 | ep93xx_spi_read_u16(espi, SSPDR); | |
809 | } | |
810 | ||
811 | /* | |
812 | * We explicitly handle FIFO level. This way we don't have to check TX | |
813 | * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns. | |
814 | */ | |
815 | espi->fifo_level = 0; | |
816 | ||
817 | /* | |
4870c217 | 818 | * Assert the chipselect. |
011f23a3 | 819 | */ |
011f23a3 MW |
820 | ep93xx_spi_cs_control(msg->spi, true); |
821 | ||
822 | list_for_each_entry(t, &msg->transfers, transfer_list) { | |
823 | ep93xx_spi_process_transfer(espi, msg, t); | |
824 | if (msg->status) | |
825 | break; | |
826 | } | |
827 | ||
828 | /* | |
829 | * Now the whole message is transferred (or failed for some reason). We | |
830 | * deselect the device and disable the SPI controller. | |
831 | */ | |
832 | ep93xx_spi_cs_control(msg->spi, false); | |
833 | ep93xx_spi_disable(espi); | |
834 | } | |
835 | ||
836 | #define work_to_espi(work) (container_of((work), struct ep93xx_spi, msg_work)) | |
837 | ||
838 | /** | |
839 | * ep93xx_spi_work() - EP93xx SPI workqueue worker function | |
840 | * @work: work struct | |
841 | * | |
842 | * Workqueue worker function. This function is called when there are new | |
843 | * SPI messages to be processed. Message is taken out from the queue and then | |
844 | * passed to ep93xx_spi_process_message(). | |
845 | * | |
846 | * After message is transferred, protocol driver is notified by calling | |
847 | * @msg->complete(). In case of error, @msg->status is set to negative error | |
848 | * number, otherwise it contains zero (and @msg->actual_length is updated). | |
849 | */ | |
850 | static void ep93xx_spi_work(struct work_struct *work) | |
851 | { | |
852 | struct ep93xx_spi *espi = work_to_espi(work); | |
853 | struct spi_message *msg; | |
854 | ||
855 | spin_lock_irq(&espi->lock); | |
856 | if (!espi->running || espi->current_msg || | |
857 | list_empty(&espi->msg_queue)) { | |
858 | spin_unlock_irq(&espi->lock); | |
859 | return; | |
860 | } | |
861 | msg = list_first_entry(&espi->msg_queue, struct spi_message, queue); | |
862 | list_del_init(&msg->queue); | |
863 | espi->current_msg = msg; | |
864 | spin_unlock_irq(&espi->lock); | |
865 | ||
866 | ep93xx_spi_process_message(espi, msg); | |
867 | ||
868 | /* | |
869 | * Update the current message and re-schedule ourselves if there are | |
870 | * more messages in the queue. | |
871 | */ | |
872 | spin_lock_irq(&espi->lock); | |
873 | espi->current_msg = NULL; | |
874 | if (espi->running && !list_empty(&espi->msg_queue)) | |
875 | queue_work(espi->wq, &espi->msg_work); | |
876 | spin_unlock_irq(&espi->lock); | |
877 | ||
878 | /* notify the protocol driver that we are done with this message */ | |
879 | msg->complete(msg->context); | |
880 | } | |
881 | ||
882 | static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id) | |
883 | { | |
884 | struct ep93xx_spi *espi = dev_id; | |
885 | u8 irq_status = ep93xx_spi_read_u8(espi, SSPIIR); | |
886 | ||
887 | /* | |
888 | * If we got ROR (receive overrun) interrupt we know that something is | |
889 | * wrong. Just abort the message. | |
890 | */ | |
891 | if (unlikely(irq_status & SSPIIR_RORIS)) { | |
892 | /* clear the overrun interrupt */ | |
893 | ep93xx_spi_write_u8(espi, SSPICR, 0); | |
894 | dev_warn(&espi->pdev->dev, | |
895 | "receive overrun, aborting the message\n"); | |
896 | espi->current_msg->status = -EIO; | |
897 | } else { | |
898 | /* | |
899 | * Interrupt is either RX (RIS) or TX (TIS). For both cases we | |
900 | * simply execute next data transfer. | |
901 | */ | |
902 | if (ep93xx_spi_read_write(espi)) { | |
903 | /* | |
904 | * In normal case, there still is some processing left | |
905 | * for current transfer. Let's wait for the next | |
906 | * interrupt then. | |
907 | */ | |
908 | return IRQ_HANDLED; | |
909 | } | |
910 | } | |
911 | ||
912 | /* | |
913 | * Current transfer is finished, either with error or with success. In | |
914 | * any case we disable interrupts and notify the worker to handle | |
915 | * any post-processing of the message. | |
916 | */ | |
917 | ep93xx_spi_disable_interrupts(espi); | |
918 | complete(&espi->wait); | |
919 | return IRQ_HANDLED; | |
920 | } | |
921 | ||
626a96db MW |
922 | static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param) |
923 | { | |
924 | if (ep93xx_dma_chan_is_m2p(chan)) | |
925 | return false; | |
926 | ||
927 | chan->private = filter_param; | |
928 | return true; | |
929 | } | |
930 | ||
931 | static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi) | |
932 | { | |
933 | dma_cap_mask_t mask; | |
934 | int ret; | |
935 | ||
936 | espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL); | |
937 | if (!espi->zeropage) | |
938 | return -ENOMEM; | |
939 | ||
940 | dma_cap_zero(mask); | |
941 | dma_cap_set(DMA_SLAVE, mask); | |
942 | ||
943 | espi->dma_rx_data.port = EP93XX_DMA_SSP; | |
a485df4b | 944 | espi->dma_rx_data.direction = DMA_DEV_TO_MEM; |
626a96db MW |
945 | espi->dma_rx_data.name = "ep93xx-spi-rx"; |
946 | ||
947 | espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter, | |
948 | &espi->dma_rx_data); | |
949 | if (!espi->dma_rx) { | |
950 | ret = -ENODEV; | |
951 | goto fail_free_page; | |
952 | } | |
953 | ||
954 | espi->dma_tx_data.port = EP93XX_DMA_SSP; | |
a485df4b | 955 | espi->dma_tx_data.direction = DMA_MEM_TO_DEV; |
626a96db MW |
956 | espi->dma_tx_data.name = "ep93xx-spi-tx"; |
957 | ||
958 | espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter, | |
959 | &espi->dma_tx_data); | |
960 | if (!espi->dma_tx) { | |
961 | ret = -ENODEV; | |
962 | goto fail_release_rx; | |
963 | } | |
964 | ||
965 | return 0; | |
966 | ||
967 | fail_release_rx: | |
968 | dma_release_channel(espi->dma_rx); | |
969 | espi->dma_rx = NULL; | |
970 | fail_free_page: | |
971 | free_page((unsigned long)espi->zeropage); | |
972 | ||
973 | return ret; | |
974 | } | |
975 | ||
976 | static void ep93xx_spi_release_dma(struct ep93xx_spi *espi) | |
977 | { | |
978 | if (espi->dma_rx) { | |
979 | dma_release_channel(espi->dma_rx); | |
980 | sg_free_table(&espi->rx_sgt); | |
981 | } | |
982 | if (espi->dma_tx) { | |
983 | dma_release_channel(espi->dma_tx); | |
984 | sg_free_table(&espi->tx_sgt); | |
985 | } | |
986 | ||
987 | if (espi->zeropage) | |
988 | free_page((unsigned long)espi->zeropage); | |
989 | } | |
990 | ||
fd4a319b | 991 | static int ep93xx_spi_probe(struct platform_device *pdev) |
011f23a3 MW |
992 | { |
993 | struct spi_master *master; | |
994 | struct ep93xx_spi_info *info; | |
995 | struct ep93xx_spi *espi; | |
996 | struct resource *res; | |
6d6467ee | 997 | int irq; |
011f23a3 MW |
998 | int error; |
999 | ||
1000 | info = pdev->dev.platform_data; | |
1001 | ||
1002 | master = spi_alloc_master(&pdev->dev, sizeof(*espi)); | |
1003 | if (!master) { | |
1004 | dev_err(&pdev->dev, "failed to allocate spi master\n"); | |
1005 | return -ENOMEM; | |
1006 | } | |
1007 | ||
1008 | master->setup = ep93xx_spi_setup; | |
1009 | master->transfer = ep93xx_spi_transfer; | |
1010 | master->cleanup = ep93xx_spi_cleanup; | |
1011 | master->bus_num = pdev->id; | |
1012 | master->num_chipselect = info->num_chipselect; | |
1013 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
24778be2 | 1014 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
011f23a3 MW |
1015 | |
1016 | platform_set_drvdata(pdev, master); | |
1017 | ||
1018 | espi = spi_master_get_devdata(master); | |
1019 | ||
1020 | espi->clk = clk_get(&pdev->dev, NULL); | |
1021 | if (IS_ERR(espi->clk)) { | |
1022 | dev_err(&pdev->dev, "unable to get spi clock\n"); | |
1023 | error = PTR_ERR(espi->clk); | |
1024 | goto fail_release_master; | |
1025 | } | |
1026 | ||
1027 | spin_lock_init(&espi->lock); | |
1028 | init_completion(&espi->wait); | |
1029 | ||
1030 | /* | |
1031 | * Calculate maximum and minimum supported clock rates | |
1032 | * for the controller. | |
1033 | */ | |
1034 | espi->max_rate = clk_get_rate(espi->clk) / 2; | |
1035 | espi->min_rate = clk_get_rate(espi->clk) / (254 * 256); | |
1036 | espi->pdev = pdev; | |
1037 | ||
6d6467ee HH |
1038 | irq = platform_get_irq(pdev, 0); |
1039 | if (irq < 0) { | |
011f23a3 MW |
1040 | error = -EBUSY; |
1041 | dev_err(&pdev->dev, "failed to get irq resources\n"); | |
1042 | goto fail_put_clock; | |
1043 | } | |
1044 | ||
1045 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1046 | if (!res) { | |
1047 | dev_err(&pdev->dev, "unable to get iomem resource\n"); | |
1048 | error = -ENODEV; | |
1049 | goto fail_put_clock; | |
1050 | } | |
1051 | ||
626a96db | 1052 | espi->sspdr_phys = res->start + SSPDR; |
6d6467ee | 1053 | |
b0ee5605 TR |
1054 | espi->regs_base = devm_ioremap_resource(&pdev->dev, res); |
1055 | if (IS_ERR(espi->regs_base)) { | |
1056 | error = PTR_ERR(espi->regs_base); | |
6d6467ee | 1057 | goto fail_put_clock; |
011f23a3 MW |
1058 | } |
1059 | ||
6d6467ee HH |
1060 | error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt, |
1061 | 0, "ep93xx-spi", espi); | |
011f23a3 MW |
1062 | if (error) { |
1063 | dev_err(&pdev->dev, "failed to request irq\n"); | |
6d6467ee | 1064 | goto fail_put_clock; |
011f23a3 MW |
1065 | } |
1066 | ||
626a96db MW |
1067 | if (info->use_dma && ep93xx_spi_setup_dma(espi)) |
1068 | dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n"); | |
1069 | ||
011f23a3 MW |
1070 | espi->wq = create_singlethread_workqueue("ep93xx_spid"); |
1071 | if (!espi->wq) { | |
1072 | dev_err(&pdev->dev, "unable to create workqueue\n"); | |
27474d26 | 1073 | error = -ENOMEM; |
626a96db | 1074 | goto fail_free_dma; |
011f23a3 MW |
1075 | } |
1076 | INIT_WORK(&espi->msg_work, ep93xx_spi_work); | |
1077 | INIT_LIST_HEAD(&espi->msg_queue); | |
1078 | espi->running = true; | |
1079 | ||
1080 | /* make sure that the hardware is disabled */ | |
1081 | ep93xx_spi_write_u8(espi, SSPCR1, 0); | |
1082 | ||
1083 | error = spi_register_master(master); | |
1084 | if (error) { | |
1085 | dev_err(&pdev->dev, "failed to register SPI master\n"); | |
1086 | goto fail_free_queue; | |
1087 | } | |
1088 | ||
1089 | dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n", | |
6d6467ee | 1090 | (unsigned long)res->start, irq); |
011f23a3 MW |
1091 | |
1092 | return 0; | |
1093 | ||
1094 | fail_free_queue: | |
1095 | destroy_workqueue(espi->wq); | |
626a96db MW |
1096 | fail_free_dma: |
1097 | ep93xx_spi_release_dma(espi); | |
011f23a3 MW |
1098 | fail_put_clock: |
1099 | clk_put(espi->clk); | |
1100 | fail_release_master: | |
1101 | spi_master_put(master); | |
011f23a3 MW |
1102 | |
1103 | return error; | |
1104 | } | |
1105 | ||
fd4a319b | 1106 | static int ep93xx_spi_remove(struct platform_device *pdev) |
011f23a3 MW |
1107 | { |
1108 | struct spi_master *master = platform_get_drvdata(pdev); | |
1109 | struct ep93xx_spi *espi = spi_master_get_devdata(master); | |
011f23a3 MW |
1110 | |
1111 | spin_lock_irq(&espi->lock); | |
1112 | espi->running = false; | |
1113 | spin_unlock_irq(&espi->lock); | |
1114 | ||
1115 | destroy_workqueue(espi->wq); | |
1116 | ||
1117 | /* | |
1118 | * Complete remaining messages with %-ESHUTDOWN status. | |
1119 | */ | |
1120 | spin_lock_irq(&espi->lock); | |
1121 | while (!list_empty(&espi->msg_queue)) { | |
1122 | struct spi_message *msg; | |
1123 | ||
1124 | msg = list_first_entry(&espi->msg_queue, | |
1125 | struct spi_message, queue); | |
1126 | list_del_init(&msg->queue); | |
1127 | msg->status = -ESHUTDOWN; | |
1128 | spin_unlock_irq(&espi->lock); | |
1129 | msg->complete(msg->context); | |
1130 | spin_lock_irq(&espi->lock); | |
1131 | } | |
1132 | spin_unlock_irq(&espi->lock); | |
1133 | ||
626a96db | 1134 | ep93xx_spi_release_dma(espi); |
011f23a3 | 1135 | clk_put(espi->clk); |
011f23a3 MW |
1136 | |
1137 | spi_unregister_master(master); | |
1138 | return 0; | |
1139 | } | |
1140 | ||
1141 | static struct platform_driver ep93xx_spi_driver = { | |
1142 | .driver = { | |
1143 | .name = "ep93xx-spi", | |
1144 | .owner = THIS_MODULE, | |
1145 | }, | |
940ab889 | 1146 | .probe = ep93xx_spi_probe, |
fd4a319b | 1147 | .remove = ep93xx_spi_remove, |
011f23a3 | 1148 | }; |
940ab889 | 1149 | module_platform_driver(ep93xx_spi_driver); |
011f23a3 MW |
1150 | |
1151 | MODULE_DESCRIPTION("EP93xx SPI Controller driver"); | |
1152 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>"); | |
1153 | MODULE_LICENSE("GPL"); | |
1154 | MODULE_ALIAS("platform:ep93xx-spi"); |