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011f23a3 MW |
1 | /* |
2 | * Driver for Cirrus Logic EP93xx SPI controller. | |
3 | * | |
626a96db | 4 | * Copyright (C) 2010-2011 Mika Westerberg |
011f23a3 MW |
5 | * |
6 | * Explicit FIFO handling code was inspired by amba-pl022 driver. | |
7 | * | |
8 | * Chip select support using other than built-in GPIOs by H. Hartley Sweeten. | |
9 | * | |
10 | * For more information about the SPI controller see documentation on Cirrus | |
11 | * Logic web site: | |
12 | * http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | */ | |
18 | ||
19 | #include <linux/io.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/device.h> | |
626a96db | 24 | #include <linux/dmaengine.h> |
011f23a3 MW |
25 | #include <linux/bitops.h> |
26 | #include <linux/interrupt.h> | |
5bdb7613 | 27 | #include <linux/module.h> |
011f23a3 | 28 | #include <linux/platform_device.h> |
011f23a3 | 29 | #include <linux/sched.h> |
626a96db | 30 | #include <linux/scatterlist.h> |
55f0cd3f | 31 | #include <linux/gpio.h> |
011f23a3 MW |
32 | #include <linux/spi/spi.h> |
33 | ||
a3b29245 AB |
34 | #include <linux/platform_data/dma-ep93xx.h> |
35 | #include <linux/platform_data/spi-ep93xx.h> | |
011f23a3 MW |
36 | |
37 | #define SSPCR0 0x0000 | |
38 | #define SSPCR0_MODE_SHIFT 6 | |
39 | #define SSPCR0_SCR_SHIFT 8 | |
40 | ||
41 | #define SSPCR1 0x0004 | |
42 | #define SSPCR1_RIE BIT(0) | |
43 | #define SSPCR1_TIE BIT(1) | |
44 | #define SSPCR1_RORIE BIT(2) | |
45 | #define SSPCR1_LBM BIT(3) | |
46 | #define SSPCR1_SSE BIT(4) | |
47 | #define SSPCR1_MS BIT(5) | |
48 | #define SSPCR1_SOD BIT(6) | |
49 | ||
50 | #define SSPDR 0x0008 | |
51 | ||
52 | #define SSPSR 0x000c | |
53 | #define SSPSR_TFE BIT(0) | |
54 | #define SSPSR_TNF BIT(1) | |
55 | #define SSPSR_RNE BIT(2) | |
56 | #define SSPSR_RFF BIT(3) | |
57 | #define SSPSR_BSY BIT(4) | |
58 | #define SSPCPSR 0x0010 | |
59 | ||
60 | #define SSPIIR 0x0014 | |
61 | #define SSPIIR_RIS BIT(0) | |
62 | #define SSPIIR_TIS BIT(1) | |
63 | #define SSPIIR_RORIS BIT(2) | |
64 | #define SSPICR SSPIIR | |
65 | ||
66 | /* timeout in milliseconds */ | |
67 | #define SPI_TIMEOUT 5 | |
68 | /* maximum depth of RX/TX FIFO */ | |
69 | #define SPI_FIFO_SIZE 8 | |
70 | ||
71 | /** | |
72 | * struct ep93xx_spi - EP93xx SPI controller structure | |
011f23a3 MW |
73 | * @pdev: pointer to platform device |
74 | * @clk: clock for the controller | |
75 | * @regs_base: pointer to ioremap()'d registers | |
626a96db | 76 | * @sspdr_phys: physical address of the SSPDR register |
011f23a3 | 77 | * @wait: wait here until given transfer is completed |
011f23a3 MW |
78 | * @current_msg: message that is currently processed (or %NULL if none) |
79 | * @tx: current byte in transfer to transmit | |
80 | * @rx: current byte in transfer to receive | |
81 | * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one | |
82 | * frame decreases this level and sending one frame increases it. | |
626a96db MW |
83 | * @dma_rx: RX DMA channel |
84 | * @dma_tx: TX DMA channel | |
85 | * @dma_rx_data: RX parameters passed to the DMA engine | |
86 | * @dma_tx_data: TX parameters passed to the DMA engine | |
87 | * @rx_sgt: sg table for RX transfers | |
88 | * @tx_sgt: sg table for TX transfers | |
89 | * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by | |
90 | * the client | |
011f23a3 MW |
91 | */ |
92 | struct ep93xx_spi { | |
011f23a3 MW |
93 | const struct platform_device *pdev; |
94 | struct clk *clk; | |
95 | void __iomem *regs_base; | |
626a96db | 96 | unsigned long sspdr_phys; |
011f23a3 | 97 | struct completion wait; |
011f23a3 MW |
98 | struct spi_message *current_msg; |
99 | size_t tx; | |
100 | size_t rx; | |
101 | size_t fifo_level; | |
626a96db MW |
102 | struct dma_chan *dma_rx; |
103 | struct dma_chan *dma_tx; | |
104 | struct ep93xx_dma_data dma_rx_data; | |
105 | struct ep93xx_dma_data dma_tx_data; | |
106 | struct sg_table rx_sgt; | |
107 | struct sg_table tx_sgt; | |
108 | void *zeropage; | |
011f23a3 MW |
109 | }; |
110 | ||
011f23a3 MW |
111 | /* converts bits per word to CR0.DSS value */ |
112 | #define bits_per_word_to_dss(bpw) ((bpw) - 1) | |
113 | ||
8d7586bd HS |
114 | static void ep93xx_spi_write_u8(const struct ep93xx_spi *espi, |
115 | u16 reg, u8 value) | |
011f23a3 | 116 | { |
8d7586bd | 117 | writeb(value, espi->regs_base + reg); |
011f23a3 MW |
118 | } |
119 | ||
8d7586bd | 120 | static u8 ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg) |
011f23a3 | 121 | { |
8d7586bd | 122 | return readb(spi->regs_base + reg); |
011f23a3 MW |
123 | } |
124 | ||
8d7586bd HS |
125 | static void ep93xx_spi_write_u16(const struct ep93xx_spi *espi, |
126 | u16 reg, u16 value) | |
011f23a3 | 127 | { |
8d7586bd | 128 | writew(value, espi->regs_base + reg); |
011f23a3 MW |
129 | } |
130 | ||
8d7586bd | 131 | static u16 ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg) |
011f23a3 | 132 | { |
8d7586bd | 133 | return readw(spi->regs_base + reg); |
011f23a3 MW |
134 | } |
135 | ||
136 | static int ep93xx_spi_enable(const struct ep93xx_spi *espi) | |
137 | { | |
138 | u8 regval; | |
139 | int err; | |
140 | ||
141 | err = clk_enable(espi->clk); | |
142 | if (err) | |
143 | return err; | |
144 | ||
145 | regval = ep93xx_spi_read_u8(espi, SSPCR1); | |
146 | regval |= SSPCR1_SSE; | |
147 | ep93xx_spi_write_u8(espi, SSPCR1, regval); | |
148 | ||
149 | return 0; | |
150 | } | |
151 | ||
152 | static void ep93xx_spi_disable(const struct ep93xx_spi *espi) | |
153 | { | |
154 | u8 regval; | |
155 | ||
156 | regval = ep93xx_spi_read_u8(espi, SSPCR1); | |
157 | regval &= ~SSPCR1_SSE; | |
158 | ep93xx_spi_write_u8(espi, SSPCR1, regval); | |
159 | ||
160 | clk_disable(espi->clk); | |
161 | } | |
162 | ||
163 | static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi) | |
164 | { | |
165 | u8 regval; | |
166 | ||
167 | regval = ep93xx_spi_read_u8(espi, SSPCR1); | |
168 | regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); | |
169 | ep93xx_spi_write_u8(espi, SSPCR1, regval); | |
170 | } | |
171 | ||
172 | static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi) | |
173 | { | |
174 | u8 regval; | |
175 | ||
176 | regval = ep93xx_spi_read_u8(espi, SSPCR1); | |
177 | regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); | |
178 | ep93xx_spi_write_u8(espi, SSPCR1, regval); | |
179 | } | |
180 | ||
181 | /** | |
182 | * ep93xx_spi_calc_divisors() - calculates SPI clock divisors | |
183 | * @espi: ep93xx SPI controller struct | |
011f23a3 | 184 | * @rate: desired SPI output clock rate |
f7ef1da9 HS |
185 | * @div_cpsr: pointer to return the cpsr (pre-scaler) divider |
186 | * @div_scr: pointer to return the scr divider | |
011f23a3 MW |
187 | */ |
188 | static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi, | |
56fc0b42 | 189 | u32 rate, u8 *div_cpsr, u8 *div_scr) |
011f23a3 | 190 | { |
56fc0b42 | 191 | struct spi_master *master = platform_get_drvdata(espi->pdev); |
011f23a3 MW |
192 | unsigned long spi_clk_rate = clk_get_rate(espi->clk); |
193 | int cpsr, scr; | |
194 | ||
195 | /* | |
196 | * Make sure that max value is between values supported by the | |
197 | * controller. Note that minimum value is already checked in | |
84ddb3c1 | 198 | * ep93xx_spi_transfer_one_message(). |
011f23a3 | 199 | */ |
56fc0b42 | 200 | rate = clamp(rate, master->min_speed_hz, master->max_speed_hz); |
011f23a3 MW |
201 | |
202 | /* | |
203 | * Calculate divisors so that we can get speed according the | |
204 | * following formula: | |
205 | * rate = spi_clock_rate / (cpsr * (1 + scr)) | |
206 | * | |
207 | * cpsr must be even number and starts from 2, scr can be any number | |
208 | * between 0 and 255. | |
209 | */ | |
210 | for (cpsr = 2; cpsr <= 254; cpsr += 2) { | |
211 | for (scr = 0; scr <= 255; scr++) { | |
212 | if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) { | |
f7ef1da9 HS |
213 | *div_scr = (u8)scr; |
214 | *div_cpsr = (u8)cpsr; | |
011f23a3 MW |
215 | return 0; |
216 | } | |
217 | } | |
218 | } | |
219 | ||
220 | return -EINVAL; | |
221 | } | |
222 | ||
55f0cd3f | 223 | static void ep93xx_spi_cs_control(struct spi_device *spi, bool enable) |
011f23a3 | 224 | { |
55f0cd3f HS |
225 | if (spi->mode & SPI_CS_HIGH) |
226 | enable = !enable; | |
011f23a3 | 227 | |
55f0cd3f HS |
228 | if (gpio_is_valid(spi->cs_gpio)) |
229 | gpio_set_value(spi->cs_gpio, !enable); | |
011f23a3 MW |
230 | } |
231 | ||
f7ef1da9 | 232 | static int ep93xx_spi_chip_setup(const struct ep93xx_spi *espi, |
55f0cd3f HS |
233 | struct spi_device *spi, |
234 | struct spi_transfer *xfer) | |
011f23a3 | 235 | { |
55f0cd3f | 236 | u8 dss = bits_per_word_to_dss(xfer->bits_per_word); |
f7ef1da9 HS |
237 | u8 div_cpsr = 0; |
238 | u8 div_scr = 0; | |
011f23a3 | 239 | u16 cr0; |
f7ef1da9 HS |
240 | int err; |
241 | ||
55f0cd3f HS |
242 | err = ep93xx_spi_calc_divisors(espi, xfer->speed_hz, |
243 | &div_cpsr, &div_scr); | |
f7ef1da9 HS |
244 | if (err) |
245 | return err; | |
011f23a3 | 246 | |
f7ef1da9 | 247 | cr0 = div_scr << SSPCR0_SCR_SHIFT; |
55f0cd3f | 248 | cr0 |= (spi->mode & (SPI_CPHA | SPI_CPOL)) << SSPCR0_MODE_SHIFT; |
d9b65dfd | 249 | cr0 |= dss; |
011f23a3 MW |
250 | |
251 | dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n", | |
55f0cd3f | 252 | spi->mode, div_cpsr, div_scr, dss); |
a1829d2b | 253 | dev_dbg(&espi->pdev->dev, "setup: cr0 %#x\n", cr0); |
011f23a3 | 254 | |
f7ef1da9 | 255 | ep93xx_spi_write_u8(espi, SSPCPSR, div_cpsr); |
011f23a3 | 256 | ep93xx_spi_write_u16(espi, SSPCR0, cr0); |
f7ef1da9 HS |
257 | |
258 | return 0; | |
011f23a3 MW |
259 | } |
260 | ||
011f23a3 MW |
261 | static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t) |
262 | { | |
701c3587 | 263 | if (t->bits_per_word > 8) { |
011f23a3 MW |
264 | u16 tx_val = 0; |
265 | ||
266 | if (t->tx_buf) | |
267 | tx_val = ((u16 *)t->tx_buf)[espi->tx]; | |
268 | ep93xx_spi_write_u16(espi, SSPDR, tx_val); | |
269 | espi->tx += sizeof(tx_val); | |
270 | } else { | |
271 | u8 tx_val = 0; | |
272 | ||
273 | if (t->tx_buf) | |
274 | tx_val = ((u8 *)t->tx_buf)[espi->tx]; | |
275 | ep93xx_spi_write_u8(espi, SSPDR, tx_val); | |
276 | espi->tx += sizeof(tx_val); | |
277 | } | |
278 | } | |
279 | ||
280 | static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t) | |
281 | { | |
701c3587 | 282 | if (t->bits_per_word > 8) { |
011f23a3 MW |
283 | u16 rx_val; |
284 | ||
285 | rx_val = ep93xx_spi_read_u16(espi, SSPDR); | |
286 | if (t->rx_buf) | |
287 | ((u16 *)t->rx_buf)[espi->rx] = rx_val; | |
288 | espi->rx += sizeof(rx_val); | |
289 | } else { | |
290 | u8 rx_val; | |
291 | ||
292 | rx_val = ep93xx_spi_read_u8(espi, SSPDR); | |
293 | if (t->rx_buf) | |
294 | ((u8 *)t->rx_buf)[espi->rx] = rx_val; | |
295 | espi->rx += sizeof(rx_val); | |
296 | } | |
297 | } | |
298 | ||
299 | /** | |
300 | * ep93xx_spi_read_write() - perform next RX/TX transfer | |
301 | * @espi: ep93xx SPI controller struct | |
302 | * | |
303 | * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If | |
304 | * called several times, the whole transfer will be completed. Returns | |
305 | * %-EINPROGRESS when current transfer was not yet completed otherwise %0. | |
306 | * | |
307 | * When this function is finished, RX FIFO should be empty and TX FIFO should be | |
308 | * full. | |
309 | */ | |
310 | static int ep93xx_spi_read_write(struct ep93xx_spi *espi) | |
311 | { | |
312 | struct spi_message *msg = espi->current_msg; | |
313 | struct spi_transfer *t = msg->state; | |
314 | ||
315 | /* read as long as RX FIFO has frames in it */ | |
316 | while ((ep93xx_spi_read_u8(espi, SSPSR) & SSPSR_RNE)) { | |
317 | ep93xx_do_read(espi, t); | |
318 | espi->fifo_level--; | |
319 | } | |
320 | ||
321 | /* write as long as TX FIFO has room */ | |
322 | while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < t->len) { | |
323 | ep93xx_do_write(espi, t); | |
324 | espi->fifo_level++; | |
325 | } | |
326 | ||
626a96db | 327 | if (espi->rx == t->len) |
011f23a3 | 328 | return 0; |
011f23a3 MW |
329 | |
330 | return -EINPROGRESS; | |
331 | } | |
332 | ||
626a96db MW |
333 | static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi) |
334 | { | |
335 | /* | |
336 | * Now everything is set up for the current transfer. We prime the TX | |
337 | * FIFO, enable interrupts, and wait for the transfer to complete. | |
338 | */ | |
339 | if (ep93xx_spi_read_write(espi)) { | |
340 | ep93xx_spi_enable_interrupts(espi); | |
341 | wait_for_completion(&espi->wait); | |
342 | } | |
343 | } | |
344 | ||
345 | /** | |
346 | * ep93xx_spi_dma_prepare() - prepares a DMA transfer | |
347 | * @espi: ep93xx SPI controller struct | |
348 | * @dir: DMA transfer direction | |
349 | * | |
350 | * Function configures the DMA, maps the buffer and prepares the DMA | |
351 | * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR | |
352 | * in case of failure. | |
353 | */ | |
354 | static struct dma_async_tx_descriptor * | |
d4b9b578 | 355 | ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir) |
626a96db MW |
356 | { |
357 | struct spi_transfer *t = espi->current_msg->state; | |
358 | struct dma_async_tx_descriptor *txd; | |
359 | enum dma_slave_buswidth buswidth; | |
360 | struct dma_slave_config conf; | |
361 | struct scatterlist *sg; | |
362 | struct sg_table *sgt; | |
363 | struct dma_chan *chan; | |
364 | const void *buf, *pbuf; | |
365 | size_t len = t->len; | |
366 | int i, ret, nents; | |
367 | ||
701c3587 | 368 | if (t->bits_per_word > 8) |
626a96db MW |
369 | buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; |
370 | else | |
371 | buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
372 | ||
373 | memset(&conf, 0, sizeof(conf)); | |
374 | conf.direction = dir; | |
375 | ||
d4b9b578 | 376 | if (dir == DMA_DEV_TO_MEM) { |
626a96db MW |
377 | chan = espi->dma_rx; |
378 | buf = t->rx_buf; | |
379 | sgt = &espi->rx_sgt; | |
380 | ||
381 | conf.src_addr = espi->sspdr_phys; | |
382 | conf.src_addr_width = buswidth; | |
383 | } else { | |
384 | chan = espi->dma_tx; | |
385 | buf = t->tx_buf; | |
386 | sgt = &espi->tx_sgt; | |
387 | ||
388 | conf.dst_addr = espi->sspdr_phys; | |
389 | conf.dst_addr_width = buswidth; | |
390 | } | |
391 | ||
392 | ret = dmaengine_slave_config(chan, &conf); | |
393 | if (ret) | |
394 | return ERR_PTR(ret); | |
395 | ||
396 | /* | |
397 | * We need to split the transfer into PAGE_SIZE'd chunks. This is | |
398 | * because we are using @espi->zeropage to provide a zero RX buffer | |
399 | * for the TX transfers and we have only allocated one page for that. | |
400 | * | |
401 | * For performance reasons we allocate a new sg_table only when | |
402 | * needed. Otherwise we will re-use the current one. Eventually the | |
403 | * last sg_table is released in ep93xx_spi_release_dma(). | |
404 | */ | |
405 | ||
406 | nents = DIV_ROUND_UP(len, PAGE_SIZE); | |
407 | if (nents != sgt->nents) { | |
408 | sg_free_table(sgt); | |
409 | ||
410 | ret = sg_alloc_table(sgt, nents, GFP_KERNEL); | |
411 | if (ret) | |
412 | return ERR_PTR(ret); | |
413 | } | |
414 | ||
415 | pbuf = buf; | |
416 | for_each_sg(sgt->sgl, sg, sgt->nents, i) { | |
417 | size_t bytes = min_t(size_t, len, PAGE_SIZE); | |
418 | ||
419 | if (buf) { | |
420 | sg_set_page(sg, virt_to_page(pbuf), bytes, | |
421 | offset_in_page(pbuf)); | |
422 | } else { | |
423 | sg_set_page(sg, virt_to_page(espi->zeropage), | |
424 | bytes, 0); | |
425 | } | |
426 | ||
427 | pbuf += bytes; | |
428 | len -= bytes; | |
429 | } | |
430 | ||
431 | if (WARN_ON(len)) { | |
a1829d2b | 432 | dev_warn(&espi->pdev->dev, "len = %zu expected 0!\n", len); |
626a96db MW |
433 | return ERR_PTR(-EINVAL); |
434 | } | |
435 | ||
436 | nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); | |
437 | if (!nents) | |
438 | return ERR_PTR(-ENOMEM); | |
439 | ||
d4b9b578 | 440 | txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, DMA_CTRL_ACK); |
626a96db MW |
441 | if (!txd) { |
442 | dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); | |
443 | return ERR_PTR(-ENOMEM); | |
444 | } | |
445 | return txd; | |
446 | } | |
447 | ||
448 | /** | |
449 | * ep93xx_spi_dma_finish() - finishes with a DMA transfer | |
450 | * @espi: ep93xx SPI controller struct | |
451 | * @dir: DMA transfer direction | |
452 | * | |
453 | * Function finishes with the DMA transfer. After this, the DMA buffer is | |
454 | * unmapped. | |
455 | */ | |
456 | static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi, | |
d4b9b578 | 457 | enum dma_transfer_direction dir) |
626a96db MW |
458 | { |
459 | struct dma_chan *chan; | |
460 | struct sg_table *sgt; | |
461 | ||
d4b9b578 | 462 | if (dir == DMA_DEV_TO_MEM) { |
626a96db MW |
463 | chan = espi->dma_rx; |
464 | sgt = &espi->rx_sgt; | |
465 | } else { | |
466 | chan = espi->dma_tx; | |
467 | sgt = &espi->tx_sgt; | |
468 | } | |
469 | ||
470 | dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); | |
471 | } | |
472 | ||
473 | static void ep93xx_spi_dma_callback(void *callback_param) | |
474 | { | |
475 | complete(callback_param); | |
476 | } | |
477 | ||
478 | static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi) | |
479 | { | |
480 | struct spi_message *msg = espi->current_msg; | |
481 | struct dma_async_tx_descriptor *rxd, *txd; | |
482 | ||
d4b9b578 | 483 | rxd = ep93xx_spi_dma_prepare(espi, DMA_DEV_TO_MEM); |
626a96db MW |
484 | if (IS_ERR(rxd)) { |
485 | dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd)); | |
486 | msg->status = PTR_ERR(rxd); | |
487 | return; | |
488 | } | |
489 | ||
d4b9b578 | 490 | txd = ep93xx_spi_dma_prepare(espi, DMA_MEM_TO_DEV); |
626a96db | 491 | if (IS_ERR(txd)) { |
d4b9b578 | 492 | ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); |
f7aa23cb | 493 | dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(txd)); |
626a96db MW |
494 | msg->status = PTR_ERR(txd); |
495 | return; | |
496 | } | |
497 | ||
498 | /* We are ready when RX is done */ | |
499 | rxd->callback = ep93xx_spi_dma_callback; | |
500 | rxd->callback_param = &espi->wait; | |
501 | ||
502 | /* Now submit both descriptors and wait while they finish */ | |
503 | dmaengine_submit(rxd); | |
504 | dmaengine_submit(txd); | |
505 | ||
506 | dma_async_issue_pending(espi->dma_rx); | |
507 | dma_async_issue_pending(espi->dma_tx); | |
508 | ||
509 | wait_for_completion(&espi->wait); | |
510 | ||
d4b9b578 HS |
511 | ep93xx_spi_dma_finish(espi, DMA_MEM_TO_DEV); |
512 | ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); | |
626a96db MW |
513 | } |
514 | ||
011f23a3 MW |
515 | /** |
516 | * ep93xx_spi_process_transfer() - processes one SPI transfer | |
517 | * @espi: ep93xx SPI controller struct | |
518 | * @msg: current message | |
519 | * @t: transfer to process | |
520 | * | |
521 | * This function processes one SPI transfer given in @t. Function waits until | |
522 | * transfer is complete (may sleep) and updates @msg->status based on whether | |
25985edc | 523 | * transfer was successfully processed or not. |
011f23a3 MW |
524 | */ |
525 | static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi, | |
526 | struct spi_message *msg, | |
527 | struct spi_transfer *t) | |
528 | { | |
4870c217 | 529 | int err; |
011f23a3 MW |
530 | |
531 | msg->state = t; | |
532 | ||
55f0cd3f | 533 | err = ep93xx_spi_chip_setup(espi, msg->spi, t); |
4870c217 | 534 | if (err) { |
f7ef1da9 HS |
535 | dev_err(&espi->pdev->dev, |
536 | "failed to setup chip for transfer\n"); | |
4870c217 HS |
537 | msg->status = err; |
538 | return; | |
539 | } | |
011f23a3 | 540 | |
011f23a3 MW |
541 | espi->rx = 0; |
542 | espi->tx = 0; | |
543 | ||
544 | /* | |
626a96db MW |
545 | * There is no point of setting up DMA for the transfers which will |
546 | * fit into the FIFO and can be transferred with a single interrupt. | |
547 | * So in these cases we will be using PIO and don't bother for DMA. | |
011f23a3 | 548 | */ |
626a96db MW |
549 | if (espi->dma_rx && t->len > SPI_FIFO_SIZE) |
550 | ep93xx_spi_dma_transfer(espi); | |
551 | else | |
552 | ep93xx_spi_pio_transfer(espi); | |
011f23a3 MW |
553 | |
554 | /* | |
555 | * In case of error during transmit, we bail out from processing | |
556 | * the message. | |
557 | */ | |
558 | if (msg->status) | |
559 | return; | |
560 | ||
626a96db MW |
561 | msg->actual_length += t->len; |
562 | ||
011f23a3 MW |
563 | /* |
564 | * After this transfer is finished, perform any possible | |
565 | * post-transfer actions requested by the protocol driver. | |
566 | */ | |
567 | if (t->delay_usecs) { | |
568 | set_current_state(TASK_UNINTERRUPTIBLE); | |
569 | schedule_timeout(usecs_to_jiffies(t->delay_usecs)); | |
570 | } | |
571 | if (t->cs_change) { | |
572 | if (!list_is_last(&t->transfer_list, &msg->transfers)) { | |
573 | /* | |
574 | * In case protocol driver is asking us to drop the | |
575 | * chipselect briefly, we let the scheduler to handle | |
576 | * any "delay" here. | |
577 | */ | |
578 | ep93xx_spi_cs_control(msg->spi, false); | |
579 | cond_resched(); | |
580 | ep93xx_spi_cs_control(msg->spi, true); | |
581 | } | |
582 | } | |
011f23a3 MW |
583 | } |
584 | ||
585 | /* | |
586 | * ep93xx_spi_process_message() - process one SPI message | |
587 | * @espi: ep93xx SPI controller struct | |
588 | * @msg: message to process | |
589 | * | |
590 | * This function processes a single SPI message. We go through all transfers in | |
591 | * the message and pass them to ep93xx_spi_process_transfer(). Chipselect is | |
592 | * asserted during the whole message (unless per transfer cs_change is set). | |
593 | * | |
594 | * @msg->status contains %0 in case of success or negative error code in case of | |
595 | * failure. | |
596 | */ | |
597 | static void ep93xx_spi_process_message(struct ep93xx_spi *espi, | |
598 | struct spi_message *msg) | |
599 | { | |
600 | unsigned long timeout; | |
601 | struct spi_transfer *t; | |
602 | int err; | |
603 | ||
604 | /* | |
605 | * Enable the SPI controller and its clock. | |
606 | */ | |
607 | err = ep93xx_spi_enable(espi); | |
608 | if (err) { | |
609 | dev_err(&espi->pdev->dev, "failed to enable SPI controller\n"); | |
610 | msg->status = err; | |
611 | return; | |
612 | } | |
613 | ||
614 | /* | |
615 | * Just to be sure: flush any data from RX FIFO. | |
616 | */ | |
617 | timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT); | |
618 | while (ep93xx_spi_read_u16(espi, SSPSR) & SSPSR_RNE) { | |
619 | if (time_after(jiffies, timeout)) { | |
620 | dev_warn(&espi->pdev->dev, | |
621 | "timeout while flushing RX FIFO\n"); | |
622 | msg->status = -ETIMEDOUT; | |
623 | return; | |
624 | } | |
625 | ep93xx_spi_read_u16(espi, SSPDR); | |
626 | } | |
627 | ||
628 | /* | |
629 | * We explicitly handle FIFO level. This way we don't have to check TX | |
630 | * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns. | |
631 | */ | |
632 | espi->fifo_level = 0; | |
633 | ||
634 | /* | |
4870c217 | 635 | * Assert the chipselect. |
011f23a3 | 636 | */ |
011f23a3 MW |
637 | ep93xx_spi_cs_control(msg->spi, true); |
638 | ||
639 | list_for_each_entry(t, &msg->transfers, transfer_list) { | |
640 | ep93xx_spi_process_transfer(espi, msg, t); | |
641 | if (msg->status) | |
642 | break; | |
643 | } | |
644 | ||
645 | /* | |
646 | * Now the whole message is transferred (or failed for some reason). We | |
647 | * deselect the device and disable the SPI controller. | |
648 | */ | |
649 | ep93xx_spi_cs_control(msg->spi, false); | |
650 | ep93xx_spi_disable(espi); | |
651 | } | |
652 | ||
84ddb3c1 HS |
653 | static int ep93xx_spi_transfer_one_message(struct spi_master *master, |
654 | struct spi_message *msg) | |
011f23a3 | 655 | { |
84ddb3c1 | 656 | struct ep93xx_spi *espi = spi_master_get_devdata(master); |
011f23a3 | 657 | |
84ddb3c1 HS |
658 | msg->state = NULL; |
659 | msg->status = 0; | |
660 | msg->actual_length = 0; | |
011f23a3 | 661 | |
84ddb3c1 HS |
662 | espi->current_msg = msg; |
663 | ep93xx_spi_process_message(espi, msg); | |
011f23a3 | 664 | espi->current_msg = NULL; |
011f23a3 | 665 | |
84ddb3c1 HS |
666 | spi_finalize_current_message(master); |
667 | ||
668 | return 0; | |
011f23a3 MW |
669 | } |
670 | ||
671 | static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id) | |
672 | { | |
673 | struct ep93xx_spi *espi = dev_id; | |
674 | u8 irq_status = ep93xx_spi_read_u8(espi, SSPIIR); | |
675 | ||
676 | /* | |
677 | * If we got ROR (receive overrun) interrupt we know that something is | |
678 | * wrong. Just abort the message. | |
679 | */ | |
680 | if (unlikely(irq_status & SSPIIR_RORIS)) { | |
681 | /* clear the overrun interrupt */ | |
682 | ep93xx_spi_write_u8(espi, SSPICR, 0); | |
683 | dev_warn(&espi->pdev->dev, | |
684 | "receive overrun, aborting the message\n"); | |
685 | espi->current_msg->status = -EIO; | |
686 | } else { | |
687 | /* | |
688 | * Interrupt is either RX (RIS) or TX (TIS). For both cases we | |
689 | * simply execute next data transfer. | |
690 | */ | |
691 | if (ep93xx_spi_read_write(espi)) { | |
692 | /* | |
693 | * In normal case, there still is some processing left | |
694 | * for current transfer. Let's wait for the next | |
695 | * interrupt then. | |
696 | */ | |
697 | return IRQ_HANDLED; | |
698 | } | |
699 | } | |
700 | ||
701 | /* | |
702 | * Current transfer is finished, either with error or with success. In | |
703 | * any case we disable interrupts and notify the worker to handle | |
704 | * any post-processing of the message. | |
705 | */ | |
706 | ep93xx_spi_disable_interrupts(espi); | |
707 | complete(&espi->wait); | |
708 | return IRQ_HANDLED; | |
709 | } | |
710 | ||
626a96db MW |
711 | static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param) |
712 | { | |
713 | if (ep93xx_dma_chan_is_m2p(chan)) | |
714 | return false; | |
715 | ||
716 | chan->private = filter_param; | |
717 | return true; | |
718 | } | |
719 | ||
720 | static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi) | |
721 | { | |
722 | dma_cap_mask_t mask; | |
723 | int ret; | |
724 | ||
725 | espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL); | |
726 | if (!espi->zeropage) | |
727 | return -ENOMEM; | |
728 | ||
729 | dma_cap_zero(mask); | |
730 | dma_cap_set(DMA_SLAVE, mask); | |
731 | ||
732 | espi->dma_rx_data.port = EP93XX_DMA_SSP; | |
a485df4b | 733 | espi->dma_rx_data.direction = DMA_DEV_TO_MEM; |
626a96db MW |
734 | espi->dma_rx_data.name = "ep93xx-spi-rx"; |
735 | ||
736 | espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter, | |
737 | &espi->dma_rx_data); | |
738 | if (!espi->dma_rx) { | |
739 | ret = -ENODEV; | |
740 | goto fail_free_page; | |
741 | } | |
742 | ||
743 | espi->dma_tx_data.port = EP93XX_DMA_SSP; | |
a485df4b | 744 | espi->dma_tx_data.direction = DMA_MEM_TO_DEV; |
626a96db MW |
745 | espi->dma_tx_data.name = "ep93xx-spi-tx"; |
746 | ||
747 | espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter, | |
748 | &espi->dma_tx_data); | |
749 | if (!espi->dma_tx) { | |
750 | ret = -ENODEV; | |
751 | goto fail_release_rx; | |
752 | } | |
753 | ||
754 | return 0; | |
755 | ||
756 | fail_release_rx: | |
757 | dma_release_channel(espi->dma_rx); | |
758 | espi->dma_rx = NULL; | |
759 | fail_free_page: | |
760 | free_page((unsigned long)espi->zeropage); | |
761 | ||
762 | return ret; | |
763 | } | |
764 | ||
765 | static void ep93xx_spi_release_dma(struct ep93xx_spi *espi) | |
766 | { | |
767 | if (espi->dma_rx) { | |
768 | dma_release_channel(espi->dma_rx); | |
769 | sg_free_table(&espi->rx_sgt); | |
770 | } | |
771 | if (espi->dma_tx) { | |
772 | dma_release_channel(espi->dma_tx); | |
773 | sg_free_table(&espi->tx_sgt); | |
774 | } | |
775 | ||
776 | if (espi->zeropage) | |
777 | free_page((unsigned long)espi->zeropage); | |
778 | } | |
779 | ||
fd4a319b | 780 | static int ep93xx_spi_probe(struct platform_device *pdev) |
011f23a3 MW |
781 | { |
782 | struct spi_master *master; | |
783 | struct ep93xx_spi_info *info; | |
784 | struct ep93xx_spi *espi; | |
785 | struct resource *res; | |
6d6467ee | 786 | int irq; |
011f23a3 | 787 | int error; |
55f0cd3f | 788 | int i; |
011f23a3 | 789 | |
8074cf06 | 790 | info = dev_get_platdata(&pdev->dev); |
55f0cd3f HS |
791 | if (!info) { |
792 | dev_err(&pdev->dev, "missing platform data\n"); | |
793 | return -EINVAL; | |
794 | } | |
011f23a3 | 795 | |
48a7776e HS |
796 | irq = platform_get_irq(pdev, 0); |
797 | if (irq < 0) { | |
798 | dev_err(&pdev->dev, "failed to get irq resources\n"); | |
799 | return -EBUSY; | |
800 | } | |
801 | ||
802 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
803 | if (!res) { | |
804 | dev_err(&pdev->dev, "unable to get iomem resource\n"); | |
805 | return -ENODEV; | |
806 | } | |
807 | ||
011f23a3 | 808 | master = spi_alloc_master(&pdev->dev, sizeof(*espi)); |
b2d185ed | 809 | if (!master) |
011f23a3 | 810 | return -ENOMEM; |
011f23a3 | 811 | |
84ddb3c1 | 812 | master->transfer_one_message = ep93xx_spi_transfer_one_message; |
011f23a3 | 813 | master->bus_num = pdev->id; |
011f23a3 | 814 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
24778be2 | 815 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
011f23a3 | 816 | |
55f0cd3f HS |
817 | master->num_chipselect = info->num_chipselect; |
818 | master->cs_gpios = devm_kzalloc(&master->dev, | |
819 | sizeof(int) * master->num_chipselect, | |
820 | GFP_KERNEL); | |
821 | if (!master->cs_gpios) { | |
822 | error = -ENOMEM; | |
823 | goto fail_release_master; | |
824 | } | |
825 | ||
826 | for (i = 0; i < master->num_chipselect; i++) { | |
827 | master->cs_gpios[i] = info->chipselect[i]; | |
828 | ||
829 | if (!gpio_is_valid(master->cs_gpios[i])) | |
830 | continue; | |
831 | ||
832 | error = devm_gpio_request_one(&pdev->dev, master->cs_gpios[i], | |
833 | GPIOF_OUT_INIT_HIGH, | |
834 | "ep93xx-spi"); | |
835 | if (error) { | |
836 | dev_err(&pdev->dev, "could not request cs gpio %d\n", | |
837 | master->cs_gpios[i]); | |
838 | goto fail_release_master; | |
839 | } | |
840 | } | |
841 | ||
011f23a3 MW |
842 | platform_set_drvdata(pdev, master); |
843 | ||
844 | espi = spi_master_get_devdata(master); | |
845 | ||
e6eb8d9b | 846 | espi->clk = devm_clk_get(&pdev->dev, NULL); |
011f23a3 MW |
847 | if (IS_ERR(espi->clk)) { |
848 | dev_err(&pdev->dev, "unable to get spi clock\n"); | |
849 | error = PTR_ERR(espi->clk); | |
850 | goto fail_release_master; | |
851 | } | |
852 | ||
011f23a3 MW |
853 | init_completion(&espi->wait); |
854 | ||
855 | /* | |
856 | * Calculate maximum and minimum supported clock rates | |
857 | * for the controller. | |
858 | */ | |
56fc0b42 AL |
859 | master->max_speed_hz = clk_get_rate(espi->clk) / 2; |
860 | master->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256); | |
011f23a3 MW |
861 | espi->pdev = pdev; |
862 | ||
626a96db | 863 | espi->sspdr_phys = res->start + SSPDR; |
6d6467ee | 864 | |
b0ee5605 TR |
865 | espi->regs_base = devm_ioremap_resource(&pdev->dev, res); |
866 | if (IS_ERR(espi->regs_base)) { | |
867 | error = PTR_ERR(espi->regs_base); | |
e6eb8d9b | 868 | goto fail_release_master; |
011f23a3 MW |
869 | } |
870 | ||
6d6467ee HH |
871 | error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt, |
872 | 0, "ep93xx-spi", espi); | |
011f23a3 MW |
873 | if (error) { |
874 | dev_err(&pdev->dev, "failed to request irq\n"); | |
e6eb8d9b | 875 | goto fail_release_master; |
011f23a3 MW |
876 | } |
877 | ||
626a96db MW |
878 | if (info->use_dma && ep93xx_spi_setup_dma(espi)) |
879 | dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n"); | |
880 | ||
011f23a3 MW |
881 | /* make sure that the hardware is disabled */ |
882 | ep93xx_spi_write_u8(espi, SSPCR1, 0); | |
883 | ||
434eaf3b | 884 | error = devm_spi_register_master(&pdev->dev, master); |
011f23a3 MW |
885 | if (error) { |
886 | dev_err(&pdev->dev, "failed to register SPI master\n"); | |
84ddb3c1 | 887 | goto fail_free_dma; |
011f23a3 MW |
888 | } |
889 | ||
890 | dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n", | |
6d6467ee | 891 | (unsigned long)res->start, irq); |
011f23a3 MW |
892 | |
893 | return 0; | |
894 | ||
626a96db MW |
895 | fail_free_dma: |
896 | ep93xx_spi_release_dma(espi); | |
011f23a3 MW |
897 | fail_release_master: |
898 | spi_master_put(master); | |
011f23a3 MW |
899 | |
900 | return error; | |
901 | } | |
902 | ||
fd4a319b | 903 | static int ep93xx_spi_remove(struct platform_device *pdev) |
011f23a3 MW |
904 | { |
905 | struct spi_master *master = platform_get_drvdata(pdev); | |
906 | struct ep93xx_spi *espi = spi_master_get_devdata(master); | |
011f23a3 | 907 | |
626a96db | 908 | ep93xx_spi_release_dma(espi); |
011f23a3 | 909 | |
011f23a3 MW |
910 | return 0; |
911 | } | |
912 | ||
913 | static struct platform_driver ep93xx_spi_driver = { | |
914 | .driver = { | |
915 | .name = "ep93xx-spi", | |
011f23a3 | 916 | }, |
940ab889 | 917 | .probe = ep93xx_spi_probe, |
fd4a319b | 918 | .remove = ep93xx_spi_remove, |
011f23a3 | 919 | }; |
940ab889 | 920 | module_platform_driver(ep93xx_spi_driver); |
011f23a3 MW |
921 | |
922 | MODULE_DESCRIPTION("EP93xx SPI Controller driver"); | |
923 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>"); | |
924 | MODULE_LICENSE("GPL"); | |
925 | MODULE_ALIAS("platform:ep93xx-spi"); |