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Commit | Line | Data |
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6576bf00 FE |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // | |
3 | // Copyright 2013 Freescale Semiconductor, Inc. | |
4 | // | |
5 | // Freescale DSPI driver | |
6 | // This file contains a driver for the Freescale DSPI | |
349ad66c | 7 | |
a3108360 XL |
8 | #include <linux/clk.h> |
9 | #include <linux/delay.h> | |
90ba3703 SM |
10 | #include <linux/dmaengine.h> |
11 | #include <linux/dma-mapping.h> | |
a3108360 XL |
12 | #include <linux/err.h> |
13 | #include <linux/errno.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/io.h> | |
349ad66c | 16 | #include <linux/kernel.h> |
95bf15f3 | 17 | #include <linux/math64.h> |
349ad66c | 18 | #include <linux/module.h> |
a3108360 XL |
19 | #include <linux/of.h> |
20 | #include <linux/of_device.h> | |
432a17d7 | 21 | #include <linux/pinctrl/consumer.h> |
349ad66c | 22 | #include <linux/platform_device.h> |
a3108360 | 23 | #include <linux/pm_runtime.h> |
1acbdeb9 | 24 | #include <linux/regmap.h> |
349ad66c | 25 | #include <linux/sched.h> |
349ad66c | 26 | #include <linux/spi/spi.h> |
ec7ed770 | 27 | #include <linux/spi/spi-fsl-dspi.h> |
349ad66c | 28 | #include <linux/spi/spi_bitbang.h> |
95bf15f3 | 29 | #include <linux/time.h> |
349ad66c CF |
30 | |
31 | #define DRIVER_NAME "fsl-dspi" | |
32 | ||
349ad66c | 33 | #define DSPI_FIFO_SIZE 4 |
90ba3703 | 34 | #define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024) |
349ad66c CF |
35 | |
36 | #define SPI_MCR 0x00 | |
37 | #define SPI_MCR_MASTER (1 << 31) | |
38 | #define SPI_MCR_PCSIS (0x3F << 16) | |
39 | #define SPI_MCR_CLR_TXF (1 << 11) | |
40 | #define SPI_MCR_CLR_RXF (1 << 10) | |
3e7cc625 | 41 | #define SPI_MCR_XSPI (1 << 3) |
349ad66c CF |
42 | |
43 | #define SPI_TCR 0x08 | |
c042af95 | 44 | #define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16) |
349ad66c | 45 | |
5cc7b047 | 46 | #define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4)) |
349ad66c CF |
47 | #define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27) |
48 | #define SPI_CTAR_CPOL(x) ((x) << 26) | |
49 | #define SPI_CTAR_CPHA(x) ((x) << 25) | |
50 | #define SPI_CTAR_LSBFE(x) ((x) << 24) | |
95bf15f3 | 51 | #define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22) |
349ad66c CF |
52 | #define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20) |
53 | #define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18) | |
54 | #define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16) | |
55 | #define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12) | |
56 | #define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8) | |
57 | #define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4) | |
58 | #define SPI_CTAR_BR(x) ((x) & 0x0000000f) | |
95bf15f3 | 59 | #define SPI_CTAR_SCALE_BITS 0xf |
349ad66c CF |
60 | |
61 | #define SPI_CTAR0_SLAVE 0x0c | |
62 | ||
63 | #define SPI_SR 0x2c | |
64 | #define SPI_SR_EOQF 0x10000000 | |
d1f4a38c | 65 | #define SPI_SR_TCFQF 0x80000000 |
5ee67b58 | 66 | #define SPI_SR_CLEAR 0xdaad0000 |
349ad66c | 67 | |
90ba3703 SM |
68 | #define SPI_RSER_TFFFE BIT(25) |
69 | #define SPI_RSER_TFFFD BIT(24) | |
70 | #define SPI_RSER_RFDFE BIT(17) | |
71 | #define SPI_RSER_RFDFD BIT(16) | |
349ad66c CF |
72 | |
73 | #define SPI_RSER 0x30 | |
74 | #define SPI_RSER_EOQFE 0x10000000 | |
d1f4a38c | 75 | #define SPI_RSER_TCFQE 0x80000000 |
349ad66c CF |
76 | |
77 | #define SPI_PUSHR 0x34 | |
9e1dc9bd EH |
78 | #define SPI_PUSHR_CMD_CONT (1 << 15) |
79 | #define SPI_PUSHR_CONT (SPI_PUSHR_CMD_CONT << 16) | |
80 | #define SPI_PUSHR_CMD_CTAS(x) (((x) & 0x0003) << 12) | |
81 | #define SPI_PUSHR_CTAS(x) (SPI_PUSHR_CMD_CTAS(x) << 16) | |
82 | #define SPI_PUSHR_CMD_EOQ (1 << 11) | |
83 | #define SPI_PUSHR_EOQ (SPI_PUSHR_CMD_EOQ << 16) | |
84 | #define SPI_PUSHR_CMD_CTCNT (1 << 10) | |
85 | #define SPI_PUSHR_CTCNT (SPI_PUSHR_CMD_CTCNT << 16) | |
86 | #define SPI_PUSHR_CMD_PCS(x) ((1 << x) & 0x003f) | |
87 | #define SPI_PUSHR_PCS(x) (SPI_PUSHR_CMD_PCS(x) << 16) | |
349ad66c CF |
88 | #define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff) |
89 | ||
90 | #define SPI_PUSHR_SLAVE 0x34 | |
91 | ||
92 | #define SPI_POPR 0x38 | |
93 | #define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff) | |
94 | ||
95 | #define SPI_TXFR0 0x3c | |
96 | #define SPI_TXFR1 0x40 | |
97 | #define SPI_TXFR2 0x44 | |
98 | #define SPI_TXFR3 0x48 | |
99 | #define SPI_RXFR0 0x7c | |
100 | #define SPI_RXFR1 0x80 | |
101 | #define SPI_RXFR2 0x84 | |
102 | #define SPI_RXFR3 0x88 | |
103 | ||
58ba07ec EH |
104 | #define SPI_CTARE(x) (0x11c + (((x) & 0x3) * 4)) |
105 | #define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16) | |
106 | #define SPI_CTARE_DTCP(x) ((x) & 0x7ff) | |
107 | ||
108 | #define SPI_SREX 0x13c | |
109 | ||
349ad66c CF |
110 | #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1) |
111 | #define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf) | |
112 | #define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf) | |
113 | #define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7) | |
114 | ||
51d583ae EH |
115 | #define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4) |
116 | #define SPI_FRAME_EBITS_MASK SPI_CTARE_FMSZE(1) | |
117 | ||
58ba07ec EH |
118 | /* Register offsets for regmap_pushr */ |
119 | #define PUSHR_CMD 0x0 | |
120 | #define PUSHR_TX 0x2 | |
121 | ||
349ad66c CF |
122 | #define SPI_CS_INIT 0x01 |
123 | #define SPI_CS_ASSERT 0x02 | |
124 | #define SPI_CS_DROP 0x04 | |
125 | ||
90ba3703 SM |
126 | #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000) |
127 | ||
349ad66c | 128 | struct chip_data { |
349ad66c CF |
129 | u32 ctar_val; |
130 | u16 void_write_data; | |
131 | }; | |
132 | ||
d1f4a38c HW |
133 | enum dspi_trans_mode { |
134 | DSPI_EOQ_MODE = 0, | |
135 | DSPI_TCFQ_MODE, | |
90ba3703 | 136 | DSPI_DMA_MODE, |
d1f4a38c HW |
137 | }; |
138 | ||
139 | struct fsl_dspi_devtype_data { | |
140 | enum dspi_trans_mode trans_mode; | |
9419b200 | 141 | u8 max_clock_factor; |
58ba07ec | 142 | bool xspi_mode; |
d1f4a38c HW |
143 | }; |
144 | ||
145 | static const struct fsl_dspi_devtype_data vf610_data = { | |
90ba3703 | 146 | .trans_mode = DSPI_DMA_MODE, |
9419b200 | 147 | .max_clock_factor = 2, |
d1f4a38c HW |
148 | }; |
149 | ||
150 | static const struct fsl_dspi_devtype_data ls1021a_v1_data = { | |
151 | .trans_mode = DSPI_TCFQ_MODE, | |
9419b200 | 152 | .max_clock_factor = 8, |
58ba07ec | 153 | .xspi_mode = true, |
d1f4a38c HW |
154 | }; |
155 | ||
156 | static const struct fsl_dspi_devtype_data ls2085a_data = { | |
157 | .trans_mode = DSPI_TCFQ_MODE, | |
9419b200 | 158 | .max_clock_factor = 8, |
d1f4a38c HW |
159 | }; |
160 | ||
ec7ed770 AD |
161 | static const struct fsl_dspi_devtype_data coldfire_data = { |
162 | .trans_mode = DSPI_EOQ_MODE, | |
163 | .max_clock_factor = 8, | |
164 | }; | |
165 | ||
90ba3703 | 166 | struct fsl_dspi_dma { |
1eaccf21 | 167 | /* Length of transfer in words of DSPI_FIFO_SIZE */ |
90ba3703 SM |
168 | u32 curr_xfer_len; |
169 | ||
170 | u32 *tx_dma_buf; | |
171 | struct dma_chan *chan_tx; | |
172 | dma_addr_t tx_dma_phys; | |
173 | struct completion cmd_tx_complete; | |
174 | struct dma_async_tx_descriptor *tx_desc; | |
175 | ||
176 | u32 *rx_dma_buf; | |
177 | struct dma_chan *chan_rx; | |
178 | dma_addr_t rx_dma_phys; | |
179 | struct completion cmd_rx_complete; | |
180 | struct dma_async_tx_descriptor *rx_desc; | |
181 | }; | |
182 | ||
349ad66c | 183 | struct fsl_dspi { |
9298bc72 | 184 | struct spi_master *master; |
349ad66c CF |
185 | struct platform_device *pdev; |
186 | ||
1acbdeb9 | 187 | struct regmap *regmap; |
58ba07ec | 188 | struct regmap *regmap_pushr; |
349ad66c | 189 | int irq; |
88386e85 | 190 | struct clk *clk; |
349ad66c | 191 | |
88386e85 | 192 | struct spi_transfer *cur_transfer; |
9298bc72 | 193 | struct spi_message *cur_msg; |
349ad66c CF |
194 | struct chip_data *cur_chip; |
195 | size_t len; | |
dadcf4ab | 196 | const void *tx; |
349ad66c CF |
197 | void *rx; |
198 | void *rx_end; | |
349ad66c | 199 | u16 void_write_data; |
9e1dc9bd | 200 | u16 tx_cmd; |
dadcf4ab EH |
201 | u8 bits_per_word; |
202 | u8 bytes_per_word; | |
94b968b5 | 203 | const struct fsl_dspi_devtype_data *devtype_data; |
349ad66c | 204 | |
88386e85 CF |
205 | wait_queue_head_t waitq; |
206 | u32 waitflags; | |
c042af95 | 207 | |
90ba3703 | 208 | struct fsl_dspi_dma *dma; |
349ad66c CF |
209 | }; |
210 | ||
8fcd151d | 211 | static u32 dspi_pop_tx(struct fsl_dspi *dspi) |
dadcf4ab | 212 | { |
8fcd151d | 213 | u32 txdata = 0; |
dadcf4ab EH |
214 | |
215 | if (dspi->tx) { | |
216 | if (dspi->bytes_per_word == 1) | |
217 | txdata = *(u8 *)dspi->tx; | |
8fcd151d | 218 | else if (dspi->bytes_per_word == 2) |
dadcf4ab | 219 | txdata = *(u16 *)dspi->tx; |
8fcd151d EH |
220 | else /* dspi->bytes_per_word == 4 */ |
221 | txdata = *(u32 *)dspi->tx; | |
dadcf4ab EH |
222 | dspi->tx += dspi->bytes_per_word; |
223 | } | |
224 | dspi->len -= dspi->bytes_per_word; | |
225 | return txdata; | |
226 | } | |
ccf7d8ee | 227 | |
dadcf4ab | 228 | static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi) |
349ad66c | 229 | { |
dadcf4ab | 230 | u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi); |
349ad66c | 231 | |
dadcf4ab EH |
232 | if (dspi->len > 0) |
233 | cmd |= SPI_PUSHR_CMD_CONT; | |
234 | return cmd << 16 | data; | |
235 | } | |
236 | ||
237 | static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata) | |
238 | { | |
239 | if (!dspi->rx) | |
240 | return; | |
241 | ||
242 | /* Mask of undefined bits */ | |
243 | rxdata &= (1 << dspi->bits_per_word) - 1; | |
349ad66c | 244 | |
dadcf4ab EH |
245 | if (dspi->bytes_per_word == 1) |
246 | *(u8 *)dspi->rx = rxdata; | |
8fcd151d | 247 | else if (dspi->bytes_per_word == 2) |
dadcf4ab | 248 | *(u16 *)dspi->rx = rxdata; |
8fcd151d EH |
249 | else /* dspi->bytes_per_word == 4 */ |
250 | *(u32 *)dspi->rx = rxdata; | |
dadcf4ab | 251 | dspi->rx += dspi->bytes_per_word; |
349ad66c CF |
252 | } |
253 | ||
90ba3703 SM |
254 | static void dspi_tx_dma_callback(void *arg) |
255 | { | |
256 | struct fsl_dspi *dspi = arg; | |
257 | struct fsl_dspi_dma *dma = dspi->dma; | |
258 | ||
259 | complete(&dma->cmd_tx_complete); | |
260 | } | |
261 | ||
262 | static void dspi_rx_dma_callback(void *arg) | |
263 | { | |
264 | struct fsl_dspi *dspi = arg; | |
265 | struct fsl_dspi_dma *dma = dspi->dma; | |
1eaccf21 | 266 | int i; |
90ba3703 | 267 | |
4779f23d | 268 | if (dspi->rx) { |
dadcf4ab EH |
269 | for (i = 0; i < dma->curr_xfer_len; i++) |
270 | dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]); | |
90ba3703 SM |
271 | } |
272 | ||
273 | complete(&dma->cmd_rx_complete); | |
274 | } | |
275 | ||
276 | static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi) | |
277 | { | |
278 | struct fsl_dspi_dma *dma = dspi->dma; | |
279 | struct device *dev = &dspi->pdev->dev; | |
280 | int time_left; | |
1eaccf21 | 281 | int i; |
90ba3703 | 282 | |
dadcf4ab EH |
283 | for (i = 0; i < dma->curr_xfer_len; i++) |
284 | dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi); | |
90ba3703 | 285 | |
90ba3703 SM |
286 | dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx, |
287 | dma->tx_dma_phys, | |
1eaccf21 SM |
288 | dma->curr_xfer_len * |
289 | DMA_SLAVE_BUSWIDTH_4_BYTES, | |
290 | DMA_MEM_TO_DEV, | |
90ba3703 SM |
291 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
292 | if (!dma->tx_desc) { | |
293 | dev_err(dev, "Not able to get desc for DMA xfer\n"); | |
294 | return -EIO; | |
295 | } | |
296 | ||
297 | dma->tx_desc->callback = dspi_tx_dma_callback; | |
298 | dma->tx_desc->callback_param = dspi; | |
299 | if (dma_submit_error(dmaengine_submit(dma->tx_desc))) { | |
300 | dev_err(dev, "DMA submit failed\n"); | |
301 | return -EINVAL; | |
302 | } | |
303 | ||
304 | dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx, | |
305 | dma->rx_dma_phys, | |
1eaccf21 SM |
306 | dma->curr_xfer_len * |
307 | DMA_SLAVE_BUSWIDTH_4_BYTES, | |
308 | DMA_DEV_TO_MEM, | |
90ba3703 SM |
309 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
310 | if (!dma->rx_desc) { | |
311 | dev_err(dev, "Not able to get desc for DMA xfer\n"); | |
312 | return -EIO; | |
313 | } | |
314 | ||
315 | dma->rx_desc->callback = dspi_rx_dma_callback; | |
316 | dma->rx_desc->callback_param = dspi; | |
317 | if (dma_submit_error(dmaengine_submit(dma->rx_desc))) { | |
318 | dev_err(dev, "DMA submit failed\n"); | |
319 | return -EINVAL; | |
320 | } | |
321 | ||
322 | reinit_completion(&dspi->dma->cmd_rx_complete); | |
323 | reinit_completion(&dspi->dma->cmd_tx_complete); | |
324 | ||
325 | dma_async_issue_pending(dma->chan_rx); | |
326 | dma_async_issue_pending(dma->chan_tx); | |
327 | ||
328 | time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete, | |
329 | DMA_COMPLETION_TIMEOUT); | |
330 | if (time_left == 0) { | |
331 | dev_err(dev, "DMA tx timeout\n"); | |
332 | dmaengine_terminate_all(dma->chan_tx); | |
333 | dmaengine_terminate_all(dma->chan_rx); | |
334 | return -ETIMEDOUT; | |
335 | } | |
336 | ||
337 | time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete, | |
338 | DMA_COMPLETION_TIMEOUT); | |
339 | if (time_left == 0) { | |
340 | dev_err(dev, "DMA rx timeout\n"); | |
341 | dmaengine_terminate_all(dma->chan_tx); | |
342 | dmaengine_terminate_all(dma->chan_rx); | |
343 | return -ETIMEDOUT; | |
344 | } | |
345 | ||
346 | return 0; | |
347 | } | |
348 | ||
349 | static int dspi_dma_xfer(struct fsl_dspi *dspi) | |
350 | { | |
351 | struct fsl_dspi_dma *dma = dspi->dma; | |
352 | struct device *dev = &dspi->pdev->dev; | |
5f8f8035 | 353 | struct spi_message *message = dspi->cur_msg; |
90ba3703 SM |
354 | int curr_remaining_bytes; |
355 | int bytes_per_buffer; | |
90ba3703 SM |
356 | int ret = 0; |
357 | ||
90ba3703 | 358 | curr_remaining_bytes = dspi->len; |
1eaccf21 | 359 | bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE; |
90ba3703 SM |
360 | while (curr_remaining_bytes) { |
361 | /* Check if current transfer fits the DMA buffer */ | |
dadcf4ab EH |
362 | dma->curr_xfer_len = curr_remaining_bytes |
363 | / dspi->bytes_per_word; | |
1eaccf21 | 364 | if (dma->curr_xfer_len > bytes_per_buffer) |
90ba3703 SM |
365 | dma->curr_xfer_len = bytes_per_buffer; |
366 | ||
367 | ret = dspi_next_xfer_dma_submit(dspi); | |
368 | if (ret) { | |
369 | dev_err(dev, "DMA transfer failed\n"); | |
370 | goto exit; | |
371 | ||
372 | } else { | |
5f8f8035 AS |
373 | const int len = |
374 | dma->curr_xfer_len * dspi->bytes_per_word; | |
375 | curr_remaining_bytes -= len; | |
376 | message->actual_length += len; | |
90ba3703 SM |
377 | if (curr_remaining_bytes < 0) |
378 | curr_remaining_bytes = 0; | |
90ba3703 SM |
379 | } |
380 | } | |
381 | ||
382 | exit: | |
383 | return ret; | |
384 | } | |
385 | ||
386 | static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) | |
387 | { | |
388 | struct fsl_dspi_dma *dma; | |
389 | struct dma_slave_config cfg; | |
390 | struct device *dev = &dspi->pdev->dev; | |
391 | int ret; | |
392 | ||
393 | dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); | |
394 | if (!dma) | |
395 | return -ENOMEM; | |
396 | ||
397 | dma->chan_rx = dma_request_slave_channel(dev, "rx"); | |
398 | if (!dma->chan_rx) { | |
399 | dev_err(dev, "rx dma channel not available\n"); | |
400 | ret = -ENODEV; | |
401 | return ret; | |
402 | } | |
403 | ||
404 | dma->chan_tx = dma_request_slave_channel(dev, "tx"); | |
405 | if (!dma->chan_tx) { | |
406 | dev_err(dev, "tx dma channel not available\n"); | |
407 | ret = -ENODEV; | |
408 | goto err_tx_channel; | |
409 | } | |
410 | ||
411 | dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE, | |
412 | &dma->tx_dma_phys, GFP_KERNEL); | |
413 | if (!dma->tx_dma_buf) { | |
414 | ret = -ENOMEM; | |
415 | goto err_tx_dma_buf; | |
416 | } | |
417 | ||
418 | dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE, | |
419 | &dma->rx_dma_phys, GFP_KERNEL); | |
420 | if (!dma->rx_dma_buf) { | |
421 | ret = -ENOMEM; | |
422 | goto err_rx_dma_buf; | |
423 | } | |
424 | ||
425 | cfg.src_addr = phy_addr + SPI_POPR; | |
426 | cfg.dst_addr = phy_addr + SPI_PUSHR; | |
427 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
428 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
429 | cfg.src_maxburst = 1; | |
430 | cfg.dst_maxburst = 1; | |
431 | ||
432 | cfg.direction = DMA_DEV_TO_MEM; | |
433 | ret = dmaengine_slave_config(dma->chan_rx, &cfg); | |
434 | if (ret) { | |
435 | dev_err(dev, "can't configure rx dma channel\n"); | |
436 | ret = -EINVAL; | |
437 | goto err_slave_config; | |
438 | } | |
439 | ||
440 | cfg.direction = DMA_MEM_TO_DEV; | |
441 | ret = dmaengine_slave_config(dma->chan_tx, &cfg); | |
442 | if (ret) { | |
443 | dev_err(dev, "can't configure tx dma channel\n"); | |
444 | ret = -EINVAL; | |
445 | goto err_slave_config; | |
446 | } | |
447 | ||
448 | dspi->dma = dma; | |
449 | init_completion(&dma->cmd_tx_complete); | |
450 | init_completion(&dma->cmd_rx_complete); | |
451 | ||
452 | return 0; | |
453 | ||
454 | err_slave_config: | |
27d21e9f SM |
455 | dma_free_coherent(dev, DSPI_DMA_BUFSIZE, |
456 | dma->rx_dma_buf, dma->rx_dma_phys); | |
90ba3703 | 457 | err_rx_dma_buf: |
27d21e9f SM |
458 | dma_free_coherent(dev, DSPI_DMA_BUFSIZE, |
459 | dma->tx_dma_buf, dma->tx_dma_phys); | |
90ba3703 SM |
460 | err_tx_dma_buf: |
461 | dma_release_channel(dma->chan_tx); | |
462 | err_tx_channel: | |
463 | dma_release_channel(dma->chan_rx); | |
464 | ||
465 | devm_kfree(dev, dma); | |
466 | dspi->dma = NULL; | |
467 | ||
468 | return ret; | |
469 | } | |
470 | ||
471 | static void dspi_release_dma(struct fsl_dspi *dspi) | |
472 | { | |
473 | struct fsl_dspi_dma *dma = dspi->dma; | |
474 | struct device *dev = &dspi->pdev->dev; | |
475 | ||
476 | if (dma) { | |
477 | if (dma->chan_tx) { | |
478 | dma_unmap_single(dev, dma->tx_dma_phys, | |
479 | DSPI_DMA_BUFSIZE, DMA_TO_DEVICE); | |
480 | dma_release_channel(dma->chan_tx); | |
481 | } | |
482 | ||
483 | if (dma->chan_rx) { | |
484 | dma_unmap_single(dev, dma->rx_dma_phys, | |
485 | DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE); | |
486 | dma_release_channel(dma->chan_rx); | |
487 | } | |
488 | } | |
489 | } | |
490 | ||
349ad66c CF |
491 | static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, |
492 | unsigned long clkrate) | |
493 | { | |
494 | /* Valid baud rate pre-scaler values */ | |
495 | int pbr_tbl[4] = {2, 3, 5, 7}; | |
496 | int brs[16] = { 2, 4, 6, 8, | |
497 | 16, 32, 64, 128, | |
498 | 256, 512, 1024, 2048, | |
499 | 4096, 8192, 16384, 32768 }; | |
6fd63087 AB |
500 | int scale_needed, scale, minscale = INT_MAX; |
501 | int i, j; | |
502 | ||
503 | scale_needed = clkrate / speed_hz; | |
e689d6df AB |
504 | if (clkrate % speed_hz) |
505 | scale_needed++; | |
6fd63087 AB |
506 | |
507 | for (i = 0; i < ARRAY_SIZE(brs); i++) | |
508 | for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) { | |
509 | scale = brs[i] * pbr_tbl[j]; | |
510 | if (scale >= scale_needed) { | |
511 | if (scale < minscale) { | |
512 | minscale = scale; | |
513 | *br = i; | |
514 | *pbr = j; | |
515 | } | |
516 | break; | |
349ad66c CF |
517 | } |
518 | } | |
349ad66c | 519 | |
6fd63087 AB |
520 | if (minscale == INT_MAX) { |
521 | pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n", | |
522 | speed_hz, clkrate); | |
523 | *pbr = ARRAY_SIZE(pbr_tbl) - 1; | |
524 | *br = ARRAY_SIZE(brs) - 1; | |
525 | } | |
349ad66c | 526 | } |
349ad66c | 527 | |
95bf15f3 AB |
528 | static void ns_delay_scale(char *psc, char *sc, int delay_ns, |
529 | unsigned long clkrate) | |
530 | { | |
531 | int pscale_tbl[4] = {1, 3, 5, 7}; | |
532 | int scale_needed, scale, minscale = INT_MAX; | |
533 | int i, j; | |
534 | u32 remainder; | |
535 | ||
536 | scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC, | |
537 | &remainder); | |
538 | if (remainder) | |
539 | scale_needed++; | |
540 | ||
541 | for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++) | |
542 | for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) { | |
543 | scale = pscale_tbl[i] * (2 << j); | |
544 | if (scale >= scale_needed) { | |
545 | if (scale < minscale) { | |
546 | minscale = scale; | |
547 | *psc = i; | |
548 | *sc = j; | |
549 | } | |
550 | break; | |
349ad66c CF |
551 | } |
552 | } | |
553 | ||
95bf15f3 AB |
554 | if (minscale == INT_MAX) { |
555 | pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value", | |
556 | delay_ns, clkrate); | |
557 | *psc = ARRAY_SIZE(pscale_tbl) - 1; | |
558 | *sc = SPI_CTAR_SCALE_BITS; | |
559 | } | |
349ad66c CF |
560 | } |
561 | ||
dadcf4ab | 562 | static void fifo_write(struct fsl_dspi *dspi) |
349ad66c | 563 | { |
dadcf4ab | 564 | regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi)); |
d1f4a38c | 565 | } |
349ad66c | 566 | |
8fcd151d EH |
567 | static void cmd_fifo_write(struct fsl_dspi *dspi) |
568 | { | |
569 | u16 cmd = dspi->tx_cmd; | |
570 | ||
571 | if (dspi->len > 0) | |
572 | cmd |= SPI_PUSHR_CMD_CONT; | |
573 | regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd); | |
574 | } | |
575 | ||
576 | static void tx_fifo_write(struct fsl_dspi *dspi, u16 txdata) | |
577 | { | |
578 | regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata); | |
579 | } | |
580 | ||
dadcf4ab | 581 | static void dspi_tcfq_write(struct fsl_dspi *dspi) |
d1f4a38c | 582 | { |
dadcf4ab EH |
583 | /* Clear transfer count */ |
584 | dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT; | |
8fcd151d EH |
585 | |
586 | if (dspi->devtype_data->xspi_mode && dspi->bits_per_word > 16) { | |
587 | /* Write two TX FIFO entries first, and then the corresponding | |
588 | * CMD FIFO entry. | |
589 | */ | |
590 | u32 data = dspi_pop_tx(dspi); | |
591 | ||
592 | if (dspi->cur_chip->ctar_val & SPI_CTAR_LSBFE(1)) { | |
593 | /* LSB */ | |
594 | tx_fifo_write(dspi, data & 0xFFFF); | |
595 | tx_fifo_write(dspi, data >> 16); | |
596 | } else { | |
597 | /* MSB */ | |
598 | tx_fifo_write(dspi, data >> 16); | |
599 | tx_fifo_write(dspi, data & 0xFFFF); | |
600 | } | |
601 | cmd_fifo_write(dspi); | |
602 | } else { | |
603 | /* Write one entry to both TX FIFO and CMD FIFO | |
604 | * simultaneously. | |
605 | */ | |
606 | fifo_write(dspi); | |
607 | } | |
d1f4a38c | 608 | } |
349ad66c | 609 | |
dadcf4ab | 610 | static u32 fifo_read(struct fsl_dspi *dspi) |
d1f4a38c | 611 | { |
dadcf4ab | 612 | u32 rxdata = 0; |
d1f4a38c | 613 | |
dadcf4ab EH |
614 | regmap_read(dspi->regmap, SPI_POPR, &rxdata); |
615 | return rxdata; | |
349ad66c CF |
616 | } |
617 | ||
dadcf4ab | 618 | static void dspi_tcfq_read(struct fsl_dspi *dspi) |
349ad66c | 619 | { |
dadcf4ab | 620 | dspi_push_rx(dspi, fifo_read(dspi)); |
d1f4a38c | 621 | } |
349ad66c | 622 | |
dadcf4ab | 623 | static void dspi_eoq_write(struct fsl_dspi *dspi) |
d1f4a38c | 624 | { |
dadcf4ab EH |
625 | int fifo_size = DSPI_FIFO_SIZE; |
626 | ||
627 | /* Fill TX FIFO with as many transfers as possible */ | |
628 | while (dspi->len && fifo_size--) { | |
629 | /* Request EOQF for last transfer in FIFO */ | |
630 | if (dspi->len == dspi->bytes_per_word || fifo_size == 0) | |
631 | dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ; | |
632 | /* Clear transfer count for first transfer in FIFO */ | |
633 | if (fifo_size == (DSPI_FIFO_SIZE - 1)) | |
634 | dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT; | |
635 | /* Write combined TX FIFO and CMD FIFO entry */ | |
636 | fifo_write(dspi); | |
349ad66c | 637 | } |
d1f4a38c HW |
638 | } |
639 | ||
dadcf4ab | 640 | static void dspi_eoq_read(struct fsl_dspi *dspi) |
d1f4a38c | 641 | { |
dadcf4ab | 642 | int fifo_size = DSPI_FIFO_SIZE; |
d1f4a38c | 643 | |
dadcf4ab EH |
644 | /* Read one FIFO entry at and push to rx buffer */ |
645 | while ((dspi->rx < dspi->rx_end) && fifo_size--) | |
646 | dspi_push_rx(dspi, fifo_read(dspi)); | |
349ad66c CF |
647 | } |
648 | ||
9298bc72 CF |
649 | static int dspi_transfer_one_message(struct spi_master *master, |
650 | struct spi_message *message) | |
349ad66c | 651 | { |
9298bc72 CF |
652 | struct fsl_dspi *dspi = spi_master_get_devdata(master); |
653 | struct spi_device *spi = message->spi; | |
654 | struct spi_transfer *transfer; | |
655 | int status = 0; | |
d1f4a38c HW |
656 | enum dspi_trans_mode trans_mode; |
657 | ||
9298bc72 CF |
658 | message->actual_length = 0; |
659 | ||
660 | list_for_each_entry(transfer, &message->transfers, transfer_list) { | |
661 | dspi->cur_transfer = transfer; | |
662 | dspi->cur_msg = message; | |
663 | dspi->cur_chip = spi_get_ctldata(spi); | |
9e1dc9bd EH |
664 | /* Prepare command word for CMD FIFO */ |
665 | dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) | | |
666 | SPI_PUSHR_CMD_PCS(spi->chip_select); | |
92dc20d8 | 667 | if (list_is_last(&dspi->cur_transfer->transfer_list, |
9e1dc9bd EH |
668 | &dspi->cur_msg->transfers)) { |
669 | /* Leave PCS activated after last transfer when | |
670 | * cs_change is set. | |
671 | */ | |
672 | if (transfer->cs_change) | |
673 | dspi->tx_cmd |= SPI_PUSHR_CMD_CONT; | |
674 | } else { | |
675 | /* Keep PCS active between transfers in same message | |
676 | * when cs_change is not set, and de-activate PCS | |
677 | * between transfers in the same message when | |
678 | * cs_change is set. | |
679 | */ | |
680 | if (!transfer->cs_change) | |
681 | dspi->tx_cmd |= SPI_PUSHR_CMD_CONT; | |
682 | } | |
683 | ||
9298bc72 CF |
684 | dspi->void_write_data = dspi->cur_chip->void_write_data; |
685 | ||
dadcf4ab | 686 | dspi->tx = transfer->tx_buf; |
9298bc72 CF |
687 | dspi->rx = transfer->rx_buf; |
688 | dspi->rx_end = dspi->rx + transfer->len; | |
689 | dspi->len = transfer->len; | |
dadcf4ab EH |
690 | /* Validated transfer specific frame size (defaults applied) */ |
691 | dspi->bits_per_word = transfer->bits_per_word; | |
692 | if (transfer->bits_per_word <= 8) | |
693 | dspi->bytes_per_word = 1; | |
8fcd151d | 694 | else if (transfer->bits_per_word <= 16) |
dadcf4ab | 695 | dspi->bytes_per_word = 2; |
8fcd151d EH |
696 | else |
697 | dspi->bytes_per_word = 4; | |
9298bc72 | 698 | |
9298bc72 | 699 | regmap_update_bits(dspi->regmap, SPI_MCR, |
d87e08f1 EH |
700 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, |
701 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); | |
ef22d160 | 702 | regmap_write(dspi->regmap, SPI_CTAR(0), |
dadcf4ab EH |
703 | dspi->cur_chip->ctar_val | |
704 | SPI_FRAME_BITS(transfer->bits_per_word)); | |
51d583ae EH |
705 | if (dspi->devtype_data->xspi_mode) |
706 | regmap_write(dspi->regmap, SPI_CTARE(0), | |
707 | SPI_FRAME_EBITS(transfer->bits_per_word) | |
708 | | SPI_CTARE_DTCP(1)); | |
349ad66c | 709 | |
d1f4a38c HW |
710 | trans_mode = dspi->devtype_data->trans_mode; |
711 | switch (trans_mode) { | |
712 | case DSPI_EOQ_MODE: | |
713 | regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); | |
c042af95 | 714 | dspi_eoq_write(dspi); |
d1f4a38c HW |
715 | break; |
716 | case DSPI_TCFQ_MODE: | |
717 | regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE); | |
c042af95 | 718 | dspi_tcfq_write(dspi); |
d1f4a38c | 719 | break; |
90ba3703 SM |
720 | case DSPI_DMA_MODE: |
721 | regmap_write(dspi->regmap, SPI_RSER, | |
722 | SPI_RSER_TFFFE | SPI_RSER_TFFFD | | |
723 | SPI_RSER_RFDFE | SPI_RSER_RFDFD); | |
724 | status = dspi_dma_xfer(dspi); | |
98114304 | 725 | break; |
d1f4a38c HW |
726 | default: |
727 | dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", | |
728 | trans_mode); | |
729 | status = -EINVAL; | |
730 | goto out; | |
731 | } | |
1acbdeb9 | 732 | |
98114304 SM |
733 | if (trans_mode != DSPI_DMA_MODE) { |
734 | if (wait_event_interruptible(dspi->waitq, | |
735 | dspi->waitflags)) | |
736 | dev_err(&dspi->pdev->dev, | |
737 | "wait transfer complete fail!\n"); | |
738 | dspi->waitflags = 0; | |
739 | } | |
349ad66c | 740 | |
9298bc72 CF |
741 | if (transfer->delay_usecs) |
742 | udelay(transfer->delay_usecs); | |
349ad66c CF |
743 | } |
744 | ||
d1f4a38c | 745 | out: |
9298bc72 CF |
746 | message->status = status; |
747 | spi_finalize_current_message(master); | |
748 | ||
749 | return status; | |
349ad66c CF |
750 | } |
751 | ||
9298bc72 | 752 | static int dspi_setup(struct spi_device *spi) |
349ad66c CF |
753 | { |
754 | struct chip_data *chip; | |
755 | struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); | |
ec7ed770 | 756 | struct fsl_dspi_platform_data *pdata; |
95bf15f3 AB |
757 | u32 cs_sck_delay = 0, sck_cs_delay = 0; |
758 | unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0; | |
dadcf4ab | 759 | unsigned char pasc = 0, asc = 0; |
95bf15f3 | 760 | unsigned long clkrate; |
349ad66c CF |
761 | |
762 | /* Only alloc on first setup */ | |
763 | chip = spi_get_ctldata(spi); | |
764 | if (chip == NULL) { | |
973fbce6 | 765 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
349ad66c CF |
766 | if (!chip) |
767 | return -ENOMEM; | |
768 | } | |
769 | ||
ec7ed770 | 770 | pdata = dev_get_platdata(&dspi->pdev->dev); |
95bf15f3 | 771 | |
ec7ed770 AD |
772 | if (!pdata) { |
773 | of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay", | |
774 | &cs_sck_delay); | |
775 | ||
776 | of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay", | |
777 | &sck_cs_delay); | |
778 | } else { | |
779 | cs_sck_delay = pdata->cs_sck_delay; | |
780 | sck_cs_delay = pdata->sck_cs_delay; | |
781 | } | |
95bf15f3 | 782 | |
349ad66c CF |
783 | chip->void_write_data = 0; |
784 | ||
95bf15f3 AB |
785 | clkrate = clk_get_rate(dspi->clk); |
786 | hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate); | |
787 | ||
788 | /* Set PCS to SCK delay scale values */ | |
789 | ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate); | |
790 | ||
791 | /* Set After SCK delay scale values */ | |
792 | ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate); | |
349ad66c | 793 | |
dadcf4ab | 794 | chip->ctar_val = SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0) |
349ad66c CF |
795 | | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0) |
796 | | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0) | |
95bf15f3 AB |
797 | | SPI_CTAR_PCSSCK(pcssck) |
798 | | SPI_CTAR_CSSCK(cssck) | |
799 | | SPI_CTAR_PASC(pasc) | |
800 | | SPI_CTAR_ASC(asc) | |
349ad66c CF |
801 | | SPI_CTAR_PBR(pbr) |
802 | | SPI_CTAR_BR(br); | |
803 | ||
804 | spi_set_ctldata(spi, chip); | |
805 | ||
806 | return 0; | |
807 | } | |
808 | ||
973fbce6 BD |
809 | static void dspi_cleanup(struct spi_device *spi) |
810 | { | |
811 | struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi); | |
812 | ||
813 | dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n", | |
814 | spi->master->bus_num, spi->chip_select); | |
815 | ||
816 | kfree(chip); | |
817 | } | |
818 | ||
349ad66c CF |
819 | static irqreturn_t dspi_interrupt(int irq, void *dev_id) |
820 | { | |
821 | struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; | |
9298bc72 | 822 | struct spi_message *msg = dspi->cur_msg; |
d1f4a38c | 823 | enum dspi_trans_mode trans_mode; |
c042af95 | 824 | u32 spi_sr, spi_tcr; |
0a4ec2c1 | 825 | u16 spi_tcnt; |
d1f4a38c HW |
826 | |
827 | regmap_read(dspi->regmap, SPI_SR, &spi_sr); | |
828 | regmap_write(dspi->regmap, SPI_SR, spi_sr); | |
829 | ||
349ad66c | 830 | |
c042af95 | 831 | if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) { |
0a4ec2c1 EH |
832 | /* Get transfer counter (in number of SPI transfers). It was |
833 | * reset to 0 when transfer(s) were started. | |
834 | */ | |
c042af95 HW |
835 | regmap_read(dspi->regmap, SPI_TCR, &spi_tcr); |
836 | spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr); | |
0a4ec2c1 | 837 | /* Update total number of bytes that were transferred */ |
dadcf4ab | 838 | msg->actual_length += spi_tcnt * dspi->bytes_per_word; |
c042af95 HW |
839 | |
840 | trans_mode = dspi->devtype_data->trans_mode; | |
d1f4a38c HW |
841 | switch (trans_mode) { |
842 | case DSPI_EOQ_MODE: | |
c042af95 | 843 | dspi_eoq_read(dspi); |
d1f4a38c HW |
844 | break; |
845 | case DSPI_TCFQ_MODE: | |
c042af95 | 846 | dspi_tcfq_read(dspi); |
d1f4a38c HW |
847 | break; |
848 | default: | |
849 | dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", | |
850 | trans_mode); | |
c042af95 HW |
851 | return IRQ_HANDLED; |
852 | } | |
853 | ||
854 | if (!dspi->len) { | |
c042af95 HW |
855 | dspi->waitflags = 1; |
856 | wake_up_interruptible(&dspi->waitq); | |
857 | } else { | |
858 | switch (trans_mode) { | |
859 | case DSPI_EOQ_MODE: | |
860 | dspi_eoq_write(dspi); | |
861 | break; | |
862 | case DSPI_TCFQ_MODE: | |
863 | dspi_tcfq_write(dspi); | |
864 | break; | |
865 | default: | |
866 | dev_err(&dspi->pdev->dev, | |
867 | "unsupported trans_mode %u\n", | |
868 | trans_mode); | |
869 | } | |
d1f4a38c HW |
870 | } |
871 | } | |
c042af95 | 872 | |
349ad66c CF |
873 | return IRQ_HANDLED; |
874 | } | |
875 | ||
790d1902 | 876 | static const struct of_device_id fsl_dspi_dt_ids[] = { |
230c08b2 JL |
877 | { .compatible = "fsl,vf610-dspi", .data = &vf610_data, }, |
878 | { .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, }, | |
879 | { .compatible = "fsl,ls2085a-dspi", .data = &ls2085a_data, }, | |
349ad66c CF |
880 | { /* sentinel */ } |
881 | }; | |
882 | MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); | |
883 | ||
884 | #ifdef CONFIG_PM_SLEEP | |
885 | static int dspi_suspend(struct device *dev) | |
886 | { | |
887 | struct spi_master *master = dev_get_drvdata(dev); | |
888 | struct fsl_dspi *dspi = spi_master_get_devdata(master); | |
889 | ||
890 | spi_master_suspend(master); | |
891 | clk_disable_unprepare(dspi->clk); | |
892 | ||
432a17d7 MK |
893 | pinctrl_pm_select_sleep_state(dev); |
894 | ||
349ad66c CF |
895 | return 0; |
896 | } | |
897 | ||
898 | static int dspi_resume(struct device *dev) | |
899 | { | |
349ad66c CF |
900 | struct spi_master *master = dev_get_drvdata(dev); |
901 | struct fsl_dspi *dspi = spi_master_get_devdata(master); | |
1c5ea2b4 | 902 | int ret; |
349ad66c | 903 | |
432a17d7 MK |
904 | pinctrl_pm_select_default_state(dev); |
905 | ||
1c5ea2b4 FE |
906 | ret = clk_prepare_enable(dspi->clk); |
907 | if (ret) | |
908 | return ret; | |
349ad66c CF |
909 | spi_master_resume(master); |
910 | ||
911 | return 0; | |
912 | } | |
913 | #endif /* CONFIG_PM_SLEEP */ | |
914 | ||
ba811add | 915 | static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume); |
349ad66c | 916 | |
8570043e EH |
917 | static const struct regmap_range dspi_volatile_ranges[] = { |
918 | regmap_reg_range(SPI_MCR, SPI_TCR), | |
919 | regmap_reg_range(SPI_SR, SPI_SR), | |
920 | regmap_reg_range(SPI_PUSHR, SPI_RXFR3), | |
921 | }; | |
922 | ||
923 | static const struct regmap_access_table dspi_volatile_table = { | |
924 | .yes_ranges = dspi_volatile_ranges, | |
925 | .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges), | |
926 | }; | |
927 | ||
409851c3 | 928 | static const struct regmap_config dspi_regmap_config = { |
1acbdeb9 CF |
929 | .reg_bits = 32, |
930 | .val_bits = 32, | |
931 | .reg_stride = 4, | |
932 | .max_register = 0x88, | |
8570043e | 933 | .volatile_table = &dspi_volatile_table, |
349ad66c CF |
934 | }; |
935 | ||
58ba07ec EH |
936 | static const struct regmap_range dspi_xspi_volatile_ranges[] = { |
937 | regmap_reg_range(SPI_MCR, SPI_TCR), | |
938 | regmap_reg_range(SPI_SR, SPI_SR), | |
939 | regmap_reg_range(SPI_PUSHR, SPI_RXFR3), | |
940 | regmap_reg_range(SPI_SREX, SPI_SREX), | |
941 | }; | |
942 | ||
943 | static const struct regmap_access_table dspi_xspi_volatile_table = { | |
944 | .yes_ranges = dspi_xspi_volatile_ranges, | |
945 | .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges), | |
946 | }; | |
947 | ||
948 | static const struct regmap_config dspi_xspi_regmap_config[] = { | |
949 | { | |
950 | .reg_bits = 32, | |
951 | .val_bits = 32, | |
952 | .reg_stride = 4, | |
953 | .max_register = 0x13c, | |
954 | .volatile_table = &dspi_xspi_volatile_table, | |
955 | }, | |
956 | { | |
957 | .name = "pushr", | |
958 | .reg_bits = 16, | |
959 | .val_bits = 16, | |
960 | .reg_stride = 2, | |
961 | .max_register = 0x2, | |
962 | }, | |
963 | }; | |
964 | ||
5ee67b58 YY |
965 | static void dspi_init(struct fsl_dspi *dspi) |
966 | { | |
3e7cc625 EH |
967 | regmap_write(dspi->regmap, SPI_MCR, SPI_MCR_MASTER | SPI_MCR_PCSIS | |
968 | (dspi->devtype_data->xspi_mode ? SPI_MCR_XSPI : 0)); | |
5ee67b58 | 969 | regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); |
51d583ae EH |
970 | if (dspi->devtype_data->xspi_mode) |
971 | regmap_write(dspi->regmap, SPI_CTARE(0), | |
972 | SPI_CTARE_FMSZE(0) | SPI_CTARE_DTCP(1)); | |
5ee67b58 YY |
973 | } |
974 | ||
349ad66c CF |
975 | static int dspi_probe(struct platform_device *pdev) |
976 | { | |
977 | struct device_node *np = pdev->dev.of_node; | |
978 | struct spi_master *master; | |
979 | struct fsl_dspi *dspi; | |
980 | struct resource *res; | |
58ba07ec | 981 | const struct regmap_config *regmap_config; |
1acbdeb9 | 982 | void __iomem *base; |
ec7ed770 | 983 | struct fsl_dspi_platform_data *pdata; |
349ad66c CF |
984 | int ret = 0, cs_num, bus_num; |
985 | ||
986 | master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); | |
987 | if (!master) | |
988 | return -ENOMEM; | |
989 | ||
990 | dspi = spi_master_get_devdata(master); | |
991 | dspi->pdev = pdev; | |
9298bc72 CF |
992 | dspi->master = master; |
993 | ||
994 | master->transfer = NULL; | |
995 | master->setup = dspi_setup; | |
996 | master->transfer_one_message = dspi_transfer_one_message; | |
997 | master->dev.of_node = pdev->dev.of_node; | |
349ad66c | 998 | |
973fbce6 | 999 | master->cleanup = dspi_cleanup; |
00ac9562 | 1000 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; |
349ad66c | 1001 | |
ec7ed770 AD |
1002 | pdata = dev_get_platdata(&pdev->dev); |
1003 | if (pdata) { | |
1004 | master->num_chipselect = pdata->cs_num; | |
1005 | master->bus_num = pdata->bus_num; | |
349ad66c | 1006 | |
ec7ed770 AD |
1007 | dspi->devtype_data = &coldfire_data; |
1008 | } else { | |
349ad66c | 1009 | |
ec7ed770 AD |
1010 | ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); |
1011 | if (ret < 0) { | |
1012 | dev_err(&pdev->dev, "can't get spi-num-chipselects\n"); | |
1013 | goto out_master_put; | |
1014 | } | |
1015 | master->num_chipselect = cs_num; | |
1016 | ||
1017 | ret = of_property_read_u32(np, "bus-num", &bus_num); | |
1018 | if (ret < 0) { | |
1019 | dev_err(&pdev->dev, "can't get bus-num\n"); | |
1020 | goto out_master_put; | |
1021 | } | |
1022 | master->bus_num = bus_num; | |
1023 | ||
1024 | dspi->devtype_data = of_device_get_match_data(&pdev->dev); | |
1025 | if (!dspi->devtype_data) { | |
1026 | dev_err(&pdev->dev, "can't get devtype_data\n"); | |
1027 | ret = -EFAULT; | |
1028 | goto out_master_put; | |
1029 | } | |
d1f4a38c HW |
1030 | } |
1031 | ||
35c9d461 EH |
1032 | if (dspi->devtype_data->xspi_mode) |
1033 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); | |
1034 | else | |
1035 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); | |
1036 | ||
349ad66c | 1037 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1acbdeb9 CF |
1038 | base = devm_ioremap_resource(&pdev->dev, res); |
1039 | if (IS_ERR(base)) { | |
1040 | ret = PTR_ERR(base); | |
349ad66c CF |
1041 | goto out_master_put; |
1042 | } | |
1043 | ||
58ba07ec EH |
1044 | if (dspi->devtype_data->xspi_mode) |
1045 | regmap_config = &dspi_xspi_regmap_config[0]; | |
1046 | else | |
1047 | regmap_config = &dspi_regmap_config; | |
1048 | dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config); | |
1acbdeb9 CF |
1049 | if (IS_ERR(dspi->regmap)) { |
1050 | dev_err(&pdev->dev, "failed to init regmap: %ld\n", | |
1051 | PTR_ERR(dspi->regmap)); | |
fbad6c24 CJ |
1052 | ret = PTR_ERR(dspi->regmap); |
1053 | goto out_master_put; | |
1acbdeb9 CF |
1054 | } |
1055 | ||
58ba07ec EH |
1056 | if (dspi->devtype_data->xspi_mode) { |
1057 | dspi->regmap_pushr = devm_regmap_init_mmio( | |
1058 | &pdev->dev, base + SPI_PUSHR, | |
1059 | &dspi_xspi_regmap_config[1]); | |
1060 | if (IS_ERR(dspi->regmap_pushr)) { | |
1061 | dev_err(&pdev->dev, | |
1062 | "failed to init pushr regmap: %ld\n", | |
1063 | PTR_ERR(dspi->regmap_pushr)); | |
80dc12cd | 1064 | ret = PTR_ERR(dspi->regmap_pushr); |
58ba07ec EH |
1065 | goto out_master_put; |
1066 | } | |
1067 | } | |
1068 | ||
d8ffee2f KK |
1069 | dspi->clk = devm_clk_get(&pdev->dev, "dspi"); |
1070 | if (IS_ERR(dspi->clk)) { | |
1071 | ret = PTR_ERR(dspi->clk); | |
1072 | dev_err(&pdev->dev, "unable to get clock\n"); | |
1073 | goto out_master_put; | |
1074 | } | |
1075 | ret = clk_prepare_enable(dspi->clk); | |
1076 | if (ret) | |
1077 | goto out_master_put; | |
1078 | ||
5ee67b58 | 1079 | dspi_init(dspi); |
349ad66c CF |
1080 | dspi->irq = platform_get_irq(pdev, 0); |
1081 | if (dspi->irq < 0) { | |
1082 | dev_err(&pdev->dev, "can't get platform irq\n"); | |
1083 | ret = dspi->irq; | |
d8ffee2f | 1084 | goto out_clk_put; |
349ad66c CF |
1085 | } |
1086 | ||
1087 | ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0, | |
1088 | pdev->name, dspi); | |
1089 | if (ret < 0) { | |
1090 | dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n"); | |
d8ffee2f | 1091 | goto out_clk_put; |
349ad66c CF |
1092 | } |
1093 | ||
90ba3703 | 1094 | if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) { |
cddebdd1 NY |
1095 | ret = dspi_request_dma(dspi, res->start); |
1096 | if (ret < 0) { | |
90ba3703 SM |
1097 | dev_err(&pdev->dev, "can't get dma channels\n"); |
1098 | goto out_clk_put; | |
1099 | } | |
1100 | } | |
1101 | ||
9419b200 BD |
1102 | master->max_speed_hz = |
1103 | clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor; | |
1104 | ||
349ad66c | 1105 | init_waitqueue_head(&dspi->waitq); |
017145fe | 1106 | platform_set_drvdata(pdev, master); |
349ad66c | 1107 | |
9298bc72 | 1108 | ret = spi_register_master(master); |
349ad66c CF |
1109 | if (ret != 0) { |
1110 | dev_err(&pdev->dev, "Problem registering DSPI master\n"); | |
1111 | goto out_clk_put; | |
1112 | } | |
1113 | ||
349ad66c CF |
1114 | return ret; |
1115 | ||
1116 | out_clk_put: | |
1117 | clk_disable_unprepare(dspi->clk); | |
1118 | out_master_put: | |
1119 | spi_master_put(master); | |
349ad66c CF |
1120 | |
1121 | return ret; | |
1122 | } | |
1123 | ||
1124 | static int dspi_remove(struct platform_device *pdev) | |
1125 | { | |
017145fe AL |
1126 | struct spi_master *master = platform_get_drvdata(pdev); |
1127 | struct fsl_dspi *dspi = spi_master_get_devdata(master); | |
349ad66c CF |
1128 | |
1129 | /* Disconnect from the SPI framework */ | |
90ba3703 | 1130 | dspi_release_dma(dspi); |
05209f45 | 1131 | clk_disable_unprepare(dspi->clk); |
9298bc72 | 1132 | spi_unregister_master(dspi->master); |
349ad66c CF |
1133 | |
1134 | return 0; | |
1135 | } | |
1136 | ||
1137 | static struct platform_driver fsl_dspi_driver = { | |
1138 | .driver.name = DRIVER_NAME, | |
1139 | .driver.of_match_table = fsl_dspi_dt_ids, | |
1140 | .driver.owner = THIS_MODULE, | |
1141 | .driver.pm = &dspi_pm, | |
1142 | .probe = dspi_probe, | |
1143 | .remove = dspi_remove, | |
1144 | }; | |
1145 | module_platform_driver(fsl_dspi_driver); | |
1146 | ||
1147 | MODULE_DESCRIPTION("Freescale DSPI Controller Driver"); | |
b444d1df | 1148 | MODULE_LICENSE("GPL"); |
349ad66c | 1149 | MODULE_ALIAS("platform:" DRIVER_NAME); |