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Commit | Line | Data |
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349ad66c CF |
1 | /* |
2 | * drivers/spi/spi-fsl-dspi.c | |
3 | * | |
4 | * Copyright 2013 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * Freescale DSPI driver | |
7 | * This file contains a driver for the Freescale DSPI | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | */ | |
15 | ||
a3108360 XL |
16 | #include <linux/clk.h> |
17 | #include <linux/delay.h> | |
90ba3703 SM |
18 | #include <linux/dmaengine.h> |
19 | #include <linux/dma-mapping.h> | |
a3108360 XL |
20 | #include <linux/err.h> |
21 | #include <linux/errno.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
349ad66c | 24 | #include <linux/kernel.h> |
95bf15f3 | 25 | #include <linux/math64.h> |
349ad66c | 26 | #include <linux/module.h> |
a3108360 XL |
27 | #include <linux/of.h> |
28 | #include <linux/of_device.h> | |
432a17d7 | 29 | #include <linux/pinctrl/consumer.h> |
349ad66c | 30 | #include <linux/platform_device.h> |
a3108360 | 31 | #include <linux/pm_runtime.h> |
1acbdeb9 | 32 | #include <linux/regmap.h> |
349ad66c | 33 | #include <linux/sched.h> |
349ad66c CF |
34 | #include <linux/spi/spi.h> |
35 | #include <linux/spi/spi_bitbang.h> | |
95bf15f3 | 36 | #include <linux/time.h> |
349ad66c CF |
37 | |
38 | #define DRIVER_NAME "fsl-dspi" | |
39 | ||
40 | #define TRAN_STATE_RX_VOID 0x01 | |
41 | #define TRAN_STATE_TX_VOID 0x02 | |
42 | #define TRAN_STATE_WORD_ODD_NUM 0x04 | |
43 | ||
44 | #define DSPI_FIFO_SIZE 4 | |
90ba3703 | 45 | #define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024) |
349ad66c CF |
46 | |
47 | #define SPI_MCR 0x00 | |
48 | #define SPI_MCR_MASTER (1 << 31) | |
49 | #define SPI_MCR_PCSIS (0x3F << 16) | |
50 | #define SPI_MCR_CLR_TXF (1 << 11) | |
51 | #define SPI_MCR_CLR_RXF (1 << 10) | |
52 | ||
53 | #define SPI_TCR 0x08 | |
c042af95 | 54 | #define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16) |
349ad66c | 55 | |
5cc7b047 | 56 | #define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4)) |
349ad66c CF |
57 | #define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27) |
58 | #define SPI_CTAR_CPOL(x) ((x) << 26) | |
59 | #define SPI_CTAR_CPHA(x) ((x) << 25) | |
60 | #define SPI_CTAR_LSBFE(x) ((x) << 24) | |
95bf15f3 | 61 | #define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22) |
349ad66c CF |
62 | #define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20) |
63 | #define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18) | |
64 | #define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16) | |
65 | #define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12) | |
66 | #define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8) | |
67 | #define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4) | |
68 | #define SPI_CTAR_BR(x) ((x) & 0x0000000f) | |
95bf15f3 | 69 | #define SPI_CTAR_SCALE_BITS 0xf |
349ad66c CF |
70 | |
71 | #define SPI_CTAR0_SLAVE 0x0c | |
72 | ||
73 | #define SPI_SR 0x2c | |
74 | #define SPI_SR_EOQF 0x10000000 | |
d1f4a38c | 75 | #define SPI_SR_TCFQF 0x80000000 |
349ad66c | 76 | |
90ba3703 SM |
77 | #define SPI_RSER_TFFFE BIT(25) |
78 | #define SPI_RSER_TFFFD BIT(24) | |
79 | #define SPI_RSER_RFDFE BIT(17) | |
80 | #define SPI_RSER_RFDFD BIT(16) | |
81 | ||
349ad66c CF |
82 | #define SPI_RSER 0x30 |
83 | #define SPI_RSER_EOQFE 0x10000000 | |
d1f4a38c | 84 | #define SPI_RSER_TCFQE 0x80000000 |
349ad66c CF |
85 | |
86 | #define SPI_PUSHR 0x34 | |
87 | #define SPI_PUSHR_CONT (1 << 31) | |
5cc7b047 | 88 | #define SPI_PUSHR_CTAS(x) (((x) & 0x00000003) << 28) |
349ad66c CF |
89 | #define SPI_PUSHR_EOQ (1 << 27) |
90 | #define SPI_PUSHR_CTCNT (1 << 26) | |
91 | #define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16) | |
92 | #define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff) | |
93 | ||
94 | #define SPI_PUSHR_SLAVE 0x34 | |
95 | ||
96 | #define SPI_POPR 0x38 | |
97 | #define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff) | |
98 | ||
99 | #define SPI_TXFR0 0x3c | |
100 | #define SPI_TXFR1 0x40 | |
101 | #define SPI_TXFR2 0x44 | |
102 | #define SPI_TXFR3 0x48 | |
103 | #define SPI_RXFR0 0x7c | |
104 | #define SPI_RXFR1 0x80 | |
105 | #define SPI_RXFR2 0x84 | |
106 | #define SPI_RXFR3 0x88 | |
107 | ||
108 | #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1) | |
109 | #define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf) | |
110 | #define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf) | |
111 | #define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7) | |
112 | ||
113 | #define SPI_CS_INIT 0x01 | |
114 | #define SPI_CS_ASSERT 0x02 | |
115 | #define SPI_CS_DROP 0x04 | |
116 | ||
c042af95 HW |
117 | #define SPI_TCR_TCNT_MAX 0x10000 |
118 | ||
90ba3703 SM |
119 | #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000) |
120 | ||
349ad66c CF |
121 | struct chip_data { |
122 | u32 mcr_val; | |
123 | u32 ctar_val; | |
124 | u16 void_write_data; | |
125 | }; | |
126 | ||
d1f4a38c HW |
127 | enum dspi_trans_mode { |
128 | DSPI_EOQ_MODE = 0, | |
129 | DSPI_TCFQ_MODE, | |
90ba3703 | 130 | DSPI_DMA_MODE, |
d1f4a38c HW |
131 | }; |
132 | ||
133 | struct fsl_dspi_devtype_data { | |
134 | enum dspi_trans_mode trans_mode; | |
9419b200 | 135 | u8 max_clock_factor; |
d1f4a38c HW |
136 | }; |
137 | ||
138 | static const struct fsl_dspi_devtype_data vf610_data = { | |
90ba3703 | 139 | .trans_mode = DSPI_DMA_MODE, |
9419b200 | 140 | .max_clock_factor = 2, |
d1f4a38c HW |
141 | }; |
142 | ||
143 | static const struct fsl_dspi_devtype_data ls1021a_v1_data = { | |
144 | .trans_mode = DSPI_TCFQ_MODE, | |
9419b200 | 145 | .max_clock_factor = 8, |
d1f4a38c HW |
146 | }; |
147 | ||
148 | static const struct fsl_dspi_devtype_data ls2085a_data = { | |
149 | .trans_mode = DSPI_TCFQ_MODE, | |
9419b200 | 150 | .max_clock_factor = 8, |
d1f4a38c HW |
151 | }; |
152 | ||
90ba3703 | 153 | struct fsl_dspi_dma { |
1eaccf21 | 154 | /* Length of transfer in words of DSPI_FIFO_SIZE */ |
90ba3703 SM |
155 | u32 curr_xfer_len; |
156 | ||
157 | u32 *tx_dma_buf; | |
158 | struct dma_chan *chan_tx; | |
159 | dma_addr_t tx_dma_phys; | |
160 | struct completion cmd_tx_complete; | |
161 | struct dma_async_tx_descriptor *tx_desc; | |
162 | ||
163 | u32 *rx_dma_buf; | |
164 | struct dma_chan *chan_rx; | |
165 | dma_addr_t rx_dma_phys; | |
166 | struct completion cmd_rx_complete; | |
167 | struct dma_async_tx_descriptor *rx_desc; | |
168 | }; | |
169 | ||
349ad66c | 170 | struct fsl_dspi { |
9298bc72 | 171 | struct spi_master *master; |
349ad66c CF |
172 | struct platform_device *pdev; |
173 | ||
1acbdeb9 | 174 | struct regmap *regmap; |
349ad66c | 175 | int irq; |
88386e85 | 176 | struct clk *clk; |
349ad66c | 177 | |
88386e85 | 178 | struct spi_transfer *cur_transfer; |
9298bc72 | 179 | struct spi_message *cur_msg; |
349ad66c CF |
180 | struct chip_data *cur_chip; |
181 | size_t len; | |
182 | void *tx; | |
183 | void *tx_end; | |
184 | void *rx; | |
185 | void *rx_end; | |
186 | char dataflags; | |
187 | u8 cs; | |
188 | u16 void_write_data; | |
9298bc72 | 189 | u32 cs_change; |
94b968b5 | 190 | const struct fsl_dspi_devtype_data *devtype_data; |
349ad66c | 191 | |
88386e85 CF |
192 | wait_queue_head_t waitq; |
193 | u32 waitflags; | |
c042af95 HW |
194 | |
195 | u32 spi_tcnt; | |
90ba3703 | 196 | struct fsl_dspi_dma *dma; |
349ad66c CF |
197 | }; |
198 | ||
199 | static inline int is_double_byte_mode(struct fsl_dspi *dspi) | |
200 | { | |
1acbdeb9 | 201 | unsigned int val; |
349ad66c | 202 | |
ef22d160 | 203 | regmap_read(dspi->regmap, SPI_CTAR(0), &val); |
349ad66c | 204 | |
1acbdeb9 | 205 | return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1; |
349ad66c CF |
206 | } |
207 | ||
90ba3703 SM |
208 | static void dspi_tx_dma_callback(void *arg) |
209 | { | |
210 | struct fsl_dspi *dspi = arg; | |
211 | struct fsl_dspi_dma *dma = dspi->dma; | |
212 | ||
213 | complete(&dma->cmd_tx_complete); | |
214 | } | |
215 | ||
216 | static void dspi_rx_dma_callback(void *arg) | |
217 | { | |
218 | struct fsl_dspi *dspi = arg; | |
219 | struct fsl_dspi_dma *dma = dspi->dma; | |
220 | int rx_word; | |
1eaccf21 | 221 | int i; |
90ba3703 SM |
222 | u16 d; |
223 | ||
224 | rx_word = is_double_byte_mode(dspi); | |
225 | ||
90ba3703 | 226 | if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) { |
1eaccf21 | 227 | for (i = 0; i < dma->curr_xfer_len; i++) { |
90ba3703 SM |
228 | d = dspi->dma->rx_dma_buf[i]; |
229 | rx_word ? (*(u16 *)dspi->rx = d) : | |
230 | (*(u8 *)dspi->rx = d); | |
231 | dspi->rx += rx_word + 1; | |
232 | } | |
233 | } | |
234 | ||
235 | complete(&dma->cmd_rx_complete); | |
236 | } | |
237 | ||
238 | static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi) | |
239 | { | |
240 | struct fsl_dspi_dma *dma = dspi->dma; | |
241 | struct device *dev = &dspi->pdev->dev; | |
242 | int time_left; | |
243 | int tx_word; | |
1eaccf21 | 244 | int i; |
90ba3703 SM |
245 | u16 val; |
246 | ||
247 | tx_word = is_double_byte_mode(dspi); | |
248 | ||
1eaccf21 | 249 | for (i = 0; i < dma->curr_xfer_len - 1; i++) { |
90ba3703 SM |
250 | val = tx_word ? *(u16 *) dspi->tx : *(u8 *) dspi->tx; |
251 | dspi->dma->tx_dma_buf[i] = | |
252 | SPI_PUSHR_TXDATA(val) | SPI_PUSHR_PCS(dspi->cs) | | |
253 | SPI_PUSHR_CTAS(0) | SPI_PUSHR_CONT; | |
254 | dspi->tx += tx_word + 1; | |
255 | } | |
256 | ||
257 | val = tx_word ? *(u16 *) dspi->tx : *(u8 *) dspi->tx; | |
258 | dspi->dma->tx_dma_buf[i] = SPI_PUSHR_TXDATA(val) | | |
259 | SPI_PUSHR_PCS(dspi->cs) | | |
260 | SPI_PUSHR_CTAS(0); | |
261 | dspi->tx += tx_word + 1; | |
262 | ||
263 | dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx, | |
264 | dma->tx_dma_phys, | |
1eaccf21 SM |
265 | dma->curr_xfer_len * |
266 | DMA_SLAVE_BUSWIDTH_4_BYTES, | |
267 | DMA_MEM_TO_DEV, | |
90ba3703 SM |
268 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
269 | if (!dma->tx_desc) { | |
270 | dev_err(dev, "Not able to get desc for DMA xfer\n"); | |
271 | return -EIO; | |
272 | } | |
273 | ||
274 | dma->tx_desc->callback = dspi_tx_dma_callback; | |
275 | dma->tx_desc->callback_param = dspi; | |
276 | if (dma_submit_error(dmaengine_submit(dma->tx_desc))) { | |
277 | dev_err(dev, "DMA submit failed\n"); | |
278 | return -EINVAL; | |
279 | } | |
280 | ||
281 | dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx, | |
282 | dma->rx_dma_phys, | |
1eaccf21 SM |
283 | dma->curr_xfer_len * |
284 | DMA_SLAVE_BUSWIDTH_4_BYTES, | |
285 | DMA_DEV_TO_MEM, | |
90ba3703 SM |
286 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
287 | if (!dma->rx_desc) { | |
288 | dev_err(dev, "Not able to get desc for DMA xfer\n"); | |
289 | return -EIO; | |
290 | } | |
291 | ||
292 | dma->rx_desc->callback = dspi_rx_dma_callback; | |
293 | dma->rx_desc->callback_param = dspi; | |
294 | if (dma_submit_error(dmaengine_submit(dma->rx_desc))) { | |
295 | dev_err(dev, "DMA submit failed\n"); | |
296 | return -EINVAL; | |
297 | } | |
298 | ||
299 | reinit_completion(&dspi->dma->cmd_rx_complete); | |
300 | reinit_completion(&dspi->dma->cmd_tx_complete); | |
301 | ||
302 | dma_async_issue_pending(dma->chan_rx); | |
303 | dma_async_issue_pending(dma->chan_tx); | |
304 | ||
305 | time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete, | |
306 | DMA_COMPLETION_TIMEOUT); | |
307 | if (time_left == 0) { | |
308 | dev_err(dev, "DMA tx timeout\n"); | |
309 | dmaengine_terminate_all(dma->chan_tx); | |
310 | dmaengine_terminate_all(dma->chan_rx); | |
311 | return -ETIMEDOUT; | |
312 | } | |
313 | ||
314 | time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete, | |
315 | DMA_COMPLETION_TIMEOUT); | |
316 | if (time_left == 0) { | |
317 | dev_err(dev, "DMA rx timeout\n"); | |
318 | dmaengine_terminate_all(dma->chan_tx); | |
319 | dmaengine_terminate_all(dma->chan_rx); | |
320 | return -ETIMEDOUT; | |
321 | } | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
326 | static int dspi_dma_xfer(struct fsl_dspi *dspi) | |
327 | { | |
328 | struct fsl_dspi_dma *dma = dspi->dma; | |
329 | struct device *dev = &dspi->pdev->dev; | |
330 | int curr_remaining_bytes; | |
331 | int bytes_per_buffer; | |
1eaccf21 | 332 | int word = 1; |
90ba3703 SM |
333 | int ret = 0; |
334 | ||
1eaccf21 SM |
335 | if (is_double_byte_mode(dspi)) |
336 | word = 2; | |
90ba3703 | 337 | curr_remaining_bytes = dspi->len; |
1eaccf21 | 338 | bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE; |
90ba3703 SM |
339 | while (curr_remaining_bytes) { |
340 | /* Check if current transfer fits the DMA buffer */ | |
1eaccf21 SM |
341 | dma->curr_xfer_len = curr_remaining_bytes / word; |
342 | if (dma->curr_xfer_len > bytes_per_buffer) | |
90ba3703 SM |
343 | dma->curr_xfer_len = bytes_per_buffer; |
344 | ||
345 | ret = dspi_next_xfer_dma_submit(dspi); | |
346 | if (ret) { | |
347 | dev_err(dev, "DMA transfer failed\n"); | |
348 | goto exit; | |
349 | ||
350 | } else { | |
1eaccf21 | 351 | curr_remaining_bytes -= dma->curr_xfer_len * word; |
90ba3703 SM |
352 | if (curr_remaining_bytes < 0) |
353 | curr_remaining_bytes = 0; | |
354 | dspi->len = curr_remaining_bytes; | |
355 | } | |
356 | } | |
357 | ||
358 | exit: | |
359 | return ret; | |
360 | } | |
361 | ||
362 | static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) | |
363 | { | |
364 | struct fsl_dspi_dma *dma; | |
365 | struct dma_slave_config cfg; | |
366 | struct device *dev = &dspi->pdev->dev; | |
367 | int ret; | |
368 | ||
369 | dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); | |
370 | if (!dma) | |
371 | return -ENOMEM; | |
372 | ||
373 | dma->chan_rx = dma_request_slave_channel(dev, "rx"); | |
374 | if (!dma->chan_rx) { | |
375 | dev_err(dev, "rx dma channel not available\n"); | |
376 | ret = -ENODEV; | |
377 | return ret; | |
378 | } | |
379 | ||
380 | dma->chan_tx = dma_request_slave_channel(dev, "tx"); | |
381 | if (!dma->chan_tx) { | |
382 | dev_err(dev, "tx dma channel not available\n"); | |
383 | ret = -ENODEV; | |
384 | goto err_tx_channel; | |
385 | } | |
386 | ||
387 | dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE, | |
388 | &dma->tx_dma_phys, GFP_KERNEL); | |
389 | if (!dma->tx_dma_buf) { | |
390 | ret = -ENOMEM; | |
391 | goto err_tx_dma_buf; | |
392 | } | |
393 | ||
394 | dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE, | |
395 | &dma->rx_dma_phys, GFP_KERNEL); | |
396 | if (!dma->rx_dma_buf) { | |
397 | ret = -ENOMEM; | |
398 | goto err_rx_dma_buf; | |
399 | } | |
400 | ||
401 | cfg.src_addr = phy_addr + SPI_POPR; | |
402 | cfg.dst_addr = phy_addr + SPI_PUSHR; | |
403 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
404 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
405 | cfg.src_maxburst = 1; | |
406 | cfg.dst_maxburst = 1; | |
407 | ||
408 | cfg.direction = DMA_DEV_TO_MEM; | |
409 | ret = dmaengine_slave_config(dma->chan_rx, &cfg); | |
410 | if (ret) { | |
411 | dev_err(dev, "can't configure rx dma channel\n"); | |
412 | ret = -EINVAL; | |
413 | goto err_slave_config; | |
414 | } | |
415 | ||
416 | cfg.direction = DMA_MEM_TO_DEV; | |
417 | ret = dmaengine_slave_config(dma->chan_tx, &cfg); | |
418 | if (ret) { | |
419 | dev_err(dev, "can't configure tx dma channel\n"); | |
420 | ret = -EINVAL; | |
421 | goto err_slave_config; | |
422 | } | |
423 | ||
424 | dspi->dma = dma; | |
425 | init_completion(&dma->cmd_tx_complete); | |
426 | init_completion(&dma->cmd_rx_complete); | |
427 | ||
428 | return 0; | |
429 | ||
430 | err_slave_config: | |
27d21e9f SM |
431 | dma_free_coherent(dev, DSPI_DMA_BUFSIZE, |
432 | dma->rx_dma_buf, dma->rx_dma_phys); | |
90ba3703 | 433 | err_rx_dma_buf: |
27d21e9f SM |
434 | dma_free_coherent(dev, DSPI_DMA_BUFSIZE, |
435 | dma->tx_dma_buf, dma->tx_dma_phys); | |
90ba3703 SM |
436 | err_tx_dma_buf: |
437 | dma_release_channel(dma->chan_tx); | |
438 | err_tx_channel: | |
439 | dma_release_channel(dma->chan_rx); | |
440 | ||
441 | devm_kfree(dev, dma); | |
442 | dspi->dma = NULL; | |
443 | ||
444 | return ret; | |
445 | } | |
446 | ||
447 | static void dspi_release_dma(struct fsl_dspi *dspi) | |
448 | { | |
449 | struct fsl_dspi_dma *dma = dspi->dma; | |
450 | struct device *dev = &dspi->pdev->dev; | |
451 | ||
452 | if (dma) { | |
453 | if (dma->chan_tx) { | |
454 | dma_unmap_single(dev, dma->tx_dma_phys, | |
455 | DSPI_DMA_BUFSIZE, DMA_TO_DEVICE); | |
456 | dma_release_channel(dma->chan_tx); | |
457 | } | |
458 | ||
459 | if (dma->chan_rx) { | |
460 | dma_unmap_single(dev, dma->rx_dma_phys, | |
461 | DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE); | |
462 | dma_release_channel(dma->chan_rx); | |
463 | } | |
464 | } | |
465 | } | |
466 | ||
349ad66c CF |
467 | static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, |
468 | unsigned long clkrate) | |
469 | { | |
470 | /* Valid baud rate pre-scaler values */ | |
471 | int pbr_tbl[4] = {2, 3, 5, 7}; | |
472 | int brs[16] = { 2, 4, 6, 8, | |
473 | 16, 32, 64, 128, | |
474 | 256, 512, 1024, 2048, | |
475 | 4096, 8192, 16384, 32768 }; | |
6fd63087 AB |
476 | int scale_needed, scale, minscale = INT_MAX; |
477 | int i, j; | |
478 | ||
479 | scale_needed = clkrate / speed_hz; | |
e689d6df AB |
480 | if (clkrate % speed_hz) |
481 | scale_needed++; | |
6fd63087 AB |
482 | |
483 | for (i = 0; i < ARRAY_SIZE(brs); i++) | |
484 | for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) { | |
485 | scale = brs[i] * pbr_tbl[j]; | |
486 | if (scale >= scale_needed) { | |
487 | if (scale < minscale) { | |
488 | minscale = scale; | |
489 | *br = i; | |
490 | *pbr = j; | |
491 | } | |
492 | break; | |
349ad66c CF |
493 | } |
494 | } | |
349ad66c | 495 | |
6fd63087 AB |
496 | if (minscale == INT_MAX) { |
497 | pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n", | |
498 | speed_hz, clkrate); | |
499 | *pbr = ARRAY_SIZE(pbr_tbl) - 1; | |
500 | *br = ARRAY_SIZE(brs) - 1; | |
501 | } | |
349ad66c | 502 | } |
349ad66c | 503 | |
95bf15f3 AB |
504 | static void ns_delay_scale(char *psc, char *sc, int delay_ns, |
505 | unsigned long clkrate) | |
506 | { | |
507 | int pscale_tbl[4] = {1, 3, 5, 7}; | |
508 | int scale_needed, scale, minscale = INT_MAX; | |
509 | int i, j; | |
510 | u32 remainder; | |
511 | ||
512 | scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC, | |
513 | &remainder); | |
514 | if (remainder) | |
515 | scale_needed++; | |
516 | ||
517 | for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++) | |
518 | for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) { | |
519 | scale = pscale_tbl[i] * (2 << j); | |
520 | if (scale >= scale_needed) { | |
521 | if (scale < minscale) { | |
522 | minscale = scale; | |
523 | *psc = i; | |
524 | *sc = j; | |
525 | } | |
526 | break; | |
349ad66c CF |
527 | } |
528 | } | |
529 | ||
95bf15f3 AB |
530 | if (minscale == INT_MAX) { |
531 | pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value", | |
532 | delay_ns, clkrate); | |
533 | *psc = ARRAY_SIZE(pscale_tbl) - 1; | |
534 | *sc = SPI_CTAR_SCALE_BITS; | |
535 | } | |
349ad66c CF |
536 | } |
537 | ||
d1f4a38c | 538 | static u32 dspi_data_to_pushr(struct fsl_dspi *dspi, int tx_word) |
349ad66c | 539 | { |
349ad66c | 540 | u16 d16; |
349ad66c | 541 | |
d1f4a38c HW |
542 | if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) |
543 | d16 = tx_word ? *(u16 *)dspi->tx : *(u8 *)dspi->tx; | |
544 | else | |
545 | d16 = dspi->void_write_data; | |
349ad66c | 546 | |
d1f4a38c HW |
547 | dspi->tx += tx_word + 1; |
548 | dspi->len -= tx_word + 1; | |
349ad66c | 549 | |
d1f4a38c HW |
550 | return SPI_PUSHR_TXDATA(d16) | |
551 | SPI_PUSHR_PCS(dspi->cs) | | |
ef22d160 | 552 | SPI_PUSHR_CTAS(0) | |
d1f4a38c HW |
553 | SPI_PUSHR_CONT; |
554 | } | |
349ad66c | 555 | |
d1f4a38c HW |
556 | static void dspi_data_from_popr(struct fsl_dspi *dspi, int rx_word) |
557 | { | |
558 | u16 d; | |
559 | unsigned int val; | |
349ad66c | 560 | |
d1f4a38c HW |
561 | regmap_read(dspi->regmap, SPI_POPR, &val); |
562 | d = SPI_POPR_RXDATA(val); | |
349ad66c | 563 | |
d1f4a38c HW |
564 | if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) |
565 | rx_word ? (*(u16 *)dspi->rx = d) : (*(u8 *)dspi->rx = d); | |
349ad66c | 566 | |
d1f4a38c HW |
567 | dspi->rx += rx_word + 1; |
568 | } | |
349ad66c | 569 | |
d1f4a38c HW |
570 | static int dspi_eoq_write(struct fsl_dspi *dspi) |
571 | { | |
572 | int tx_count = 0; | |
573 | int tx_word; | |
574 | u32 dspi_pushr = 0; | |
349ad66c | 575 | |
d1f4a38c HW |
576 | tx_word = is_double_byte_mode(dspi); |
577 | ||
578 | while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) { | |
579 | /* If we are in word mode, only have a single byte to transfer | |
580 | * switch to byte mode temporarily. Will switch back at the | |
581 | * end of the transfer. | |
582 | */ | |
583 | if (tx_word && (dspi->len == 1)) { | |
584 | dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM; | |
ef22d160 | 585 | regmap_update_bits(dspi->regmap, SPI_CTAR(0), |
d1f4a38c HW |
586 | SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8)); |
587 | tx_word = 0; | |
349ad66c CF |
588 | } |
589 | ||
d1f4a38c HW |
590 | dspi_pushr = dspi_data_to_pushr(dspi, tx_word); |
591 | ||
349ad66c CF |
592 | if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) { |
593 | /* last transfer in the transfer */ | |
594 | dspi_pushr |= SPI_PUSHR_EOQ; | |
9298bc72 CF |
595 | if ((dspi->cs_change) && (!dspi->len)) |
596 | dspi_pushr &= ~SPI_PUSHR_CONT; | |
349ad66c CF |
597 | } else if (tx_word && (dspi->len == 1)) |
598 | dspi_pushr |= SPI_PUSHR_EOQ; | |
599 | ||
1acbdeb9 CF |
600 | regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr); |
601 | ||
349ad66c CF |
602 | tx_count++; |
603 | } | |
604 | ||
605 | return tx_count * (tx_word + 1); | |
606 | } | |
607 | ||
d1f4a38c | 608 | static int dspi_eoq_read(struct fsl_dspi *dspi) |
349ad66c CF |
609 | { |
610 | int rx_count = 0; | |
611 | int rx_word = is_double_byte_mode(dspi); | |
9298bc72 | 612 | |
349ad66c CF |
613 | while ((dspi->rx < dspi->rx_end) |
614 | && (rx_count < DSPI_FIFO_SIZE)) { | |
d1f4a38c HW |
615 | if (rx_word && (dspi->rx_end - dspi->rx) == 1) |
616 | rx_word = 0; | |
1acbdeb9 | 617 | |
d1f4a38c HW |
618 | dspi_data_from_popr(dspi, rx_word); |
619 | rx_count++; | |
620 | } | |
349ad66c | 621 | |
d1f4a38c HW |
622 | return rx_count; |
623 | } | |
349ad66c | 624 | |
d1f4a38c HW |
625 | static int dspi_tcfq_write(struct fsl_dspi *dspi) |
626 | { | |
627 | int tx_word; | |
628 | u32 dspi_pushr = 0; | |
349ad66c | 629 | |
d1f4a38c | 630 | tx_word = is_double_byte_mode(dspi); |
1acbdeb9 | 631 | |
d1f4a38c HW |
632 | if (tx_word && (dspi->len == 1)) { |
633 | dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM; | |
ef22d160 | 634 | regmap_update_bits(dspi->regmap, SPI_CTAR(0), |
d1f4a38c HW |
635 | SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8)); |
636 | tx_word = 0; | |
349ad66c CF |
637 | } |
638 | ||
d1f4a38c HW |
639 | dspi_pushr = dspi_data_to_pushr(dspi, tx_word); |
640 | ||
641 | if ((dspi->cs_change) && (!dspi->len)) | |
642 | dspi_pushr &= ~SPI_PUSHR_CONT; | |
643 | ||
644 | regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr); | |
645 | ||
646 | return tx_word + 1; | |
647 | } | |
648 | ||
649 | static void dspi_tcfq_read(struct fsl_dspi *dspi) | |
650 | { | |
651 | int rx_word = is_double_byte_mode(dspi); | |
652 | ||
653 | if (rx_word && (dspi->rx_end - dspi->rx) == 1) | |
654 | rx_word = 0; | |
655 | ||
656 | dspi_data_from_popr(dspi, rx_word); | |
349ad66c CF |
657 | } |
658 | ||
9298bc72 CF |
659 | static int dspi_transfer_one_message(struct spi_master *master, |
660 | struct spi_message *message) | |
349ad66c | 661 | { |
9298bc72 CF |
662 | struct fsl_dspi *dspi = spi_master_get_devdata(master); |
663 | struct spi_device *spi = message->spi; | |
664 | struct spi_transfer *transfer; | |
665 | int status = 0; | |
d1f4a38c | 666 | enum dspi_trans_mode trans_mode; |
c042af95 HW |
667 | u32 spi_tcr; |
668 | ||
669 | regmap_read(dspi->regmap, SPI_TCR, &spi_tcr); | |
670 | dspi->spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr); | |
d1f4a38c | 671 | |
9298bc72 CF |
672 | message->actual_length = 0; |
673 | ||
674 | list_for_each_entry(transfer, &message->transfers, transfer_list) { | |
675 | dspi->cur_transfer = transfer; | |
676 | dspi->cur_msg = message; | |
677 | dspi->cur_chip = spi_get_ctldata(spi); | |
678 | dspi->cs = spi->chip_select; | |
9deef024 | 679 | dspi->cs_change = 0; |
92dc20d8 AV |
680 | if (list_is_last(&dspi->cur_transfer->transfer_list, |
681 | &dspi->cur_msg->transfers) || transfer->cs_change) | |
9deef024 | 682 | dspi->cs_change = 1; |
9298bc72 CF |
683 | dspi->void_write_data = dspi->cur_chip->void_write_data; |
684 | ||
685 | dspi->dataflags = 0; | |
686 | dspi->tx = (void *)transfer->tx_buf; | |
687 | dspi->tx_end = dspi->tx + transfer->len; | |
688 | dspi->rx = transfer->rx_buf; | |
689 | dspi->rx_end = dspi->rx + transfer->len; | |
690 | dspi->len = transfer->len; | |
691 | ||
692 | if (!dspi->rx) | |
693 | dspi->dataflags |= TRAN_STATE_RX_VOID; | |
694 | ||
695 | if (!dspi->tx) | |
696 | dspi->dataflags |= TRAN_STATE_TX_VOID; | |
697 | ||
698 | regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val); | |
699 | regmap_update_bits(dspi->regmap, SPI_MCR, | |
700 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, | |
701 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); | |
ef22d160 | 702 | regmap_write(dspi->regmap, SPI_CTAR(0), |
1acbdeb9 | 703 | dspi->cur_chip->ctar_val); |
349ad66c | 704 | |
d1f4a38c HW |
705 | trans_mode = dspi->devtype_data->trans_mode; |
706 | switch (trans_mode) { | |
707 | case DSPI_EOQ_MODE: | |
708 | regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); | |
c042af95 | 709 | dspi_eoq_write(dspi); |
d1f4a38c HW |
710 | break; |
711 | case DSPI_TCFQ_MODE: | |
712 | regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE); | |
c042af95 | 713 | dspi_tcfq_write(dspi); |
d1f4a38c | 714 | break; |
90ba3703 SM |
715 | case DSPI_DMA_MODE: |
716 | regmap_write(dspi->regmap, SPI_RSER, | |
717 | SPI_RSER_TFFFE | SPI_RSER_TFFFD | | |
718 | SPI_RSER_RFDFE | SPI_RSER_RFDFD); | |
719 | status = dspi_dma_xfer(dspi); | |
98114304 | 720 | break; |
d1f4a38c HW |
721 | default: |
722 | dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", | |
723 | trans_mode); | |
724 | status = -EINVAL; | |
725 | goto out; | |
726 | } | |
1acbdeb9 | 727 | |
98114304 SM |
728 | if (trans_mode != DSPI_DMA_MODE) { |
729 | if (wait_event_interruptible(dspi->waitq, | |
730 | dspi->waitflags)) | |
731 | dev_err(&dspi->pdev->dev, | |
732 | "wait transfer complete fail!\n"); | |
733 | dspi->waitflags = 0; | |
734 | } | |
349ad66c | 735 | |
9298bc72 CF |
736 | if (transfer->delay_usecs) |
737 | udelay(transfer->delay_usecs); | |
349ad66c CF |
738 | } |
739 | ||
d1f4a38c | 740 | out: |
9298bc72 CF |
741 | message->status = status; |
742 | spi_finalize_current_message(master); | |
743 | ||
744 | return status; | |
349ad66c CF |
745 | } |
746 | ||
9298bc72 | 747 | static int dspi_setup(struct spi_device *spi) |
349ad66c CF |
748 | { |
749 | struct chip_data *chip; | |
750 | struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); | |
95bf15f3 AB |
751 | u32 cs_sck_delay = 0, sck_cs_delay = 0; |
752 | unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0; | |
753 | unsigned char pasc = 0, asc = 0, fmsz = 0; | |
754 | unsigned long clkrate; | |
349ad66c | 755 | |
ceadfd8d BD |
756 | if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) { |
757 | fmsz = spi->bits_per_word - 1; | |
758 | } else { | |
759 | pr_err("Invalid wordsize\n"); | |
760 | return -ENODEV; | |
761 | } | |
762 | ||
349ad66c CF |
763 | /* Only alloc on first setup */ |
764 | chip = spi_get_ctldata(spi); | |
765 | if (chip == NULL) { | |
973fbce6 | 766 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
349ad66c CF |
767 | if (!chip) |
768 | return -ENOMEM; | |
769 | } | |
770 | ||
95bf15f3 AB |
771 | of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay", |
772 | &cs_sck_delay); | |
773 | ||
774 | of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay", | |
775 | &sck_cs_delay); | |
776 | ||
349ad66c CF |
777 | chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS | |
778 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF; | |
349ad66c CF |
779 | |
780 | chip->void_write_data = 0; | |
781 | ||
95bf15f3 AB |
782 | clkrate = clk_get_rate(dspi->clk); |
783 | hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate); | |
784 | ||
785 | /* Set PCS to SCK delay scale values */ | |
786 | ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate); | |
787 | ||
788 | /* Set After SCK delay scale values */ | |
789 | ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate); | |
349ad66c CF |
790 | |
791 | chip->ctar_val = SPI_CTAR_FMSZ(fmsz) | |
792 | | SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0) | |
793 | | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0) | |
794 | | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0) | |
95bf15f3 AB |
795 | | SPI_CTAR_PCSSCK(pcssck) |
796 | | SPI_CTAR_CSSCK(cssck) | |
797 | | SPI_CTAR_PASC(pasc) | |
798 | | SPI_CTAR_ASC(asc) | |
349ad66c CF |
799 | | SPI_CTAR_PBR(pbr) |
800 | | SPI_CTAR_BR(br); | |
801 | ||
802 | spi_set_ctldata(spi, chip); | |
803 | ||
804 | return 0; | |
805 | } | |
806 | ||
973fbce6 BD |
807 | static void dspi_cleanup(struct spi_device *spi) |
808 | { | |
809 | struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi); | |
810 | ||
811 | dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n", | |
812 | spi->master->bus_num, spi->chip_select); | |
813 | ||
814 | kfree(chip); | |
815 | } | |
816 | ||
349ad66c CF |
817 | static irqreturn_t dspi_interrupt(int irq, void *dev_id) |
818 | { | |
819 | struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; | |
9298bc72 | 820 | struct spi_message *msg = dspi->cur_msg; |
d1f4a38c | 821 | enum dspi_trans_mode trans_mode; |
c042af95 HW |
822 | u32 spi_sr, spi_tcr; |
823 | u32 spi_tcnt, tcnt_diff; | |
824 | int tx_word; | |
d1f4a38c HW |
825 | |
826 | regmap_read(dspi->regmap, SPI_SR, &spi_sr); | |
827 | regmap_write(dspi->regmap, SPI_SR, spi_sr); | |
828 | ||
349ad66c | 829 | |
c042af95 HW |
830 | if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) { |
831 | tx_word = is_double_byte_mode(dspi); | |
1acbdeb9 | 832 | |
c042af95 HW |
833 | regmap_read(dspi->regmap, SPI_TCR, &spi_tcr); |
834 | spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr); | |
835 | /* | |
836 | * The width of SPI Transfer Counter in SPI_TCR is 16bits, | |
837 | * so the max couner is 65535. When the counter reach 65535, | |
838 | * it will wrap around, counter reset to zero. | |
839 | * spi_tcnt my be less than dspi->spi_tcnt, it means the | |
840 | * counter already wrapped around. | |
841 | * SPI Transfer Counter is a counter of transmitted frames. | |
842 | * The size of frame maybe two bytes. | |
843 | */ | |
844 | tcnt_diff = ((spi_tcnt + SPI_TCR_TCNT_MAX) - dspi->spi_tcnt) | |
845 | % SPI_TCR_TCNT_MAX; | |
846 | tcnt_diff *= (tx_word + 1); | |
847 | if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) | |
848 | tcnt_diff--; | |
849 | ||
850 | msg->actual_length += tcnt_diff; | |
851 | ||
852 | dspi->spi_tcnt = spi_tcnt; | |
853 | ||
854 | trans_mode = dspi->devtype_data->trans_mode; | |
d1f4a38c HW |
855 | switch (trans_mode) { |
856 | case DSPI_EOQ_MODE: | |
c042af95 | 857 | dspi_eoq_read(dspi); |
d1f4a38c HW |
858 | break; |
859 | case DSPI_TCFQ_MODE: | |
c042af95 | 860 | dspi_tcfq_read(dspi); |
d1f4a38c HW |
861 | break; |
862 | default: | |
863 | dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", | |
864 | trans_mode); | |
c042af95 HW |
865 | return IRQ_HANDLED; |
866 | } | |
867 | ||
868 | if (!dspi->len) { | |
869 | if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) { | |
870 | regmap_update_bits(dspi->regmap, | |
ef22d160 | 871 | SPI_CTAR(0), |
c042af95 HW |
872 | SPI_FRAME_BITS_MASK, |
873 | SPI_FRAME_BITS(16)); | |
874 | dspi->dataflags &= ~TRAN_STATE_WORD_ODD_NUM; | |
875 | } | |
876 | ||
877 | dspi->waitflags = 1; | |
878 | wake_up_interruptible(&dspi->waitq); | |
879 | } else { | |
880 | switch (trans_mode) { | |
881 | case DSPI_EOQ_MODE: | |
882 | dspi_eoq_write(dspi); | |
883 | break; | |
884 | case DSPI_TCFQ_MODE: | |
885 | dspi_tcfq_write(dspi); | |
886 | break; | |
887 | default: | |
888 | dev_err(&dspi->pdev->dev, | |
889 | "unsupported trans_mode %u\n", | |
890 | trans_mode); | |
891 | } | |
d1f4a38c HW |
892 | } |
893 | } | |
c042af95 | 894 | |
349ad66c CF |
895 | return IRQ_HANDLED; |
896 | } | |
897 | ||
790d1902 | 898 | static const struct of_device_id fsl_dspi_dt_ids[] = { |
d1f4a38c HW |
899 | { .compatible = "fsl,vf610-dspi", .data = (void *)&vf610_data, }, |
900 | { .compatible = "fsl,ls1021a-v1.0-dspi", | |
901 | .data = (void *)&ls1021a_v1_data, }, | |
902 | { .compatible = "fsl,ls2085a-dspi", .data = (void *)&ls2085a_data, }, | |
349ad66c CF |
903 | { /* sentinel */ } |
904 | }; | |
905 | MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); | |
906 | ||
907 | #ifdef CONFIG_PM_SLEEP | |
908 | static int dspi_suspend(struct device *dev) | |
909 | { | |
910 | struct spi_master *master = dev_get_drvdata(dev); | |
911 | struct fsl_dspi *dspi = spi_master_get_devdata(master); | |
912 | ||
913 | spi_master_suspend(master); | |
914 | clk_disable_unprepare(dspi->clk); | |
915 | ||
432a17d7 MK |
916 | pinctrl_pm_select_sleep_state(dev); |
917 | ||
349ad66c CF |
918 | return 0; |
919 | } | |
920 | ||
921 | static int dspi_resume(struct device *dev) | |
922 | { | |
349ad66c CF |
923 | struct spi_master *master = dev_get_drvdata(dev); |
924 | struct fsl_dspi *dspi = spi_master_get_devdata(master); | |
1c5ea2b4 | 925 | int ret; |
349ad66c | 926 | |
432a17d7 MK |
927 | pinctrl_pm_select_default_state(dev); |
928 | ||
1c5ea2b4 FE |
929 | ret = clk_prepare_enable(dspi->clk); |
930 | if (ret) | |
931 | return ret; | |
349ad66c CF |
932 | spi_master_resume(master); |
933 | ||
934 | return 0; | |
935 | } | |
936 | #endif /* CONFIG_PM_SLEEP */ | |
937 | ||
ba811add | 938 | static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume); |
349ad66c | 939 | |
409851c3 | 940 | static const struct regmap_config dspi_regmap_config = { |
1acbdeb9 CF |
941 | .reg_bits = 32, |
942 | .val_bits = 32, | |
943 | .reg_stride = 4, | |
944 | .max_register = 0x88, | |
349ad66c CF |
945 | }; |
946 | ||
947 | static int dspi_probe(struct platform_device *pdev) | |
948 | { | |
949 | struct device_node *np = pdev->dev.of_node; | |
950 | struct spi_master *master; | |
951 | struct fsl_dspi *dspi; | |
952 | struct resource *res; | |
1acbdeb9 | 953 | void __iomem *base; |
349ad66c CF |
954 | int ret = 0, cs_num, bus_num; |
955 | ||
956 | master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); | |
957 | if (!master) | |
958 | return -ENOMEM; | |
959 | ||
960 | dspi = spi_master_get_devdata(master); | |
961 | dspi->pdev = pdev; | |
9298bc72 CF |
962 | dspi->master = master; |
963 | ||
964 | master->transfer = NULL; | |
965 | master->setup = dspi_setup; | |
966 | master->transfer_one_message = dspi_transfer_one_message; | |
967 | master->dev.of_node = pdev->dev.of_node; | |
349ad66c | 968 | |
973fbce6 | 969 | master->cleanup = dspi_cleanup; |
349ad66c CF |
970 | master->mode_bits = SPI_CPOL | SPI_CPHA; |
971 | master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) | | |
972 | SPI_BPW_MASK(16); | |
973 | ||
974 | ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); | |
975 | if (ret < 0) { | |
976 | dev_err(&pdev->dev, "can't get spi-num-chipselects\n"); | |
977 | goto out_master_put; | |
978 | } | |
979 | master->num_chipselect = cs_num; | |
980 | ||
981 | ret = of_property_read_u32(np, "bus-num", &bus_num); | |
982 | if (ret < 0) { | |
983 | dev_err(&pdev->dev, "can't get bus-num\n"); | |
984 | goto out_master_put; | |
985 | } | |
986 | master->bus_num = bus_num; | |
987 | ||
53d89160 | 988 | dspi->devtype_data = of_device_get_match_data(&pdev->dev); |
d1f4a38c HW |
989 | if (!dspi->devtype_data) { |
990 | dev_err(&pdev->dev, "can't get devtype_data\n"); | |
991 | ret = -EFAULT; | |
992 | goto out_master_put; | |
993 | } | |
994 | ||
349ad66c | 995 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1acbdeb9 CF |
996 | base = devm_ioremap_resource(&pdev->dev, res); |
997 | if (IS_ERR(base)) { | |
998 | ret = PTR_ERR(base); | |
349ad66c CF |
999 | goto out_master_put; |
1000 | } | |
1001 | ||
d2233325 | 1002 | dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base, |
1acbdeb9 CF |
1003 | &dspi_regmap_config); |
1004 | if (IS_ERR(dspi->regmap)) { | |
1005 | dev_err(&pdev->dev, "failed to init regmap: %ld\n", | |
1006 | PTR_ERR(dspi->regmap)); | |
1007 | return PTR_ERR(dspi->regmap); | |
1008 | } | |
1009 | ||
349ad66c CF |
1010 | dspi->irq = platform_get_irq(pdev, 0); |
1011 | if (dspi->irq < 0) { | |
1012 | dev_err(&pdev->dev, "can't get platform irq\n"); | |
1013 | ret = dspi->irq; | |
1014 | goto out_master_put; | |
1015 | } | |
1016 | ||
1017 | ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0, | |
1018 | pdev->name, dspi); | |
1019 | if (ret < 0) { | |
1020 | dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n"); | |
1021 | goto out_master_put; | |
1022 | } | |
1023 | ||
1024 | dspi->clk = devm_clk_get(&pdev->dev, "dspi"); | |
1025 | if (IS_ERR(dspi->clk)) { | |
1026 | ret = PTR_ERR(dspi->clk); | |
1027 | dev_err(&pdev->dev, "unable to get clock\n"); | |
1028 | goto out_master_put; | |
1029 | } | |
1c5ea2b4 FE |
1030 | ret = clk_prepare_enable(dspi->clk); |
1031 | if (ret) | |
1032 | goto out_master_put; | |
349ad66c | 1033 | |
90ba3703 SM |
1034 | if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) { |
1035 | if (dspi_request_dma(dspi, res->start)) { | |
1036 | dev_err(&pdev->dev, "can't get dma channels\n"); | |
1037 | goto out_clk_put; | |
1038 | } | |
1039 | } | |
1040 | ||
9419b200 BD |
1041 | master->max_speed_hz = |
1042 | clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor; | |
1043 | ||
349ad66c | 1044 | init_waitqueue_head(&dspi->waitq); |
017145fe | 1045 | platform_set_drvdata(pdev, master); |
349ad66c | 1046 | |
9298bc72 | 1047 | ret = spi_register_master(master); |
349ad66c CF |
1048 | if (ret != 0) { |
1049 | dev_err(&pdev->dev, "Problem registering DSPI master\n"); | |
1050 | goto out_clk_put; | |
1051 | } | |
1052 | ||
349ad66c CF |
1053 | return ret; |
1054 | ||
1055 | out_clk_put: | |
1056 | clk_disable_unprepare(dspi->clk); | |
1057 | out_master_put: | |
1058 | spi_master_put(master); | |
349ad66c CF |
1059 | |
1060 | return ret; | |
1061 | } | |
1062 | ||
1063 | static int dspi_remove(struct platform_device *pdev) | |
1064 | { | |
017145fe AL |
1065 | struct spi_master *master = platform_get_drvdata(pdev); |
1066 | struct fsl_dspi *dspi = spi_master_get_devdata(master); | |
349ad66c CF |
1067 | |
1068 | /* Disconnect from the SPI framework */ | |
90ba3703 | 1069 | dspi_release_dma(dspi); |
05209f45 | 1070 | clk_disable_unprepare(dspi->clk); |
9298bc72 | 1071 | spi_unregister_master(dspi->master); |
349ad66c CF |
1072 | |
1073 | return 0; | |
1074 | } | |
1075 | ||
1076 | static struct platform_driver fsl_dspi_driver = { | |
1077 | .driver.name = DRIVER_NAME, | |
1078 | .driver.of_match_table = fsl_dspi_dt_ids, | |
1079 | .driver.owner = THIS_MODULE, | |
1080 | .driver.pm = &dspi_pm, | |
1081 | .probe = dspi_probe, | |
1082 | .remove = dspi_remove, | |
1083 | }; | |
1084 | module_platform_driver(fsl_dspi_driver); | |
1085 | ||
1086 | MODULE_DESCRIPTION("Freescale DSPI Controller Driver"); | |
b444d1df | 1087 | MODULE_LICENSE("GPL"); |
349ad66c | 1088 | MODULE_ALIAS("platform:" DRIVER_NAME); |