[mirror_ubuntu-bionic-kernel.git] / drivers / spi / spi-fsl-dspi.c

/*
 * drivers/spi/spi-fsl-dspi.c
 *
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * Freescale DSPI driver
 * This file contains a driver for the Freescale DSPI
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_device.h>

#define DRIVER_NAME "fsl-dspi"

#define TRAN_STATE_RX_VOID		0x01
#define TRAN_STATE_TX_VOID		0x02
#define TRAN_STATE_WORD_ODD_NUM	0x04

#define DSPI_FIFO_SIZE			4

#define SPI_MCR		0x00
#define SPI_MCR_MASTER		(1 << 31)
#define SPI_MCR_PCSIS		(0x3F << 16)
#define SPI_MCR_CLR_TXF	(1 << 11)
#define SPI_MCR_CLR_RXF	(1 << 10)

#define SPI_TCR			0x08

#define SPI_CTAR(x)		(0x0c + (x * 4))
#define SPI_CTAR_FMSZ(x)	(((x) & 0x0000000f) << 27)
#define SPI_CTAR_CPOL(x)	((x) << 26)
#define SPI_CTAR_CPHA(x)	((x) << 25)
#define SPI_CTAR_LSBFE(x)	((x) << 24)
#define SPI_CTAR_PCSSCR(x)	(((x) & 0x00000003) << 22)
#define SPI_CTAR_PASC(x)	(((x) & 0x00000003) << 20)
#define SPI_CTAR_PDT(x)	(((x) & 0x00000003) << 18)
#define SPI_CTAR_PBR(x)	(((x) & 0x00000003) << 16)
#define SPI_CTAR_CSSCK(x)	(((x) & 0x0000000f) << 12)
#define SPI_CTAR_ASC(x)	(((x) & 0x0000000f) << 8)
#define SPI_CTAR_DT(x)		(((x) & 0x0000000f) << 4)
#define SPI_CTAR_BR(x)		((x) & 0x0000000f)

#define SPI_CTAR0_SLAVE	0x0c

#define SPI_SR			0x2c
#define SPI_SR_EOQF		0x10000000

#define SPI_RSER		0x30
#define SPI_RSER_EOQFE		0x10000000

#define SPI_PUSHR		0x34
#define SPI_PUSHR_CONT		(1 << 31)
#define SPI_PUSHR_CTAS(x)	(((x) & 0x00000007) << 28)
#define SPI_PUSHR_EOQ		(1 << 27)
#define SPI_PUSHR_CTCNT	(1 << 26)
#define SPI_PUSHR_PCS(x)	(((1 << x) & 0x0000003f) << 16)
#define SPI_PUSHR_TXDATA(x)	((x) & 0x0000ffff)

#define SPI_PUSHR_SLAVE	0x34

#define SPI_POPR		0x38
#define SPI_POPR_RXDATA(x)	((x) & 0x0000ffff)

#define SPI_TXFR0		0x3c
#define SPI_TXFR1		0x40
#define SPI_TXFR2		0x44
#define SPI_TXFR3		0x48
#define SPI_RXFR0		0x7c
#define SPI_RXFR1		0x80
#define SPI_RXFR2		0x84
#define SPI_RXFR3		0x88

#define SPI_FRAME_BITS(bits)	SPI_CTAR_FMSZ((bits) - 1)
#define SPI_FRAME_BITS_MASK	SPI_CTAR_FMSZ(0xf)
#define SPI_FRAME_BITS_16	SPI_CTAR_FMSZ(0xf)
#define SPI_FRAME_BITS_8	SPI_CTAR_FMSZ(0x7)

#define SPI_CS_INIT		0x01
#define SPI_CS_ASSERT		0x02
#define SPI_CS_DROP		0x04

struct chip_data {
	u32 mcr_val;
	u32 ctar_val;
	u16 void_write_data;
};

struct fsl_dspi {
	struct spi_bitbang	bitbang;
	struct platform_device	*pdev;

	void __iomem		*base;
	int			irq;
	struct clk 		*clk;

	struct spi_transfer 	*cur_transfer;
	struct chip_data	*cur_chip;
	size_t			len;
	void			*tx;
	void			*tx_end;
	void			*rx;
	void			*rx_end;
	char			dataflags;
	u8			cs;
	u16			void_write_data;

	wait_queue_head_t 	waitq;
	u32 			waitflags;
};

static inline int is_double_byte_mode(struct fsl_dspi *dspi)
{
	return ((readl(dspi->base + SPI_CTAR(dspi->cs)) & SPI_FRAME_BITS_MASK)
			== SPI_FRAME_BITS(8)) ? 0 : 1;
}

static void set_bit_mode(struct fsl_dspi *dspi, unsigned char bits)
{
	u32 temp;

	temp = readl(dspi->base + SPI_CTAR(dspi->cs));
	temp &= ~SPI_FRAME_BITS_MASK;
	temp |= SPI_FRAME_BITS(bits);
	writel(temp, dspi->base + SPI_CTAR(dspi->cs));
}

static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
		unsigned long clkrate)
{
	/* Valid baud rate pre-scaler values */
	int pbr_tbl[4] = {2, 3, 5, 7};
	int brs[16] = {	2,	4,	6,	8,
		16,	32,	64,	128,
		256,	512,	1024,	2048,
		4096,	8192,	16384,	32768 };
	int temp, i = 0, j = 0;

	temp = clkrate / 2 / speed_hz;

	for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
		for (j = 0; j < ARRAY_SIZE(brs); j++) {
			if (pbr_tbl[i] * brs[j] >= temp) {
				*pbr = i;
				*br = j;
				return;
			}
		}

	pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld\
		,we use the max prescaler value.\n", speed_hz, clkrate);
	*pbr = ARRAY_SIZE(pbr_tbl) - 1;
	*br =  ARRAY_SIZE(brs) - 1;
}

static int dspi_transfer_write(struct fsl_dspi *dspi)
{
	int tx_count = 0;
	int tx_word;
	u16 d16;
	u8  d8;
	u32 dspi_pushr = 0;
	int first = 1;

	tx_word = is_double_byte_mode(dspi);

	/* If we are in word mode, but only have a single byte to transfer
	 * then switch to byte mode temporarily.  Will switch back at the
	 * end of the transfer.
	 */
	if (tx_word && (dspi->len == 1)) {
		dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
		set_bit_mode(dspi, 8);
		tx_word = 0;
	}

	while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
		if (tx_word) {
			if (dspi->len == 1)
				break;

			if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
				d16 = *(u16 *)dspi->tx;
				dspi->tx += 2;
			} else {
				d16 = dspi->void_write_data;
			}

			dspi_pushr = SPI_PUSHR_TXDATA(d16) |
				SPI_PUSHR_PCS(dspi->cs) |
				SPI_PUSHR_CTAS(dspi->cs) |
				SPI_PUSHR_CONT;

			dspi->len -= 2;
		} else {
			if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {

				d8 = *(u8 *)dspi->tx;
				dspi->tx++;
			} else {
				d8 = (u8)dspi->void_write_data;
			}

			dspi_pushr = SPI_PUSHR_TXDATA(d8) |
				SPI_PUSHR_PCS(dspi->cs) |
				SPI_PUSHR_CTAS(dspi->cs) |
				SPI_PUSHR_CONT;

			dspi->len--;
		}

		if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) {
			/* last transfer in the transfer */
			dspi_pushr |= SPI_PUSHR_EOQ;
		} else if (tx_word && (dspi->len == 1))
			dspi_pushr |= SPI_PUSHR_EOQ;

		if (first) {
			first = 0;
			dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */
		}

		writel(dspi_pushr, dspi->base + SPI_PUSHR);
		tx_count++;
	}

	return tx_count * (tx_word + 1);
}

static int dspi_transfer_read(struct fsl_dspi *dspi)
{
	int rx_count = 0;
	int rx_word = is_double_byte_mode(dspi);
	u16 d;
	while ((dspi->rx < dspi->rx_end)
			&& (rx_count < DSPI_FIFO_SIZE)) {
		if (rx_word) {
			if ((dspi->rx_end - dspi->rx) == 1)
				break;

			d = SPI_POPR_RXDATA(readl(dspi->base + SPI_POPR));

			if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
				*(u16 *)dspi->rx = d;
			dspi->rx += 2;

		} else {
			d = SPI_POPR_RXDATA(readl(dspi->base + SPI_POPR));
			if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
				*(u8 *)dspi->rx = d;
			dspi->rx++;
		}
		rx_count++;
	}

	return rx_count;
}

static int dspi_txrx_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
	dspi->cur_transfer = t;
	dspi->cur_chip = spi_get_ctldata(spi);
	dspi->cs = spi->chip_select;
	dspi->void_write_data = dspi->cur_chip->void_write_data;

	dspi->dataflags = 0;
	dspi->tx = (void *)t->tx_buf;
	dspi->tx_end = dspi->tx + t->len;
	dspi->rx = t->rx_buf;
	dspi->rx_end = dspi->rx + t->len;
	dspi->len = t->len;

	if (!dspi->rx)
		dspi->dataflags |= TRAN_STATE_RX_VOID;

	if (!dspi->tx)
		dspi->dataflags |= TRAN_STATE_TX_VOID;

	writel(dspi->cur_chip->mcr_val, dspi->base + SPI_MCR);
	writel(dspi->cur_chip->ctar_val, dspi->base + SPI_CTAR(dspi->cs));
	writel(SPI_RSER_EOQFE, dspi->base + SPI_RSER);

	if (t->speed_hz)
		writel(dspi->cur_chip->ctar_val,
				dspi->base + SPI_CTAR(dspi->cs));

	dspi_transfer_write(dspi);

	if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
		dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
	dspi->waitflags = 0;

	return t->len - dspi->len;
}

static void dspi_chipselect(struct spi_device *spi, int value)
{
	struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
	u32 pushr = readl(dspi->base + SPI_PUSHR);

	switch (value) {
	case BITBANG_CS_ACTIVE:
		pushr |= SPI_PUSHR_CONT;
		break;
	case BITBANG_CS_INACTIVE:
		pushr &= ~SPI_PUSHR_CONT;
		break;
	}

	writel(pushr, dspi->base + SPI_PUSHR);
}

static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct chip_data *chip;
	struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
	unsigned char br = 0, pbr = 0, fmsz = 0;

	/* Only alloc on first setup */
	chip = spi_get_ctldata(spi);
	if (chip == NULL) {
		chip = kcalloc(1, sizeof(struct chip_data), GFP_KERNEL);
		if (!chip)
			return -ENOMEM;
	}

	chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
		SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
	if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
		fmsz = spi->bits_per_word - 1;
	} else {
		pr_err("Invalid wordsize\n");
		kfree(chip);
		return -ENODEV;
	}

	chip->void_write_data = 0;

	hz_to_spi_baud(&pbr, &br,
			spi->max_speed_hz, clk_get_rate(dspi->clk));

	chip->ctar_val =  SPI_CTAR_FMSZ(fmsz)
		| SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
		| SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
		| SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
		| SPI_CTAR_PBR(pbr)
		| SPI_CTAR_BR(br);

	spi_set_ctldata(spi, chip);

	return 0;
}

static int dspi_setup(struct spi_device *spi)
{
	if (!spi->max_speed_hz)
		return -EINVAL;

	return dspi_setup_transfer(spi, NULL);
}

static irqreturn_t dspi_interrupt(int irq, void *dev_id)
{
	struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;

	writel(SPI_SR_EOQF, dspi->base + SPI_SR);

	dspi_transfer_read(dspi);

	if (!dspi->len) {
		if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
			set_bit_mode(dspi, 16);
		dspi->waitflags = 1;
		wake_up_interruptible(&dspi->waitq);
	} else {
		dspi_transfer_write(dspi);

		return IRQ_HANDLED;
	}

	return IRQ_HANDLED;
}

static struct of_device_id fsl_dspi_dt_ids[] = {
	{ .compatible = "fsl,vf610-dspi", .data = NULL, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);

#ifdef CONFIG_PM_SLEEP
static int dspi_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct fsl_dspi *dspi = spi_master_get_devdata(master);

	spi_master_suspend(master);
	clk_disable_unprepare(dspi->clk);

	return 0;
}

static int dspi_resume(struct device *dev)
{

	struct spi_master *master = dev_get_drvdata(dev);
	struct fsl_dspi *dspi = spi_master_get_devdata(master);

	clk_prepare_enable(dspi->clk);
	spi_master_resume(master);

	return 0;
}
#endif /* CONFIG_PM_SLEEP */

static const struct dev_pm_ops dspi_pm = {
	SET_SYSTEM_SLEEP_PM_OPS(dspi_suspend, dspi_resume)
};

static int dspi_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct spi_master *master;
	struct fsl_dspi *dspi;
	struct resource *res;
	int ret = 0, cs_num, bus_num;

	master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
	if (!master)
		return -ENOMEM;

	dspi = spi_master_get_devdata(master);
	dspi->pdev = pdev;
	dspi->bitbang.master = master;
	dspi->bitbang.chipselect = dspi_chipselect;
	dspi->bitbang.setup_transfer = dspi_setup_transfer;
	dspi->bitbang.txrx_bufs = dspi_txrx_transfer;
	dspi->bitbang.master->setup = dspi_setup;
	dspi->bitbang.master->dev.of_node = pdev->dev.of_node;

	master->mode_bits = SPI_CPOL | SPI_CPHA;
	master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) |
					SPI_BPW_MASK(16);

	ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
	if (ret < 0) {
		dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
		goto out_master_put;
	}
	master->num_chipselect = cs_num;

	ret = of_property_read_u32(np, "bus-num", &bus_num);
	if (ret < 0) {
		dev_err(&pdev->dev, "can't get bus-num\n");
		goto out_master_put;
	}
	master->bus_num = bus_num;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	dspi->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(dspi->base)) {
		ret = PTR_ERR(dspi->base);
		goto out_master_put;
	}

	dspi->irq = platform_get_irq(pdev, 0);
	if (dspi->irq < 0) {
		dev_err(&pdev->dev, "can't get platform irq\n");
		ret = dspi->irq;
		goto out_master_put;
	}

	ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
			pdev->name, dspi);
	if (ret < 0) {
		dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
		goto out_master_put;
	}

	dspi->clk = devm_clk_get(&pdev->dev, "dspi");
	if (IS_ERR(dspi->clk)) {
		ret = PTR_ERR(dspi->clk);
		dev_err(&pdev->dev, "unable to get clock\n");
		goto out_master_put;
	}
	clk_prepare_enable(dspi->clk);

	init_waitqueue_head(&dspi->waitq);
	platform_set_drvdata(pdev, dspi);

	ret = spi_bitbang_start(&dspi->bitbang);
	if (ret != 0) {
		dev_err(&pdev->dev, "Problem registering DSPI master\n");
		goto out_clk_put;
	}

	pr_info(KERN_INFO "Freescale DSPI master initialized\n");
	return ret;

out_clk_put:
	clk_disable_unprepare(dspi->clk);
out_master_put:
	spi_master_put(master);

	return ret;
}

static int dspi_remove(struct platform_device *pdev)
{
	struct fsl_dspi *dspi = platform_get_drvdata(pdev);

	/* Disconnect from the SPI framework */
	spi_bitbang_stop(&dspi->bitbang);
	clk_disable_unprepare(dspi->clk);
	spi_master_put(dspi->bitbang.master);

	return 0;
}

static struct platform_driver fsl_dspi_driver = {
	.driver.name    = DRIVER_NAME,
	.driver.of_match_table = fsl_dspi_dt_ids,
	.driver.owner   = THIS_MODULE,
	.driver.pm = &dspi_pm,
	.probe          = dspi_probe,
	.remove		= dspi_remove,
};
module_platform_driver(fsl_dspi_driver);

MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
349ad66c CF	1	/*
	2	* drivers/spi/spi-fsl-dspi.c
	3	*
	4	* Copyright 2013 Freescale Semiconductor, Inc.
	5	*
	6	* Freescale DSPI driver
	7	* This file contains a driver for the Freescale DSPI
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/errno.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/sched.h>
	22	#include <linux/delay.h>
	23	#include <linux/io.h>
	24	#include <linux/clk.h>
	25	#include <linux/err.h>
	26	#include <linux/spi/spi.h>
	27	#include <linux/spi/spi_bitbang.h>
	28	#include <linux/pm_runtime.h>
	29	#include <linux/of.h>
	30	#include <linux/of_device.h>
	31
	32	#define DRIVER_NAME "fsl-dspi"
	33
	34	#define TRAN_STATE_RX_VOID 0x01
	35	#define TRAN_STATE_TX_VOID 0x02
	36	#define TRAN_STATE_WORD_ODD_NUM 0x04
	37
	38	#define DSPI_FIFO_SIZE 4
	39
	40	#define SPI_MCR 0x00
	41	#define SPI_MCR_MASTER (1 << 31)
	42	#define SPI_MCR_PCSIS (0x3F << 16)
	43	#define SPI_MCR_CLR_TXF (1 << 11)
	44	#define SPI_MCR_CLR_RXF (1 << 10)
	45
	46	#define SPI_TCR 0x08
	47
	48	#define SPI_CTAR(x) (0x0c + (x * 4))
	49	#define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27)
	50	#define SPI_CTAR_CPOL(x) ((x) << 26)
	51	#define SPI_CTAR_CPHA(x) ((x) << 25)
	52	#define SPI_CTAR_LSBFE(x) ((x) << 24)
	53	#define SPI_CTAR_PCSSCR(x) (((x) & 0x00000003) << 22)
	54	#define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20)
	55	#define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
	56	#define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
	57	#define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12)
	58	#define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
	59	#define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4)
	60	#define SPI_CTAR_BR(x) ((x) & 0x0000000f)
	61
	62	#define SPI_CTAR0_SLAVE 0x0c
	63
	64	#define SPI_SR 0x2c
65	#define SPI_SR_EOQF 0x10000000
66
67	#define SPI_RSER 0x30
68	#define SPI_RSER_EOQFE 0x10000000
69
70	#define SPI_PUSHR 0x34
71	#define SPI_PUSHR_CONT (1 << 31)
72	#define SPI_PUSHR_CTAS(x) (((x) & 0x00000007) << 28)
73	#define SPI_PUSHR_EOQ (1 << 27)
74	#define SPI_PUSHR_CTCNT (1 << 26)
75	#define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16)
76	#define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff)
77
78	#define SPI_PUSHR_SLAVE 0x34
79
80	#define SPI_POPR 0x38
81	#define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff)
82
83	#define SPI_TXFR0 0x3c
84	#define SPI_TXFR1 0x40
85	#define SPI_TXFR2 0x44
86	#define SPI_TXFR3 0x48
87	#define SPI_RXFR0 0x7c
88	#define SPI_RXFR1 0x80
89	#define SPI_RXFR2 0x84
90	#define SPI_RXFR3 0x88
91
92	#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
93	#define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf)
94	#define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf)
95	#define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7)
96
97	#define SPI_CS_INIT 0x01
98	#define SPI_CS_ASSERT 0x02
99	#define SPI_CS_DROP 0x04
100
101	struct chip_data {
102	u32 mcr_val;
103	u32 ctar_val;
104	u16 void_write_data;
105	};
106
107	struct fsl_dspi {
108	struct spi_bitbang bitbang;
109	struct platform_device *pdev;
110
2ef3599d	111	void __iomem *base;
349ad66c CF	112	int irq;
	113	struct clk *clk;
	114
	115	struct spi_transfer *cur_transfer;
	116	struct chip_data *cur_chip;
	117	size_t len;
	118	void *tx;
	119	void *tx_end;
	120	void *rx;
	121	void *rx_end;
	122	char dataflags;
	123	u8 cs;
	124	u16 void_write_data;
	125
	126	wait_queue_head_t waitq;
	127	u32 waitflags;
	128	};
	129
	130	static inline int is_double_byte_mode(struct fsl_dspi *dspi)
	131	{
	132	return ((readl(dspi->base + SPI_CTAR(dspi->cs)) & SPI_FRAME_BITS_MASK)
	133	== SPI_FRAME_BITS(8)) ? 0 : 1;
	134	}
	135
	136	static void set_bit_mode(struct fsl_dspi *dspi, unsigned char bits)
	137	{
	138	u32 temp;
	139
	140	temp = readl(dspi->base + SPI_CTAR(dspi->cs));
	141	temp &= ~SPI_FRAME_BITS_MASK;
	142	temp \|= SPI_FRAME_BITS(bits);
	143	writel(temp, dspi->base + SPI_CTAR(dspi->cs));
	144	}
	145
	146	static void hz_to_spi_baud(char pbr, char br, int speed_hz,
	147	unsigned long clkrate)
	148	{
	149	/* Valid baud rate pre-scaler values */
	150	int pbr_tbl[4] = {2, 3, 5, 7};
	151	int brs[16] = { 2, 4, 6, 8,
	152	16, 32, 64, 128,
	153	256, 512, 1024, 2048,
	154	4096, 8192, 16384, 32768 };
	155	int temp, i = 0, j = 0;
	156
	157	temp = clkrate / 2 / speed_hz;
	158
	159	for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
	160	for (j = 0; j < ARRAY_SIZE(brs); j++) {
	161	if (pbr_tbl[i] * brs[j] >= temp) {
	162	*pbr = i;
	163	*br = j;
	164	return;
	165	}
	166	}
	167
b444d1df	168	pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld\
349ad66c CF	169	,we use the max prescaler value.\n", speed_hz, clkrate);
	170	*pbr = ARRAY_SIZE(pbr_tbl) - 1;
	171	*br = ARRAY_SIZE(brs) - 1;
	172	}
	173
	174	static int dspi_transfer_write(struct fsl_dspi *dspi)
	175	{
	176	int tx_count = 0;
	177	int tx_word;
	178	u16 d16;
	179	u8 d8;
	180	u32 dspi_pushr = 0;
	181	int first = 1;
	182
	183	tx_word = is_double_byte_mode(dspi);
	184
	185	/* If we are in word mode, but only have a single byte to transfer
	186	* then switch to byte mode temporarily. Will switch back at the
	187	* end of the transfer.
	188	*/
	189	if (tx_word && (dspi->len == 1)) {
	190	dspi->dataflags \|= TRAN_STATE_WORD_ODD_NUM;
	191	set_bit_mode(dspi, 8);
	192	tx_word = 0;
	193	}
	194
	195	while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
	196	if (tx_word) {
	197	if (dspi->len == 1)
	198	break;
	199
	200	if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
	201	d16 = (u16 )dspi->tx;
	202	dspi->tx += 2;
	203	} else {
	204	d16 = dspi->void_write_data;
	205	}
	206
	207	dspi_pushr = SPI_PUSHR_TXDATA(d16) \|
	208	SPI_PUSHR_PCS(dspi->cs) \|
	209	SPI_PUSHR_CTAS(dspi->cs) \|
	210	SPI_PUSHR_CONT;
	211
	212	dspi->len -= 2;
	213	} else {
	214	if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
	215
	216	d8 = (u8 )dspi->tx;
	217	dspi->tx++;
	218	} else {
	219	d8 = (u8)dspi->void_write_data;
	220	}
	221
	222	dspi_pushr = SPI_PUSHR_TXDATA(d8) \|
	223	SPI_PUSHR_PCS(dspi->cs) \|
	224	SPI_PUSHR_CTAS(dspi->cs) \|
	225	SPI_PUSHR_CONT;
	226
	227	dspi->len--;
	228	}
	229
	230	if (dspi->len == 0 \|\| tx_count == DSPI_FIFO_SIZE - 1) {
	231	/* last transfer in the transfer */
	232	dspi_pushr \|= SPI_PUSHR_EOQ;
233	} else if (tx_word && (dspi->len == 1))
234	dspi_pushr \|= SPI_PUSHR_EOQ;
235
236	if (first) {
237	first = 0;
238	dspi_pushr \|= SPI_PUSHR_CTCNT; /* clear counter */
239	}
240
241	writel(dspi_pushr, dspi->base + SPI_PUSHR);
242	tx_count++;
243	}
244
245	return tx_count * (tx_word + 1);
246	}
247
248	static int dspi_transfer_read(struct fsl_dspi *dspi)
249	{
250	int rx_count = 0;
251	int rx_word = is_double_byte_mode(dspi);
252	u16 d;
253	while ((dspi->rx < dspi->rx_end)
254	&& (rx_count < DSPI_FIFO_SIZE)) {
255	if (rx_word) {
256	if ((dspi->rx_end - dspi->rx) == 1)
257	break;
258
259	d = SPI_POPR_RXDATA(readl(dspi->base + SPI_POPR));
260
261	if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
262	(u16 )dspi->rx = d;
263	dspi->rx += 2;
264
265	} else {
266	d = SPI_POPR_RXDATA(readl(dspi->base + SPI_POPR));
267	if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
268	(u8 )dspi->rx = d;
269	dspi->rx++;
270	}
271	rx_count++;
272	}
273
274	return rx_count;
275	}
276
277	static int dspi_txrx_transfer(struct spi_device spi, struct spi_transfer t)
278	{
279	struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
280	dspi->cur_transfer = t;
281	dspi->cur_chip = spi_get_ctldata(spi);
282	dspi->cs = spi->chip_select;
283	dspi->void_write_data = dspi->cur_chip->void_write_data;
284
285	dspi->dataflags = 0;
286	dspi->tx = (void *)t->tx_buf;
287	dspi->tx_end = dspi->tx + t->len;
288	dspi->rx = t->rx_buf;
289	dspi->rx_end = dspi->rx + t->len;
290	dspi->len = t->len;
291
292	if (!dspi->rx)
293	dspi->dataflags \|= TRAN_STATE_RX_VOID;
294
295	if (!dspi->tx)
296	dspi->dataflags \|= TRAN_STATE_TX_VOID;
297
298	writel(dspi->cur_chip->mcr_val, dspi->base + SPI_MCR);
299	writel(dspi->cur_chip->ctar_val, dspi->base + SPI_CTAR(dspi->cs));
300	writel(SPI_RSER_EOQFE, dspi->base + SPI_RSER);
301
302	if (t->speed_hz)
303	writel(dspi->cur_chip->ctar_val,
304	dspi->base + SPI_CTAR(dspi->cs));
305
306	dspi_transfer_write(dspi);
307
308	if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
309	dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
310	dspi->waitflags = 0;
311
312	return t->len - dspi->len;
313	}
314
315	static void dspi_chipselect(struct spi_device *spi, int value)
316	{
317	struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
318	u32 pushr = readl(dspi->base + SPI_PUSHR);
319
320	switch (value) {
321	case BITBANG_CS_ACTIVE:
322	pushr \|= SPI_PUSHR_CONT;
e07725be	323	break;
349ad66c CF	324	case BITBANG_CS_INACTIVE:
349ad66c CF	325	pushr &= ~SPI_PUSHR_CONT;
e07725be	326	break;
349ad66c CF	327	}
	328
	329	writel(pushr, dspi->base + SPI_PUSHR);
	330	}
	331
	332	static int dspi_setup_transfer(struct spi_device spi, struct spi_transfer t)
	333	{
	334	struct chip_data *chip;
	335	struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
	336	unsigned char br = 0, pbr = 0, fmsz = 0;
	337
	338	/* Only alloc on first setup */
	339	chip = spi_get_ctldata(spi);
	340	if (chip == NULL) {
	341	chip = kcalloc(1, sizeof(struct chip_data), GFP_KERNEL);
	342	if (!chip)
	343	return -ENOMEM;
	344	}
	345
	346	chip->mcr_val = SPI_MCR_MASTER \| SPI_MCR_PCSIS \|
	347	SPI_MCR_CLR_TXF \| SPI_MCR_CLR_RXF;
	348	if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
	349	fmsz = spi->bits_per_word - 1;
	350	} else {
	351	pr_err("Invalid wordsize\n");
	352	kfree(chip);
	353	return -ENODEV;
	354	}
	355
	356	chip->void_write_data = 0;
	357
	358	hz_to_spi_baud(&pbr, &br,
	359	spi->max_speed_hz, clk_get_rate(dspi->clk));
	360
	361	chip->ctar_val = SPI_CTAR_FMSZ(fmsz)
	362	\| SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
	363	\| SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
	364	\| SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
	365	\| SPI_CTAR_PBR(pbr)
	366	\| SPI_CTAR_BR(br);
	367
	368	spi_set_ctldata(spi, chip);
	369
	370	return 0;
	371	}
	372
	373	static int dspi_setup(struct spi_device *spi)
	374	{
	375	if (!spi->max_speed_hz)
	376	return -EINVAL;
	377
349ad66c CF	378	return dspi_setup_transfer(spi, NULL);
	379	}
	380
	381	static irqreturn_t dspi_interrupt(int irq, void *dev_id)
	382	{
	383	struct fsl_dspi dspi = (struct fsl_dspi )dev_id;
	384
	385	writel(SPI_SR_EOQF, dspi->base + SPI_SR);
	386
	387	dspi_transfer_read(dspi);
	388
	389	if (!dspi->len) {
	390	if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
	391	set_bit_mode(dspi, 16);
	392	dspi->waitflags = 1;
	393	wake_up_interruptible(&dspi->waitq);
	394	} else {
	395	dspi_transfer_write(dspi);
	396
	397	return IRQ_HANDLED;
	398	}
	399
	400	return IRQ_HANDLED;
	401	}
	402
	403	static struct of_device_id fsl_dspi_dt_ids[] = {
	404	{ .compatible = "fsl,vf610-dspi", .data = NULL, },
	405	{ /* sentinel */ }
	406	};
	407	MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
	408
	409	#ifdef CONFIG_PM_SLEEP
	410	static int dspi_suspend(struct device *dev)
	411	{
	412	struct spi_master *master = dev_get_drvdata(dev);
	413	struct fsl_dspi *dspi = spi_master_get_devdata(master);
	414
	415	spi_master_suspend(master);
	416	clk_disable_unprepare(dspi->clk);
	417
	418	return 0;
	419	}
	420
	421	static int dspi_resume(struct device *dev)
	422	{
	423
	424	struct spi_master *master = dev_get_drvdata(dev);
	425	struct fsl_dspi *dspi = spi_master_get_devdata(master);
	426
	427	clk_prepare_enable(dspi->clk);
	428	spi_master_resume(master);
	429
	430	return 0;
	431	}
	432	#endif /* CONFIG_PM_SLEEP */
	433
	434	static const struct dev_pm_ops dspi_pm = {
	435	SET_SYSTEM_SLEEP_PM_OPS(dspi_suspend, dspi_resume)
	436	};
	437
	438	static int dspi_probe(struct platform_device *pdev)
	439	{
	440	struct device_node *np = pdev->dev.of_node;
	441	struct spi_master *master;
442	struct fsl_dspi *dspi;
443	struct resource *res;
444	int ret = 0, cs_num, bus_num;
445
446	master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
447	if (!master)
448	return -ENOMEM;
449
450	dspi = spi_master_get_devdata(master);
451	dspi->pdev = pdev;
94c69f76	452	dspi->bitbang.master = master;
349ad66c CF	453	dspi->bitbang.chipselect = dspi_chipselect;
	454	dspi->bitbang.setup_transfer = dspi_setup_transfer;
	455	dspi->bitbang.txrx_bufs = dspi_txrx_transfer;
	456	dspi->bitbang.master->setup = dspi_setup;
	457	dspi->bitbang.master->dev.of_node = pdev->dev.of_node;
	458
	459	master->mode_bits = SPI_CPOL \| SPI_CPHA;
	460	master->bits_per_word_mask = SPI_BPW_MASK(4) \| SPI_BPW_MASK(8) \|
	461	SPI_BPW_MASK(16);
	462
	463	ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
	464	if (ret < 0) {
	465	dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
	466	goto out_master_put;
	467	}
	468	master->num_chipselect = cs_num;
	469
	470	ret = of_property_read_u32(np, "bus-num", &bus_num);
	471	if (ret < 0) {
	472	dev_err(&pdev->dev, "can't get bus-num\n");
	473	goto out_master_put;
	474	}
	475	master->bus_num = bus_num;
	476
	477	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
349ad66c	478	dspi->base = devm_ioremap_resource(&pdev->dev, res);
272bfbd5 WY	479	if (IS_ERR(dspi->base)) {
272bfbd5 WY	480	ret = PTR_ERR(dspi->base);
349ad66c CF	481	goto out_master_put;
	482	}
	483
	484	dspi->irq = platform_get_irq(pdev, 0);
	485	if (dspi->irq < 0) {
	486	dev_err(&pdev->dev, "can't get platform irq\n");
	487	ret = dspi->irq;
	488	goto out_master_put;
	489	}
	490
	491	ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
	492	pdev->name, dspi);
	493	if (ret < 0) {
	494	dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
	495	goto out_master_put;
	496	}
	497
	498	dspi->clk = devm_clk_get(&pdev->dev, "dspi");
	499	if (IS_ERR(dspi->clk)) {
	500	ret = PTR_ERR(dspi->clk);
	501	dev_err(&pdev->dev, "unable to get clock\n");
	502	goto out_master_put;
	503	}
	504	clk_prepare_enable(dspi->clk);
	505
	506	init_waitqueue_head(&dspi->waitq);
	507	platform_set_drvdata(pdev, dspi);
	508
	509	ret = spi_bitbang_start(&dspi->bitbang);
	510	if (ret != 0) {
	511	dev_err(&pdev->dev, "Problem registering DSPI master\n");
	512	goto out_clk_put;
	513	}
	514
	515	pr_info(KERN_INFO "Freescale DSPI master initialized\n");
	516	return ret;
	517
	518	out_clk_put:
	519	clk_disable_unprepare(dspi->clk);
	520	out_master_put:
	521	spi_master_put(master);
349ad66c CF	522
	523	return ret;
	524	}
	525
	526	static int dspi_remove(struct platform_device *pdev)
	527	{
	528	struct fsl_dspi *dspi = platform_get_drvdata(pdev);
	529
	530	/* Disconnect from the SPI framework */
	531	spi_bitbang_stop(&dspi->bitbang);
05209f45	532	clk_disable_unprepare(dspi->clk);
349ad66c CF	533	spi_master_put(dspi->bitbang.master);
	534
	535	return 0;
	536	}
	537
	538	static struct platform_driver fsl_dspi_driver = {
	539	.driver.name = DRIVER_NAME,
	540	.driver.of_match_table = fsl_dspi_dt_ids,
	541	.driver.owner = THIS_MODULE,
	542	.driver.pm = &dspi_pm,
	543	.probe = dspi_probe,
	544	.remove = dspi_remove,
	545	};
	546	module_platform_driver(fsl_dspi_driver);
	547
	548	MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
b444d1df	549	MODULE_LICENSE("GPL");
349ad66c	550	MODULE_ALIAS("platform:" DRIVER_NAME);