]>
Commit | Line | Data |
---|---|---|
349ad66c CF |
1 | /* |
2 | * drivers/spi/spi-fsl-dspi.c | |
3 | * | |
4 | * Copyright 2013 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * Freescale DSPI driver | |
7 | * This file contains a driver for the Freescale DSPI | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | */ | |
15 | ||
a3108360 XL |
16 | #include <linux/clk.h> |
17 | #include <linux/delay.h> | |
90ba3703 SM |
18 | #include <linux/dmaengine.h> |
19 | #include <linux/dma-mapping.h> | |
a3108360 XL |
20 | #include <linux/err.h> |
21 | #include <linux/errno.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
349ad66c | 24 | #include <linux/kernel.h> |
95bf15f3 | 25 | #include <linux/math64.h> |
349ad66c | 26 | #include <linux/module.h> |
a3108360 XL |
27 | #include <linux/of.h> |
28 | #include <linux/of_device.h> | |
432a17d7 | 29 | #include <linux/pinctrl/consumer.h> |
349ad66c | 30 | #include <linux/platform_device.h> |
a3108360 | 31 | #include <linux/pm_runtime.h> |
1acbdeb9 | 32 | #include <linux/regmap.h> |
349ad66c | 33 | #include <linux/sched.h> |
349ad66c | 34 | #include <linux/spi/spi.h> |
ec7ed770 | 35 | #include <linux/spi/spi-fsl-dspi.h> |
349ad66c | 36 | #include <linux/spi/spi_bitbang.h> |
95bf15f3 | 37 | #include <linux/time.h> |
349ad66c CF |
38 | |
39 | #define DRIVER_NAME "fsl-dspi" | |
40 | ||
349ad66c | 41 | #define DSPI_FIFO_SIZE 4 |
90ba3703 | 42 | #define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024) |
349ad66c CF |
43 | |
44 | #define SPI_MCR 0x00 | |
45 | #define SPI_MCR_MASTER (1 << 31) | |
46 | #define SPI_MCR_PCSIS (0x3F << 16) | |
47 | #define SPI_MCR_CLR_TXF (1 << 11) | |
48 | #define SPI_MCR_CLR_RXF (1 << 10) | |
3e7cc625 | 49 | #define SPI_MCR_XSPI (1 << 3) |
349ad66c CF |
50 | |
51 | #define SPI_TCR 0x08 | |
c042af95 | 52 | #define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16) |
349ad66c | 53 | |
5cc7b047 | 54 | #define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4)) |
349ad66c CF |
55 | #define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27) |
56 | #define SPI_CTAR_CPOL(x) ((x) << 26) | |
57 | #define SPI_CTAR_CPHA(x) ((x) << 25) | |
58 | #define SPI_CTAR_LSBFE(x) ((x) << 24) | |
95bf15f3 | 59 | #define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22) |
349ad66c CF |
60 | #define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20) |
61 | #define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18) | |
62 | #define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16) | |
63 | #define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12) | |
64 | #define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8) | |
65 | #define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4) | |
66 | #define SPI_CTAR_BR(x) ((x) & 0x0000000f) | |
95bf15f3 | 67 | #define SPI_CTAR_SCALE_BITS 0xf |
349ad66c CF |
68 | |
69 | #define SPI_CTAR0_SLAVE 0x0c | |
70 | ||
71 | #define SPI_SR 0x2c | |
72 | #define SPI_SR_EOQF 0x10000000 | |
d1f4a38c | 73 | #define SPI_SR_TCFQF 0x80000000 |
5ee67b58 | 74 | #define SPI_SR_CLEAR 0xdaad0000 |
349ad66c | 75 | |
90ba3703 SM |
76 | #define SPI_RSER_TFFFE BIT(25) |
77 | #define SPI_RSER_TFFFD BIT(24) | |
78 | #define SPI_RSER_RFDFE BIT(17) | |
79 | #define SPI_RSER_RFDFD BIT(16) | |
349ad66c CF |
80 | |
81 | #define SPI_RSER 0x30 | |
82 | #define SPI_RSER_EOQFE 0x10000000 | |
d1f4a38c | 83 | #define SPI_RSER_TCFQE 0x80000000 |
349ad66c CF |
84 | |
85 | #define SPI_PUSHR 0x34 | |
9e1dc9bd EH |
86 | #define SPI_PUSHR_CMD_CONT (1 << 15) |
87 | #define SPI_PUSHR_CONT (SPI_PUSHR_CMD_CONT << 16) | |
88 | #define SPI_PUSHR_CMD_CTAS(x) (((x) & 0x0003) << 12) | |
89 | #define SPI_PUSHR_CTAS(x) (SPI_PUSHR_CMD_CTAS(x) << 16) | |
90 | #define SPI_PUSHR_CMD_EOQ (1 << 11) | |
91 | #define SPI_PUSHR_EOQ (SPI_PUSHR_CMD_EOQ << 16) | |
92 | #define SPI_PUSHR_CMD_CTCNT (1 << 10) | |
93 | #define SPI_PUSHR_CTCNT (SPI_PUSHR_CMD_CTCNT << 16) | |
94 | #define SPI_PUSHR_CMD_PCS(x) ((1 << x) & 0x003f) | |
95 | #define SPI_PUSHR_PCS(x) (SPI_PUSHR_CMD_PCS(x) << 16) | |
349ad66c CF |
96 | #define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff) |
97 | ||
98 | #define SPI_PUSHR_SLAVE 0x34 | |
99 | ||
100 | #define SPI_POPR 0x38 | |
101 | #define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff) | |
102 | ||
103 | #define SPI_TXFR0 0x3c | |
104 | #define SPI_TXFR1 0x40 | |
105 | #define SPI_TXFR2 0x44 | |
106 | #define SPI_TXFR3 0x48 | |
107 | #define SPI_RXFR0 0x7c | |
108 | #define SPI_RXFR1 0x80 | |
109 | #define SPI_RXFR2 0x84 | |
110 | #define SPI_RXFR3 0x88 | |
111 | ||
58ba07ec EH |
112 | #define SPI_CTARE(x) (0x11c + (((x) & 0x3) * 4)) |
113 | #define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16) | |
114 | #define SPI_CTARE_DTCP(x) ((x) & 0x7ff) | |
115 | ||
116 | #define SPI_SREX 0x13c | |
117 | ||
349ad66c CF |
118 | #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1) |
119 | #define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf) | |
120 | #define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf) | |
121 | #define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7) | |
122 | ||
51d583ae EH |
123 | #define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4) |
124 | #define SPI_FRAME_EBITS_MASK SPI_CTARE_FMSZE(1) | |
125 | ||
58ba07ec EH |
126 | /* Register offsets for regmap_pushr */ |
127 | #define PUSHR_CMD 0x0 | |
128 | #define PUSHR_TX 0x2 | |
129 | ||
349ad66c CF |
130 | #define SPI_CS_INIT 0x01 |
131 | #define SPI_CS_ASSERT 0x02 | |
132 | #define SPI_CS_DROP 0x04 | |
133 | ||
90ba3703 SM |
134 | #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000) |
135 | ||
349ad66c | 136 | struct chip_data { |
349ad66c CF |
137 | u32 ctar_val; |
138 | u16 void_write_data; | |
139 | }; | |
140 | ||
d1f4a38c HW |
141 | enum dspi_trans_mode { |
142 | DSPI_EOQ_MODE = 0, | |
143 | DSPI_TCFQ_MODE, | |
90ba3703 | 144 | DSPI_DMA_MODE, |
d1f4a38c HW |
145 | }; |
146 | ||
147 | struct fsl_dspi_devtype_data { | |
148 | enum dspi_trans_mode trans_mode; | |
9419b200 | 149 | u8 max_clock_factor; |
58ba07ec | 150 | bool xspi_mode; |
d1f4a38c HW |
151 | }; |
152 | ||
153 | static const struct fsl_dspi_devtype_data vf610_data = { | |
90ba3703 | 154 | .trans_mode = DSPI_DMA_MODE, |
9419b200 | 155 | .max_clock_factor = 2, |
d1f4a38c HW |
156 | }; |
157 | ||
158 | static const struct fsl_dspi_devtype_data ls1021a_v1_data = { | |
159 | .trans_mode = DSPI_TCFQ_MODE, | |
9419b200 | 160 | .max_clock_factor = 8, |
58ba07ec | 161 | .xspi_mode = true, |
d1f4a38c HW |
162 | }; |
163 | ||
164 | static const struct fsl_dspi_devtype_data ls2085a_data = { | |
165 | .trans_mode = DSPI_TCFQ_MODE, | |
9419b200 | 166 | .max_clock_factor = 8, |
d1f4a38c HW |
167 | }; |
168 | ||
ec7ed770 AD |
169 | static const struct fsl_dspi_devtype_data coldfire_data = { |
170 | .trans_mode = DSPI_EOQ_MODE, | |
171 | .max_clock_factor = 8, | |
172 | }; | |
173 | ||
90ba3703 | 174 | struct fsl_dspi_dma { |
1eaccf21 | 175 | /* Length of transfer in words of DSPI_FIFO_SIZE */ |
90ba3703 SM |
176 | u32 curr_xfer_len; |
177 | ||
178 | u32 *tx_dma_buf; | |
179 | struct dma_chan *chan_tx; | |
180 | dma_addr_t tx_dma_phys; | |
181 | struct completion cmd_tx_complete; | |
182 | struct dma_async_tx_descriptor *tx_desc; | |
183 | ||
184 | u32 *rx_dma_buf; | |
185 | struct dma_chan *chan_rx; | |
186 | dma_addr_t rx_dma_phys; | |
187 | struct completion cmd_rx_complete; | |
188 | struct dma_async_tx_descriptor *rx_desc; | |
189 | }; | |
190 | ||
349ad66c | 191 | struct fsl_dspi { |
9298bc72 | 192 | struct spi_master *master; |
349ad66c CF |
193 | struct platform_device *pdev; |
194 | ||
1acbdeb9 | 195 | struct regmap *regmap; |
58ba07ec | 196 | struct regmap *regmap_pushr; |
349ad66c | 197 | int irq; |
88386e85 | 198 | struct clk *clk; |
349ad66c | 199 | |
88386e85 | 200 | struct spi_transfer *cur_transfer; |
9298bc72 | 201 | struct spi_message *cur_msg; |
349ad66c CF |
202 | struct chip_data *cur_chip; |
203 | size_t len; | |
dadcf4ab | 204 | const void *tx; |
349ad66c CF |
205 | void *rx; |
206 | void *rx_end; | |
349ad66c | 207 | u16 void_write_data; |
9e1dc9bd | 208 | u16 tx_cmd; |
dadcf4ab EH |
209 | u8 bits_per_word; |
210 | u8 bytes_per_word; | |
94b968b5 | 211 | const struct fsl_dspi_devtype_data *devtype_data; |
349ad66c | 212 | |
88386e85 CF |
213 | wait_queue_head_t waitq; |
214 | u32 waitflags; | |
c042af95 | 215 | |
90ba3703 | 216 | struct fsl_dspi_dma *dma; |
349ad66c CF |
217 | }; |
218 | ||
8fcd151d | 219 | static u32 dspi_pop_tx(struct fsl_dspi *dspi) |
dadcf4ab | 220 | { |
8fcd151d | 221 | u32 txdata = 0; |
dadcf4ab EH |
222 | |
223 | if (dspi->tx) { | |
224 | if (dspi->bytes_per_word == 1) | |
225 | txdata = *(u8 *)dspi->tx; | |
8fcd151d | 226 | else if (dspi->bytes_per_word == 2) |
dadcf4ab | 227 | txdata = *(u16 *)dspi->tx; |
8fcd151d EH |
228 | else /* dspi->bytes_per_word == 4 */ |
229 | txdata = *(u32 *)dspi->tx; | |
dadcf4ab EH |
230 | dspi->tx += dspi->bytes_per_word; |
231 | } | |
232 | dspi->len -= dspi->bytes_per_word; | |
233 | return txdata; | |
234 | } | |
ccf7d8ee | 235 | |
dadcf4ab | 236 | static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi) |
349ad66c | 237 | { |
dadcf4ab | 238 | u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi); |
349ad66c | 239 | |
dadcf4ab EH |
240 | if (dspi->len > 0) |
241 | cmd |= SPI_PUSHR_CMD_CONT; | |
242 | return cmd << 16 | data; | |
243 | } | |
244 | ||
245 | static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata) | |
246 | { | |
247 | if (!dspi->rx) | |
248 | return; | |
249 | ||
250 | /* Mask of undefined bits */ | |
251 | rxdata &= (1 << dspi->bits_per_word) - 1; | |
349ad66c | 252 | |
dadcf4ab EH |
253 | if (dspi->bytes_per_word == 1) |
254 | *(u8 *)dspi->rx = rxdata; | |
8fcd151d | 255 | else if (dspi->bytes_per_word == 2) |
dadcf4ab | 256 | *(u16 *)dspi->rx = rxdata; |
8fcd151d EH |
257 | else /* dspi->bytes_per_word == 4 */ |
258 | *(u32 *)dspi->rx = rxdata; | |
dadcf4ab | 259 | dspi->rx += dspi->bytes_per_word; |
349ad66c CF |
260 | } |
261 | ||
90ba3703 SM |
262 | static void dspi_tx_dma_callback(void *arg) |
263 | { | |
264 | struct fsl_dspi *dspi = arg; | |
265 | struct fsl_dspi_dma *dma = dspi->dma; | |
266 | ||
267 | complete(&dma->cmd_tx_complete); | |
268 | } | |
269 | ||
270 | static void dspi_rx_dma_callback(void *arg) | |
271 | { | |
272 | struct fsl_dspi *dspi = arg; | |
273 | struct fsl_dspi_dma *dma = dspi->dma; | |
1eaccf21 | 274 | int i; |
90ba3703 | 275 | |
4779f23d | 276 | if (dspi->rx) { |
dadcf4ab EH |
277 | for (i = 0; i < dma->curr_xfer_len; i++) |
278 | dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]); | |
90ba3703 SM |
279 | } |
280 | ||
281 | complete(&dma->cmd_rx_complete); | |
282 | } | |
283 | ||
284 | static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi) | |
285 | { | |
286 | struct fsl_dspi_dma *dma = dspi->dma; | |
287 | struct device *dev = &dspi->pdev->dev; | |
288 | int time_left; | |
1eaccf21 | 289 | int i; |
90ba3703 | 290 | |
dadcf4ab EH |
291 | for (i = 0; i < dma->curr_xfer_len; i++) |
292 | dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi); | |
90ba3703 | 293 | |
90ba3703 SM |
294 | dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx, |
295 | dma->tx_dma_phys, | |
1eaccf21 SM |
296 | dma->curr_xfer_len * |
297 | DMA_SLAVE_BUSWIDTH_4_BYTES, | |
298 | DMA_MEM_TO_DEV, | |
90ba3703 SM |
299 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
300 | if (!dma->tx_desc) { | |
301 | dev_err(dev, "Not able to get desc for DMA xfer\n"); | |
302 | return -EIO; | |
303 | } | |
304 | ||
305 | dma->tx_desc->callback = dspi_tx_dma_callback; | |
306 | dma->tx_desc->callback_param = dspi; | |
307 | if (dma_submit_error(dmaengine_submit(dma->tx_desc))) { | |
308 | dev_err(dev, "DMA submit failed\n"); | |
309 | return -EINVAL; | |
310 | } | |
311 | ||
312 | dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx, | |
313 | dma->rx_dma_phys, | |
1eaccf21 SM |
314 | dma->curr_xfer_len * |
315 | DMA_SLAVE_BUSWIDTH_4_BYTES, | |
316 | DMA_DEV_TO_MEM, | |
90ba3703 SM |
317 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
318 | if (!dma->rx_desc) { | |
319 | dev_err(dev, "Not able to get desc for DMA xfer\n"); | |
320 | return -EIO; | |
321 | } | |
322 | ||
323 | dma->rx_desc->callback = dspi_rx_dma_callback; | |
324 | dma->rx_desc->callback_param = dspi; | |
325 | if (dma_submit_error(dmaengine_submit(dma->rx_desc))) { | |
326 | dev_err(dev, "DMA submit failed\n"); | |
327 | return -EINVAL; | |
328 | } | |
329 | ||
330 | reinit_completion(&dspi->dma->cmd_rx_complete); | |
331 | reinit_completion(&dspi->dma->cmd_tx_complete); | |
332 | ||
333 | dma_async_issue_pending(dma->chan_rx); | |
334 | dma_async_issue_pending(dma->chan_tx); | |
335 | ||
336 | time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete, | |
337 | DMA_COMPLETION_TIMEOUT); | |
338 | if (time_left == 0) { | |
339 | dev_err(dev, "DMA tx timeout\n"); | |
340 | dmaengine_terminate_all(dma->chan_tx); | |
341 | dmaengine_terminate_all(dma->chan_rx); | |
342 | return -ETIMEDOUT; | |
343 | } | |
344 | ||
345 | time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete, | |
346 | DMA_COMPLETION_TIMEOUT); | |
347 | if (time_left == 0) { | |
348 | dev_err(dev, "DMA rx timeout\n"); | |
349 | dmaengine_terminate_all(dma->chan_tx); | |
350 | dmaengine_terminate_all(dma->chan_rx); | |
351 | return -ETIMEDOUT; | |
352 | } | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
357 | static int dspi_dma_xfer(struct fsl_dspi *dspi) | |
358 | { | |
359 | struct fsl_dspi_dma *dma = dspi->dma; | |
360 | struct device *dev = &dspi->pdev->dev; | |
361 | int curr_remaining_bytes; | |
362 | int bytes_per_buffer; | |
90ba3703 SM |
363 | int ret = 0; |
364 | ||
90ba3703 | 365 | curr_remaining_bytes = dspi->len; |
1eaccf21 | 366 | bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE; |
90ba3703 SM |
367 | while (curr_remaining_bytes) { |
368 | /* Check if current transfer fits the DMA buffer */ | |
dadcf4ab EH |
369 | dma->curr_xfer_len = curr_remaining_bytes |
370 | / dspi->bytes_per_word; | |
1eaccf21 | 371 | if (dma->curr_xfer_len > bytes_per_buffer) |
90ba3703 SM |
372 | dma->curr_xfer_len = bytes_per_buffer; |
373 | ||
374 | ret = dspi_next_xfer_dma_submit(dspi); | |
375 | if (ret) { | |
376 | dev_err(dev, "DMA transfer failed\n"); | |
377 | goto exit; | |
378 | ||
379 | } else { | |
dadcf4ab EH |
380 | curr_remaining_bytes -= dma->curr_xfer_len |
381 | * dspi->bytes_per_word; | |
90ba3703 SM |
382 | if (curr_remaining_bytes < 0) |
383 | curr_remaining_bytes = 0; | |
90ba3703 SM |
384 | } |
385 | } | |
386 | ||
387 | exit: | |
388 | return ret; | |
389 | } | |
390 | ||
391 | static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) | |
392 | { | |
393 | struct fsl_dspi_dma *dma; | |
394 | struct dma_slave_config cfg; | |
395 | struct device *dev = &dspi->pdev->dev; | |
396 | int ret; | |
397 | ||
398 | dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); | |
399 | if (!dma) | |
400 | return -ENOMEM; | |
401 | ||
402 | dma->chan_rx = dma_request_slave_channel(dev, "rx"); | |
403 | if (!dma->chan_rx) { | |
404 | dev_err(dev, "rx dma channel not available\n"); | |
405 | ret = -ENODEV; | |
406 | return ret; | |
407 | } | |
408 | ||
409 | dma->chan_tx = dma_request_slave_channel(dev, "tx"); | |
410 | if (!dma->chan_tx) { | |
411 | dev_err(dev, "tx dma channel not available\n"); | |
412 | ret = -ENODEV; | |
413 | goto err_tx_channel; | |
414 | } | |
415 | ||
416 | dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE, | |
417 | &dma->tx_dma_phys, GFP_KERNEL); | |
418 | if (!dma->tx_dma_buf) { | |
419 | ret = -ENOMEM; | |
420 | goto err_tx_dma_buf; | |
421 | } | |
422 | ||
423 | dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE, | |
424 | &dma->rx_dma_phys, GFP_KERNEL); | |
425 | if (!dma->rx_dma_buf) { | |
426 | ret = -ENOMEM; | |
427 | goto err_rx_dma_buf; | |
428 | } | |
429 | ||
430 | cfg.src_addr = phy_addr + SPI_POPR; | |
431 | cfg.dst_addr = phy_addr + SPI_PUSHR; | |
432 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
433 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
434 | cfg.src_maxburst = 1; | |
435 | cfg.dst_maxburst = 1; | |
436 | ||
437 | cfg.direction = DMA_DEV_TO_MEM; | |
438 | ret = dmaengine_slave_config(dma->chan_rx, &cfg); | |
439 | if (ret) { | |
440 | dev_err(dev, "can't configure rx dma channel\n"); | |
441 | ret = -EINVAL; | |
442 | goto err_slave_config; | |
443 | } | |
444 | ||
445 | cfg.direction = DMA_MEM_TO_DEV; | |
446 | ret = dmaengine_slave_config(dma->chan_tx, &cfg); | |
447 | if (ret) { | |
448 | dev_err(dev, "can't configure tx dma channel\n"); | |
449 | ret = -EINVAL; | |
450 | goto err_slave_config; | |
451 | } | |
452 | ||
453 | dspi->dma = dma; | |
454 | init_completion(&dma->cmd_tx_complete); | |
455 | init_completion(&dma->cmd_rx_complete); | |
456 | ||
457 | return 0; | |
458 | ||
459 | err_slave_config: | |
27d21e9f SM |
460 | dma_free_coherent(dev, DSPI_DMA_BUFSIZE, |
461 | dma->rx_dma_buf, dma->rx_dma_phys); | |
90ba3703 | 462 | err_rx_dma_buf: |
27d21e9f SM |
463 | dma_free_coherent(dev, DSPI_DMA_BUFSIZE, |
464 | dma->tx_dma_buf, dma->tx_dma_phys); | |
90ba3703 SM |
465 | err_tx_dma_buf: |
466 | dma_release_channel(dma->chan_tx); | |
467 | err_tx_channel: | |
468 | dma_release_channel(dma->chan_rx); | |
469 | ||
470 | devm_kfree(dev, dma); | |
471 | dspi->dma = NULL; | |
472 | ||
473 | return ret; | |
474 | } | |
475 | ||
476 | static void dspi_release_dma(struct fsl_dspi *dspi) | |
477 | { | |
478 | struct fsl_dspi_dma *dma = dspi->dma; | |
479 | struct device *dev = &dspi->pdev->dev; | |
480 | ||
481 | if (dma) { | |
482 | if (dma->chan_tx) { | |
483 | dma_unmap_single(dev, dma->tx_dma_phys, | |
484 | DSPI_DMA_BUFSIZE, DMA_TO_DEVICE); | |
485 | dma_release_channel(dma->chan_tx); | |
486 | } | |
487 | ||
488 | if (dma->chan_rx) { | |
489 | dma_unmap_single(dev, dma->rx_dma_phys, | |
490 | DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE); | |
491 | dma_release_channel(dma->chan_rx); | |
492 | } | |
493 | } | |
494 | } | |
495 | ||
349ad66c CF |
496 | static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, |
497 | unsigned long clkrate) | |
498 | { | |
499 | /* Valid baud rate pre-scaler values */ | |
500 | int pbr_tbl[4] = {2, 3, 5, 7}; | |
501 | int brs[16] = { 2, 4, 6, 8, | |
502 | 16, 32, 64, 128, | |
503 | 256, 512, 1024, 2048, | |
504 | 4096, 8192, 16384, 32768 }; | |
6fd63087 AB |
505 | int scale_needed, scale, minscale = INT_MAX; |
506 | int i, j; | |
507 | ||
508 | scale_needed = clkrate / speed_hz; | |
e689d6df AB |
509 | if (clkrate % speed_hz) |
510 | scale_needed++; | |
6fd63087 AB |
511 | |
512 | for (i = 0; i < ARRAY_SIZE(brs); i++) | |
513 | for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) { | |
514 | scale = brs[i] * pbr_tbl[j]; | |
515 | if (scale >= scale_needed) { | |
516 | if (scale < minscale) { | |
517 | minscale = scale; | |
518 | *br = i; | |
519 | *pbr = j; | |
520 | } | |
521 | break; | |
349ad66c CF |
522 | } |
523 | } | |
349ad66c | 524 | |
6fd63087 AB |
525 | if (minscale == INT_MAX) { |
526 | pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n", | |
527 | speed_hz, clkrate); | |
528 | *pbr = ARRAY_SIZE(pbr_tbl) - 1; | |
529 | *br = ARRAY_SIZE(brs) - 1; | |
530 | } | |
349ad66c | 531 | } |
349ad66c | 532 | |
95bf15f3 AB |
533 | static void ns_delay_scale(char *psc, char *sc, int delay_ns, |
534 | unsigned long clkrate) | |
535 | { | |
536 | int pscale_tbl[4] = {1, 3, 5, 7}; | |
537 | int scale_needed, scale, minscale = INT_MAX; | |
538 | int i, j; | |
539 | u32 remainder; | |
540 | ||
541 | scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC, | |
542 | &remainder); | |
543 | if (remainder) | |
544 | scale_needed++; | |
545 | ||
546 | for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++) | |
547 | for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) { | |
548 | scale = pscale_tbl[i] * (2 << j); | |
549 | if (scale >= scale_needed) { | |
550 | if (scale < minscale) { | |
551 | minscale = scale; | |
552 | *psc = i; | |
553 | *sc = j; | |
554 | } | |
555 | break; | |
349ad66c CF |
556 | } |
557 | } | |
558 | ||
95bf15f3 AB |
559 | if (minscale == INT_MAX) { |
560 | pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value", | |
561 | delay_ns, clkrate); | |
562 | *psc = ARRAY_SIZE(pscale_tbl) - 1; | |
563 | *sc = SPI_CTAR_SCALE_BITS; | |
564 | } | |
349ad66c CF |
565 | } |
566 | ||
dadcf4ab | 567 | static void fifo_write(struct fsl_dspi *dspi) |
349ad66c | 568 | { |
dadcf4ab | 569 | regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi)); |
d1f4a38c | 570 | } |
349ad66c | 571 | |
8fcd151d EH |
572 | static void cmd_fifo_write(struct fsl_dspi *dspi) |
573 | { | |
574 | u16 cmd = dspi->tx_cmd; | |
575 | ||
576 | if (dspi->len > 0) | |
577 | cmd |= SPI_PUSHR_CMD_CONT; | |
578 | regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd); | |
579 | } | |
580 | ||
581 | static void tx_fifo_write(struct fsl_dspi *dspi, u16 txdata) | |
582 | { | |
583 | regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata); | |
584 | } | |
585 | ||
dadcf4ab | 586 | static void dspi_tcfq_write(struct fsl_dspi *dspi) |
d1f4a38c | 587 | { |
dadcf4ab EH |
588 | /* Clear transfer count */ |
589 | dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT; | |
8fcd151d EH |
590 | |
591 | if (dspi->devtype_data->xspi_mode && dspi->bits_per_word > 16) { | |
592 | /* Write two TX FIFO entries first, and then the corresponding | |
593 | * CMD FIFO entry. | |
594 | */ | |
595 | u32 data = dspi_pop_tx(dspi); | |
596 | ||
597 | if (dspi->cur_chip->ctar_val & SPI_CTAR_LSBFE(1)) { | |
598 | /* LSB */ | |
599 | tx_fifo_write(dspi, data & 0xFFFF); | |
600 | tx_fifo_write(dspi, data >> 16); | |
601 | } else { | |
602 | /* MSB */ | |
603 | tx_fifo_write(dspi, data >> 16); | |
604 | tx_fifo_write(dspi, data & 0xFFFF); | |
605 | } | |
606 | cmd_fifo_write(dspi); | |
607 | } else { | |
608 | /* Write one entry to both TX FIFO and CMD FIFO | |
609 | * simultaneously. | |
610 | */ | |
611 | fifo_write(dspi); | |
612 | } | |
d1f4a38c | 613 | } |
349ad66c | 614 | |
dadcf4ab | 615 | static u32 fifo_read(struct fsl_dspi *dspi) |
d1f4a38c | 616 | { |
dadcf4ab | 617 | u32 rxdata = 0; |
d1f4a38c | 618 | |
dadcf4ab EH |
619 | regmap_read(dspi->regmap, SPI_POPR, &rxdata); |
620 | return rxdata; | |
349ad66c CF |
621 | } |
622 | ||
dadcf4ab | 623 | static void dspi_tcfq_read(struct fsl_dspi *dspi) |
349ad66c | 624 | { |
dadcf4ab | 625 | dspi_push_rx(dspi, fifo_read(dspi)); |
d1f4a38c | 626 | } |
349ad66c | 627 | |
dadcf4ab | 628 | static void dspi_eoq_write(struct fsl_dspi *dspi) |
d1f4a38c | 629 | { |
dadcf4ab EH |
630 | int fifo_size = DSPI_FIFO_SIZE; |
631 | ||
632 | /* Fill TX FIFO with as many transfers as possible */ | |
633 | while (dspi->len && fifo_size--) { | |
634 | /* Request EOQF for last transfer in FIFO */ | |
635 | if (dspi->len == dspi->bytes_per_word || fifo_size == 0) | |
636 | dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ; | |
637 | /* Clear transfer count for first transfer in FIFO */ | |
638 | if (fifo_size == (DSPI_FIFO_SIZE - 1)) | |
639 | dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT; | |
640 | /* Write combined TX FIFO and CMD FIFO entry */ | |
641 | fifo_write(dspi); | |
349ad66c | 642 | } |
d1f4a38c HW |
643 | } |
644 | ||
dadcf4ab | 645 | static void dspi_eoq_read(struct fsl_dspi *dspi) |
d1f4a38c | 646 | { |
dadcf4ab | 647 | int fifo_size = DSPI_FIFO_SIZE; |
d1f4a38c | 648 | |
dadcf4ab EH |
649 | /* Read one FIFO entry at and push to rx buffer */ |
650 | while ((dspi->rx < dspi->rx_end) && fifo_size--) | |
651 | dspi_push_rx(dspi, fifo_read(dspi)); | |
349ad66c CF |
652 | } |
653 | ||
9298bc72 CF |
654 | static int dspi_transfer_one_message(struct spi_master *master, |
655 | struct spi_message *message) | |
349ad66c | 656 | { |
9298bc72 CF |
657 | struct fsl_dspi *dspi = spi_master_get_devdata(master); |
658 | struct spi_device *spi = message->spi; | |
659 | struct spi_transfer *transfer; | |
660 | int status = 0; | |
d1f4a38c HW |
661 | enum dspi_trans_mode trans_mode; |
662 | ||
9298bc72 CF |
663 | message->actual_length = 0; |
664 | ||
665 | list_for_each_entry(transfer, &message->transfers, transfer_list) { | |
666 | dspi->cur_transfer = transfer; | |
667 | dspi->cur_msg = message; | |
668 | dspi->cur_chip = spi_get_ctldata(spi); | |
9e1dc9bd EH |
669 | /* Prepare command word for CMD FIFO */ |
670 | dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) | | |
671 | SPI_PUSHR_CMD_PCS(spi->chip_select); | |
92dc20d8 | 672 | if (list_is_last(&dspi->cur_transfer->transfer_list, |
9e1dc9bd EH |
673 | &dspi->cur_msg->transfers)) { |
674 | /* Leave PCS activated after last transfer when | |
675 | * cs_change is set. | |
676 | */ | |
677 | if (transfer->cs_change) | |
678 | dspi->tx_cmd |= SPI_PUSHR_CMD_CONT; | |
679 | } else { | |
680 | /* Keep PCS active between transfers in same message | |
681 | * when cs_change is not set, and de-activate PCS | |
682 | * between transfers in the same message when | |
683 | * cs_change is set. | |
684 | */ | |
685 | if (!transfer->cs_change) | |
686 | dspi->tx_cmd |= SPI_PUSHR_CMD_CONT; | |
687 | } | |
688 | ||
9298bc72 CF |
689 | dspi->void_write_data = dspi->cur_chip->void_write_data; |
690 | ||
dadcf4ab | 691 | dspi->tx = transfer->tx_buf; |
9298bc72 CF |
692 | dspi->rx = transfer->rx_buf; |
693 | dspi->rx_end = dspi->rx + transfer->len; | |
694 | dspi->len = transfer->len; | |
dadcf4ab EH |
695 | /* Validated transfer specific frame size (defaults applied) */ |
696 | dspi->bits_per_word = transfer->bits_per_word; | |
697 | if (transfer->bits_per_word <= 8) | |
698 | dspi->bytes_per_word = 1; | |
8fcd151d | 699 | else if (transfer->bits_per_word <= 16) |
dadcf4ab | 700 | dspi->bytes_per_word = 2; |
8fcd151d EH |
701 | else |
702 | dspi->bytes_per_word = 4; | |
9298bc72 | 703 | |
9298bc72 | 704 | regmap_update_bits(dspi->regmap, SPI_MCR, |
d87e08f1 EH |
705 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, |
706 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); | |
ef22d160 | 707 | regmap_write(dspi->regmap, SPI_CTAR(0), |
dadcf4ab EH |
708 | dspi->cur_chip->ctar_val | |
709 | SPI_FRAME_BITS(transfer->bits_per_word)); | |
51d583ae EH |
710 | if (dspi->devtype_data->xspi_mode) |
711 | regmap_write(dspi->regmap, SPI_CTARE(0), | |
712 | SPI_FRAME_EBITS(transfer->bits_per_word) | |
713 | | SPI_CTARE_DTCP(1)); | |
349ad66c | 714 | |
d1f4a38c HW |
715 | trans_mode = dspi->devtype_data->trans_mode; |
716 | switch (trans_mode) { | |
717 | case DSPI_EOQ_MODE: | |
718 | regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); | |
c042af95 | 719 | dspi_eoq_write(dspi); |
d1f4a38c HW |
720 | break; |
721 | case DSPI_TCFQ_MODE: | |
722 | regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE); | |
c042af95 | 723 | dspi_tcfq_write(dspi); |
d1f4a38c | 724 | break; |
90ba3703 SM |
725 | case DSPI_DMA_MODE: |
726 | regmap_write(dspi->regmap, SPI_RSER, | |
727 | SPI_RSER_TFFFE | SPI_RSER_TFFFD | | |
728 | SPI_RSER_RFDFE | SPI_RSER_RFDFD); | |
729 | status = dspi_dma_xfer(dspi); | |
98114304 | 730 | break; |
d1f4a38c HW |
731 | default: |
732 | dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", | |
733 | trans_mode); | |
734 | status = -EINVAL; | |
735 | goto out; | |
736 | } | |
1acbdeb9 | 737 | |
98114304 SM |
738 | if (trans_mode != DSPI_DMA_MODE) { |
739 | if (wait_event_interruptible(dspi->waitq, | |
740 | dspi->waitflags)) | |
741 | dev_err(&dspi->pdev->dev, | |
742 | "wait transfer complete fail!\n"); | |
743 | dspi->waitflags = 0; | |
744 | } | |
349ad66c | 745 | |
9298bc72 CF |
746 | if (transfer->delay_usecs) |
747 | udelay(transfer->delay_usecs); | |
349ad66c CF |
748 | } |
749 | ||
d1f4a38c | 750 | out: |
9298bc72 CF |
751 | message->status = status; |
752 | spi_finalize_current_message(master); | |
753 | ||
754 | return status; | |
349ad66c CF |
755 | } |
756 | ||
9298bc72 | 757 | static int dspi_setup(struct spi_device *spi) |
349ad66c CF |
758 | { |
759 | struct chip_data *chip; | |
760 | struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); | |
ec7ed770 | 761 | struct fsl_dspi_platform_data *pdata; |
95bf15f3 AB |
762 | u32 cs_sck_delay = 0, sck_cs_delay = 0; |
763 | unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0; | |
dadcf4ab | 764 | unsigned char pasc = 0, asc = 0; |
95bf15f3 | 765 | unsigned long clkrate; |
349ad66c CF |
766 | |
767 | /* Only alloc on first setup */ | |
768 | chip = spi_get_ctldata(spi); | |
769 | if (chip == NULL) { | |
973fbce6 | 770 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
349ad66c CF |
771 | if (!chip) |
772 | return -ENOMEM; | |
773 | } | |
774 | ||
ec7ed770 | 775 | pdata = dev_get_platdata(&dspi->pdev->dev); |
95bf15f3 | 776 | |
ec7ed770 AD |
777 | if (!pdata) { |
778 | of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay", | |
779 | &cs_sck_delay); | |
780 | ||
781 | of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay", | |
782 | &sck_cs_delay); | |
783 | } else { | |
784 | cs_sck_delay = pdata->cs_sck_delay; | |
785 | sck_cs_delay = pdata->sck_cs_delay; | |
786 | } | |
95bf15f3 | 787 | |
349ad66c CF |
788 | chip->void_write_data = 0; |
789 | ||
95bf15f3 AB |
790 | clkrate = clk_get_rate(dspi->clk); |
791 | hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate); | |
792 | ||
793 | /* Set PCS to SCK delay scale values */ | |
794 | ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate); | |
795 | ||
796 | /* Set After SCK delay scale values */ | |
797 | ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate); | |
349ad66c | 798 | |
dadcf4ab | 799 | chip->ctar_val = SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0) |
349ad66c CF |
800 | | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0) |
801 | | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0) | |
95bf15f3 AB |
802 | | SPI_CTAR_PCSSCK(pcssck) |
803 | | SPI_CTAR_CSSCK(cssck) | |
804 | | SPI_CTAR_PASC(pasc) | |
805 | | SPI_CTAR_ASC(asc) | |
349ad66c CF |
806 | | SPI_CTAR_PBR(pbr) |
807 | | SPI_CTAR_BR(br); | |
808 | ||
809 | spi_set_ctldata(spi, chip); | |
810 | ||
811 | return 0; | |
812 | } | |
813 | ||
973fbce6 BD |
814 | static void dspi_cleanup(struct spi_device *spi) |
815 | { | |
816 | struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi); | |
817 | ||
818 | dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n", | |
819 | spi->master->bus_num, spi->chip_select); | |
820 | ||
821 | kfree(chip); | |
822 | } | |
823 | ||
349ad66c CF |
824 | static irqreturn_t dspi_interrupt(int irq, void *dev_id) |
825 | { | |
826 | struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; | |
9298bc72 | 827 | struct spi_message *msg = dspi->cur_msg; |
d1f4a38c | 828 | enum dspi_trans_mode trans_mode; |
c042af95 | 829 | u32 spi_sr, spi_tcr; |
0a4ec2c1 | 830 | u16 spi_tcnt; |
d1f4a38c HW |
831 | |
832 | regmap_read(dspi->regmap, SPI_SR, &spi_sr); | |
833 | regmap_write(dspi->regmap, SPI_SR, spi_sr); | |
834 | ||
349ad66c | 835 | |
c042af95 | 836 | if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) { |
0a4ec2c1 EH |
837 | /* Get transfer counter (in number of SPI transfers). It was |
838 | * reset to 0 when transfer(s) were started. | |
839 | */ | |
c042af95 HW |
840 | regmap_read(dspi->regmap, SPI_TCR, &spi_tcr); |
841 | spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr); | |
0a4ec2c1 | 842 | /* Update total number of bytes that were transferred */ |
dadcf4ab | 843 | msg->actual_length += spi_tcnt * dspi->bytes_per_word; |
c042af95 HW |
844 | |
845 | trans_mode = dspi->devtype_data->trans_mode; | |
d1f4a38c HW |
846 | switch (trans_mode) { |
847 | case DSPI_EOQ_MODE: | |
c042af95 | 848 | dspi_eoq_read(dspi); |
d1f4a38c HW |
849 | break; |
850 | case DSPI_TCFQ_MODE: | |
c042af95 | 851 | dspi_tcfq_read(dspi); |
d1f4a38c HW |
852 | break; |
853 | default: | |
854 | dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", | |
855 | trans_mode); | |
c042af95 HW |
856 | return IRQ_HANDLED; |
857 | } | |
858 | ||
859 | if (!dspi->len) { | |
c042af95 HW |
860 | dspi->waitflags = 1; |
861 | wake_up_interruptible(&dspi->waitq); | |
862 | } else { | |
863 | switch (trans_mode) { | |
864 | case DSPI_EOQ_MODE: | |
865 | dspi_eoq_write(dspi); | |
866 | break; | |
867 | case DSPI_TCFQ_MODE: | |
868 | dspi_tcfq_write(dspi); | |
869 | break; | |
870 | default: | |
871 | dev_err(&dspi->pdev->dev, | |
872 | "unsupported trans_mode %u\n", | |
873 | trans_mode); | |
874 | } | |
d1f4a38c HW |
875 | } |
876 | } | |
c042af95 | 877 | |
349ad66c CF |
878 | return IRQ_HANDLED; |
879 | } | |
880 | ||
790d1902 | 881 | static const struct of_device_id fsl_dspi_dt_ids[] = { |
230c08b2 JL |
882 | { .compatible = "fsl,vf610-dspi", .data = &vf610_data, }, |
883 | { .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, }, | |
884 | { .compatible = "fsl,ls2085a-dspi", .data = &ls2085a_data, }, | |
349ad66c CF |
885 | { /* sentinel */ } |
886 | }; | |
887 | MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); | |
888 | ||
889 | #ifdef CONFIG_PM_SLEEP | |
890 | static int dspi_suspend(struct device *dev) | |
891 | { | |
892 | struct spi_master *master = dev_get_drvdata(dev); | |
893 | struct fsl_dspi *dspi = spi_master_get_devdata(master); | |
894 | ||
895 | spi_master_suspend(master); | |
896 | clk_disable_unprepare(dspi->clk); | |
897 | ||
432a17d7 MK |
898 | pinctrl_pm_select_sleep_state(dev); |
899 | ||
349ad66c CF |
900 | return 0; |
901 | } | |
902 | ||
903 | static int dspi_resume(struct device *dev) | |
904 | { | |
349ad66c CF |
905 | struct spi_master *master = dev_get_drvdata(dev); |
906 | struct fsl_dspi *dspi = spi_master_get_devdata(master); | |
1c5ea2b4 | 907 | int ret; |
349ad66c | 908 | |
432a17d7 MK |
909 | pinctrl_pm_select_default_state(dev); |
910 | ||
1c5ea2b4 FE |
911 | ret = clk_prepare_enable(dspi->clk); |
912 | if (ret) | |
913 | return ret; | |
349ad66c CF |
914 | spi_master_resume(master); |
915 | ||
916 | return 0; | |
917 | } | |
918 | #endif /* CONFIG_PM_SLEEP */ | |
919 | ||
ba811add | 920 | static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume); |
349ad66c | 921 | |
8570043e EH |
922 | static const struct regmap_range dspi_volatile_ranges[] = { |
923 | regmap_reg_range(SPI_MCR, SPI_TCR), | |
924 | regmap_reg_range(SPI_SR, SPI_SR), | |
925 | regmap_reg_range(SPI_PUSHR, SPI_RXFR3), | |
926 | }; | |
927 | ||
928 | static const struct regmap_access_table dspi_volatile_table = { | |
929 | .yes_ranges = dspi_volatile_ranges, | |
930 | .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges), | |
931 | }; | |
932 | ||
409851c3 | 933 | static const struct regmap_config dspi_regmap_config = { |
1acbdeb9 CF |
934 | .reg_bits = 32, |
935 | .val_bits = 32, | |
936 | .reg_stride = 4, | |
937 | .max_register = 0x88, | |
8570043e | 938 | .volatile_table = &dspi_volatile_table, |
349ad66c CF |
939 | }; |
940 | ||
58ba07ec EH |
941 | static const struct regmap_range dspi_xspi_volatile_ranges[] = { |
942 | regmap_reg_range(SPI_MCR, SPI_TCR), | |
943 | regmap_reg_range(SPI_SR, SPI_SR), | |
944 | regmap_reg_range(SPI_PUSHR, SPI_RXFR3), | |
945 | regmap_reg_range(SPI_SREX, SPI_SREX), | |
946 | }; | |
947 | ||
948 | static const struct regmap_access_table dspi_xspi_volatile_table = { | |
949 | .yes_ranges = dspi_xspi_volatile_ranges, | |
950 | .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges), | |
951 | }; | |
952 | ||
953 | static const struct regmap_config dspi_xspi_regmap_config[] = { | |
954 | { | |
955 | .reg_bits = 32, | |
956 | .val_bits = 32, | |
957 | .reg_stride = 4, | |
958 | .max_register = 0x13c, | |
959 | .volatile_table = &dspi_xspi_volatile_table, | |
960 | }, | |
961 | { | |
962 | .name = "pushr", | |
963 | .reg_bits = 16, | |
964 | .val_bits = 16, | |
965 | .reg_stride = 2, | |
966 | .max_register = 0x2, | |
967 | }, | |
968 | }; | |
969 | ||
5ee67b58 YY |
970 | static void dspi_init(struct fsl_dspi *dspi) |
971 | { | |
3e7cc625 EH |
972 | regmap_write(dspi->regmap, SPI_MCR, SPI_MCR_MASTER | SPI_MCR_PCSIS | |
973 | (dspi->devtype_data->xspi_mode ? SPI_MCR_XSPI : 0)); | |
5ee67b58 | 974 | regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); |
51d583ae EH |
975 | if (dspi->devtype_data->xspi_mode) |
976 | regmap_write(dspi->regmap, SPI_CTARE(0), | |
977 | SPI_CTARE_FMSZE(0) | SPI_CTARE_DTCP(1)); | |
5ee67b58 YY |
978 | } |
979 | ||
349ad66c CF |
980 | static int dspi_probe(struct platform_device *pdev) |
981 | { | |
982 | struct device_node *np = pdev->dev.of_node; | |
983 | struct spi_master *master; | |
984 | struct fsl_dspi *dspi; | |
985 | struct resource *res; | |
58ba07ec | 986 | const struct regmap_config *regmap_config; |
1acbdeb9 | 987 | void __iomem *base; |
ec7ed770 | 988 | struct fsl_dspi_platform_data *pdata; |
349ad66c CF |
989 | int ret = 0, cs_num, bus_num; |
990 | ||
991 | master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); | |
992 | if (!master) | |
993 | return -ENOMEM; | |
994 | ||
995 | dspi = spi_master_get_devdata(master); | |
996 | dspi->pdev = pdev; | |
9298bc72 CF |
997 | dspi->master = master; |
998 | ||
999 | master->transfer = NULL; | |
1000 | master->setup = dspi_setup; | |
1001 | master->transfer_one_message = dspi_transfer_one_message; | |
1002 | master->dev.of_node = pdev->dev.of_node; | |
349ad66c | 1003 | |
973fbce6 | 1004 | master->cleanup = dspi_cleanup; |
00ac9562 | 1005 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; |
349ad66c | 1006 | |
ec7ed770 AD |
1007 | pdata = dev_get_platdata(&pdev->dev); |
1008 | if (pdata) { | |
1009 | master->num_chipselect = pdata->cs_num; | |
1010 | master->bus_num = pdata->bus_num; | |
349ad66c | 1011 | |
ec7ed770 AD |
1012 | dspi->devtype_data = &coldfire_data; |
1013 | } else { | |
349ad66c | 1014 | |
ec7ed770 AD |
1015 | ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); |
1016 | if (ret < 0) { | |
1017 | dev_err(&pdev->dev, "can't get spi-num-chipselects\n"); | |
1018 | goto out_master_put; | |
1019 | } | |
1020 | master->num_chipselect = cs_num; | |
1021 | ||
1022 | ret = of_property_read_u32(np, "bus-num", &bus_num); | |
1023 | if (ret < 0) { | |
1024 | dev_err(&pdev->dev, "can't get bus-num\n"); | |
1025 | goto out_master_put; | |
1026 | } | |
1027 | master->bus_num = bus_num; | |
1028 | ||
1029 | dspi->devtype_data = of_device_get_match_data(&pdev->dev); | |
1030 | if (!dspi->devtype_data) { | |
1031 | dev_err(&pdev->dev, "can't get devtype_data\n"); | |
1032 | ret = -EFAULT; | |
1033 | goto out_master_put; | |
1034 | } | |
d1f4a38c HW |
1035 | } |
1036 | ||
35c9d461 EH |
1037 | if (dspi->devtype_data->xspi_mode) |
1038 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); | |
1039 | else | |
1040 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); | |
1041 | ||
349ad66c | 1042 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1acbdeb9 CF |
1043 | base = devm_ioremap_resource(&pdev->dev, res); |
1044 | if (IS_ERR(base)) { | |
1045 | ret = PTR_ERR(base); | |
349ad66c CF |
1046 | goto out_master_put; |
1047 | } | |
1048 | ||
58ba07ec EH |
1049 | if (dspi->devtype_data->xspi_mode) |
1050 | regmap_config = &dspi_xspi_regmap_config[0]; | |
1051 | else | |
1052 | regmap_config = &dspi_regmap_config; | |
1053 | dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config); | |
1acbdeb9 CF |
1054 | if (IS_ERR(dspi->regmap)) { |
1055 | dev_err(&pdev->dev, "failed to init regmap: %ld\n", | |
1056 | PTR_ERR(dspi->regmap)); | |
fbad6c24 CJ |
1057 | ret = PTR_ERR(dspi->regmap); |
1058 | goto out_master_put; | |
1acbdeb9 CF |
1059 | } |
1060 | ||
58ba07ec EH |
1061 | if (dspi->devtype_data->xspi_mode) { |
1062 | dspi->regmap_pushr = devm_regmap_init_mmio( | |
1063 | &pdev->dev, base + SPI_PUSHR, | |
1064 | &dspi_xspi_regmap_config[1]); | |
1065 | if (IS_ERR(dspi->regmap_pushr)) { | |
1066 | dev_err(&pdev->dev, | |
1067 | "failed to init pushr regmap: %ld\n", | |
1068 | PTR_ERR(dspi->regmap_pushr)); | |
80dc12cd | 1069 | ret = PTR_ERR(dspi->regmap_pushr); |
58ba07ec EH |
1070 | goto out_master_put; |
1071 | } | |
1072 | } | |
1073 | ||
d8ffee2f KK |
1074 | dspi->clk = devm_clk_get(&pdev->dev, "dspi"); |
1075 | if (IS_ERR(dspi->clk)) { | |
1076 | ret = PTR_ERR(dspi->clk); | |
1077 | dev_err(&pdev->dev, "unable to get clock\n"); | |
1078 | goto out_master_put; | |
1079 | } | |
1080 | ret = clk_prepare_enable(dspi->clk); | |
1081 | if (ret) | |
1082 | goto out_master_put; | |
1083 | ||
5ee67b58 | 1084 | dspi_init(dspi); |
349ad66c CF |
1085 | dspi->irq = platform_get_irq(pdev, 0); |
1086 | if (dspi->irq < 0) { | |
1087 | dev_err(&pdev->dev, "can't get platform irq\n"); | |
1088 | ret = dspi->irq; | |
d8ffee2f | 1089 | goto out_clk_put; |
349ad66c CF |
1090 | } |
1091 | ||
1092 | ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0, | |
1093 | pdev->name, dspi); | |
1094 | if (ret < 0) { | |
1095 | dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n"); | |
d8ffee2f | 1096 | goto out_clk_put; |
349ad66c CF |
1097 | } |
1098 | ||
90ba3703 | 1099 | if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) { |
cddebdd1 NY |
1100 | ret = dspi_request_dma(dspi, res->start); |
1101 | if (ret < 0) { | |
90ba3703 SM |
1102 | dev_err(&pdev->dev, "can't get dma channels\n"); |
1103 | goto out_clk_put; | |
1104 | } | |
1105 | } | |
1106 | ||
9419b200 BD |
1107 | master->max_speed_hz = |
1108 | clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor; | |
1109 | ||
349ad66c | 1110 | init_waitqueue_head(&dspi->waitq); |
017145fe | 1111 | platform_set_drvdata(pdev, master); |
349ad66c | 1112 | |
9298bc72 | 1113 | ret = spi_register_master(master); |
349ad66c CF |
1114 | if (ret != 0) { |
1115 | dev_err(&pdev->dev, "Problem registering DSPI master\n"); | |
1116 | goto out_clk_put; | |
1117 | } | |
1118 | ||
349ad66c CF |
1119 | return ret; |
1120 | ||
1121 | out_clk_put: | |
1122 | clk_disable_unprepare(dspi->clk); | |
1123 | out_master_put: | |
1124 | spi_master_put(master); | |
349ad66c CF |
1125 | |
1126 | return ret; | |
1127 | } | |
1128 | ||
1129 | static int dspi_remove(struct platform_device *pdev) | |
1130 | { | |
017145fe AL |
1131 | struct spi_master *master = platform_get_drvdata(pdev); |
1132 | struct fsl_dspi *dspi = spi_master_get_devdata(master); | |
349ad66c CF |
1133 | |
1134 | /* Disconnect from the SPI framework */ | |
90ba3703 | 1135 | dspi_release_dma(dspi); |
05209f45 | 1136 | clk_disable_unprepare(dspi->clk); |
9298bc72 | 1137 | spi_unregister_master(dspi->master); |
349ad66c CF |
1138 | |
1139 | return 0; | |
1140 | } | |
1141 | ||
1142 | static struct platform_driver fsl_dspi_driver = { | |
1143 | .driver.name = DRIVER_NAME, | |
1144 | .driver.of_match_table = fsl_dspi_dt_ids, | |
1145 | .driver.owner = THIS_MODULE, | |
1146 | .driver.pm = &dspi_pm, | |
1147 | .probe = dspi_probe, | |
1148 | .remove = dspi_remove, | |
1149 | }; | |
1150 | module_platform_driver(fsl_dspi_driver); | |
1151 | ||
1152 | MODULE_DESCRIPTION("Freescale DSPI Controller Driver"); | |
b444d1df | 1153 | MODULE_LICENSE("GPL"); |
349ad66c | 1154 | MODULE_ALIAS("platform:" DRIVER_NAME); |