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349ad66c CF |
1 | /* |
2 | * drivers/spi/spi-fsl-dspi.c | |
3 | * | |
4 | * Copyright 2013 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * Freescale DSPI driver | |
7 | * This file contains a driver for the Freescale DSPI | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | */ | |
15 | ||
a3108360 XL |
16 | #include <linux/clk.h> |
17 | #include <linux/delay.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/errno.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io.h> | |
349ad66c | 22 | #include <linux/kernel.h> |
95bf15f3 | 23 | #include <linux/math64.h> |
349ad66c | 24 | #include <linux/module.h> |
a3108360 XL |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
432a17d7 | 27 | #include <linux/pinctrl/consumer.h> |
349ad66c | 28 | #include <linux/platform_device.h> |
a3108360 | 29 | #include <linux/pm_runtime.h> |
1acbdeb9 | 30 | #include <linux/regmap.h> |
349ad66c | 31 | #include <linux/sched.h> |
349ad66c CF |
32 | #include <linux/spi/spi.h> |
33 | #include <linux/spi/spi_bitbang.h> | |
95bf15f3 | 34 | #include <linux/time.h> |
349ad66c CF |
35 | |
36 | #define DRIVER_NAME "fsl-dspi" | |
37 | ||
38 | #define TRAN_STATE_RX_VOID 0x01 | |
39 | #define TRAN_STATE_TX_VOID 0x02 | |
40 | #define TRAN_STATE_WORD_ODD_NUM 0x04 | |
41 | ||
42 | #define DSPI_FIFO_SIZE 4 | |
43 | ||
44 | #define SPI_MCR 0x00 | |
45 | #define SPI_MCR_MASTER (1 << 31) | |
46 | #define SPI_MCR_PCSIS (0x3F << 16) | |
47 | #define SPI_MCR_CLR_TXF (1 << 11) | |
48 | #define SPI_MCR_CLR_RXF (1 << 10) | |
49 | ||
50 | #define SPI_TCR 0x08 | |
c042af95 | 51 | #define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16) |
349ad66c | 52 | |
5cc7b047 | 53 | #define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4)) |
349ad66c CF |
54 | #define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27) |
55 | #define SPI_CTAR_CPOL(x) ((x) << 26) | |
56 | #define SPI_CTAR_CPHA(x) ((x) << 25) | |
57 | #define SPI_CTAR_LSBFE(x) ((x) << 24) | |
95bf15f3 | 58 | #define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22) |
349ad66c CF |
59 | #define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20) |
60 | #define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18) | |
61 | #define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16) | |
62 | #define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12) | |
63 | #define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8) | |
64 | #define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4) | |
65 | #define SPI_CTAR_BR(x) ((x) & 0x0000000f) | |
95bf15f3 | 66 | #define SPI_CTAR_SCALE_BITS 0xf |
349ad66c CF |
67 | |
68 | #define SPI_CTAR0_SLAVE 0x0c | |
69 | ||
70 | #define SPI_SR 0x2c | |
71 | #define SPI_SR_EOQF 0x10000000 | |
d1f4a38c | 72 | #define SPI_SR_TCFQF 0x80000000 |
349ad66c CF |
73 | |
74 | #define SPI_RSER 0x30 | |
75 | #define SPI_RSER_EOQFE 0x10000000 | |
d1f4a38c | 76 | #define SPI_RSER_TCFQE 0x80000000 |
349ad66c CF |
77 | |
78 | #define SPI_PUSHR 0x34 | |
79 | #define SPI_PUSHR_CONT (1 << 31) | |
5cc7b047 | 80 | #define SPI_PUSHR_CTAS(x) (((x) & 0x00000003) << 28) |
349ad66c CF |
81 | #define SPI_PUSHR_EOQ (1 << 27) |
82 | #define SPI_PUSHR_CTCNT (1 << 26) | |
83 | #define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16) | |
84 | #define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff) | |
85 | ||
86 | #define SPI_PUSHR_SLAVE 0x34 | |
87 | ||
88 | #define SPI_POPR 0x38 | |
89 | #define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff) | |
90 | ||
91 | #define SPI_TXFR0 0x3c | |
92 | #define SPI_TXFR1 0x40 | |
93 | #define SPI_TXFR2 0x44 | |
94 | #define SPI_TXFR3 0x48 | |
95 | #define SPI_RXFR0 0x7c | |
96 | #define SPI_RXFR1 0x80 | |
97 | #define SPI_RXFR2 0x84 | |
98 | #define SPI_RXFR3 0x88 | |
99 | ||
100 | #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1) | |
101 | #define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf) | |
102 | #define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf) | |
103 | #define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7) | |
104 | ||
105 | #define SPI_CS_INIT 0x01 | |
106 | #define SPI_CS_ASSERT 0x02 | |
107 | #define SPI_CS_DROP 0x04 | |
108 | ||
c042af95 HW |
109 | #define SPI_TCR_TCNT_MAX 0x10000 |
110 | ||
349ad66c CF |
111 | struct chip_data { |
112 | u32 mcr_val; | |
113 | u32 ctar_val; | |
114 | u16 void_write_data; | |
115 | }; | |
116 | ||
d1f4a38c HW |
117 | enum dspi_trans_mode { |
118 | DSPI_EOQ_MODE = 0, | |
119 | DSPI_TCFQ_MODE, | |
120 | }; | |
121 | ||
122 | struct fsl_dspi_devtype_data { | |
123 | enum dspi_trans_mode trans_mode; | |
124 | }; | |
125 | ||
126 | static const struct fsl_dspi_devtype_data vf610_data = { | |
127 | .trans_mode = DSPI_EOQ_MODE, | |
128 | }; | |
129 | ||
130 | static const struct fsl_dspi_devtype_data ls1021a_v1_data = { | |
131 | .trans_mode = DSPI_TCFQ_MODE, | |
132 | }; | |
133 | ||
134 | static const struct fsl_dspi_devtype_data ls2085a_data = { | |
135 | .trans_mode = DSPI_TCFQ_MODE, | |
136 | }; | |
137 | ||
349ad66c | 138 | struct fsl_dspi { |
9298bc72 | 139 | struct spi_master *master; |
349ad66c CF |
140 | struct platform_device *pdev; |
141 | ||
1acbdeb9 | 142 | struct regmap *regmap; |
349ad66c | 143 | int irq; |
88386e85 | 144 | struct clk *clk; |
349ad66c | 145 | |
88386e85 | 146 | struct spi_transfer *cur_transfer; |
9298bc72 | 147 | struct spi_message *cur_msg; |
349ad66c CF |
148 | struct chip_data *cur_chip; |
149 | size_t len; | |
150 | void *tx; | |
151 | void *tx_end; | |
152 | void *rx; | |
153 | void *rx_end; | |
154 | char dataflags; | |
155 | u8 cs; | |
156 | u16 void_write_data; | |
9298bc72 | 157 | u32 cs_change; |
d1f4a38c | 158 | struct fsl_dspi_devtype_data *devtype_data; |
349ad66c | 159 | |
88386e85 CF |
160 | wait_queue_head_t waitq; |
161 | u32 waitflags; | |
c042af95 HW |
162 | |
163 | u32 spi_tcnt; | |
349ad66c CF |
164 | }; |
165 | ||
166 | static inline int is_double_byte_mode(struct fsl_dspi *dspi) | |
167 | { | |
1acbdeb9 | 168 | unsigned int val; |
349ad66c | 169 | |
ef22d160 | 170 | regmap_read(dspi->regmap, SPI_CTAR(0), &val); |
349ad66c | 171 | |
1acbdeb9 | 172 | return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1; |
349ad66c CF |
173 | } |
174 | ||
175 | static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, | |
176 | unsigned long clkrate) | |
177 | { | |
178 | /* Valid baud rate pre-scaler values */ | |
179 | int pbr_tbl[4] = {2, 3, 5, 7}; | |
180 | int brs[16] = { 2, 4, 6, 8, | |
181 | 16, 32, 64, 128, | |
182 | 256, 512, 1024, 2048, | |
183 | 4096, 8192, 16384, 32768 }; | |
6fd63087 AB |
184 | int scale_needed, scale, minscale = INT_MAX; |
185 | int i, j; | |
186 | ||
187 | scale_needed = clkrate / speed_hz; | |
e689d6df AB |
188 | if (clkrate % speed_hz) |
189 | scale_needed++; | |
6fd63087 AB |
190 | |
191 | for (i = 0; i < ARRAY_SIZE(brs); i++) | |
192 | for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) { | |
193 | scale = brs[i] * pbr_tbl[j]; | |
194 | if (scale >= scale_needed) { | |
195 | if (scale < minscale) { | |
196 | minscale = scale; | |
197 | *br = i; | |
198 | *pbr = j; | |
199 | } | |
200 | break; | |
349ad66c CF |
201 | } |
202 | } | |
349ad66c | 203 | |
6fd63087 AB |
204 | if (minscale == INT_MAX) { |
205 | pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n", | |
206 | speed_hz, clkrate); | |
207 | *pbr = ARRAY_SIZE(pbr_tbl) - 1; | |
208 | *br = ARRAY_SIZE(brs) - 1; | |
209 | } | |
349ad66c | 210 | } |
349ad66c | 211 | |
95bf15f3 AB |
212 | static void ns_delay_scale(char *psc, char *sc, int delay_ns, |
213 | unsigned long clkrate) | |
214 | { | |
215 | int pscale_tbl[4] = {1, 3, 5, 7}; | |
216 | int scale_needed, scale, minscale = INT_MAX; | |
217 | int i, j; | |
218 | u32 remainder; | |
219 | ||
220 | scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC, | |
221 | &remainder); | |
222 | if (remainder) | |
223 | scale_needed++; | |
224 | ||
225 | for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++) | |
226 | for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) { | |
227 | scale = pscale_tbl[i] * (2 << j); | |
228 | if (scale >= scale_needed) { | |
229 | if (scale < minscale) { | |
230 | minscale = scale; | |
231 | *psc = i; | |
232 | *sc = j; | |
233 | } | |
234 | break; | |
349ad66c CF |
235 | } |
236 | } | |
237 | ||
95bf15f3 AB |
238 | if (minscale == INT_MAX) { |
239 | pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value", | |
240 | delay_ns, clkrate); | |
241 | *psc = ARRAY_SIZE(pscale_tbl) - 1; | |
242 | *sc = SPI_CTAR_SCALE_BITS; | |
243 | } | |
349ad66c CF |
244 | } |
245 | ||
d1f4a38c | 246 | static u32 dspi_data_to_pushr(struct fsl_dspi *dspi, int tx_word) |
349ad66c | 247 | { |
349ad66c | 248 | u16 d16; |
349ad66c | 249 | |
d1f4a38c HW |
250 | if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) |
251 | d16 = tx_word ? *(u16 *)dspi->tx : *(u8 *)dspi->tx; | |
252 | else | |
253 | d16 = dspi->void_write_data; | |
349ad66c | 254 | |
d1f4a38c HW |
255 | dspi->tx += tx_word + 1; |
256 | dspi->len -= tx_word + 1; | |
349ad66c | 257 | |
d1f4a38c HW |
258 | return SPI_PUSHR_TXDATA(d16) | |
259 | SPI_PUSHR_PCS(dspi->cs) | | |
ef22d160 | 260 | SPI_PUSHR_CTAS(0) | |
d1f4a38c HW |
261 | SPI_PUSHR_CONT; |
262 | } | |
349ad66c | 263 | |
d1f4a38c HW |
264 | static void dspi_data_from_popr(struct fsl_dspi *dspi, int rx_word) |
265 | { | |
266 | u16 d; | |
267 | unsigned int val; | |
349ad66c | 268 | |
d1f4a38c HW |
269 | regmap_read(dspi->regmap, SPI_POPR, &val); |
270 | d = SPI_POPR_RXDATA(val); | |
349ad66c | 271 | |
d1f4a38c HW |
272 | if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) |
273 | rx_word ? (*(u16 *)dspi->rx = d) : (*(u8 *)dspi->rx = d); | |
349ad66c | 274 | |
d1f4a38c HW |
275 | dspi->rx += rx_word + 1; |
276 | } | |
349ad66c | 277 | |
d1f4a38c HW |
278 | static int dspi_eoq_write(struct fsl_dspi *dspi) |
279 | { | |
280 | int tx_count = 0; | |
281 | int tx_word; | |
282 | u32 dspi_pushr = 0; | |
349ad66c | 283 | |
d1f4a38c HW |
284 | tx_word = is_double_byte_mode(dspi); |
285 | ||
286 | while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) { | |
287 | /* If we are in word mode, only have a single byte to transfer | |
288 | * switch to byte mode temporarily. Will switch back at the | |
289 | * end of the transfer. | |
290 | */ | |
291 | if (tx_word && (dspi->len == 1)) { | |
292 | dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM; | |
ef22d160 | 293 | regmap_update_bits(dspi->regmap, SPI_CTAR(0), |
d1f4a38c HW |
294 | SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8)); |
295 | tx_word = 0; | |
349ad66c CF |
296 | } |
297 | ||
d1f4a38c HW |
298 | dspi_pushr = dspi_data_to_pushr(dspi, tx_word); |
299 | ||
349ad66c CF |
300 | if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) { |
301 | /* last transfer in the transfer */ | |
302 | dspi_pushr |= SPI_PUSHR_EOQ; | |
9298bc72 CF |
303 | if ((dspi->cs_change) && (!dspi->len)) |
304 | dspi_pushr &= ~SPI_PUSHR_CONT; | |
349ad66c CF |
305 | } else if (tx_word && (dspi->len == 1)) |
306 | dspi_pushr |= SPI_PUSHR_EOQ; | |
307 | ||
1acbdeb9 CF |
308 | regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr); |
309 | ||
349ad66c CF |
310 | tx_count++; |
311 | } | |
312 | ||
313 | return tx_count * (tx_word + 1); | |
314 | } | |
315 | ||
d1f4a38c | 316 | static int dspi_eoq_read(struct fsl_dspi *dspi) |
349ad66c CF |
317 | { |
318 | int rx_count = 0; | |
319 | int rx_word = is_double_byte_mode(dspi); | |
9298bc72 | 320 | |
349ad66c CF |
321 | while ((dspi->rx < dspi->rx_end) |
322 | && (rx_count < DSPI_FIFO_SIZE)) { | |
d1f4a38c HW |
323 | if (rx_word && (dspi->rx_end - dspi->rx) == 1) |
324 | rx_word = 0; | |
1acbdeb9 | 325 | |
d1f4a38c HW |
326 | dspi_data_from_popr(dspi, rx_word); |
327 | rx_count++; | |
328 | } | |
349ad66c | 329 | |
d1f4a38c HW |
330 | return rx_count; |
331 | } | |
349ad66c | 332 | |
d1f4a38c HW |
333 | static int dspi_tcfq_write(struct fsl_dspi *dspi) |
334 | { | |
335 | int tx_word; | |
336 | u32 dspi_pushr = 0; | |
349ad66c | 337 | |
d1f4a38c | 338 | tx_word = is_double_byte_mode(dspi); |
1acbdeb9 | 339 | |
d1f4a38c HW |
340 | if (tx_word && (dspi->len == 1)) { |
341 | dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM; | |
ef22d160 | 342 | regmap_update_bits(dspi->regmap, SPI_CTAR(0), |
d1f4a38c HW |
343 | SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8)); |
344 | tx_word = 0; | |
349ad66c CF |
345 | } |
346 | ||
d1f4a38c HW |
347 | dspi_pushr = dspi_data_to_pushr(dspi, tx_word); |
348 | ||
349 | if ((dspi->cs_change) && (!dspi->len)) | |
350 | dspi_pushr &= ~SPI_PUSHR_CONT; | |
351 | ||
352 | regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr); | |
353 | ||
354 | return tx_word + 1; | |
355 | } | |
356 | ||
357 | static void dspi_tcfq_read(struct fsl_dspi *dspi) | |
358 | { | |
359 | int rx_word = is_double_byte_mode(dspi); | |
360 | ||
361 | if (rx_word && (dspi->rx_end - dspi->rx) == 1) | |
362 | rx_word = 0; | |
363 | ||
364 | dspi_data_from_popr(dspi, rx_word); | |
349ad66c CF |
365 | } |
366 | ||
9298bc72 CF |
367 | static int dspi_transfer_one_message(struct spi_master *master, |
368 | struct spi_message *message) | |
349ad66c | 369 | { |
9298bc72 CF |
370 | struct fsl_dspi *dspi = spi_master_get_devdata(master); |
371 | struct spi_device *spi = message->spi; | |
372 | struct spi_transfer *transfer; | |
373 | int status = 0; | |
d1f4a38c | 374 | enum dspi_trans_mode trans_mode; |
c042af95 HW |
375 | u32 spi_tcr; |
376 | ||
377 | regmap_read(dspi->regmap, SPI_TCR, &spi_tcr); | |
378 | dspi->spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr); | |
d1f4a38c | 379 | |
9298bc72 CF |
380 | message->actual_length = 0; |
381 | ||
382 | list_for_each_entry(transfer, &message->transfers, transfer_list) { | |
383 | dspi->cur_transfer = transfer; | |
384 | dspi->cur_msg = message; | |
385 | dspi->cur_chip = spi_get_ctldata(spi); | |
386 | dspi->cs = spi->chip_select; | |
9deef024 | 387 | dspi->cs_change = 0; |
92dc20d8 AV |
388 | if (list_is_last(&dspi->cur_transfer->transfer_list, |
389 | &dspi->cur_msg->transfers) || transfer->cs_change) | |
9deef024 | 390 | dspi->cs_change = 1; |
9298bc72 CF |
391 | dspi->void_write_data = dspi->cur_chip->void_write_data; |
392 | ||
393 | dspi->dataflags = 0; | |
394 | dspi->tx = (void *)transfer->tx_buf; | |
395 | dspi->tx_end = dspi->tx + transfer->len; | |
396 | dspi->rx = transfer->rx_buf; | |
397 | dspi->rx_end = dspi->rx + transfer->len; | |
398 | dspi->len = transfer->len; | |
399 | ||
400 | if (!dspi->rx) | |
401 | dspi->dataflags |= TRAN_STATE_RX_VOID; | |
402 | ||
403 | if (!dspi->tx) | |
404 | dspi->dataflags |= TRAN_STATE_TX_VOID; | |
405 | ||
406 | regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val); | |
407 | regmap_update_bits(dspi->regmap, SPI_MCR, | |
408 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, | |
409 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); | |
ef22d160 | 410 | regmap_write(dspi->regmap, SPI_CTAR(0), |
1acbdeb9 | 411 | dspi->cur_chip->ctar_val); |
349ad66c | 412 | |
d1f4a38c HW |
413 | trans_mode = dspi->devtype_data->trans_mode; |
414 | switch (trans_mode) { | |
415 | case DSPI_EOQ_MODE: | |
416 | regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); | |
c042af95 | 417 | dspi_eoq_write(dspi); |
d1f4a38c HW |
418 | break; |
419 | case DSPI_TCFQ_MODE: | |
420 | regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE); | |
c042af95 | 421 | dspi_tcfq_write(dspi); |
d1f4a38c HW |
422 | break; |
423 | default: | |
424 | dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", | |
425 | trans_mode); | |
426 | status = -EINVAL; | |
427 | goto out; | |
428 | } | |
1acbdeb9 | 429 | |
9298bc72 CF |
430 | if (wait_event_interruptible(dspi->waitq, dspi->waitflags)) |
431 | dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n"); | |
432 | dspi->waitflags = 0; | |
349ad66c | 433 | |
9298bc72 CF |
434 | if (transfer->delay_usecs) |
435 | udelay(transfer->delay_usecs); | |
349ad66c CF |
436 | } |
437 | ||
d1f4a38c | 438 | out: |
9298bc72 CF |
439 | message->status = status; |
440 | spi_finalize_current_message(master); | |
441 | ||
442 | return status; | |
349ad66c CF |
443 | } |
444 | ||
9298bc72 | 445 | static int dspi_setup(struct spi_device *spi) |
349ad66c CF |
446 | { |
447 | struct chip_data *chip; | |
448 | struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); | |
95bf15f3 AB |
449 | u32 cs_sck_delay = 0, sck_cs_delay = 0; |
450 | unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0; | |
451 | unsigned char pasc = 0, asc = 0, fmsz = 0; | |
452 | unsigned long clkrate; | |
349ad66c | 453 | |
ceadfd8d BD |
454 | if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) { |
455 | fmsz = spi->bits_per_word - 1; | |
456 | } else { | |
457 | pr_err("Invalid wordsize\n"); | |
458 | return -ENODEV; | |
459 | } | |
460 | ||
349ad66c CF |
461 | /* Only alloc on first setup */ |
462 | chip = spi_get_ctldata(spi); | |
463 | if (chip == NULL) { | |
973fbce6 | 464 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
349ad66c CF |
465 | if (!chip) |
466 | return -ENOMEM; | |
467 | } | |
468 | ||
95bf15f3 AB |
469 | of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay", |
470 | &cs_sck_delay); | |
471 | ||
472 | of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay", | |
473 | &sck_cs_delay); | |
474 | ||
349ad66c CF |
475 | chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS | |
476 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF; | |
349ad66c CF |
477 | |
478 | chip->void_write_data = 0; | |
479 | ||
95bf15f3 AB |
480 | clkrate = clk_get_rate(dspi->clk); |
481 | hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate); | |
482 | ||
483 | /* Set PCS to SCK delay scale values */ | |
484 | ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate); | |
485 | ||
486 | /* Set After SCK delay scale values */ | |
487 | ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate); | |
349ad66c CF |
488 | |
489 | chip->ctar_val = SPI_CTAR_FMSZ(fmsz) | |
490 | | SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0) | |
491 | | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0) | |
492 | | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0) | |
95bf15f3 AB |
493 | | SPI_CTAR_PCSSCK(pcssck) |
494 | | SPI_CTAR_CSSCK(cssck) | |
495 | | SPI_CTAR_PASC(pasc) | |
496 | | SPI_CTAR_ASC(asc) | |
349ad66c CF |
497 | | SPI_CTAR_PBR(pbr) |
498 | | SPI_CTAR_BR(br); | |
499 | ||
500 | spi_set_ctldata(spi, chip); | |
501 | ||
502 | return 0; | |
503 | } | |
504 | ||
973fbce6 BD |
505 | static void dspi_cleanup(struct spi_device *spi) |
506 | { | |
507 | struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi); | |
508 | ||
509 | dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n", | |
510 | spi->master->bus_num, spi->chip_select); | |
511 | ||
512 | kfree(chip); | |
513 | } | |
514 | ||
349ad66c CF |
515 | static irqreturn_t dspi_interrupt(int irq, void *dev_id) |
516 | { | |
517 | struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; | |
9298bc72 | 518 | struct spi_message *msg = dspi->cur_msg; |
d1f4a38c | 519 | enum dspi_trans_mode trans_mode; |
c042af95 HW |
520 | u32 spi_sr, spi_tcr; |
521 | u32 spi_tcnt, tcnt_diff; | |
522 | int tx_word; | |
d1f4a38c HW |
523 | |
524 | regmap_read(dspi->regmap, SPI_SR, &spi_sr); | |
525 | regmap_write(dspi->regmap, SPI_SR, spi_sr); | |
526 | ||
349ad66c | 527 | |
c042af95 HW |
528 | if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) { |
529 | tx_word = is_double_byte_mode(dspi); | |
1acbdeb9 | 530 | |
c042af95 HW |
531 | regmap_read(dspi->regmap, SPI_TCR, &spi_tcr); |
532 | spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr); | |
533 | /* | |
534 | * The width of SPI Transfer Counter in SPI_TCR is 16bits, | |
535 | * so the max couner is 65535. When the counter reach 65535, | |
536 | * it will wrap around, counter reset to zero. | |
537 | * spi_tcnt my be less than dspi->spi_tcnt, it means the | |
538 | * counter already wrapped around. | |
539 | * SPI Transfer Counter is a counter of transmitted frames. | |
540 | * The size of frame maybe two bytes. | |
541 | */ | |
542 | tcnt_diff = ((spi_tcnt + SPI_TCR_TCNT_MAX) - dspi->spi_tcnt) | |
543 | % SPI_TCR_TCNT_MAX; | |
544 | tcnt_diff *= (tx_word + 1); | |
545 | if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) | |
546 | tcnt_diff--; | |
547 | ||
548 | msg->actual_length += tcnt_diff; | |
549 | ||
550 | dspi->spi_tcnt = spi_tcnt; | |
551 | ||
552 | trans_mode = dspi->devtype_data->trans_mode; | |
d1f4a38c HW |
553 | switch (trans_mode) { |
554 | case DSPI_EOQ_MODE: | |
c042af95 | 555 | dspi_eoq_read(dspi); |
d1f4a38c HW |
556 | break; |
557 | case DSPI_TCFQ_MODE: | |
c042af95 | 558 | dspi_tcfq_read(dspi); |
d1f4a38c HW |
559 | break; |
560 | default: | |
561 | dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", | |
562 | trans_mode); | |
c042af95 HW |
563 | return IRQ_HANDLED; |
564 | } | |
565 | ||
566 | if (!dspi->len) { | |
567 | if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) { | |
568 | regmap_update_bits(dspi->regmap, | |
ef22d160 | 569 | SPI_CTAR(0), |
c042af95 HW |
570 | SPI_FRAME_BITS_MASK, |
571 | SPI_FRAME_BITS(16)); | |
572 | dspi->dataflags &= ~TRAN_STATE_WORD_ODD_NUM; | |
573 | } | |
574 | ||
575 | dspi->waitflags = 1; | |
576 | wake_up_interruptible(&dspi->waitq); | |
577 | } else { | |
578 | switch (trans_mode) { | |
579 | case DSPI_EOQ_MODE: | |
580 | dspi_eoq_write(dspi); | |
581 | break; | |
582 | case DSPI_TCFQ_MODE: | |
583 | dspi_tcfq_write(dspi); | |
584 | break; | |
585 | default: | |
586 | dev_err(&dspi->pdev->dev, | |
587 | "unsupported trans_mode %u\n", | |
588 | trans_mode); | |
589 | } | |
d1f4a38c HW |
590 | } |
591 | } | |
c042af95 | 592 | |
349ad66c CF |
593 | return IRQ_HANDLED; |
594 | } | |
595 | ||
790d1902 | 596 | static const struct of_device_id fsl_dspi_dt_ids[] = { |
d1f4a38c HW |
597 | { .compatible = "fsl,vf610-dspi", .data = (void *)&vf610_data, }, |
598 | { .compatible = "fsl,ls1021a-v1.0-dspi", | |
599 | .data = (void *)&ls1021a_v1_data, }, | |
600 | { .compatible = "fsl,ls2085a-dspi", .data = (void *)&ls2085a_data, }, | |
349ad66c CF |
601 | { /* sentinel */ } |
602 | }; | |
603 | MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); | |
604 | ||
605 | #ifdef CONFIG_PM_SLEEP | |
606 | static int dspi_suspend(struct device *dev) | |
607 | { | |
608 | struct spi_master *master = dev_get_drvdata(dev); | |
609 | struct fsl_dspi *dspi = spi_master_get_devdata(master); | |
610 | ||
611 | spi_master_suspend(master); | |
612 | clk_disable_unprepare(dspi->clk); | |
613 | ||
432a17d7 MK |
614 | pinctrl_pm_select_sleep_state(dev); |
615 | ||
349ad66c CF |
616 | return 0; |
617 | } | |
618 | ||
619 | static int dspi_resume(struct device *dev) | |
620 | { | |
349ad66c CF |
621 | struct spi_master *master = dev_get_drvdata(dev); |
622 | struct fsl_dspi *dspi = spi_master_get_devdata(master); | |
623 | ||
432a17d7 MK |
624 | pinctrl_pm_select_default_state(dev); |
625 | ||
349ad66c CF |
626 | clk_prepare_enable(dspi->clk); |
627 | spi_master_resume(master); | |
628 | ||
629 | return 0; | |
630 | } | |
631 | #endif /* CONFIG_PM_SLEEP */ | |
632 | ||
ba811add | 633 | static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume); |
349ad66c | 634 | |
409851c3 | 635 | static const struct regmap_config dspi_regmap_config = { |
1acbdeb9 CF |
636 | .reg_bits = 32, |
637 | .val_bits = 32, | |
638 | .reg_stride = 4, | |
639 | .max_register = 0x88, | |
349ad66c CF |
640 | }; |
641 | ||
642 | static int dspi_probe(struct platform_device *pdev) | |
643 | { | |
644 | struct device_node *np = pdev->dev.of_node; | |
645 | struct spi_master *master; | |
646 | struct fsl_dspi *dspi; | |
647 | struct resource *res; | |
1acbdeb9 | 648 | void __iomem *base; |
349ad66c | 649 | int ret = 0, cs_num, bus_num; |
d1f4a38c HW |
650 | const struct of_device_id *of_id = |
651 | of_match_device(fsl_dspi_dt_ids, &pdev->dev); | |
349ad66c CF |
652 | |
653 | master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); | |
654 | if (!master) | |
655 | return -ENOMEM; | |
656 | ||
657 | dspi = spi_master_get_devdata(master); | |
658 | dspi->pdev = pdev; | |
9298bc72 CF |
659 | dspi->master = master; |
660 | ||
661 | master->transfer = NULL; | |
662 | master->setup = dspi_setup; | |
663 | master->transfer_one_message = dspi_transfer_one_message; | |
664 | master->dev.of_node = pdev->dev.of_node; | |
349ad66c | 665 | |
973fbce6 | 666 | master->cleanup = dspi_cleanup; |
349ad66c CF |
667 | master->mode_bits = SPI_CPOL | SPI_CPHA; |
668 | master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) | | |
669 | SPI_BPW_MASK(16); | |
670 | ||
671 | ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); | |
672 | if (ret < 0) { | |
673 | dev_err(&pdev->dev, "can't get spi-num-chipselects\n"); | |
674 | goto out_master_put; | |
675 | } | |
676 | master->num_chipselect = cs_num; | |
677 | ||
678 | ret = of_property_read_u32(np, "bus-num", &bus_num); | |
679 | if (ret < 0) { | |
680 | dev_err(&pdev->dev, "can't get bus-num\n"); | |
681 | goto out_master_put; | |
682 | } | |
683 | master->bus_num = bus_num; | |
684 | ||
d1f4a38c HW |
685 | dspi->devtype_data = (struct fsl_dspi_devtype_data *)of_id->data; |
686 | if (!dspi->devtype_data) { | |
687 | dev_err(&pdev->dev, "can't get devtype_data\n"); | |
688 | ret = -EFAULT; | |
689 | goto out_master_put; | |
690 | } | |
691 | ||
349ad66c | 692 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1acbdeb9 CF |
693 | base = devm_ioremap_resource(&pdev->dev, res); |
694 | if (IS_ERR(base)) { | |
695 | ret = PTR_ERR(base); | |
349ad66c CF |
696 | goto out_master_put; |
697 | } | |
698 | ||
d2233325 | 699 | dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base, |
1acbdeb9 CF |
700 | &dspi_regmap_config); |
701 | if (IS_ERR(dspi->regmap)) { | |
702 | dev_err(&pdev->dev, "failed to init regmap: %ld\n", | |
703 | PTR_ERR(dspi->regmap)); | |
704 | return PTR_ERR(dspi->regmap); | |
705 | } | |
706 | ||
349ad66c CF |
707 | dspi->irq = platform_get_irq(pdev, 0); |
708 | if (dspi->irq < 0) { | |
709 | dev_err(&pdev->dev, "can't get platform irq\n"); | |
710 | ret = dspi->irq; | |
711 | goto out_master_put; | |
712 | } | |
713 | ||
714 | ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0, | |
715 | pdev->name, dspi); | |
716 | if (ret < 0) { | |
717 | dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n"); | |
718 | goto out_master_put; | |
719 | } | |
720 | ||
721 | dspi->clk = devm_clk_get(&pdev->dev, "dspi"); | |
722 | if (IS_ERR(dspi->clk)) { | |
723 | ret = PTR_ERR(dspi->clk); | |
724 | dev_err(&pdev->dev, "unable to get clock\n"); | |
725 | goto out_master_put; | |
726 | } | |
727 | clk_prepare_enable(dspi->clk); | |
728 | ||
729 | init_waitqueue_head(&dspi->waitq); | |
017145fe | 730 | platform_set_drvdata(pdev, master); |
349ad66c | 731 | |
9298bc72 | 732 | ret = spi_register_master(master); |
349ad66c CF |
733 | if (ret != 0) { |
734 | dev_err(&pdev->dev, "Problem registering DSPI master\n"); | |
735 | goto out_clk_put; | |
736 | } | |
737 | ||
349ad66c CF |
738 | return ret; |
739 | ||
740 | out_clk_put: | |
741 | clk_disable_unprepare(dspi->clk); | |
742 | out_master_put: | |
743 | spi_master_put(master); | |
349ad66c CF |
744 | |
745 | return ret; | |
746 | } | |
747 | ||
748 | static int dspi_remove(struct platform_device *pdev) | |
749 | { | |
017145fe AL |
750 | struct spi_master *master = platform_get_drvdata(pdev); |
751 | struct fsl_dspi *dspi = spi_master_get_devdata(master); | |
349ad66c CF |
752 | |
753 | /* Disconnect from the SPI framework */ | |
05209f45 | 754 | clk_disable_unprepare(dspi->clk); |
9298bc72 CF |
755 | spi_unregister_master(dspi->master); |
756 | spi_master_put(dspi->master); | |
349ad66c CF |
757 | |
758 | return 0; | |
759 | } | |
760 | ||
761 | static struct platform_driver fsl_dspi_driver = { | |
762 | .driver.name = DRIVER_NAME, | |
763 | .driver.of_match_table = fsl_dspi_dt_ids, | |
764 | .driver.owner = THIS_MODULE, | |
765 | .driver.pm = &dspi_pm, | |
766 | .probe = dspi_probe, | |
767 | .remove = dspi_remove, | |
768 | }; | |
769 | module_platform_driver(fsl_dspi_driver); | |
770 | ||
771 | MODULE_DESCRIPTION("Freescale DSPI Controller Driver"); | |
b444d1df | 772 | MODULE_LICENSE("GPL"); |
349ad66c | 773 | MODULE_ALIAS("platform:" DRIVER_NAME); |