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349ad66c CF |
1 | /* |
2 | * drivers/spi/spi-fsl-dspi.c | |
3 | * | |
4 | * Copyright 2013 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * Freescale DSPI driver | |
7 | * This file contains a driver for the Freescale DSPI | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | */ | |
15 | ||
a3108360 XL |
16 | #include <linux/clk.h> |
17 | #include <linux/delay.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/errno.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io.h> | |
349ad66c | 22 | #include <linux/kernel.h> |
95bf15f3 | 23 | #include <linux/math64.h> |
349ad66c | 24 | #include <linux/module.h> |
a3108360 XL |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
349ad66c | 27 | #include <linux/platform_device.h> |
a3108360 | 28 | #include <linux/pm_runtime.h> |
1acbdeb9 | 29 | #include <linux/regmap.h> |
349ad66c | 30 | #include <linux/sched.h> |
349ad66c CF |
31 | #include <linux/spi/spi.h> |
32 | #include <linux/spi/spi_bitbang.h> | |
95bf15f3 | 33 | #include <linux/time.h> |
349ad66c CF |
34 | |
35 | #define DRIVER_NAME "fsl-dspi" | |
36 | ||
37 | #define TRAN_STATE_RX_VOID 0x01 | |
38 | #define TRAN_STATE_TX_VOID 0x02 | |
39 | #define TRAN_STATE_WORD_ODD_NUM 0x04 | |
40 | ||
41 | #define DSPI_FIFO_SIZE 4 | |
42 | ||
43 | #define SPI_MCR 0x00 | |
44 | #define SPI_MCR_MASTER (1 << 31) | |
45 | #define SPI_MCR_PCSIS (0x3F << 16) | |
46 | #define SPI_MCR_CLR_TXF (1 << 11) | |
47 | #define SPI_MCR_CLR_RXF (1 << 10) | |
48 | ||
49 | #define SPI_TCR 0x08 | |
c042af95 | 50 | #define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16) |
349ad66c | 51 | |
5cc7b047 | 52 | #define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4)) |
349ad66c CF |
53 | #define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27) |
54 | #define SPI_CTAR_CPOL(x) ((x) << 26) | |
55 | #define SPI_CTAR_CPHA(x) ((x) << 25) | |
56 | #define SPI_CTAR_LSBFE(x) ((x) << 24) | |
95bf15f3 | 57 | #define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22) |
349ad66c CF |
58 | #define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20) |
59 | #define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18) | |
60 | #define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16) | |
61 | #define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12) | |
62 | #define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8) | |
63 | #define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4) | |
64 | #define SPI_CTAR_BR(x) ((x) & 0x0000000f) | |
95bf15f3 | 65 | #define SPI_CTAR_SCALE_BITS 0xf |
349ad66c CF |
66 | |
67 | #define SPI_CTAR0_SLAVE 0x0c | |
68 | ||
69 | #define SPI_SR 0x2c | |
70 | #define SPI_SR_EOQF 0x10000000 | |
d1f4a38c | 71 | #define SPI_SR_TCFQF 0x80000000 |
349ad66c CF |
72 | |
73 | #define SPI_RSER 0x30 | |
74 | #define SPI_RSER_EOQFE 0x10000000 | |
d1f4a38c | 75 | #define SPI_RSER_TCFQE 0x80000000 |
349ad66c CF |
76 | |
77 | #define SPI_PUSHR 0x34 | |
78 | #define SPI_PUSHR_CONT (1 << 31) | |
5cc7b047 | 79 | #define SPI_PUSHR_CTAS(x) (((x) & 0x00000003) << 28) |
349ad66c CF |
80 | #define SPI_PUSHR_EOQ (1 << 27) |
81 | #define SPI_PUSHR_CTCNT (1 << 26) | |
82 | #define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16) | |
83 | #define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff) | |
84 | ||
85 | #define SPI_PUSHR_SLAVE 0x34 | |
86 | ||
87 | #define SPI_POPR 0x38 | |
88 | #define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff) | |
89 | ||
90 | #define SPI_TXFR0 0x3c | |
91 | #define SPI_TXFR1 0x40 | |
92 | #define SPI_TXFR2 0x44 | |
93 | #define SPI_TXFR3 0x48 | |
94 | #define SPI_RXFR0 0x7c | |
95 | #define SPI_RXFR1 0x80 | |
96 | #define SPI_RXFR2 0x84 | |
97 | #define SPI_RXFR3 0x88 | |
98 | ||
99 | #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1) | |
100 | #define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf) | |
101 | #define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf) | |
102 | #define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7) | |
103 | ||
104 | #define SPI_CS_INIT 0x01 | |
105 | #define SPI_CS_ASSERT 0x02 | |
106 | #define SPI_CS_DROP 0x04 | |
107 | ||
c042af95 HW |
108 | #define SPI_TCR_TCNT_MAX 0x10000 |
109 | ||
349ad66c CF |
110 | struct chip_data { |
111 | u32 mcr_val; | |
112 | u32 ctar_val; | |
113 | u16 void_write_data; | |
114 | }; | |
115 | ||
d1f4a38c HW |
116 | enum dspi_trans_mode { |
117 | DSPI_EOQ_MODE = 0, | |
118 | DSPI_TCFQ_MODE, | |
119 | }; | |
120 | ||
121 | struct fsl_dspi_devtype_data { | |
122 | enum dspi_trans_mode trans_mode; | |
123 | }; | |
124 | ||
125 | static const struct fsl_dspi_devtype_data vf610_data = { | |
126 | .trans_mode = DSPI_EOQ_MODE, | |
127 | }; | |
128 | ||
129 | static const struct fsl_dspi_devtype_data ls1021a_v1_data = { | |
130 | .trans_mode = DSPI_TCFQ_MODE, | |
131 | }; | |
132 | ||
133 | static const struct fsl_dspi_devtype_data ls2085a_data = { | |
134 | .trans_mode = DSPI_TCFQ_MODE, | |
135 | }; | |
136 | ||
349ad66c | 137 | struct fsl_dspi { |
9298bc72 | 138 | struct spi_master *master; |
349ad66c CF |
139 | struct platform_device *pdev; |
140 | ||
1acbdeb9 | 141 | struct regmap *regmap; |
349ad66c | 142 | int irq; |
88386e85 | 143 | struct clk *clk; |
349ad66c | 144 | |
88386e85 | 145 | struct spi_transfer *cur_transfer; |
9298bc72 | 146 | struct spi_message *cur_msg; |
349ad66c CF |
147 | struct chip_data *cur_chip; |
148 | size_t len; | |
149 | void *tx; | |
150 | void *tx_end; | |
151 | void *rx; | |
152 | void *rx_end; | |
153 | char dataflags; | |
154 | u8 cs; | |
155 | u16 void_write_data; | |
9298bc72 | 156 | u32 cs_change; |
d1f4a38c | 157 | struct fsl_dspi_devtype_data *devtype_data; |
349ad66c | 158 | |
88386e85 CF |
159 | wait_queue_head_t waitq; |
160 | u32 waitflags; | |
c042af95 HW |
161 | |
162 | u32 spi_tcnt; | |
349ad66c CF |
163 | }; |
164 | ||
165 | static inline int is_double_byte_mode(struct fsl_dspi *dspi) | |
166 | { | |
1acbdeb9 | 167 | unsigned int val; |
349ad66c | 168 | |
1acbdeb9 | 169 | regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val); |
349ad66c | 170 | |
1acbdeb9 | 171 | return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1; |
349ad66c CF |
172 | } |
173 | ||
174 | static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, | |
175 | unsigned long clkrate) | |
176 | { | |
177 | /* Valid baud rate pre-scaler values */ | |
178 | int pbr_tbl[4] = {2, 3, 5, 7}; | |
179 | int brs[16] = { 2, 4, 6, 8, | |
180 | 16, 32, 64, 128, | |
181 | 256, 512, 1024, 2048, | |
182 | 4096, 8192, 16384, 32768 }; | |
6fd63087 AB |
183 | int scale_needed, scale, minscale = INT_MAX; |
184 | int i, j; | |
185 | ||
186 | scale_needed = clkrate / speed_hz; | |
e689d6df AB |
187 | if (clkrate % speed_hz) |
188 | scale_needed++; | |
6fd63087 AB |
189 | |
190 | for (i = 0; i < ARRAY_SIZE(brs); i++) | |
191 | for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) { | |
192 | scale = brs[i] * pbr_tbl[j]; | |
193 | if (scale >= scale_needed) { | |
194 | if (scale < minscale) { | |
195 | minscale = scale; | |
196 | *br = i; | |
197 | *pbr = j; | |
198 | } | |
199 | break; | |
349ad66c CF |
200 | } |
201 | } | |
349ad66c | 202 | |
6fd63087 AB |
203 | if (minscale == INT_MAX) { |
204 | pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n", | |
205 | speed_hz, clkrate); | |
206 | *pbr = ARRAY_SIZE(pbr_tbl) - 1; | |
207 | *br = ARRAY_SIZE(brs) - 1; | |
208 | } | |
349ad66c | 209 | } |
349ad66c | 210 | |
95bf15f3 AB |
211 | static void ns_delay_scale(char *psc, char *sc, int delay_ns, |
212 | unsigned long clkrate) | |
213 | { | |
214 | int pscale_tbl[4] = {1, 3, 5, 7}; | |
215 | int scale_needed, scale, minscale = INT_MAX; | |
216 | int i, j; | |
217 | u32 remainder; | |
218 | ||
219 | scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC, | |
220 | &remainder); | |
221 | if (remainder) | |
222 | scale_needed++; | |
223 | ||
224 | for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++) | |
225 | for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) { | |
226 | scale = pscale_tbl[i] * (2 << j); | |
227 | if (scale >= scale_needed) { | |
228 | if (scale < minscale) { | |
229 | minscale = scale; | |
230 | *psc = i; | |
231 | *sc = j; | |
232 | } | |
233 | break; | |
349ad66c CF |
234 | } |
235 | } | |
236 | ||
95bf15f3 AB |
237 | if (minscale == INT_MAX) { |
238 | pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value", | |
239 | delay_ns, clkrate); | |
240 | *psc = ARRAY_SIZE(pscale_tbl) - 1; | |
241 | *sc = SPI_CTAR_SCALE_BITS; | |
242 | } | |
349ad66c CF |
243 | } |
244 | ||
d1f4a38c | 245 | static u32 dspi_data_to_pushr(struct fsl_dspi *dspi, int tx_word) |
349ad66c | 246 | { |
349ad66c | 247 | u16 d16; |
349ad66c | 248 | |
d1f4a38c HW |
249 | if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) |
250 | d16 = tx_word ? *(u16 *)dspi->tx : *(u8 *)dspi->tx; | |
251 | else | |
252 | d16 = dspi->void_write_data; | |
349ad66c | 253 | |
d1f4a38c HW |
254 | dspi->tx += tx_word + 1; |
255 | dspi->len -= tx_word + 1; | |
349ad66c | 256 | |
d1f4a38c HW |
257 | return SPI_PUSHR_TXDATA(d16) | |
258 | SPI_PUSHR_PCS(dspi->cs) | | |
259 | SPI_PUSHR_CTAS(dspi->cs) | | |
260 | SPI_PUSHR_CONT; | |
261 | } | |
349ad66c | 262 | |
d1f4a38c HW |
263 | static void dspi_data_from_popr(struct fsl_dspi *dspi, int rx_word) |
264 | { | |
265 | u16 d; | |
266 | unsigned int val; | |
349ad66c | 267 | |
d1f4a38c HW |
268 | regmap_read(dspi->regmap, SPI_POPR, &val); |
269 | d = SPI_POPR_RXDATA(val); | |
349ad66c | 270 | |
d1f4a38c HW |
271 | if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) |
272 | rx_word ? (*(u16 *)dspi->rx = d) : (*(u8 *)dspi->rx = d); | |
349ad66c | 273 | |
d1f4a38c HW |
274 | dspi->rx += rx_word + 1; |
275 | } | |
349ad66c | 276 | |
d1f4a38c HW |
277 | static int dspi_eoq_write(struct fsl_dspi *dspi) |
278 | { | |
279 | int tx_count = 0; | |
280 | int tx_word; | |
281 | u32 dspi_pushr = 0; | |
349ad66c | 282 | |
d1f4a38c HW |
283 | tx_word = is_double_byte_mode(dspi); |
284 | ||
285 | while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) { | |
286 | /* If we are in word mode, only have a single byte to transfer | |
287 | * switch to byte mode temporarily. Will switch back at the | |
288 | * end of the transfer. | |
289 | */ | |
290 | if (tx_word && (dspi->len == 1)) { | |
291 | dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM; | |
292 | regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs), | |
293 | SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8)); | |
294 | tx_word = 0; | |
349ad66c CF |
295 | } |
296 | ||
d1f4a38c HW |
297 | dspi_pushr = dspi_data_to_pushr(dspi, tx_word); |
298 | ||
349ad66c CF |
299 | if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) { |
300 | /* last transfer in the transfer */ | |
301 | dspi_pushr |= SPI_PUSHR_EOQ; | |
9298bc72 CF |
302 | if ((dspi->cs_change) && (!dspi->len)) |
303 | dspi_pushr &= ~SPI_PUSHR_CONT; | |
349ad66c CF |
304 | } else if (tx_word && (dspi->len == 1)) |
305 | dspi_pushr |= SPI_PUSHR_EOQ; | |
306 | ||
1acbdeb9 CF |
307 | regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr); |
308 | ||
349ad66c CF |
309 | tx_count++; |
310 | } | |
311 | ||
312 | return tx_count * (tx_word + 1); | |
313 | } | |
314 | ||
d1f4a38c | 315 | static int dspi_eoq_read(struct fsl_dspi *dspi) |
349ad66c CF |
316 | { |
317 | int rx_count = 0; | |
318 | int rx_word = is_double_byte_mode(dspi); | |
9298bc72 | 319 | |
349ad66c CF |
320 | while ((dspi->rx < dspi->rx_end) |
321 | && (rx_count < DSPI_FIFO_SIZE)) { | |
d1f4a38c HW |
322 | if (rx_word && (dspi->rx_end - dspi->rx) == 1) |
323 | rx_word = 0; | |
1acbdeb9 | 324 | |
d1f4a38c HW |
325 | dspi_data_from_popr(dspi, rx_word); |
326 | rx_count++; | |
327 | } | |
349ad66c | 328 | |
d1f4a38c HW |
329 | return rx_count; |
330 | } | |
349ad66c | 331 | |
d1f4a38c HW |
332 | static int dspi_tcfq_write(struct fsl_dspi *dspi) |
333 | { | |
334 | int tx_word; | |
335 | u32 dspi_pushr = 0; | |
349ad66c | 336 | |
d1f4a38c | 337 | tx_word = is_double_byte_mode(dspi); |
1acbdeb9 | 338 | |
d1f4a38c HW |
339 | if (tx_word && (dspi->len == 1)) { |
340 | dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM; | |
341 | regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs), | |
342 | SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8)); | |
343 | tx_word = 0; | |
349ad66c CF |
344 | } |
345 | ||
d1f4a38c HW |
346 | dspi_pushr = dspi_data_to_pushr(dspi, tx_word); |
347 | ||
348 | if ((dspi->cs_change) && (!dspi->len)) | |
349 | dspi_pushr &= ~SPI_PUSHR_CONT; | |
350 | ||
351 | regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr); | |
352 | ||
353 | return tx_word + 1; | |
354 | } | |
355 | ||
356 | static void dspi_tcfq_read(struct fsl_dspi *dspi) | |
357 | { | |
358 | int rx_word = is_double_byte_mode(dspi); | |
359 | ||
360 | if (rx_word && (dspi->rx_end - dspi->rx) == 1) | |
361 | rx_word = 0; | |
362 | ||
363 | dspi_data_from_popr(dspi, rx_word); | |
349ad66c CF |
364 | } |
365 | ||
9298bc72 CF |
366 | static int dspi_transfer_one_message(struct spi_master *master, |
367 | struct spi_message *message) | |
349ad66c | 368 | { |
9298bc72 CF |
369 | struct fsl_dspi *dspi = spi_master_get_devdata(master); |
370 | struct spi_device *spi = message->spi; | |
371 | struct spi_transfer *transfer; | |
372 | int status = 0; | |
d1f4a38c | 373 | enum dspi_trans_mode trans_mode; |
c042af95 HW |
374 | u32 spi_tcr; |
375 | ||
376 | regmap_read(dspi->regmap, SPI_TCR, &spi_tcr); | |
377 | dspi->spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr); | |
d1f4a38c | 378 | |
9298bc72 CF |
379 | message->actual_length = 0; |
380 | ||
381 | list_for_each_entry(transfer, &message->transfers, transfer_list) { | |
382 | dspi->cur_transfer = transfer; | |
383 | dspi->cur_msg = message; | |
384 | dspi->cur_chip = spi_get_ctldata(spi); | |
385 | dspi->cs = spi->chip_select; | |
9deef024 | 386 | dspi->cs_change = 0; |
9298bc72 CF |
387 | if (dspi->cur_transfer->transfer_list.next |
388 | == &dspi->cur_msg->transfers) | |
9deef024 | 389 | dspi->cs_change = 1; |
9298bc72 CF |
390 | dspi->void_write_data = dspi->cur_chip->void_write_data; |
391 | ||
392 | dspi->dataflags = 0; | |
393 | dspi->tx = (void *)transfer->tx_buf; | |
394 | dspi->tx_end = dspi->tx + transfer->len; | |
395 | dspi->rx = transfer->rx_buf; | |
396 | dspi->rx_end = dspi->rx + transfer->len; | |
397 | dspi->len = transfer->len; | |
398 | ||
399 | if (!dspi->rx) | |
400 | dspi->dataflags |= TRAN_STATE_RX_VOID; | |
401 | ||
402 | if (!dspi->tx) | |
403 | dspi->dataflags |= TRAN_STATE_TX_VOID; | |
404 | ||
405 | regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val); | |
406 | regmap_update_bits(dspi->regmap, SPI_MCR, | |
407 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, | |
408 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); | |
1acbdeb9 CF |
409 | regmap_write(dspi->regmap, SPI_CTAR(dspi->cs), |
410 | dspi->cur_chip->ctar_val); | |
9298bc72 CF |
411 | if (transfer->speed_hz) |
412 | regmap_write(dspi->regmap, SPI_CTAR(dspi->cs), | |
413 | dspi->cur_chip->ctar_val); | |
349ad66c | 414 | |
d1f4a38c HW |
415 | trans_mode = dspi->devtype_data->trans_mode; |
416 | switch (trans_mode) { | |
417 | case DSPI_EOQ_MODE: | |
418 | regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); | |
c042af95 | 419 | dspi_eoq_write(dspi); |
d1f4a38c HW |
420 | break; |
421 | case DSPI_TCFQ_MODE: | |
422 | regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE); | |
c042af95 | 423 | dspi_tcfq_write(dspi); |
d1f4a38c HW |
424 | break; |
425 | default: | |
426 | dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", | |
427 | trans_mode); | |
428 | status = -EINVAL; | |
429 | goto out; | |
430 | } | |
1acbdeb9 | 431 | |
9298bc72 CF |
432 | if (wait_event_interruptible(dspi->waitq, dspi->waitflags)) |
433 | dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n"); | |
434 | dspi->waitflags = 0; | |
349ad66c | 435 | |
9298bc72 CF |
436 | if (transfer->delay_usecs) |
437 | udelay(transfer->delay_usecs); | |
349ad66c CF |
438 | } |
439 | ||
d1f4a38c | 440 | out: |
9298bc72 CF |
441 | message->status = status; |
442 | spi_finalize_current_message(master); | |
443 | ||
444 | return status; | |
349ad66c CF |
445 | } |
446 | ||
9298bc72 | 447 | static int dspi_setup(struct spi_device *spi) |
349ad66c CF |
448 | { |
449 | struct chip_data *chip; | |
450 | struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); | |
95bf15f3 AB |
451 | u32 cs_sck_delay = 0, sck_cs_delay = 0; |
452 | unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0; | |
453 | unsigned char pasc = 0, asc = 0, fmsz = 0; | |
454 | unsigned long clkrate; | |
349ad66c | 455 | |
ceadfd8d BD |
456 | if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) { |
457 | fmsz = spi->bits_per_word - 1; | |
458 | } else { | |
459 | pr_err("Invalid wordsize\n"); | |
460 | return -ENODEV; | |
461 | } | |
462 | ||
349ad66c CF |
463 | /* Only alloc on first setup */ |
464 | chip = spi_get_ctldata(spi); | |
465 | if (chip == NULL) { | |
973fbce6 | 466 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
349ad66c CF |
467 | if (!chip) |
468 | return -ENOMEM; | |
469 | } | |
470 | ||
95bf15f3 AB |
471 | of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay", |
472 | &cs_sck_delay); | |
473 | ||
474 | of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay", | |
475 | &sck_cs_delay); | |
476 | ||
349ad66c CF |
477 | chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS | |
478 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF; | |
349ad66c CF |
479 | |
480 | chip->void_write_data = 0; | |
481 | ||
95bf15f3 AB |
482 | clkrate = clk_get_rate(dspi->clk); |
483 | hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate); | |
484 | ||
485 | /* Set PCS to SCK delay scale values */ | |
486 | ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate); | |
487 | ||
488 | /* Set After SCK delay scale values */ | |
489 | ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate); | |
349ad66c CF |
490 | |
491 | chip->ctar_val = SPI_CTAR_FMSZ(fmsz) | |
492 | | SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0) | |
493 | | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0) | |
494 | | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0) | |
95bf15f3 AB |
495 | | SPI_CTAR_PCSSCK(pcssck) |
496 | | SPI_CTAR_CSSCK(cssck) | |
497 | | SPI_CTAR_PASC(pasc) | |
498 | | SPI_CTAR_ASC(asc) | |
349ad66c CF |
499 | | SPI_CTAR_PBR(pbr) |
500 | | SPI_CTAR_BR(br); | |
501 | ||
502 | spi_set_ctldata(spi, chip); | |
503 | ||
504 | return 0; | |
505 | } | |
506 | ||
973fbce6 BD |
507 | static void dspi_cleanup(struct spi_device *spi) |
508 | { | |
509 | struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi); | |
510 | ||
511 | dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n", | |
512 | spi->master->bus_num, spi->chip_select); | |
513 | ||
514 | kfree(chip); | |
515 | } | |
516 | ||
349ad66c CF |
517 | static irqreturn_t dspi_interrupt(int irq, void *dev_id) |
518 | { | |
519 | struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; | |
9298bc72 | 520 | struct spi_message *msg = dspi->cur_msg; |
d1f4a38c | 521 | enum dspi_trans_mode trans_mode; |
c042af95 HW |
522 | u32 spi_sr, spi_tcr; |
523 | u32 spi_tcnt, tcnt_diff; | |
524 | int tx_word; | |
d1f4a38c HW |
525 | |
526 | regmap_read(dspi->regmap, SPI_SR, &spi_sr); | |
527 | regmap_write(dspi->regmap, SPI_SR, spi_sr); | |
528 | ||
349ad66c | 529 | |
c042af95 HW |
530 | if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) { |
531 | tx_word = is_double_byte_mode(dspi); | |
1acbdeb9 | 532 | |
c042af95 HW |
533 | regmap_read(dspi->regmap, SPI_TCR, &spi_tcr); |
534 | spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr); | |
535 | /* | |
536 | * The width of SPI Transfer Counter in SPI_TCR is 16bits, | |
537 | * so the max couner is 65535. When the counter reach 65535, | |
538 | * it will wrap around, counter reset to zero. | |
539 | * spi_tcnt my be less than dspi->spi_tcnt, it means the | |
540 | * counter already wrapped around. | |
541 | * SPI Transfer Counter is a counter of transmitted frames. | |
542 | * The size of frame maybe two bytes. | |
543 | */ | |
544 | tcnt_diff = ((spi_tcnt + SPI_TCR_TCNT_MAX) - dspi->spi_tcnt) | |
545 | % SPI_TCR_TCNT_MAX; | |
546 | tcnt_diff *= (tx_word + 1); | |
547 | if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) | |
548 | tcnt_diff--; | |
549 | ||
550 | msg->actual_length += tcnt_diff; | |
551 | ||
552 | dspi->spi_tcnt = spi_tcnt; | |
553 | ||
554 | trans_mode = dspi->devtype_data->trans_mode; | |
d1f4a38c HW |
555 | switch (trans_mode) { |
556 | case DSPI_EOQ_MODE: | |
c042af95 | 557 | dspi_eoq_read(dspi); |
d1f4a38c HW |
558 | break; |
559 | case DSPI_TCFQ_MODE: | |
c042af95 | 560 | dspi_tcfq_read(dspi); |
d1f4a38c HW |
561 | break; |
562 | default: | |
563 | dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", | |
564 | trans_mode); | |
c042af95 HW |
565 | return IRQ_HANDLED; |
566 | } | |
567 | ||
568 | if (!dspi->len) { | |
569 | if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) { | |
570 | regmap_update_bits(dspi->regmap, | |
571 | SPI_CTAR(dspi->cs), | |
572 | SPI_FRAME_BITS_MASK, | |
573 | SPI_FRAME_BITS(16)); | |
574 | dspi->dataflags &= ~TRAN_STATE_WORD_ODD_NUM; | |
575 | } | |
576 | ||
577 | dspi->waitflags = 1; | |
578 | wake_up_interruptible(&dspi->waitq); | |
579 | } else { | |
580 | switch (trans_mode) { | |
581 | case DSPI_EOQ_MODE: | |
582 | dspi_eoq_write(dspi); | |
583 | break; | |
584 | case DSPI_TCFQ_MODE: | |
585 | dspi_tcfq_write(dspi); | |
586 | break; | |
587 | default: | |
588 | dev_err(&dspi->pdev->dev, | |
589 | "unsupported trans_mode %u\n", | |
590 | trans_mode); | |
591 | } | |
d1f4a38c HW |
592 | } |
593 | } | |
c042af95 | 594 | |
349ad66c CF |
595 | return IRQ_HANDLED; |
596 | } | |
597 | ||
790d1902 | 598 | static const struct of_device_id fsl_dspi_dt_ids[] = { |
d1f4a38c HW |
599 | { .compatible = "fsl,vf610-dspi", .data = (void *)&vf610_data, }, |
600 | { .compatible = "fsl,ls1021a-v1.0-dspi", | |
601 | .data = (void *)&ls1021a_v1_data, }, | |
602 | { .compatible = "fsl,ls2085a-dspi", .data = (void *)&ls2085a_data, }, | |
349ad66c CF |
603 | { /* sentinel */ } |
604 | }; | |
605 | MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); | |
606 | ||
607 | #ifdef CONFIG_PM_SLEEP | |
608 | static int dspi_suspend(struct device *dev) | |
609 | { | |
610 | struct spi_master *master = dev_get_drvdata(dev); | |
611 | struct fsl_dspi *dspi = spi_master_get_devdata(master); | |
612 | ||
613 | spi_master_suspend(master); | |
614 | clk_disable_unprepare(dspi->clk); | |
615 | ||
616 | return 0; | |
617 | } | |
618 | ||
619 | static int dspi_resume(struct device *dev) | |
620 | { | |
349ad66c CF |
621 | struct spi_master *master = dev_get_drvdata(dev); |
622 | struct fsl_dspi *dspi = spi_master_get_devdata(master); | |
623 | ||
624 | clk_prepare_enable(dspi->clk); | |
625 | spi_master_resume(master); | |
626 | ||
627 | return 0; | |
628 | } | |
629 | #endif /* CONFIG_PM_SLEEP */ | |
630 | ||
ba811add | 631 | static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume); |
349ad66c | 632 | |
409851c3 | 633 | static const struct regmap_config dspi_regmap_config = { |
1acbdeb9 CF |
634 | .reg_bits = 32, |
635 | .val_bits = 32, | |
636 | .reg_stride = 4, | |
637 | .max_register = 0x88, | |
349ad66c CF |
638 | }; |
639 | ||
640 | static int dspi_probe(struct platform_device *pdev) | |
641 | { | |
642 | struct device_node *np = pdev->dev.of_node; | |
643 | struct spi_master *master; | |
644 | struct fsl_dspi *dspi; | |
645 | struct resource *res; | |
1acbdeb9 | 646 | void __iomem *base; |
349ad66c | 647 | int ret = 0, cs_num, bus_num; |
d1f4a38c HW |
648 | const struct of_device_id *of_id = |
649 | of_match_device(fsl_dspi_dt_ids, &pdev->dev); | |
349ad66c CF |
650 | |
651 | master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); | |
652 | if (!master) | |
653 | return -ENOMEM; | |
654 | ||
655 | dspi = spi_master_get_devdata(master); | |
656 | dspi->pdev = pdev; | |
9298bc72 CF |
657 | dspi->master = master; |
658 | ||
659 | master->transfer = NULL; | |
660 | master->setup = dspi_setup; | |
661 | master->transfer_one_message = dspi_transfer_one_message; | |
662 | master->dev.of_node = pdev->dev.of_node; | |
349ad66c | 663 | |
973fbce6 | 664 | master->cleanup = dspi_cleanup; |
349ad66c CF |
665 | master->mode_bits = SPI_CPOL | SPI_CPHA; |
666 | master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) | | |
667 | SPI_BPW_MASK(16); | |
668 | ||
669 | ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); | |
670 | if (ret < 0) { | |
671 | dev_err(&pdev->dev, "can't get spi-num-chipselects\n"); | |
672 | goto out_master_put; | |
673 | } | |
674 | master->num_chipselect = cs_num; | |
675 | ||
676 | ret = of_property_read_u32(np, "bus-num", &bus_num); | |
677 | if (ret < 0) { | |
678 | dev_err(&pdev->dev, "can't get bus-num\n"); | |
679 | goto out_master_put; | |
680 | } | |
681 | master->bus_num = bus_num; | |
682 | ||
d1f4a38c HW |
683 | dspi->devtype_data = (struct fsl_dspi_devtype_data *)of_id->data; |
684 | if (!dspi->devtype_data) { | |
685 | dev_err(&pdev->dev, "can't get devtype_data\n"); | |
686 | ret = -EFAULT; | |
687 | goto out_master_put; | |
688 | } | |
689 | ||
349ad66c | 690 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1acbdeb9 CF |
691 | base = devm_ioremap_resource(&pdev->dev, res); |
692 | if (IS_ERR(base)) { | |
693 | ret = PTR_ERR(base); | |
349ad66c CF |
694 | goto out_master_put; |
695 | } | |
696 | ||
d2233325 | 697 | dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base, |
1acbdeb9 CF |
698 | &dspi_regmap_config); |
699 | if (IS_ERR(dspi->regmap)) { | |
700 | dev_err(&pdev->dev, "failed to init regmap: %ld\n", | |
701 | PTR_ERR(dspi->regmap)); | |
702 | return PTR_ERR(dspi->regmap); | |
703 | } | |
704 | ||
349ad66c CF |
705 | dspi->irq = platform_get_irq(pdev, 0); |
706 | if (dspi->irq < 0) { | |
707 | dev_err(&pdev->dev, "can't get platform irq\n"); | |
708 | ret = dspi->irq; | |
709 | goto out_master_put; | |
710 | } | |
711 | ||
712 | ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0, | |
713 | pdev->name, dspi); | |
714 | if (ret < 0) { | |
715 | dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n"); | |
716 | goto out_master_put; | |
717 | } | |
718 | ||
719 | dspi->clk = devm_clk_get(&pdev->dev, "dspi"); | |
720 | if (IS_ERR(dspi->clk)) { | |
721 | ret = PTR_ERR(dspi->clk); | |
722 | dev_err(&pdev->dev, "unable to get clock\n"); | |
723 | goto out_master_put; | |
724 | } | |
725 | clk_prepare_enable(dspi->clk); | |
726 | ||
727 | init_waitqueue_head(&dspi->waitq); | |
017145fe | 728 | platform_set_drvdata(pdev, master); |
349ad66c | 729 | |
9298bc72 | 730 | ret = spi_register_master(master); |
349ad66c CF |
731 | if (ret != 0) { |
732 | dev_err(&pdev->dev, "Problem registering DSPI master\n"); | |
733 | goto out_clk_put; | |
734 | } | |
735 | ||
349ad66c CF |
736 | return ret; |
737 | ||
738 | out_clk_put: | |
739 | clk_disable_unprepare(dspi->clk); | |
740 | out_master_put: | |
741 | spi_master_put(master); | |
349ad66c CF |
742 | |
743 | return ret; | |
744 | } | |
745 | ||
746 | static int dspi_remove(struct platform_device *pdev) | |
747 | { | |
017145fe AL |
748 | struct spi_master *master = platform_get_drvdata(pdev); |
749 | struct fsl_dspi *dspi = spi_master_get_devdata(master); | |
349ad66c CF |
750 | |
751 | /* Disconnect from the SPI framework */ | |
05209f45 | 752 | clk_disable_unprepare(dspi->clk); |
9298bc72 CF |
753 | spi_unregister_master(dspi->master); |
754 | spi_master_put(dspi->master); | |
349ad66c CF |
755 | |
756 | return 0; | |
757 | } | |
758 | ||
759 | static struct platform_driver fsl_dspi_driver = { | |
760 | .driver.name = DRIVER_NAME, | |
761 | .driver.of_match_table = fsl_dspi_dt_ids, | |
762 | .driver.owner = THIS_MODULE, | |
763 | .driver.pm = &dspi_pm, | |
764 | .probe = dspi_probe, | |
765 | .remove = dspi_remove, | |
766 | }; | |
767 | module_platform_driver(fsl_dspi_driver); | |
768 | ||
769 | MODULE_DESCRIPTION("Freescale DSPI Controller Driver"); | |
b444d1df | 770 | MODULE_LICENSE("GPL"); |
349ad66c | 771 | MODULE_ALIAS("platform:" DRIVER_NAME); |